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authorLinus Walleij <linus.walleij@linaro.org>2014-09-30 06:16:25 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-10-20 03:08:26 -0400
commit1637d480f873ca305f7f090e3b3bc92430b5892f (patch)
treec254049d778fe41f11b35623561173873c6a1177
parent51d39936acba666774b596829277db3e13e5e970 (diff)
pinctrl: nomadik: force-convert to generic config bindings
This converts the Nomadik pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi36
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi150
-rw-r--r--arch/arm/boot/dts/ste-href-stuib.dtsi4
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618.dtsi12
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi8
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi38
-rw-r--r--arch/arm/boot/dts/ste-nomadik-s8815.dts8
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi12
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts24
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c4
10 files changed, 148 insertions, 148 deletions
diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
index 08a7365cb929..52dba2e39c71 100644
--- a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
@@ -23,24 +23,24 @@
23 23
24 uart0_default_mode: uart0_default { 24 uart0_default_mode: uart0_default {
25 default_cfg1 { 25 default_cfg1 {
26 ste,pins = "GPIO0", "GPIO2"; 26 pins = "GPIO0", "GPIO2";
27 ste,config = <&in_pu>; 27 ste,config = <&in_pu>;
28 }; 28 };
29 29
30 default_cfg2 { 30 default_cfg2 {
31 ste,pins = "GPIO1", "GPIO3"; 31 pins = "GPIO1", "GPIO3";
32 ste,config = <&out_hi>; 32 ste,config = <&out_hi>;
33 }; 33 };
34 }; 34 };
35 35
36 uart0_sleep_mode: uart0_sleep { 36 uart0_sleep_mode: uart0_sleep {
37 sleep_cfg1 { 37 sleep_cfg1 {
38 ste,pins = "GPIO0", "GPIO2"; 38 pins = "GPIO0", "GPIO2";
39 ste,config = <&slpm_in_pu>; 39 ste,config = <&slpm_in_pu>;
40 }; 40 };
41 41
42 sleep_cfg2 { 42 sleep_cfg2 {
43 ste,pins = "GPIO1", "GPIO3"; 43 pins = "GPIO1", "GPIO3";
44 ste,config = <&slpm_out_hi>; 44 ste,config = <&slpm_out_hi>;
45 }; 45 };
46 }; 46 };
@@ -54,24 +54,24 @@
54 }; 54 };
55 55
56 default_cfg1 { 56 default_cfg1 {
57 ste,pins = "GPIO120"; 57 pins = "GPIO120";
58 ste,config = <&in_pu>; 58 ste,config = <&in_pu>;
59 }; 59 };
60 60
61 default_cfg2 { 61 default_cfg2 {
62 ste,pins = "GPIO121"; 62 pins = "GPIO121";
63 ste,config = <&out_hi>; 63 ste,config = <&out_hi>;
64 }; 64 };
65 }; 65 };
66 66
67 uart2_sleep_mode: uart2_sleep { 67 uart2_sleep_mode: uart2_sleep {
68 sleep_cfg1 { 68 sleep_cfg1 {
69 ste,pins = "GPIO120"; 69 pins = "GPIO120";
70 ste,config = <&slpm_in_pu>; 70 ste,config = <&slpm_in_pu>;
71 }; 71 };
72 72
73 sleep_cfg2 { 73 sleep_cfg2 {
74 ste,pins = "GPIO121"; 74 pins = "GPIO121";
75 ste,config = <&slpm_out_hi>; 75 ste,config = <&slpm_out_hi>;
76 }; 76 };
77 }; 77 };
@@ -87,14 +87,14 @@
87 87
88 i2c0_default_mode: i2c_default { 88 i2c0_default_mode: i2c_default {
89 default_cfg1 { 89 default_cfg1 {
90 ste,pins = "GPIO147", "GPIO148"; 90 pins = "GPIO147", "GPIO148";
91 ste,config = <&in_pu>; 91 ste,config = <&in_pu>;
92 }; 92 };
93 }; 93 };
94 94
95 i2c0_sleep_mode: i2c_sleep { 95 i2c0_sleep_mode: i2c_sleep {
96 sleep_cfg1 { 96 sleep_cfg1 {
97 ste,pins = "GPIO147", "GPIO148"; 97 pins = "GPIO147", "GPIO148";
98 ste,config = <&slpm_in_pu>; 98 ste,config = <&slpm_in_pu>;
99 }; 99 };
100 }; 100 };
@@ -110,14 +110,14 @@
110 110
111 i2c1_default_mode: i2c_default { 111 i2c1_default_mode: i2c_default {
112 default_cfg1 { 112 default_cfg1 {
113 ste,pins = "GPIO16", "GPIO17"; 113 pins = "GPIO16", "GPIO17";
114 ste,config = <&in_pu>; 114 ste,config = <&in_pu>;
115 }; 115 };
116 }; 116 };
117 117
118 i2c1_sleep_mode: i2c_sleep { 118 i2c1_sleep_mode: i2c_sleep {
119 sleep_cfg1 { 119 sleep_cfg1 {
120 ste,pins = "GPIO16", "GPIO17"; 120 pins = "GPIO16", "GPIO17";
121 ste,config = <&slpm_in_pu>; 121 ste,config = <&slpm_in_pu>;
122 }; 122 };
123 }; 123 };
@@ -133,14 +133,14 @@
133 133
134 i2c2_default_mode: i2c_default { 134 i2c2_default_mode: i2c_default {
135 default_cfg1 { 135 default_cfg1 {
136 ste,pins = "GPIO10", "GPIO11"; 136 pins = "GPIO10", "GPIO11";
137 ste,config = <&in_pu>; 137 ste,config = <&in_pu>;
138 }; 138 };
139 }; 139 };
140 140
141 i2c2_sleep_mode: i2c_sleep { 141 i2c2_sleep_mode: i2c_sleep {
142 sleep_cfg1 { 142 sleep_cfg1 {
143 ste,pins = "GPIO11", "GPIO11"; 143 pins = "GPIO11", "GPIO11";
144 ste,config = <&slpm_in_pu>; 144 ste,config = <&slpm_in_pu>;
145 }; 145 };
146 }; 146 };
@@ -156,14 +156,14 @@
156 156
157 i2c4_default_mode: i2c_default { 157 i2c4_default_mode: i2c_default {
158 default_cfg1 { 158 default_cfg1 {
159 ste,pins = "GPIO122", "GPIO123"; 159 pins = "GPIO122", "GPIO123";
160 ste,config = <&in_pu>; 160 ste,config = <&in_pu>;
161 }; 161 };
162 }; 162 };
163 163
164 i2c4_sleep_mode: i2c_sleep { 164 i2c4_sleep_mode: i2c_sleep {
165 sleep_cfg1 { 165 sleep_cfg1 {
166 ste,pins = "GPIO122", "GPIO123"; 166 pins = "GPIO122", "GPIO123";
167 ste,config = <&slpm_in_pu>; 167 ste,config = <&slpm_in_pu>;
168 }; 168 };
169 }; 169 };
@@ -179,14 +179,14 @@
179 179
180 i2c5_default_mode: i2c_default { 180 i2c5_default_mode: i2c_default {
181 default_cfg1 { 181 default_cfg1 {
182 ste,pins = "GPIO118", "GPIO119"; 182 pins = "GPIO118", "GPIO119";
183 ste,config = <&in_pu>; 183 ste,config = <&in_pu>;
184 }; 184 };
185 }; 185 };
186 186
187 i2c5_sleep_mode: i2c_sleep { 187 i2c5_sleep_mode: i2c_sleep {
188 sleep_cfg1 { 188 sleep_cfg1 {
189 ste,pins = "GPIO118", "GPIO119"; 189 pins = "GPIO118", "GPIO119";
190 ste,config = <&slpm_in_pu>; 190 ste,config = <&slpm_in_pu>;
191 }; 191 };
192 }; 192 };
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 61aa87138927..5c5cea232743 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -22,29 +22,29 @@
22 groups = "u0_a_1"; 22 groups = "u0_a_1";
23 }; 23 };
24 default_cfg1 { 24 default_cfg1 {
25 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 25 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
26 ste,config = <&in_pu>; 26 ste,config = <&in_pu>;
27 }; 27 };
28 28
29 default_cfg2 { 29 default_cfg2 {
30 ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 30 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
31 ste,config = <&out_hi>; 31 ste,config = <&out_hi>;
32 }; 32 };
33 }; 33 };
34 34
35 uart0_sleep_mode: uart0_sleep { 35 uart0_sleep_mode: uart0_sleep {
36 sleep_cfg1 { 36 sleep_cfg1 {
37 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 37 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
38 ste,config = <&slpm_in_wkup_pdis>; 38 ste,config = <&slpm_in_wkup_pdis>;
39 }; 39 };
40 40
41 sleep_cfg2 { 41 sleep_cfg2 {
42 ste,pins = "GPIO1_AJ3"; /* RTS */ 42 pins = "GPIO1_AJ3"; /* RTS */
43 ste,config = <&slpm_out_hi_wkup_pdis>; 43 ste,config = <&slpm_out_hi_wkup_pdis>;
44 }; 44 };
45 45
46 sleep_cfg3 { 46 sleep_cfg3 {
47 ste,pins = "GPIO3_AH3"; /* TXD */ 47 pins = "GPIO3_AH3"; /* TXD */
48 ste,config = <&slpm_out_wkup_pdis>; 48 ste,config = <&slpm_out_wkup_pdis>;
49 }; 49 };
50 }; 50 };
@@ -57,24 +57,24 @@
57 groups = "u1rxtx_a_1"; 57 groups = "u1rxtx_a_1";
58 }; 58 };
59 default_cfg1 { 59 default_cfg1 {
60 ste,pins = "GPIO4_AH6"; /* RXD */ 60 pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&in_pu>; 61 ste,config = <&in_pu>;
62 }; 62 };
63 63
64 default_cfg2 { 64 default_cfg2 {
65 ste,pins = "GPIO5_AG6"; /* TXD */ 65 pins = "GPIO5_AG6"; /* TXD */
66 ste,config = <&out_hi>; 66 ste,config = <&out_hi>;
67 }; 67 };
68 }; 68 };
69 69
70 uart1_sleep_mode: uart1_sleep { 70 uart1_sleep_mode: uart1_sleep {
71 sleep_cfg1 { 71 sleep_cfg1 {
72 ste,pins = "GPIO4_AH6"; /* RXD */ 72 pins = "GPIO4_AH6"; /* RXD */
73 ste,config = <&slpm_in_wkup_pdis>; 73 ste,config = <&slpm_in_wkup_pdis>;
74 }; 74 };
75 75
76 sleep_cfg2 { 76 sleep_cfg2 {
77 ste,pins = "GPIO5_AG6"; /* TXD */ 77 pins = "GPIO5_AG6"; /* TXD */
78 ste,config = <&slpm_out_wkup_pdis>; 78 ste,config = <&slpm_out_wkup_pdis>;
79 }; 79 };
80 }; 80 };
@@ -87,24 +87,24 @@
87 groups = "u2rxtx_c_1"; 87 groups = "u2rxtx_c_1";
88 }; 88 };
89 default_cfg1 { 89 default_cfg1 {
90 ste,pins = "GPIO29_W2"; /* RXD */ 90 pins = "GPIO29_W2"; /* RXD */
91 ste,config = <&in_pu>; 91 ste,config = <&in_pu>;
92 }; 92 };
93 93
94 default_cfg2 { 94 default_cfg2 {
95 ste,pins = "GPIO30_W3"; /* TXD */ 95 pins = "GPIO30_W3"; /* TXD */
96 ste,config = <&out_hi>; 96 ste,config = <&out_hi>;
97 }; 97 };
98 }; 98 };
99 99
100 uart2_sleep_mode: uart2_sleep { 100 uart2_sleep_mode: uart2_sleep {
101 sleep_cfg1 { 101 sleep_cfg1 {
102 ste,pins = "GPIO29_W2"; /* RXD */ 102 pins = "GPIO29_W2"; /* RXD */
103 ste,config = <&in_wkup_pdis>; 103 ste,config = <&in_wkup_pdis>;
104 }; 104 };
105 105
106 sleep_cfg2 { 106 sleep_cfg2 {
107 ste,pins = "GPIO30_W3"; /* TXD */ 107 pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_wkup_pdis>; 108 ste,config = <&out_wkup_pdis>;
109 }; 109 };
110 }; 110 };
@@ -118,14 +118,14 @@
118 groups = "i2c0_a_1"; 118 groups = "i2c0_a_1";
119 }; 119 };
120 default_cfg1 { 120 default_cfg1 {
121 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 121 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>; 122 ste,config = <&in_pu>;
123 }; 123 };
124 }; 124 };
125 125
126 i2c0_sleep_mode: i2c_sleep { 126 i2c0_sleep_mode: i2c_sleep {
127 sleep_cfg1 { 127 sleep_cfg1 {
128 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 128 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>; 129 ste,config = <&slpm_in_wkup_pdis>;
130 }; 130 };
131 }; 131 };
@@ -138,14 +138,14 @@
138 groups = "i2c1_b_2"; 138 groups = "i2c1_b_2";
139 }; 139 };
140 default_cfg1 { 140 default_cfg1 {
141 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 141 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>; 142 ste,config = <&in_pu>;
143 }; 143 };
144 }; 144 };
145 145
146 i2c1_sleep_mode: i2c_sleep { 146 i2c1_sleep_mode: i2c_sleep {
147 sleep_cfg1 { 147 sleep_cfg1 {
148 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 148 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>; 149 ste,config = <&slpm_in_wkup_pdis>;
150 }; 150 };
151 }; 151 };
@@ -158,14 +158,14 @@
158 groups = "i2c2_b_2"; 158 groups = "i2c2_b_2";
159 }; 159 };
160 default_cfg1 { 160 default_cfg1 {
161 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 161 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>; 162 ste,config = <&in_pu>;
163 }; 163 };
164 }; 164 };
165 165
166 i2c2_sleep_mode: i2c_sleep { 166 i2c2_sleep_mode: i2c_sleep {
167 sleep_cfg1 { 167 sleep_cfg1 {
168 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 168 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>; 169 ste,config = <&slpm_in_wkup_pdis>;
170 }; 170 };
171 }; 171 };
@@ -178,14 +178,14 @@
178 groups = "i2c3_c_2"; 178 groups = "i2c3_c_2";
179 }; 179 };
180 default_cfg1 { 180 default_cfg1 {
181 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 181 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>; 182 ste,config = <&in_pu>;
183 }; 183 };
184 }; 184 };
185 185
186 i2c3_sleep_mode: i2c_sleep { 186 i2c3_sleep_mode: i2c_sleep {
187 sleep_cfg1 { 187 sleep_cfg1 {
188 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 188 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>; 189 ste,config = <&slpm_in_wkup_pdis>;
190 }; 190 };
191 }; 191 };
@@ -202,14 +202,14 @@
202 groups = "i2c4_b_1"; 202 groups = "i2c4_b_1";
203 }; 203 };
204 default_cfg1 { 204 default_cfg1 {
205 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 205 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>; 206 ste,config = <&in_pu>;
207 }; 207 };
208 }; 208 };
209 209
210 i2c4_sleep_mode: i2c_sleep { 210 i2c4_sleep_mode: i2c_sleep {
211 sleep_cfg1 { 211 sleep_cfg1 {
212 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 212 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>; 213 ste,config = <&slpm_in_wkup_pdis>;
214 }; 214 };
215 }; 215 };
@@ -223,15 +223,15 @@
223 groups = "spi2_oc1_2"; 223 groups = "spi2_oc1_2";
224 }; 224 };
225 default_cfg1 { 225 default_cfg1 {
226 ste,pins = "GPIO216_AG12"; /* FRM */ 226 pins = "GPIO216_AG12"; /* FRM */
227 ste,config = <&gpio_out_hi>; 227 ste,config = <&gpio_out_hi>;
228 }; 228 };
229 default_cfg2 { 229 default_cfg2 {
230 ste,pins = "GPIO218_AH11"; /* RXD */ 230 pins = "GPIO218_AH11"; /* RXD */
231 ste,config = <&in_pd>; 231 ste,config = <&in_pd>;
232 }; 232 };
233 default_cfg3 { 233 default_cfg3 {
234 ste,pins = 234 pins =
235 "GPIO215_AH13", /* TXD */ 235 "GPIO215_AH13", /* TXD */
236 "GPIO217_AH12"; /* CLK */ 236 "GPIO217_AH12"; /* CLK */
237 ste,config = <&out_lo>; 237 ste,config = <&out_lo>;
@@ -245,32 +245,32 @@
245 * as we do not state any muxing. 245 * as we do not state any muxing.
246 */ 246 */
247 idle_cfg1 { 247 idle_cfg1 {
248 ste,pins = "GPIO218_AH11"; /* RXD */ 248 pins = "GPIO218_AH11"; /* RXD */
249 ste,config = <&slpm_in_pdis>; 249 ste,config = <&slpm_in_pdis>;
250 }; 250 };
251 idle_cfg2 { 251 idle_cfg2 {
252 ste,pins = "GPIO215_AH13"; /* TXD */ 252 pins = "GPIO215_AH13"; /* TXD */
253 ste,config = <&slpm_out_lo_pdis>; 253 ste,config = <&slpm_out_lo_pdis>;
254 }; 254 };
255 idle_cfg3 { 255 idle_cfg3 {
256 ste,pins = "GPIO217_AH12"; /* CLK */ 256 pins = "GPIO217_AH12"; /* CLK */
257 ste,config = <&slpm_pdis>; 257 ste,config = <&slpm_pdis>;
258 }; 258 };
259 }; 259 };
260 260
261 spi2_sleep_mode: spi_sleep { 261 spi2_sleep_mode: spi_sleep {
262 sleep_cfg1 { 262 sleep_cfg1 {
263 ste,pins = 263 pins =
264 "GPIO216_AG12", /* FRM */ 264 "GPIO216_AG12", /* FRM */
265 "GPIO218_AH11"; /* RXD */ 265 "GPIO218_AH11"; /* RXD */
266 ste,config = <&slpm_in_wkup_pdis>; 266 ste,config = <&slpm_in_wkup_pdis>;
267 }; 267 };
268 sleep_cfg2 { 268 sleep_cfg2 {
269 ste,pins = "GPIO215_AH13"; /* TXD */ 269 pins = "GPIO215_AH13"; /* TXD */
270 ste,config = <&slpm_out_lo_wkup_pdis>; 270 ste,config = <&slpm_out_lo_wkup_pdis>;
271 }; 271 };
272 sleep_cfg3 { 272 sleep_cfg3 {
273 ste,pins = "GPIO217_AH12"; /* CLK */ 273 pins = "GPIO217_AH12"; /* CLK */
274 ste,config = <&slpm_wkup_pdis>; 274 ste,config = <&slpm_wkup_pdis>;
275 }; 275 };
276 }; 276 };
@@ -285,22 +285,22 @@
285 groups = "mc0_a_1"; 285 groups = "mc0_a_1";
286 }; 286 };
287 default_cfg1 { 287 default_cfg1 {
288 ste,pins = 288 pins =
289 "GPIO18_AC2", /* CMDDIR */ 289 "GPIO18_AC2", /* CMDDIR */
290 "GPIO19_AC1", /* DAT0DIR */ 290 "GPIO19_AC1", /* DAT0DIR */
291 "GPIO20_AB4"; /* DAT2DIR */ 291 "GPIO20_AB4"; /* DAT2DIR */
292 ste,config = <&out_hi>; 292 ste,config = <&out_hi>;
293 }; 293 };
294 default_cfg2 { 294 default_cfg2 {
295 ste,pins = "GPIO22_AA3"; /* FBCLK */ 295 pins = "GPIO22_AA3"; /* FBCLK */
296 ste,config = <&in_nopull>; 296 ste,config = <&in_nopull>;
297 }; 297 };
298 default_cfg3 { 298 default_cfg3 {
299 ste,pins = "GPIO23_AA4"; /* CLK */ 299 pins = "GPIO23_AA4"; /* CLK */
300 ste,config = <&out_lo>; 300 ste,config = <&out_lo>;
301 }; 301 };
302 default_cfg4 { 302 default_cfg4 {
303 ste,pins = 303 pins =
304 "GPIO24_AB2", /* CMD */ 304 "GPIO24_AB2", /* CMD */
305 "GPIO25_Y4", /* DAT0 */ 305 "GPIO25_Y4", /* DAT0 */
306 "GPIO26_Y2", /* DAT1 */ 306 "GPIO26_Y2", /* DAT1 */
@@ -312,14 +312,14 @@
312 312
313 sdi0_sleep_mode: sdi0_sleep { 313 sdi0_sleep_mode: sdi0_sleep {
314 sleep_cfg1 { 314 sleep_cfg1 {
315 ste,pins = 315 pins =
316 "GPIO18_AC2", /* CMDDIR */ 316 "GPIO18_AC2", /* CMDDIR */
317 "GPIO19_AC1", /* DAT0DIR */ 317 "GPIO19_AC1", /* DAT0DIR */
318 "GPIO20_AB4"; /* DAT2DIR */ 318 "GPIO20_AB4"; /* DAT2DIR */
319 ste,config = <&slpm_out_hi_wkup_pdis>; 319 ste,config = <&slpm_out_hi_wkup_pdis>;
320 }; 320 };
321 sleep_cfg2 { 321 sleep_cfg2 {
322 ste,pins = 322 pins =
323 "GPIO22_AA3", /* FBCLK */ 323 "GPIO22_AA3", /* FBCLK */
324 "GPIO24_AB2", /* CMD */ 324 "GPIO24_AB2", /* CMD */
325 "GPIO25_Y4", /* DAT0 */ 325 "GPIO25_Y4", /* DAT0 */
@@ -329,7 +329,7 @@
329 ste,config = <&slpm_in_wkup_pdis>; 329 ste,config = <&slpm_in_wkup_pdis>;
330 }; 330 };
331 sleep_cfg3 { 331 sleep_cfg3 {
332 ste,pins = "GPIO23_AA4"; /* CLK */ 332 pins = "GPIO23_AA4"; /* CLK */
333 ste,config = <&slpm_out_lo_wkup_pdis>; 333 ste,config = <&slpm_out_lo_wkup_pdis>;
334 }; 334 };
335 }; 335 };
@@ -343,15 +343,15 @@
343 groups = "mc1_a_1"; 343 groups = "mc1_a_1";
344 }; 344 };
345 default_cfg1 { 345 default_cfg1 {
346 ste,pins = "GPIO208_AH16"; /* CLK */ 346 pins = "GPIO208_AH16"; /* CLK */
347 ste,config = <&out_lo>; 347 ste,config = <&out_lo>;
348 }; 348 };
349 default_cfg2 { 349 default_cfg2 {
350 ste,pins = "GPIO209_AG15"; /* FBCLK */ 350 pins = "GPIO209_AG15"; /* FBCLK */
351 ste,config = <&in_nopull>; 351 ste,config = <&in_nopull>;
352 }; 352 };
353 default_cfg3 { 353 default_cfg3 {
354 ste,pins = 354 pins =
355 "GPIO210_AJ15", /* CMD */ 355 "GPIO210_AJ15", /* CMD */
356 "GPIO211_AG14", /* DAT0 */ 356 "GPIO211_AG14", /* DAT0 */
357 "GPIO212_AF13", /* DAT1 */ 357 "GPIO212_AF13", /* DAT1 */
@@ -363,11 +363,11 @@
363 363
364 sdi1_sleep_mode: sdi1_sleep { 364 sdi1_sleep_mode: sdi1_sleep {
365 sleep_cfg1 { 365 sleep_cfg1 {
366 ste,pins = "GPIO208_AH16"; /* CLK */ 366 pins = "GPIO208_AH16"; /* CLK */
367 ste,config = <&slpm_out_lo_wkup_pdis>; 367 ste,config = <&slpm_out_lo_wkup_pdis>;
368 }; 368 };
369 sleep_cfg2 { 369 sleep_cfg2 {
370 ste,pins = 370 pins =
371 "GPIO209_AG15", /* FBCLK */ 371 "GPIO209_AG15", /* FBCLK */
372 "GPIO210_AJ15", /* CMD */ 372 "GPIO210_AJ15", /* CMD */
373 "GPIO211_AG14", /* DAT0 */ 373 "GPIO211_AG14", /* DAT0 */
@@ -387,15 +387,15 @@
387 groups = "mc2_a_1"; 387 groups = "mc2_a_1";
388 }; 388 };
389 default_cfg1 { 389 default_cfg1 {
390 ste,pins = "GPIO128_A5"; /* CLK */ 390 pins = "GPIO128_A5"; /* CLK */
391 ste,config = <&out_lo>; 391 ste,config = <&out_lo>;
392 }; 392 };
393 default_cfg2 { 393 default_cfg2 {
394 ste,pins = "GPIO130_C8"; /* FBCLK */ 394 pins = "GPIO130_C8"; /* FBCLK */
395 ste,config = <&in_nopull>; 395 ste,config = <&in_nopull>;
396 }; 396 };
397 default_cfg3 { 397 default_cfg3 {
398 ste,pins = 398 pins =
399 "GPIO129_B4", /* CMD */ 399 "GPIO129_B4", /* CMD */
400 "GPIO131_A12", /* DAT0 */ 400 "GPIO131_A12", /* DAT0 */
401 "GPIO132_C10", /* DAT1 */ 401 "GPIO132_C10", /* DAT1 */
@@ -411,17 +411,17 @@
411 411
412 sdi2_sleep_mode: sdi2_sleep { 412 sdi2_sleep_mode: sdi2_sleep {
413 sleep_cfg1 { 413 sleep_cfg1 {
414 ste,pins = "GPIO128_A5"; /* CLK */ 414 pins = "GPIO128_A5"; /* CLK */
415 ste,config = <&out_lo_wkup_pdis>; 415 ste,config = <&out_lo_wkup_pdis>;
416 }; 416 };
417 sleep_cfg2 { 417 sleep_cfg2 {
418 ste,pins = 418 pins =
419 "GPIO130_C8", /* FBCLK */ 419 "GPIO130_C8", /* FBCLK */
420 "GPIO129_B4"; /* CMD */ 420 "GPIO129_B4"; /* CMD */
421 ste,config = <&in_wkup_pdis_en>; 421 ste,config = <&in_wkup_pdis_en>;
422 }; 422 };
423 sleep_cfg3 { 423 sleep_cfg3 {
424 ste,pins = 424 pins =
425 "GPIO131_A12", /* DAT0 */ 425 "GPIO131_A12", /* DAT0 */
426 "GPIO132_C10", /* DAT1 */ 426 "GPIO132_C10", /* DAT1 */
427 "GPIO133_B10", /* DAT2 */ 427 "GPIO133_B10", /* DAT2 */
@@ -443,15 +443,15 @@
443 groups = "mc4_a_1"; 443 groups = "mc4_a_1";
444 }; 444 };
445 default_cfg1 { 445 default_cfg1 {
446 ste,pins = "GPIO203_AE23"; /* CLK */ 446 pins = "GPIO203_AE23"; /* CLK */
447 ste,config = <&out_lo>; 447 ste,config = <&out_lo>;
448 }; 448 };
449 default_cfg2 { 449 default_cfg2 {
450 ste,pins = "GPIO202_AF25"; /* FBCLK */ 450 pins = "GPIO202_AF25"; /* FBCLK */
451 ste,config = <&in_nopull>; 451 ste,config = <&in_nopull>;
452 }; 452 };
453 default_cfg3 { 453 default_cfg3 {
454 ste,pins = 454 pins =
455 "GPIO201_AF24", /* CMD */ 455 "GPIO201_AF24", /* CMD */
456 "GPIO200_AH26", /* DAT0 */ 456 "GPIO200_AH26", /* DAT0 */
457 "GPIO199_AH23", /* DAT1 */ 457 "GPIO199_AH23", /* DAT1 */
@@ -467,11 +467,11 @@
467 467
468 sdi4_sleep_mode: sdi4_sleep { 468 sdi4_sleep_mode: sdi4_sleep {
469 sleep_cfg1 { 469 sleep_cfg1 {
470 ste,pins = "GPIO203_AE23"; /* CLK */ 470 pins = "GPIO203_AE23"; /* CLK */
471 ste,config = <&out_lo_wkup_pdis>; 471 ste,config = <&out_lo_wkup_pdis>;
472 }; 472 };
473 sleep_cfg2 { 473 sleep_cfg2 {
474 ste,pins = 474 pins =
475 "GPIO202_AF25", /* FBCLK */ 475 "GPIO202_AF25", /* FBCLK */
476 "GPIO201_AF24", /* CMD */ 476 "GPIO201_AF24", /* CMD */
477 "GPIO200_AH26", /* DAT0 */ 477 "GPIO200_AH26", /* DAT0 */
@@ -498,7 +498,7 @@
498 groups = "msp0txrx_a_1", "msp0tfstck_a_1"; 498 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
499 }; 499 };
500 default_msp0_cfg { 500 default_msp0_cfg {
501 ste,pins = 501 pins =
502 "GPIO12_AC4", /* TXD */ 502 "GPIO12_AC4", /* TXD */
503 "GPIO15_AC3", /* RXD */ 503 "GPIO15_AC3", /* RXD */
504 "GPIO13_AF3", /* TFS */ 504 "GPIO13_AF3", /* TFS */
@@ -515,11 +515,11 @@
515 groups = "msp1txrx_a_1", "msp1_a_1"; 515 groups = "msp1txrx_a_1", "msp1_a_1";
516 }; 516 };
517 default_cfg1 { 517 default_cfg1 {
518 ste,pins = "GPIO33_AF2"; 518 pins = "GPIO33_AF2";
519 ste,config = <&out_lo>; 519 ste,config = <&out_lo>;
520 }; 520 };
521 default_cfg2 { 521 default_cfg2 {
522 ste,pins = 522 pins =
523 "GPIO34_AE1", 523 "GPIO34_AE1",
524 "GPIO35_AE2", 524 "GPIO35_AE2",
525 "GPIO36_AG2"; 525 "GPIO36_AG2";
@@ -537,14 +537,14 @@
537 groups = "msp2_a_1"; 537 groups = "msp2_a_1";
538 }; 538 };
539 default_cfg1 { 539 default_cfg1 {
540 ste,pins = 540 pins =
541 "GPIO193_AH27", /* TXD */ 541 "GPIO193_AH27", /* TXD */
542 "GPIO194_AF27", /* TCK */ 542 "GPIO194_AF27", /* TCK */
543 "GPIO195_AG28"; /* TFS */ 543 "GPIO195_AG28"; /* TFS */
544 ste,config = <&in_pd>; 544 ste,config = <&in_pd>;
545 }; 545 };
546 default_cfg2 { 546 default_cfg2 {
547 ste,pins = "GPIO196_AG26"; /* RXD */ 547 pins = "GPIO196_AG26"; /* RXD */
548 ste,config = <&out_lo>; 548 ste,config = <&out_lo>;
549 }; 549 };
550 }; 550 };
@@ -558,7 +558,7 @@
558 groups = "usb_a_1"; 558 groups = "usb_a_1";
559 }; 559 };
560 default_cfg1 { 560 default_cfg1 {
561 ste,pins = 561 pins =
562 "GPIO256_AF28", /* NXT */ 562 "GPIO256_AF28", /* NXT */
563 "GPIO258_AD29", /* XCLK */ 563 "GPIO258_AD29", /* XCLK */
564 "GPIO259_AC29", /* DIR */ 564 "GPIO259_AC29", /* DIR */
@@ -573,25 +573,25 @@
573 ste,config = <&in_nopull>; 573 ste,config = <&in_nopull>;
574 }; 574 };
575 default_cfg2 { 575 default_cfg2 {
576 ste,pins = "GPIO257_AE29"; /* STP */ 576 pins = "GPIO257_AE29"; /* STP */
577 ste,config = <&out_hi>; 577 ste,config = <&out_hi>;
578 }; 578 };
579 }; 579 };
580 580
581 musb_sleep_mode: musb_sleep { 581 musb_sleep_mode: musb_sleep {
582 sleep_cfg1 { 582 sleep_cfg1 {
583 ste,pins = 583 pins =
584 "GPIO256_AF28", /* NXT */ 584 "GPIO256_AF28", /* NXT */
585 "GPIO258_AD29", /* XCLK */ 585 "GPIO258_AD29", /* XCLK */
586 "GPIO259_AC29"; /* DIR */ 586 "GPIO259_AC29"; /* DIR */
587 ste,config = <&slpm_wkup_pdis_en>; 587 ste,config = <&slpm_wkup_pdis_en>;
588 }; 588 };
589 sleep_cfg2 { 589 sleep_cfg2 {
590 ste,pins = "GPIO257_AE29"; /* STP */ 590 pins = "GPIO257_AE29"; /* STP */
591 ste,config = <&slpm_out_hi_wkup_pdis>; 591 ste,config = <&slpm_out_hi_wkup_pdis>;
592 }; 592 };
593 sleep_cfg3 { 593 sleep_cfg3 {
594 ste,pins = 594 pins =
595 "GPIO260_AD28", /* DAT7 */ 595 "GPIO260_AD28", /* DAT7 */
596 "GPIO261_AD26", /* DAT6 */ 596 "GPIO261_AD26", /* DAT6 */
597 "GPIO262_AE26", /* DAT5 */ 597 "GPIO262_AE26", /* DAT5 */
@@ -618,7 +618,7 @@
618 "lcdvsi1_a_1"; /* VSI1 for HDMI */ 618 "lcdvsi1_a_1"; /* VSI1 for HDMI */
619 }; 619 };
620 default_cfg1 { 620 default_cfg1 {
621 ste,pins = 621 pins =
622 "GPIO68_E1", /* VSI0 */ 622 "GPIO68_E1", /* VSI0 */
623 "GPIO69_E2"; /* VSI1 */ 623 "GPIO69_E2"; /* VSI1 */
624 ste,config = <&in_pu>; 624 ste,config = <&in_pu>;
@@ -626,7 +626,7 @@
626 }; 626 };
627 lcd_sleep_mode: lcd_sleep { 627 lcd_sleep_mode: lcd_sleep {
628 sleep_cfg1 { 628 sleep_cfg1 {
629 ste,pins = "GPIO69_E2"; /* VSI1 */ 629 pins = "GPIO69_E2"; /* VSI1 */
630 ste,config = <&slpm_in_wkup_pdis>; 630 ste,config = <&slpm_in_wkup_pdis>;
631 }; 631 };
632 }; 632 };
@@ -640,7 +640,7 @@
640 groups = "kp_a_2"; 640 groups = "kp_a_2";
641 }; 641 };
642 default_cfg1 { 642 default_cfg1 {
643 ste,pins = 643 pins =
644 "GPIO153_B17", /* I7 */ 644 "GPIO153_B17", /* I7 */
645 "GPIO154_C16", /* I6 */ 645 "GPIO154_C16", /* I6 */
646 "GPIO155_C19", /* I5 */ 646 "GPIO155_C19", /* I5 */
@@ -652,7 +652,7 @@
652 ste,config = <&in_pd>; 652 ste,config = <&in_pd>;
653 }; 653 };
654 default_cfg2 { 654 default_cfg2 {
655 ste,pins = 655 pins =
656 "GPIO157_A18", /* O7 */ 656 "GPIO157_A18", /* O7 */
657 "GPIO158_C18", /* O6 */ 657 "GPIO158_C18", /* O6 */
658 "GPIO159_B19", /* O5 */ 658 "GPIO159_B19", /* O5 */
@@ -666,7 +666,7 @@
666 }; 666 };
667 ske_kpa2_sleep_mode: ske_kpa2_sleep { 667 ske_kpa2_sleep_mode: ske_kpa2_sleep {
668 sleep_cfg1 { 668 sleep_cfg1 {
669 ste,pins = 669 pins =
670 "GPIO153_B17", /* I7 */ 670 "GPIO153_B17", /* I7 */
671 "GPIO154_C16", /* I6 */ 671 "GPIO154_C16", /* I6 */
672 "GPIO155_C19", /* I5 */ 672 "GPIO155_C19", /* I5 */
@@ -678,7 +678,7 @@
678 ste,config = <&slpm_in_pu_wkup_pdis_en>; 678 ste,config = <&slpm_in_pu_wkup_pdis_en>;
679 }; 679 };
680 sleep_cfg2 { 680 sleep_cfg2 {
681 ste,pins = 681 pins =
682 "GPIO157_A18", /* O7 */ 682 "GPIO157_A18", /* O7 */
683 "GPIO158_C18", /* O6 */ 683 "GPIO158_C18", /* O6 */
684 "GPIO159_B19", /* O5 */ 684 "GPIO159_B19", /* O5 */
@@ -700,7 +700,7 @@
700 groups = "kp_a_1", "kp_oc1_1"; 700 groups = "kp_a_1", "kp_oc1_1";
701 }; 701 };
702 default_cfg1 { 702 default_cfg1 {
703 ste,pins = 703 pins =
704 "GPIO91_B6", /* KP_O0 */ 704 "GPIO91_B6", /* KP_O0 */
705 "GPIO90_A3", /* KP_O1 */ 705 "GPIO90_A3", /* KP_O1 */
706 "GPIO87_B3", /* KP_O2 */ 706 "GPIO87_B3", /* KP_O2 */
@@ -710,7 +710,7 @@
710 ste,config = <&out_lo>; 710 ste,config = <&out_lo>;
711 }; 711 };
712 default_cfg2 { 712 default_cfg2 {
713 ste,pins = 713 pins =
714 "GPIO93_B7", /* KP_I0 */ 714 "GPIO93_B7", /* KP_I0 */
715 "GPIO92_D6", /* KP_I1 */ 715 "GPIO92_D6", /* KP_I1 */
716 "GPIO89_E6", /* KP_I2 */ 716 "GPIO89_E6", /* KP_I2 */
@@ -729,13 +729,13 @@
729 * These are plain GPIO pins used by WLAN 729 * These are plain GPIO pins used by WLAN
730 */ 730 */
731 default_cfg1 { 731 default_cfg1 {
732 ste,pins = 732 pins =
733 "GPIO226_AF8", /* WLAN_PMU_EN */ 733 "GPIO226_AF8", /* WLAN_PMU_EN */
734 "GPIO85_D5"; /* WLAN_ENA */ 734 "GPIO85_D5"; /* WLAN_ENA */
735 ste,config = <&gpio_out_lo>; 735 ste,config = <&gpio_out_lo>;
736 }; 736 };
737 default_cfg2 { 737 default_cfg2 {
738 ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ 738 pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
739 ste,config = <&gpio_in_pu>; 739 ste,config = <&gpio_in_pu>;
740 }; 740 };
741 }; 741 };
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 84d7c5d883f2..7d4f8184c522 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -103,7 +103,7 @@
103 prox { 103 prox {
104 prox_stuib_mode: prox_stuib { 104 prox_stuib_mode: prox_stuib {
105 stuib_cfg { 105 stuib_cfg {
106 ste,pins = "GPIO217_AH12"; 106 pins = "GPIO217_AH12";
107 ste,config = <&gpio_in_pu>; 107 ste,config = <&gpio_in_pu>;
108 }; 108 };
109 }; 109 };
@@ -111,7 +111,7 @@
111 hall { 111 hall {
112 hall_stuib_mode: stuib_tvk { 112 hall_stuib_mode: stuib_tvk {
113 stuib_cfg { 113 stuib_cfg {
114 ste,pins = "GPIO145_C13"; 114 pins = "GPIO145_C13";
115 ste,config = <&gpio_in_pu>; 115 ste,config = <&gpio_in_pu>;
116 }; 116 };
117 }; 117 };
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 18b65d1b14f2..062c6aae3afa 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -130,7 +130,7 @@
130 tc35893 { 130 tc35893 {
131 tc35893_tvk_mode: tc35893_tvk { 131 tc35893_tvk_mode: tc35893_tvk {
132 tvk_cfg { 132 tvk_cfg {
133 ste,pins = "GPIO218_AH11"; 133 pins = "GPIO218_AH11";
134 ste,config = <&gpio_in_pu>; 134 ste,config = <&gpio_in_pu>;
135 }; 135 };
136 }; 136 };
@@ -138,7 +138,7 @@
138 prox { 138 prox {
139 prox_tvk_mode: prox_tvk { 139 prox_tvk_mode: prox_tvk {
140 tvk_cfg { 140 tvk_cfg {
141 ste,pins = "GPIO217_AH12"; 141 pins = "GPIO217_AH12";
142 ste,config = <&gpio_in_pu>; 142 ste,config = <&gpio_in_pu>;
143 }; 143 };
144 }; 144 };
@@ -146,7 +146,7 @@
146 hall { 146 hall {
147 hall_tvk_mode: hall_tvk { 147 hall_tvk_mode: hall_tvk {
148 tvk_cfg { 148 tvk_cfg {
149 ste,pins = "GPIO145_C13"; 149 pins = "GPIO145_C13";
150 ste,config = <&gpio_in_pu>; 150 ste,config = <&gpio_in_pu>;
151 }; 151 };
152 }; 152 };
@@ -155,7 +155,7 @@
155 accel_tvk_mode: accel_tvk { 155 accel_tvk_mode: accel_tvk {
156 /* Accelerometer interrupt lines 1 & 2 */ 156 /* Accelerometer interrupt lines 1 & 2 */
157 tvk_cfg { 157 tvk_cfg {
158 ste,pins = "GPIO82_C1", "GPIO83_D3"; 158 pins = "GPIO82_C1", "GPIO83_D3";
159 ste,config = <&gpio_in_pu>; 159 ste,config = <&gpio_in_pu>;
160 }; 160 };
161 }; 161 };
@@ -164,11 +164,11 @@
164 magneto_tvk_mode: magneto_tvk { 164 magneto_tvk_mode: magneto_tvk {
165 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ 165 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
166 tvk_cfg1 { 166 tvk_cfg1 {
167 ste,pins = "GPIO31_V3"; 167 pins = "GPIO31_V3";
168 ste,config = <&gpio_in_pu>; 168 ste,config = <&gpio_in_pu>;
169 }; 169 };
170 tvk_cfg2 { 170 tvk_cfg2 {
171 ste,pins = "GPIO32_V2"; 171 pins = "GPIO32_V2";
172 ste,config = <&gpio_in_pd>; 172 ste,config = <&gpio_in_pd>;
173 }; 173 };
174 }; 174 };
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 5d8b7f8ced1b..7f3975b58d16 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -83,7 +83,7 @@
83 groups = "ssp0_a_1"; 83 groups = "ssp0_a_1";
84 }; 84 };
85 hrefprev60_cfg1 { 85 hrefprev60_cfg1 {
86 ste,pins = "GPIO145_C13"; /* RXD */ 86 pins = "GPIO145_C13"; /* RXD */
87 ste,config = <&in_pd>; 87 ste,config = <&in_pd>;
88 }; 88 };
89 89
@@ -97,7 +97,7 @@
97 groups = "mc0dat31dir_a_1"; 97 groups = "mc0dat31dir_a_1";
98 }; 98 };
99 hrefprev60_cfg1 { 99 hrefprev60_cfg1 {
100 ste,pins = "GPIO21_AB3"; /* DAT31DIR */ 100 pins = "GPIO21_AB3"; /* DAT31DIR */
101 ste,config = <&out_hi>; 101 ste,config = <&out_hi>;
102 }; 102 };
103 103
@@ -106,7 +106,7 @@
106 tc35892 { 106 tc35892 {
107 tc35892_hrefprev60_mode: tc35892_hrefprev60 { 107 tc35892_hrefprev60_mode: tc35892_hrefprev60 {
108 hrefprev60_cfg { 108 hrefprev60_cfg {
109 ste,pins = "GPIO217_AH12"; 109 pins = "GPIO217_AH12";
110 ste,config = <&gpio_in_pu>; 110 ste,config = <&gpio_in_pu>;
111 }; 111 };
112 }; 112 };
@@ -118,7 +118,7 @@
118 groups = "ipgpio0_c_1", "ipgpio1_c_1"; 118 groups = "ipgpio0_c_1", "ipgpio1_c_1";
119 }; 119 };
120 hrefprev60_cfg1 { 120 hrefprev60_cfg1 {
121 ste,pins = "GPIO6_AF6", "GPIO7_AG5"; 121 pins = "GPIO6_AF6", "GPIO7_AG5";
122 ste,config = <&in_pu>; 122 ste,config = <&in_pu>;
123 }; 123 };
124 }; 124 };
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 2b4104ef07de..a4bc9e77d640 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -49,7 +49,7 @@
49 /* SD card detect GPIO pin, extend default state */ 49 /* SD card detect GPIO pin, extend default state */
50 sdi0_default_mode: sdi0_default { 50 sdi0_default_mode: sdi0_default {
51 default_hrefv60_cfg1 { 51 default_hrefv60_cfg1 {
52 ste,pins = "GPIO95_E8"; 52 pins = "GPIO95_E8";
53 ste,config = <&gpio_in_pu>; 53 ste,config = <&gpio_in_pu>;
54 }; 54 };
55 }; 55 };
@@ -68,15 +68,15 @@
68 groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; 68 groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
69 }; 69 };
70 hrefv60_cfg1 { 70 hrefv60_cfg1 {
71 ste,pins = "GPIO6_AF6", "GPIO7_AG5"; 71 pins = "GPIO6_AF6", "GPIO7_AG5";
72 ste,config = <&in_pu>; 72 ste,config = <&in_pu>;
73 }; 73 };
74 hrefv60_cfg2 { 74 hrefv60_cfg2 {
75 ste,pins = "GPIO21_AB3"; 75 pins = "GPIO21_AB3";
76 ste,config = <&gpio_out_lo>; 76 ste,config = <&gpio_out_lo>;
77 }; 77 };
78 hrefv60_cfg3 { 78 hrefv60_cfg3 {
79 ste,pins = "GPIO64_F3"; 79 pins = "GPIO64_F3";
80 ste,config = <&out_lo>; 80 ste,config = <&out_lo>;
81 }; 81 };
82 }; 82 };
@@ -89,7 +89,7 @@
89 */ 89 */
90 etm_hrefv60_mode: etm_hrefv60 { 90 etm_hrefv60_mode: etm_hrefv60 {
91 hrefv60_cfg1 { 91 hrefv60_cfg1 {
92 ste,pins = 92 pins =
93 "GPIO70_G5", 93 "GPIO70_G5",
94 "GPIO71_G4", 94 "GPIO71_G4",
95 "GPIO72_H4", 95 "GPIO72_H4",
@@ -103,11 +103,11 @@
103 nahj_hrefv60_mode: nahj_hrefv60 { 103 nahj_hrefv60_mode: nahj_hrefv60 {
104 /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ 104 /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
105 hrefv60_cfg1 { 105 hrefv60_cfg1 {
106 ste,pins = "GPIO76_J2"; 106 pins = "GPIO76_J2";
107 ste,config = <&gpio_out_lo>; 107 ste,config = <&gpio_out_lo>;
108 }; 108 };
109 hrefv60_cfg2 { 109 hrefv60_cfg2 {
110 ste,pins = "GPIO216_AG12"; 110 pins = "GPIO216_AG12";
111 ste,config = <&gpio_out_hi>; 111 ste,config = <&gpio_out_hi>;
112 }; 112 };
113 }; 113 };
@@ -116,13 +116,13 @@
116 nfc_hrefv60_mode: nfc_hrefv60 { 116 nfc_hrefv60_mode: nfc_hrefv60 {
117 /* NFC ENA and RESET to low, pulldown IRQ line */ 117 /* NFC ENA and RESET to low, pulldown IRQ line */
118 hrefv60_cfg1 { 118 hrefv60_cfg1 {
119 ste,pins = 119 pins =
120 "GPIO77_H1", /* NFC_ENA */ 120 "GPIO77_H1", /* NFC_ENA */
121 "GPIO142_C11"; /* NFC_RESET */ 121 "GPIO142_C11"; /* NFC_RESET */
122 ste,config = <&gpio_out_lo>; 122 ste,config = <&gpio_out_lo>;
123 }; 123 };
124 hrefv60_cfg2 { 124 hrefv60_cfg2 {
125 ste,pins = "GPIO144_B13"; /* NFC_IRQ */ 125 pins = "GPIO144_B13"; /* NFC_IRQ */
126 ste,config = <&gpio_in_pd>; 126 ste,config = <&gpio_in_pd>;
127 }; 127 };
128 }; 128 };
@@ -130,11 +130,11 @@
130 force { 130 force {
131 force_hrefv60_mode: force_hrefv60 { 131 force_hrefv60_mode: force_hrefv60 {
132 hrefv60_cfg1 { 132 hrefv60_cfg1 {
133 ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ 133 pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
134 ste,config = <&gpio_in_pu>; 134 ste,config = <&gpio_in_pu>;
135 }; 135 };
136 hrefv60_cfg2 { 136 hrefv60_cfg2 {
137 ste,pins = 137 pins =
138 "GPIO92_D6", /* FORCE_SENSING_RST */ 138 "GPIO92_D6", /* FORCE_SENSING_RST */
139 "GPIO97_D9"; /* FORCE_SENSING_WU */ 139 "GPIO97_D9"; /* FORCE_SENSING_WU */
140 ste,config = <&gpio_out_lo>; 140 ste,config = <&gpio_out_lo>;
@@ -144,7 +144,7 @@
144 dipro { 144 dipro {
145 dipro_hrefv60_mode: dipro_hrefv60 { 145 dipro_hrefv60_mode: dipro_hrefv60 {
146 hrefv60_cfg1 { 146 hrefv60_cfg1 {
147 ste,pins = "GPIO139_C9"; /* DIPRO_INT */ 147 pins = "GPIO139_C9"; /* DIPRO_INT */
148 ste,config = <&gpio_in_pu>; 148 ste,config = <&gpio_in_pu>;
149 }; 149 };
150 }; 150 };
@@ -153,7 +153,7 @@
153 vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { 153 vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
154 /* Audio Amplifier HF enable GPIO */ 154 /* Audio Amplifier HF enable GPIO */
155 hrefv60_cfg1 { 155 hrefv60_cfg1 {
156 ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ 156 pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
157 ste,config = <&gpio_out_hi>; 157 ste,config = <&gpio_out_hi>;
158 }; 158 };
159 }; 159 };
@@ -165,7 +165,7 @@
165 * pull low to reset state 165 * pull low to reset state
166 */ 166 */
167 hrefv60_cfg1 { 167 hrefv60_cfg1 {
168 ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ 168 pins = "GPIO171_D23"; /* GBF_ENA_RESET */
169 ste,config = <&gpio_out_lo>; 169 ste,config = <&gpio_out_lo>;
170 }; 170 };
171 }; 171 };
@@ -174,7 +174,7 @@
174 hdtv_hrefv60_mode: hdtv_hrefv60 { 174 hdtv_hrefv60_mode: hdtv_hrefv60 {
175 /* MSP : HDTV INTERFACE GPIO line */ 175 /* MSP : HDTV INTERFACE GPIO line */
176 hrefv60_cfg1 { 176 hrefv60_cfg1 {
177 ste,pins = "GPIO192_AJ27"; 177 pins = "GPIO192_AJ27";
178 ste,config = <&gpio_in_pd>; 178 ste,config = <&gpio_in_pd>;
179 }; 179 };
180 }; 180 };
@@ -187,11 +187,11 @@
187 * reset signals low. 187 * reset signals low.
188 */ 188 */
189 hrefv60_cfg1 { 189 hrefv60_cfg1 {
190 ste,pins = "GPIO143_D12", "GPIO146_D13"; 190 pins = "GPIO143_D12", "GPIO146_D13";
191 ste,config = <&gpio_out_lo>; 191 ste,config = <&gpio_out_lo>;
192 }; 192 };
193 hrefv60_cfg2 { 193 hrefv60_cfg2 {
194 ste,pins = "GPIO67_G2"; 194 pins = "GPIO67_G2";
195 ste,config = <&gpio_in_pu>; 195 ste,config = <&gpio_in_pu>;
196 }; 196 };
197 }; 197 };
@@ -204,11 +204,11 @@
204 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) 204 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
205 */ 205 */
206 hrefv60_cfg1 { 206 hrefv60_cfg1 {
207 ste,pins ="GPIO65_F1"; 207 pins ="GPIO65_F1";
208 ste,config = <&gpio_out_hi>; 208 ste,config = <&gpio_out_hi>;
209 }; 209 };
210 hrefv60_cfg2 { 210 hrefv60_cfg2 {
211 ste,pins ="GPIO66_G3"; 211 pins ="GPIO66_G3";
212 ste,config = <&gpio_out_lo>; 212 ste,config = <&gpio_out_lo>;
213 }; 213 };
214 }; 214 };
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 90d8b6c7a205..cc81ae7450a9 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -37,12 +37,12 @@
37 cd_default_mode: cd_default { 37 cd_default_mode: cd_default {
38 cd_default_cfg1 { 38 cd_default_cfg1 {
39 /* CD input GPIO */ 39 /* CD input GPIO */
40 ste,pins = "GPIO111_H21"; 40 pins = "GPIO111_H21";
41 ste,input = <0>; 41 ste,input = <0>;
42 }; 42 };
43 cd_default_cfg2 { 43 cd_default_cfg2 {
44 /* CD GPIO biasing */ 44 /* CD GPIO biasing */
45 ste,pins = "GPIO112_J21"; 45 pins = "GPIO112_J21";
46 ste,output = <0>; 46 ste,output = <0>;
47 }; 47 };
48 }; 48 };
@@ -50,7 +50,7 @@
50 user-led { 50 user-led {
51 user_led_default_mode: user_led_default { 51 user_led_default_mode: user_led_default {
52 user_led_default_cfg { 52 user_led_default_cfg {
53 ste,pins = "GPIO2_C5"; 53 pins = "GPIO2_C5";
54 ste,output = <1>; 54 ste,output = <1>;
55 }; 55 };
56 }; 56 };
@@ -58,7 +58,7 @@
58 user-button { 58 user-button {
59 user_button_default_mode: user_button_default { 59 user_button_default_mode: user_button_default {
60 user_button_default_cfg { 60 user_button_default_cfg {
61 ste,pins = "GPIO3_A4"; 61 pins = "GPIO3_A4";
62 ste,input = <0>; 62 ste,input = <0>;
63 }; 63 };
64 }; 64 };
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 7cedb5aba9a9..c8b4a93180f8 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -123,18 +123,18 @@
123 mmcsd_default_mode: mmcsd_default { 123 mmcsd_default_mode: mmcsd_default {
124 mmcsd_default_cfg1 { 124 mmcsd_default_cfg1 {
125 /* MCCLK */ 125 /* MCCLK */
126 ste,pins = "GPIO8_B10"; 126 pins = "GPIO8_B10";
127 ste,output = <0>; 127 ste,output = <0>;
128 }; 128 };
129 mmcsd_default_cfg2 { 129 mmcsd_default_cfg2 {
130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ 130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
131 ste,pins = "GPIO10_C11", "GPIO15_A12", 131 pins = "GPIO10_C11", "GPIO15_A12",
132 "GPIO16_C13"; 132 "GPIO16_C13";
133 ste,output = <1>; 133 ste,output = <1>;
134 }; 134 };
135 mmcsd_default_cfg3 { 135 mmcsd_default_cfg3 {
136 /* MCCMD, MCDAT3-0, MCMSFBCLK */ 136 /* MCCMD, MCDAT3-0, MCMSFBCLK */
137 ste,pins = "GPIO9_A10", "GPIO11_B11", 137 pins = "GPIO9_A10", "GPIO11_B11",
138 "GPIO12_A11", "GPIO13_C12", 138 "GPIO12_A11", "GPIO13_C12",
139 "GPIO14_B12", "GPIO24_C15"; 139 "GPIO14_B12", "GPIO24_C15";
140 ste,input = <1>; 140 ste,input = <1>;
@@ -150,7 +150,7 @@
150 }; 150 };
151 i2c0_default_mode: i2c0_default { 151 i2c0_default_mode: i2c0_default {
152 i2c0_default_cfg { 152 i2c0_default_cfg {
153 ste,pins = "GPIO62_D3", "GPIO63_D2"; 153 pins = "GPIO62_D3", "GPIO63_D2";
154 ste,input = <0>; 154 ste,input = <0>;
155 }; 155 };
156 }; 156 };
@@ -164,7 +164,7 @@
164 }; 164 };
165 i2c1_default_mode: i2c1_default { 165 i2c1_default_mode: i2c1_default {
166 i2c1_default_cfg { 166 i2c1_default_cfg {
167 ste,pins = "GPIO53_L4", "GPIO54_L3"; 167 pins = "GPIO53_L4", "GPIO54_L3";
168 ste,input = <0>; 168 ste,input = <0>;
169 }; 169 };
170 }; 170 };
@@ -172,7 +172,7 @@
172 i2c2 { 172 i2c2 {
173 i2c2_default_mode: i2c2_default { 173 i2c2_default_mode: i2c2_default {
174 i2c2_default_cfg { 174 i2c2_default_cfg {
175 ste,pins = "GPIO73_C21", "GPIO74_C20"; 175 pins = "GPIO73_C21", "GPIO74_C20";
176 ste,input = <0>; 176 ste,input = <0>;
177 }; 177 };
178 }; 178 };
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index d43f8b19e7dd..206826a855c0 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -409,12 +409,12 @@
409 }; 409 };
410 /* LAN IRQ pin */ 410 /* LAN IRQ pin */
411 snowball_cfg1 { 411 snowball_cfg1 {
412 ste,pins = "GPIO140_B11"; 412 pins = "GPIO140_B11";
413 ste,config = <&in_nopull>; 413 ste,config = <&in_nopull>;
414 }; 414 };
415 /* LAN reset pin */ 415 /* LAN reset pin */
416 snowball_cfg2 { 416 snowball_cfg2 {
417 ste,pins = "GPIO141_C12"; 417 pins = "GPIO141_C12";
418 ste,config = <&gpio_out_hi>; 418 ste,config = <&gpio_out_hi>;
419 }; 419 };
420 420
@@ -427,7 +427,7 @@
427 groups = "mc0dat31dir_a_1"; 427 groups = "mc0dat31dir_a_1";
428 }; 428 };
429 snowball_cfg1 { 429 snowball_cfg1 {
430 ste,pins = "GPIO21_AB3"; /* DAT31DIR */ 430 pins = "GPIO21_AB3"; /* DAT31DIR */
431 ste,config = <&out_hi>; 431 ste,config = <&out_hi>;
432 }; 432 };
433 433
@@ -440,15 +440,15 @@
440 groups = "ssp0_a_1"; 440 groups = "ssp0_a_1";
441 }; 441 };
442 snowball_cfg1 { 442 snowball_cfg1 {
443 ste,pins = "GPIO144_B13"; /* FRM */ 443 pins = "GPIO144_B13"; /* FRM */
444 ste,config = <&gpio_out_hi>; 444 ste,config = <&gpio_out_hi>;
445 }; 445 };
446 snowball_cfg2 { 446 snowball_cfg2 {
447 ste,pins = "GPIO145_C13"; /* RXD */ 447 pins = "GPIO145_C13"; /* RXD */
448 ste,config = <&in_pd>; 448 ste,config = <&in_pd>;
449 }; 449 };
450 snowball_cfg3 { 450 snowball_cfg3 {
451 ste,pins = 451 pins =
452 "GPIO146_D13", /* TXD */ 452 "GPIO146_D13", /* TXD */
453 "GPIO143_D12"; /* CLK */ 453 "GPIO143_D12"; /* CLK */
454 ste,config = <&out_lo>; 454 ste,config = <&out_lo>;
@@ -459,7 +459,7 @@
459 gpio_led { 459 gpio_led {
460 gpioled_snowball_mode: gpioled_default { 460 gpioled_snowball_mode: gpioled_default {
461 snowball_cfg1 { 461 snowball_cfg1 {
462 ste,pins = "GPIO142_C11"; 462 pins = "GPIO142_C11";
463 ste,config = <&gpio_out_hi>; 463 ste,config = <&gpio_out_hi>;
464 }; 464 };
465 465
@@ -469,7 +469,7 @@
469 accel_snowball_mode: accel_snowball { 469 accel_snowball_mode: accel_snowball {
470 /* Accelerometer lines */ 470 /* Accelerometer lines */
471 snowball_cfg1 { 471 snowball_cfg1 {
472 ste,pins = 472 pins =
473 "GPIO163_C20", /* ACCEL_IRQ1 */ 473 "GPIO163_C20", /* ACCEL_IRQ1 */
474 "GPIO164_B21"; /* ACCEL_IRQ2 */ 474 "GPIO164_B21"; /* ACCEL_IRQ2 */
475 ste,config = <&gpio_in_pu>; 475 ste,config = <&gpio_in_pu>;
@@ -479,7 +479,7 @@
479 magnetometer { 479 magnetometer {
480 magneto_snowball_mode: magneto_snowball { 480 magneto_snowball_mode: magneto_snowball {
481 snowball_cfg1 { 481 snowball_cfg1 {
482 ste,pins = "GPIO165_C21"; /* MAG_DRDY */ 482 pins = "GPIO165_C21"; /* MAG_DRDY */
483 ste,config = <&gpio_in_pu>; 483 ste,config = <&gpio_in_pu>;
484 }; 484 };
485 }; 485 };
@@ -491,7 +491,7 @@
491 * pull low to reset state 491 * pull low to reset state
492 */ 492 */
493 snowball_cfg1 { 493 snowball_cfg1 {
494 ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ 494 pins = "GPIO171_D23"; /* GBF_ENA_RESET */
495 ste,config = <&gpio_out_lo>; 495 ste,config = <&gpio_out_lo>;
496 }; 496 };
497 }; 497 };
@@ -503,13 +503,13 @@
503 * These are plain GPIO pins used by WLAN 503 * These are plain GPIO pins used by WLAN
504 */ 504 */
505 snowball_cfg1 { 505 snowball_cfg1 {
506 ste,pins = 506 pins =
507 "GPIO161_D21", /* WLAN_PMU_EN */ 507 "GPIO161_D21", /* WLAN_PMU_EN */
508 "GPIO215_AH13"; /* WLAN_ENA */ 508 "GPIO215_AH13"; /* WLAN_ENA */
509 ste,config = <&gpio_out_lo>; 509 ste,config = <&gpio_out_lo>;
510 }; 510 };
511 snowball_cfg2 { 511 snowball_cfg2 {
512 ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */ 512 pins = "GPIO216_AG12"; /* WLAN_IRQ */
513 ste,config = <&gpio_in_pu>; 513 ste,config = <&gpio_in_pu>;
514 }; 514 };
515 }; 515 };
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index dec72f2e6a2b..ad99ba886e50 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -1552,7 +1552,7 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1552 const char *gpio_name; 1552 const char *gpio_name;
1553 const char *pin; 1553 const char *pin;
1554 1554
1555 ret = of_property_count_strings(np, "ste,pins"); 1555 ret = of_property_count_strings(np, "pins");
1556 if (ret < 0) 1556 if (ret < 0)
1557 goto exit; 1557 goto exit;
1558 ret = pinctrl_utils_reserve_map(pctldev, map, 1558 ret = pinctrl_utils_reserve_map(pctldev, map,
@@ -1561,7 +1561,7 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1561 if (ret < 0) 1561 if (ret < 0)
1562 goto exit; 1562 goto exit;
1563 1563
1564 of_property_for_each_string(np, "ste,pins", prop, pin) { 1564 of_property_for_each_string(np, "pins", prop, pin) {
1565 gpio_name = nmk_find_pin_name(pctldev, pin); 1565 gpio_name = nmk_find_pin_name(pctldev, pin);
1566 1566
1567 ret = nmk_dt_add_map_configs(map, reserved_maps, 1567 ret = nmk_dt_add_map_configs(map, reserved_maps,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 01:13:19 -0500