diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-02 17:23:01 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-02 17:23:01 -0400 |
commit | ee1a8d402e7e204d57fb108aa40003b6d1633036 (patch) | |
tree | 3abf4be63d11bbbd04c89bd668a17533f942b911 /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
parent | 40e71e7015ab85c8606f50736525220948a3b24b (diff) | |
parent | 9686bb66a4c50e43ffee903a9fc62237ee2de1e6 (diff) |
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann:
"These changes from 30 individual branches for the most part update
device tree files, but there are also a few source code changes that
have crept in this time, usually in order to atomically move over a
driver from using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
ARM: at91: dt: rm9200ek: add spi support
ARM: at91: dt: rm9200: add spi support
ARM: at91/DT: at91sam9n12: add SPI DMA client infos
ARM: at91/DT: sama5d3: add SPI DMA client infos
ARM: at91/DT: fix SPI compatibility string
ARM: Kirkwood: Fix the internal register ranges translation
ARM: dts: bcm281xx: change comment to C89 style
ARM: mmc: bcm281xx SDHCI driver (dt mods)
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
ARM: dts: omap4-panda: Fix DVI EDID reads
ARM: dts: omap4-panda: Add USB Host support
arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: dts: AM43x EPOS EVM support
ARM: dts: OMAP5: Add bandgap DT entry
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
...
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 4d237cffcc41..e994011220e7 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |||
@@ -16,6 +16,22 @@ | |||
16 | }; | 16 | }; |
17 | }; | 17 | }; |
18 | 18 | ||
19 | &ecspi1 { | ||
20 | fsl,spi-num-chipselects = <1>; | ||
21 | cs-gpios = <&gpio3 19 0>; | ||
22 | pinctrl-names = "default"; | ||
23 | pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; | ||
24 | status = "disabled"; /* pin conflict with WEIM NOR */ | ||
25 | |||
26 | flash: m25p80@0 { | ||
27 | #address-cells = <1>; | ||
28 | #size-cells = <1>; | ||
29 | compatible = "st,m25p32"; | ||
30 | spi-max-frequency = <20000000>; | ||
31 | reg = <0>; | ||
32 | }; | ||
33 | }; | ||
34 | |||
19 | &fec { | 35 | &fec { |
20 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
21 | pinctrl-0 = <&pinctrl_enet_2>; | 37 | pinctrl-0 = <&pinctrl_enet_2>; |
@@ -23,6 +39,12 @@ | |||
23 | status = "okay"; | 39 | status = "okay"; |
24 | }; | 40 | }; |
25 | 41 | ||
42 | &gpmi { | ||
43 | pinctrl-names = "default"; | ||
44 | pinctrl-0 = <&pinctrl_gpmi_nand_1>; | ||
45 | status = "okay"; | ||
46 | }; | ||
47 | |||
26 | &uart4 { | 48 | &uart4 { |
27 | pinctrl-names = "default"; | 49 | pinctrl-names = "default"; |
28 | pinctrl-0 = <&pinctrl_uart4_1>; | 50 | pinctrl-0 = <&pinctrl_uart4_1>; |
@@ -36,3 +58,22 @@ | |||
36 | wp-gpios = <&gpio1 13 0>; | 58 | wp-gpios = <&gpio1 13 0>; |
37 | status = "okay"; | 59 | status = "okay"; |
38 | }; | 60 | }; |
61 | |||
62 | &weim { | ||
63 | pinctrl-names = "default"; | ||
64 | pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; | ||
65 | #address-cells = <2>; | ||
66 | #size-cells = <1>; | ||
67 | ranges = <0 0 0x08000000 0x08000000>; | ||
68 | status = "disabled"; /* pin conflict with SPI NOR */ | ||
69 | |||
70 | nor@0,0 { | ||
71 | compatible = "cfi-flash"; | ||
72 | reg = <0 0 0x02000000>; | ||
73 | #address-cells = <1>; | ||
74 | #size-cells = <1>; | ||
75 | bank-width = <2>; | ||
76 | fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 | ||
77 | 0x0000c000 0x1404a38e 0x00000000>; | ||
78 | }; | ||
79 | }; | ||