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authorIngo Molnar <mingo@kernel.org>2014-04-14 10:44:42 -0400
committerIngo Molnar <mingo@kernel.org>2014-04-14 10:44:42 -0400
commit740c699a8d316c8bf8593f19e2ca47795e690622 (patch)
treea78886955770a477945c5d84e06b2e7678733b54 /arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
parente69af4657e7764d03ad555f0b583d9c4217bcefa (diff)
parentc9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)
Merge tag 'v3.15-rc1' into perf/urgent
Pick up the latest fixes. Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi')
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi317
1 files changed, 317 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..cefaa6994623
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -0,0 +1,317 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx27.dtsi"
14
15/ {
16 model = "Phytec pcm038";
17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19 memory {
20 reg = <0xa0000000 0x08000000>;
21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_3v3: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "3V3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 };
35
36 reg_5v0: regulator@1 {
37 compatible = "regulator-fixed";
38 reg = <1>;
39 regulator-name = "5V0";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 };
43 };
44};
45
46&audmux {
47 status = "okay";
48
49 /* SSI0 <=> PINS_4 (MC13783 Audio) */
50 ssi0 {
51 fsl,audmux-port = <0>;
52 fsl,port-config = <0xcb205000>;
53 };
54
55 pins4 {
56 fsl,audmux-port = <2>;
57 fsl,port-config = <0x00001000>;
58 };
59};
60
61&cspi1 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_cspi1>;
64 fsl,spi-num-chipselects = <1>;
65 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
66 status = "okay";
67
68 pmic: mc13783@0 {
69 #address-cells = <1>;
70 #size-cells = <0>;
71 compatible = "fsl,mc13783";
72 reg = <0>;
73 spi-cs-high;
74 spi-max-frequency = <20000000>;
75 interrupt-parent = <&gpio2>;
76 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
77 fsl,mc13xxx-uses-adc;
78 fsl,mc13xxx-uses-rtc;
79
80 pmicleds: leds {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
84 };
85
86 regulators {
87 /* SW1A and SW1B joined operation */
88 sw1_reg: sw1a {
89 regulator-min-microvolt = <1200000>;
90 regulator-max-microvolt = <1520000>;
91 regulator-always-on;
92 regulator-boot-on;
93 };
94
95 /* SW2A and SW2B joined operation */
96 sw2_reg: sw2a {
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <1800000>;
99 regulator-always-on;
100 regulator-boot-on;
101 };
102
103 sw3_reg: sw3 {
104 regulator-min-microvolt = <5000000>;
105 regulator-max-microvolt = <5000000>;
106 regulator-always-on;
107 regulator-boot-on;
108 };
109
110 vaudio_reg: vaudio {
111 regulator-always-on;
112 regulator-boot-on;
113 };
114
115 violo_reg: violo {
116 regulator-min-microvolt = <1800000>;
117 regulator-max-microvolt = <1800000>;
118 regulator-always-on;
119 regulator-boot-on;
120 };
121
122 viohi_reg: viohi {
123 regulator-always-on;
124 regulator-boot-on;
125 };
126
127 vgen_reg: vgen {
128 regulator-min-microvolt = <1500000>;
129 regulator-max-microvolt = <1500000>;
130 regulator-always-on;
131 regulator-boot-on;
132 };
133
134 vcam_reg: vcam {
135 regulator-min-microvolt = <2800000>;
136 regulator-max-microvolt = <2800000>;
137 };
138
139 vrf1_reg: vrf1 {
140 regulator-min-microvolt = <2775000>;
141 regulator-max-microvolt = <2775000>;
142 regulator-always-on;
143 regulator-boot-on;
144 };
145
146 vrf2_reg: vrf2 {
147 regulator-min-microvolt = <2775000>;
148 regulator-max-microvolt = <2775000>;
149 regulator-always-on;
150 regulator-boot-on;
151 };
152
153 vmmc1_reg: vmmc1 {
154 regulator-min-microvolt = <1600000>;
155 regulator-max-microvolt = <3000000>;
156 };
157
158 gpo1_reg: gpo1 { };
159
160 pwgt1spi_reg: pwgt1spi {
161 regulator-always-on;
162 };
163 };
164 };
165};
166
167&fec {
168 phy-mode = "mii";
169 phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
170 phy-supply = <&reg_3v3>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_fec1>;
173 status = "okay";
174};
175
176&i2c2 {
177 clock-frequency = <400000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2>;
180 status = "okay";
181
182 at24@52 {
183 compatible = "at,24c32";
184 pagesize = <32>;
185 reg = <0x52>;
186 };
187
188 pcf8563@51 {
189 compatible = "nxp,pcf8563";
190 reg = <0x51>;
191 };
192
193 lm75@4a {
194 compatible = "national,lm75";
195 reg = <0x4a>;
196 };
197};
198
199&iomuxc {
200 imx27_phycore_som {
201 pinctrl_cspi1: cspi1grp {
202 fsl,pins = <
203 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
204 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
205 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
206 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
207 MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
208 >;
209 };
210
211 pinctrl_fec1: fec1grp {
212 fsl,pins = <
213 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
214 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
215 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
216 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
217 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
218 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
219 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
220 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
221 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
222 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
223 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
224 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
225 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
226 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
227 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
228 MX27_PAD_ATA_DATA13__FEC_COL 0x0
229 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
230 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
231 MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
232 >;
233 };
234
235 pinctrl_i2c2: i2c2grp {
236 fsl,pins = <
237 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
238 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
239 >;
240 };
241
242 pinctrl_nfc: nfcgrp {
243 fsl,pins = <
244 MX27_PAD_NFRB__NFRB 0x0
245 MX27_PAD_NFCLE__NFCLE 0x0
246 MX27_PAD_NFWP_B__NFWP_B 0x0
247 MX27_PAD_NFCE_B__NFCE_B 0x0
248 MX27_PAD_NFALE__NFALE 0x0
249 MX27_PAD_NFRE_B__NFRE_B 0x0
250 MX27_PAD_NFWE_B__NFWE_B 0x0
251 >;
252 };
253
254 pinctrl_usbotg: usbotggrp {
255 fsl,pins = <
256 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
257 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
258 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
259 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
260 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
261 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
262 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
263 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
264 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
265 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
266 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
267 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
268 >;
269 };
270 };
271};
272
273&nfc {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_nfc>;
276 nand-bus-width = <8>;
277 nand-ecc-mode = "hw";
278 nand-on-flash-bbt;
279 status = "okay";
280};
281
282&usbotg {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_usbotg>;
285 dr_mode = "otg";
286 phy_type = "ulpi";
287 vbus-supply = <&sw3_reg>;
288 status = "okay";
289};
290
291&usbphy0 {
292 vcc-supply = <&sw3_reg>;
293};
294
295&weim {
296 status = "okay";
297
298 nor: nor@c0000000 {
299 compatible = "cfi-flash";
300 reg = <0 0x00000000 0x02000000>;
301 bank-width = <2>;
302 linux,mtd-name = "physmap-flash.0";
303 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
304 #address-cells = <1>;
305 #size-cells = <1>;
306 };
307
308 sram: sram@c8000000 {
309 compatible = "mtd-ram";
310 reg = <1 0x00000000 0x00800000>;
311 bank-width = <2>;
312 linux,mtd-name = "mtd-ram.0";
313 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
314 #address-cells = <1>;
315 #size-cells = <1>;
316 };
317};
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