Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, this is the largest branch, though this time a little under
  half of the total changes with 307 individual non-merge changesets.

  The largest changes are the addition of new machines, in particular
  the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support
  for the old i.MX1 platform.

  Other changes include
   - at91: various sam9 and sama5 updates
   - exynos: much extended Peach Pi/Pit (Chromebook 2) support
   - keystone: new peripherals
   - meson: added DT for meson6 SoC
   - mvebu: new device support for Armada 370/375
   - qcom: improved support for IPQ8064 and MSM8x60
   - rockchip: much improved support for rk3288
   - shmobile: lots of updates all over the place
   - sunxi: dts license change
   - sunxi: more a23 device support
   - vexpress: CLCD DT description"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits)
  ARM: DTS: meson: update DTSI to add watchdog node
  ARM: dts: keystone-k2l: fix mdio io start address
  ARM: dts: keystone-k2e: fix mdio io start address
  ARM: dts: keystone-k2e: update usb1 node for dma properties
  ARM: dts: keystone: fix io range for usb_phy0
  Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt"
  Revert "ARM: dts: hix5hd2: add wdg node"
  ARM: dts: add rk3288 i2s controller
  ARM: vexpress: Add CLCD Device Tree properties
  ARM: bcm2835: add I2S pinctrl to device tree
  ARM: meson: documentation: add bindings documentation
  ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
  ARM: dts: mt6589: Change compatible string for GIC
  ARM: dts: mediatek: Add compatible property for aquaris5
  ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk
  ARM: dts: mt6589: Fix typo in GIC unit address
  ARM: dts: Build dtb for Mediatek board
  ARM: dts: keystone: fix bindings for pcie and usb clock nodes
  ARM: dts: keystone: k2l: Fix chip selects for SPI devices
  ARM: dts: keystone: add dsp gpio controllers nodes
  ...

1 files changed, 152 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
new file mode 100644
index 000000000000..af4eee5794aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx1.dtsi"
+
+/ {
+        model = "Freescale MX1 ADS";
+        compatible = "fsl,imx1ads", "fsl,imx1";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory {
+                reg = <0x08000000 0x04000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32 {
+                        compatible = "fsl,imx-clk32", "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32000>;
+                };
+        };
+};
+
+&cspi1 {
+        pinctrl-0 = <&pinctrl_cspi1>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&i2c {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c>;
+        status = "okay";
+
+        extgpio0: pcf8575@22 {
+                compatible = "nxp,pcf8575";
+                reg = <0x22>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        extgpio1: pcf8575@24 {
+                compatible = "nxp,pcf8575";
+                reg = <0x24>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim>;
+        status = "okay";
+
+        nor: nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0x00000000 0x02000000>;
+                bank-width = <4>;
+                fsl,weim-cs-timing = <0x00003e00 0x00000801>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&iomuxc {
+        imx1-ads {
+                pinctrl_cspi1: cspi1grp {
+                        fsl,pins = <
+                                MX1_PAD_SPI1_MISO__SPI1_MISO    0x0
+                                MX1_PAD_SPI1_MOSI__SPI1_MOSI    0x0
+                                MX1_PAD_SPI1_RDY__SPI1_RDY      0x0
+                                MX1_PAD_SPI1_SCLK__SPI1_SCLK    0x0
+                                MX1_PAD_SPI1_SS__GPIO3_15       0x0
+                        >;
+                };
+
+                pinctrl_i2c: i2cgrp {
+                        fsl,pins = <
+                                MX1_PAD_I2C_SCL__I2C_SCL        0x0
+                                MX1_PAD_I2C_SDA__I2C_SDA        0x0
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX1_PAD_UART1_TXD__UART1_TXD    0x0
+                                MX1_PAD_UART1_RXD__UART1_RXD    0x0
+                                MX1_PAD_UART1_CTS__UART1_CTS    0x0
+                                MX1_PAD_UART1_RTS__UART1_RTS    0x0
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX1_PAD_UART2_TXD__UART2_TXD    0x0
+                                MX1_PAD_UART2_RXD__UART2_RXD    0x0
+                                MX1_PAD_UART2_CTS__UART2_CTS    0x0
+                                MX1_PAD_UART2_RTS__UART2_RTS    0x0
+                        >;
+                };
+
+                pinctrl_weim: weimgrp {
+                        fsl,pins = <
+                                MX1_PAD_A0__A0                  0x0
+                                MX1_PAD_A16__A16                0x0
+                                MX1_PAD_A17__A17                0x0
+                                MX1_PAD_A18__A18                0x0
+                                MX1_PAD_A19__A19                0x0
+                                MX1_PAD_A20__A20                0x0
+                                MX1_PAD_A21__A21                0x0
+                                MX1_PAD_A22__A22                0x0
+                                MX1_PAD_A23__A23                0x0
+                                MX1_PAD_A24__A24                0x0
+                                MX1_PAD_BCLK__BCLK              0x0
+                                MX1_PAD_CS4__CS4                0x0
+                                MX1_PAD_DTACK__DTACK            0x0
+                                MX1_PAD_ECB__ECB                0x0
+                                MX1_PAD_LBA__LBA                0x0
+                        >;
+                };
+        };
+};