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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-08 17:22:23 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-08 17:22:23 -0400
commiteb785bef684f2b7d03b530efc8e6f199e9777e2f (patch)
treee43c96f5fb5fafe59a680da792d2d182e2270fb2 /arch/arm/boot
parentcf377ad7d42c566356d79049536d9cb37499cb77 (diff)
parentee48874d4aa50d9c4921b44a38dc33110b90638b (diff)
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, this is the largest branch, though this time a little under half of the total changes with 307 individual non-merge changesets. The largest changes are the addition of new machines, in particular the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support for the old i.MX1 platform. Other changes include - at91: various sam9 and sama5 updates - exynos: much extended Peach Pi/Pit (Chromebook 2) support - keystone: new peripherals - meson: added DT for meson6 SoC - mvebu: new device support for Armada 370/375 - qcom: improved support for IPQ8064 and MSM8x60 - rockchip: much improved support for rk3288 - shmobile: lots of updates all over the place - sunxi: dts license change - sunxi: more a23 device support - vexpress: CLCD DT description" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits) ARM: DTS: meson: update DTSI to add watchdog node ARM: dts: keystone-k2l: fix mdio io start address ARM: dts: keystone-k2e: fix mdio io start address ARM: dts: keystone-k2e: update usb1 node for dma properties ARM: dts: keystone: fix io range for usb_phy0 Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt" Revert "ARM: dts: hix5hd2: add wdg node" ARM: dts: add rk3288 i2s controller ARM: vexpress: Add CLCD Device Tree properties ARM: bcm2835: add I2S pinctrl to device tree ARM: meson: documentation: add bindings documentation ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS ARM: dts: mt6589: Change compatible string for GIC ARM: dts: mediatek: Add compatible property for aquaris5 ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk ARM: dts: mt6589: Fix typo in GIC unit address ARM: dts: Build dtb for Mediatek board ARM: dts: keystone: fix bindings for pcie and usb clock nodes ARM: dts: keystone: k2l: Fix chip selects for SPI devices ARM: dts: keystone: add dsp gpio controllers nodes ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile25
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi5
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi4
-rw-r--r--arch/arm/boot/dts/am4372.dtsi8
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn104.dts8
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts47
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi4
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi23
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi6
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi10
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi47
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts8
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi1
-rw-r--r--arch/arm/boot/dts/cros-adc-thermistors.dtsi44
-rw-r--r--arch/arm/boot/dts/da850-evm.dts72
-rw-r--r--arch/arm/boot/dts/da850.dtsi19
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts2
-rw-r--r--arch/arm/boot/dts/dra7.dtsi24
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts120
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi5
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts8
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts8
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts22
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi164
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts18
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts195
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi15
-rw-r--r--arch/arm/boot/dts/exynos5260-xyref5260.dts18
-rw-r--r--arch/arm/boot/dts/exynos5410-smdk5410.dts18
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts16
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts482
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts16
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts472
-rw-r--r--arch/arm/boot/dts/imx1-ads.dts152
-rw-r--r--arch/arm/boot/dts/imx1-apf9328.dts129
-rw-r--r--arch/arm/boot/dts/imx1-pinfunc.h302
-rw-r--r--arch/arm/boot/dts/imx1.dtsi266
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx25-pinfunc.h33
-rw-r--r--arch/arm/boot/dts/imx25.dtsi4
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts17
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts4
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10055.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10056.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10057.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10058.dts4
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts4
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts107
-rw-r--r--arch/arm/boot/dts/imx28.dtsi43
-rw-r--r--arch/arm/boot/dts/imx35.dtsi1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi2
-rw-r--r--arch/arm/boot/dts/imx51.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts2
-rw-r--r--arch/arm/boot/dts/imx53.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6dl-gw552x.dts20
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts203
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts203
-rw-r--r--arch/arm/boot/dts/imx6q-gw552x.dts24
-rw-r--r--arch/arm/boot/dts/imx6q-hummingboard.dts21
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi192
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi314
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi338
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi278
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi267
-rw-r--r--arch/arm/boot/dts/imx6qdl-hummingboard.dtsi200
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi45
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi24
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts104
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi31
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts93
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi7
-rw-r--r--arch/arm/boot/dts/k2e.dtsi13
-rw-r--r--arch/arm/boot/dts/k2hk.dtsi56
-rw-r--r--arch/arm/boot/dts/k2l.dtsi46
-rw-r--r--arch/arm/boot/dts/keystone.dtsi10
-rw-r--r--arch/arm/boot/dts/meson.dtsi110
-rw-r--r--arch/arm/boot/dts/meson6-atv1200.dts66
-rw-r--r--arch/arm/boot/dts/meson6.dtsi78
-rw-r--r--arch/arm/boot/dts/mt6589-aquaris5.dts5
-rw-r--r--arch/arm/boot/dts/mt6589.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts4
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi (renamed from arch/arm/boot/dts/omap3-gta04.dts)150
-rw-r--r--arch/arm/boot/dts/omap3-gta04a3.dts48
-rw-r--r--arch/arm/boot/dts/omap3-gta04a4.dts13
-rw-r--r--arch/arm/boot/dts/omap3-gta04a5.dts17
-rw-r--r--arch/arm/boot/dts/omap3-ha-common.dtsi88
-rw-r--r--arch/arm/boot/dts/omap3-ha-lcd.dts165
-rw-r--r--arch/arm/boot/dts/omap3-ha.dts28
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts5
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts54
-rw-r--r--arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi5
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi337
-rw-r--r--arch/arm/boot/dts/omap3-thunder.dts129
-rw-r--r--arch/arm/boot/dts/omap3.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi8
-rw-r--r--arch/arm/boot/dts/omap5-cm-t54.dts272
-rw-r--r--arch/arm/boot/dts/omap5-sbc-t54.dts8
-rw-r--r--arch/arm/boot/dts/omap5.dtsi37
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi4
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts43
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi183
-rw-r--r--arch/arm/boot/dts/qcom-apq8074-dragonboard.dts21
-rw-r--r--arch/arm/boot/dts/qcom-apq8084-ifc6540.dts23
-rw-r--r--arch/arm/boot/dts/qcom-apq8084-mtp.dts6
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi51
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts85
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi250
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts42
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi93
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts27
-rw-r--r--arch/arm/boot/dts/qcom-msm8960.dtsi87
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi15
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi6
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi16
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts40
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi127
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts35
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts37
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi108
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts47
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi531
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts15
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi67
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts68
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi69
-rw-r--r--arch/arm/boot/dts/rk3288-evb-act8846.dts10
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts132
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi87
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi380
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi109
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi37
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi30
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi4
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts4
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi24
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts7
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi13
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts4
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts9
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi17
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts130
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi17
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi56
-rw-r--r--arch/arm/boot/dts/sun7i-a20-hummingbird.dts236
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts137
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi102
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts41
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi237
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts98
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big.dts1136
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts18
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi100
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi36
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi36
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts31
-rw-r--r--arch/arm/boot/dts/vf610-colibri-eval-v3.dts46
-rw-r--r--arch/arm/boot/dts/vf610-colibri.dtsi (renamed from arch/arm/boot/dts/vf610-colibri.dts)22
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts25
-rw-r--r--arch/arm/boot/dts/vf610.dtsi60
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi14
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts27
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts18
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts12
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts14
193 files changed, 11238 insertions, 1717 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d3e687ecfc95..7c80af906897 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -163,8 +163,11 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
163 kirkwood-ts419-6282.dtb 163 kirkwood-ts419-6282.dtb
164dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 164dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
165dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 165dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
166dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
166dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 167dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
167dtb-$(CONFIG_ARCH_MXC) += \ 168dtb-$(CONFIG_ARCH_MXC) += \
169 imx1-ads.dtb \
170 imx1-apf9328.dtb \
168 imx25-eukrea-mbimxsd25-baseboard.dtb \ 171 imx25-eukrea-mbimxsd25-baseboard.dtb \
169 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ 172 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
170 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ 173 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
@@ -203,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
203 imx6dl-gw52xx.dtb \ 206 imx6dl-gw52xx.dtb \
204 imx6dl-gw53xx.dtb \ 207 imx6dl-gw53xx.dtb \
205 imx6dl-gw54xx.dtb \ 208 imx6dl-gw54xx.dtb \
209 imx6dl-gw552x.dtb \
206 imx6dl-hummingboard.dtb \ 210 imx6dl-hummingboard.dtb \
207 imx6dl-nitrogen6x.dtb \ 211 imx6dl-nitrogen6x.dtb \
208 imx6dl-phytec-pbab01.dtb \ 212 imx6dl-phytec-pbab01.dtb \
@@ -227,6 +231,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
227 imx6q-gw53xx.dtb \ 231 imx6q-gw53xx.dtb \
228 imx6q-gw5400-a.dtb \ 232 imx6q-gw5400-a.dtb \
229 imx6q-gw54xx.dtb \ 233 imx6q-gw54xx.dtb \
234 imx6q-gw552x.dtb \
235 imx6q-hummingboard.dtb \
230 imx6q-nitrogen6x.dtb \ 236 imx6q-nitrogen6x.dtb \
231 imx6q-phytec-pbab01.dtb \ 237 imx6q-phytec-pbab01.dtb \
232 imx6q-rex-pro.dtb \ 238 imx6q-rex-pro.dtb \
@@ -244,7 +250,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
244 imx6q-tx6q-1110.dtb \ 250 imx6q-tx6q-1110.dtb \
245 imx6sl-evk.dtb \ 251 imx6sl-evk.dtb \
246 imx6sx-sdb.dtb \ 252 imx6sx-sdb.dtb \
247 vf610-colibri.dtb \ 253 vf610-colibri-eval-v3.dtb \
248 vf610-cosmic.dtb \ 254 vf610-cosmic.dtb \
249 vf610-twr.dtb 255 vf610-twr.dtb
250dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 256dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@@ -290,7 +296,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
290 omap3-devkit8000.dtb \ 296 omap3-devkit8000.dtb \
291 omap3-evm.dtb \ 297 omap3-evm.dtb \
292 omap3-evm-37xx.dtb \ 298 omap3-evm-37xx.dtb \
293 omap3-gta04.dtb \ 299 omap3-gta04a3.dtb \
300 omap3-gta04a4.dtb \
301 omap3-gta04a5.dtb \
302 omap3-ha.dtb \
303 omap3-ha-lcd.dtb \
294 omap3-igep0020.dtb \ 304 omap3-igep0020.dtb \
295 omap3-igep0030.dtb \ 305 omap3-igep0030.dtb \
296 omap3-ldp.dtb \ 306 omap3-ldp.dtb \
@@ -313,6 +323,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
313 omap3-sbc-t3517.dtb \ 323 omap3-sbc-t3517.dtb \
314 omap3-sbc-t3530.dtb \ 324 omap3-sbc-t3530.dtb \
315 omap3-sbc-t3730.dtb \ 325 omap3-sbc-t3730.dtb \
326 omap3-thunder.dtb \
316 omap3-zoom3.dtb 327 omap3-zoom3.dtb
317dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ 328dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
318 am335x-bone.dtb \ 329 am335x-bone.dtb \
@@ -345,7 +356,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
345dtb-$(CONFIG_ARCH_QCOM) += \ 356dtb-$(CONFIG_ARCH_QCOM) += \
346 qcom-apq8064-ifc6410.dtb \ 357 qcom-apq8064-ifc6410.dtb \
347 qcom-apq8074-dragonboard.dtb \ 358 qcom-apq8074-dragonboard.dtb \
359 qcom-apq8084-ifc6540.dtb \
348 qcom-apq8084-mtp.dtb \ 360 qcom-apq8084-mtp.dtb \
361 qcom-ipq8064-ap148.dtb \
349 qcom-msm8660-surf.dtb \ 362 qcom-msm8660-surf.dtb \
350 qcom-msm8960-cdp.dtb 363 qcom-msm8960-cdp.dtb
351dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 364dtb-$(CONFIG_ARCH_ROCKCHIP) += \
@@ -379,7 +392,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
379 r8a7791-henninger.dtb \ 392 r8a7791-henninger.dtb \
380 r8a7791-koelsch.dtb \ 393 r8a7791-koelsch.dtb \
381 r8a7790-lager.dtb \ 394 r8a7790-lager.dtb \
382 r8a7779-marzen.dtb 395 r8a7779-marzen.dtb \
396 r8a7794-alt.dtb
383dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 397dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
384 socfpga_cyclone5_socdk.dtb \ 398 socfpga_cyclone5_socdk.dtb \
385 socfpga_cyclone5_sockit.dtb \ 399 socfpga_cyclone5_sockit.dtb \
@@ -410,6 +424,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
410dtb-$(CONFIG_MACH_SUN5I) += \ 424dtb-$(CONFIG_MACH_SUN5I) += \
411 sun5i-a10s-olinuxino-micro.dtb \ 425 sun5i-a10s-olinuxino-micro.dtb \
412 sun5i-a10s-r7-tv-dongle.dtb \ 426 sun5i-a10s-r7-tv-dongle.dtb \
427 sun5i-a13-hsg-h702.dtb \
413 sun5i-a13-olinuxino.dtb \ 428 sun5i-a13-olinuxino.dtb \
414 sun5i-a13-olinuxino-micro.dtb 429 sun5i-a13-olinuxino-micro.dtb
415dtb-$(CONFIG_MACH_SUN6I) += \ 430dtb-$(CONFIG_MACH_SUN6I) += \
@@ -420,7 +435,9 @@ dtb-$(CONFIG_MACH_SUN6I) += \
420dtb-$(CONFIG_MACH_SUN7I) += \ 435dtb-$(CONFIG_MACH_SUN7I) += \
421 sun7i-a20-cubieboard2.dtb \ 436 sun7i-a20-cubieboard2.dtb \
422 sun7i-a20-cubietruck.dtb \ 437 sun7i-a20-cubietruck.dtb \
438 sun7i-a20-hummingbird.dtb \
423 sun7i-a20-i12-tvbox.dtb \ 439 sun7i-a20-i12-tvbox.dtb \
440 sun7i-a20-olinuxino-lime.dtb \
424 sun7i-a20-olinuxino-micro.dtb \ 441 sun7i-a20-olinuxino-micro.dtb \
425 sun7i-a20-pcduino3.dtb 442 sun7i-a20-pcduino3.dtb
426dtb-$(CONFIG_MACH_SUN8I) += \ 443dtb-$(CONFIG_MACH_SUN8I) += \
@@ -444,6 +461,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
444 tegra114-roth.dtb \ 461 tegra114-roth.dtb \
445 tegra114-tn7.dtb \ 462 tegra114-tn7.dtb \
446 tegra124-jetson-tk1.dtb \ 463 tegra124-jetson-tk1.dtb \
464 tegra124-nyan-big.dtb \
447 tegra124-venice2.dtb 465 tegra124-venice2.dtb
448dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 466dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
449dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 467dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
@@ -495,6 +513,7 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
495 dove-d2plug.dtb \ 513 dove-d2plug.dtb \
496 dove-d3plug.dtb \ 514 dove-d3plug.dtb \
497 dove-dove-db.dtb 515 dove-dove-db.dtb
516dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
498 517
499targets += dtbs dtbs_install 518targets += dtbs dtbs_install
500targets += $(dtb-y) 519targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index d9d98697cca9..6cc25ed912ee 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -224,6 +224,7 @@
224&tps { 224&tps {
225 regulators { 225 regulators {
226 dcdc1_reg: regulator@0 { 226 dcdc1_reg: regulator@0 {
227 regulator-name = "vdds_dpr";
227 regulator-always-on; 228 regulator-always-on;
228 }; 229 };
229 230
@@ -246,18 +247,22 @@
246 }; 247 };
247 248
248 ldo1_reg: regulator@3 { 249 ldo1_reg: regulator@3 {
250 regulator-name = "vio,vrtc,vdds";
249 regulator-always-on; 251 regulator-always-on;
250 }; 252 };
251 253
252 ldo2_reg: regulator@4 { 254 ldo2_reg: regulator@4 {
255 regulator-name = "vdd_3v3aux";
253 regulator-always-on; 256 regulator-always-on;
254 }; 257 };
255 258
256 ldo3_reg: regulator@5 { 259 ldo3_reg: regulator@5 {
260 regulator-name = "vdd_1v8";
257 regulator-always-on; 261 regulator-always-on;
258 }; 262 };
259 263
260 ldo4_reg: regulator@6 { 264 ldo4_reg: regulator@6 {
265 regulator-name = "vdd_3v3a";
261 regulator-always-on; 266 regulator-always-on;
262 }; 267 };
263 }; 268 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c8238c467acf..9e7d45571cd5 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -354,6 +354,10 @@
354 ti,hwmods = "mailbox"; 354 ti,hwmods = "mailbox";
355 ti,mbox-num-users = <4>; 355 ti,mbox-num-users = <4>;
356 ti,mbox-num-fifos = <8>; 356 ti,mbox-num-fifos = <8>;
357 mbox_wkupm3: wkup_m3 {
358 ti,mbox-tx = <0 0 0>;
359 ti,mbox-rx = <0 0 3>;
360 };
357 }; 361 };
358 362
359 timer1: timer@44e31000 { 363 timer1: timer@44e31000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 24531de979f2..46660ffd2b65 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -58,10 +58,12 @@
58 }; 58 };
59 59
60 am43xx_pinmux: pinmux@44e10800 { 60 am43xx_pinmux: pinmux@44e10800 {
61 compatible = "pinctrl-single"; 61 compatible = "ti,am437-padconf", "pinctrl-single";
62 reg = <0x44e10800 0x31c>; 62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <0>; 64 #size-cells = <0>;
65 #interrupt-cells = <1>;
66 interrupt-controller;
65 pinctrl-single,register-width = <32>; 67 pinctrl-single,register-width = <32>;
66 pinctrl-single,function-mask = <0xffffffff>; 68 pinctrl-single,function-mask = <0xffffffff>;
67 }; 69 };
@@ -168,6 +170,10 @@
168 ti,hwmods = "mailbox"; 170 ti,hwmods = "mailbox";
169 ti,mbox-num-users = <4>; 171 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <8>; 172 ti,mbox-num-fifos = <8>;
173 mbox_wkupm3: wkup_m3 {
174 ti,mbox-tx = <0 0 0>;
175 ti,mbox-rx = <0 0 3>;
176 };
171 }; 177 };
172 178
173 timer1: timer@44e31000 { 179 timer1: timer@44e31000 {
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 416f4e5a69c1..a495e5821ab8 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -43,6 +43,8 @@
43 }; 43 };
44 44
45 mdio { 45 mdio {
46 pinctrl-0 = <&mdio_pins>;
47 pinctrl-names = "default";
46 phy0: ethernet-phy@0 { 48 phy0: ethernet-phy@0 {
47 reg = <0>; 49 reg = <0>;
48 }; 50 };
@@ -53,11 +55,15 @@
53 }; 55 };
54 56
55 ethernet@70000 { 57 ethernet@70000 {
58 pinctrl-0 = <&ge0_rgmii_pins>;
59 pinctrl-names = "default";
56 status = "okay"; 60 status = "okay";
57 phy = <&phy0>; 61 phy = <&phy0>;
58 phy-mode = "rgmii-id"; 62 phy-mode = "rgmii-id";
59 }; 63 };
60 ethernet@74000 { 64 ethernet@74000 {
65 pinctrl-0 = <&ge1_rgmii_pins>;
66 pinctrl-names = "default";
61 status = "okay"; 67 status = "okay";
62 phy = <&phy1>; 68 phy = <&phy1>;
63 phy-mode = "rgmii-id"; 69 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 097df7d8f0f6..2b6d24e0d1e8 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -91,6 +91,8 @@
91 }; 91 };
92 92
93 mdio { 93 mdio {
94 pinctrl-0 = <&mdio_pins>;
95 pinctrl-names = "default";
94 phy0: ethernet-phy@0 { 96 phy0: ethernet-phy@0 {
95 reg = <0>; 97 reg = <0>;
96 }; 98 };
@@ -100,11 +102,15 @@
100 }; 102 };
101 }; 103 };
102 ethernet@70000 { 104 ethernet@70000 {
105 pinctrl-0 = <&ge0_rgmii_pins>;
106 pinctrl-names = "default";
103 status = "okay"; 107 status = "okay";
104 phy = <&phy0>; 108 phy = <&phy0>;
105 phy-mode = "rgmii-id"; 109 phy-mode = "rgmii-id";
106 }; 110 };
107 ethernet@74000 { 111 ethernet@74000 {
112 pinctrl-0 = <&ge1_rgmii_pins>;
113 pinctrl-names = "default";
108 status = "okay"; 114 status = "okay";
109 phy = <&phy1>; 115 phy = <&phy1>;
110 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 285524fb915e..3aebd93cc33c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -101,12 +101,16 @@
101 }; 101 };
102 102
103 mdio { 103 mdio {
104 pinctrl-0 = <&mdio_pins>;
105 pinctrl-names = "default";
104 phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 106 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
105 reg = <0>; 107 reg = <0>;
106 }; 108 };
107 }; 109 };
108 110
109 ethernet@74000 { 111 ethernet@74000 {
112 pinctrl-0 = <&ge1_rgmii_pins>;
113 pinctrl-names = "default";
110 status = "okay"; 114 status = "okay";
111 phy = <&phy0>; 115 phy = <&phy0>;
112 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
@@ -122,7 +126,7 @@
122 status = "okay"; 126 status = "okay";
123 127
124 isl12057: isl12057@68 { 128 isl12057: isl12057@68 {
125 compatible = "isl,isl12057"; 129 compatible = "isil,isl12057";
126 reg = <0x68>; 130 reg = <0x68>;
127 }; 131 };
128 132
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 4ec1ce561d34..c2f414bb9aba 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -86,6 +86,8 @@
86 }; 86 };
87 87
88 mdio { 88 mdio {
89 pinctrl-0 = <&mdio_pins>;
90 pinctrl-names = "default";
89 phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 91 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
90 reg = <0>; 92 reg = <0>;
91 }; 93 };
@@ -96,12 +98,16 @@
96 }; 98 };
97 99
98 ethernet@70000 { 100 ethernet@70000 {
101 pinctrl-0 = <&ge0_rgmii_pins>;
102 pinctrl-names = "default";
99 status = "okay"; 103 status = "okay";
100 phy = <&phy0>; 104 phy = <&phy0>;
101 phy-mode = "rgmii-id"; 105 phy-mode = "rgmii-id";
102 }; 106 };
103 107
104 ethernet@74000 { 108 ethernet@74000 {
109 pinctrl-0 = <&ge1_rgmii_pins>;
110 pinctrl-names = "default";
105 status = "okay"; 111 status = "okay";
106 phy = <&phy1>; 112 phy = <&phy1>;
107 phy-mode = "rgmii-id"; 113 phy-mode = "rgmii-id";
@@ -117,7 +123,7 @@
117 status = "okay"; 123 status = "okay";
118 124
119 isl12057: isl12057@68 { 125 isl12057: isl12057@68 {
120 compatible = "isl,isl12057"; 126 compatible = "isil,isl12057";
121 reg = <0x68>; 127 reg = <0x68>;
122 }; 128 };
123 129
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 4169f4096ea3..f57a8f841498 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -9,6 +9,15 @@
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 *
13 * Note: this Device Tree assumes that the bootloader has remapped the
14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
17 * boards were delivered with an older version of the bootloader that
18 * left internal registers mapped at 0xd0000000. If you are in this
19 * situation, you should either update your bootloader (preferred
20 * solution) or the below Device Tree should be adjusted.
12 */ 21 */
13 22
14/dts-v1/; 23/dts-v1/;
@@ -30,7 +39,7 @@
30 }; 39 };
31 40
32 soc { 41 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
34 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; 43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
35 44
36 pcie-controller { 45 pcie-controller {
@@ -50,6 +59,18 @@
50 }; 59 };
51 60
52 internal-regs { 61 internal-regs {
62 pinctrl {
63 fan_pins: fan-pins {
64 marvell,pins = "mpp8";
65 marvell,function = "gpio";
66 };
67
68 led_pins: led-pins {
69 marvell,pins = "mpp32";
70 marvell,function = "gpio";
71 };
72 };
73
53 serial@12000 { 74 serial@12000 {
54 status = "okay"; 75 status = "okay";
55 }; 76 };
@@ -59,6 +80,8 @@
59 }; 80 };
60 81
61 mdio { 82 mdio {
83 pinctrl-0 = <&mdio_pins>;
84 pinctrl-names = "default";
62 phy0: ethernet-phy@0 { 85 phy0: ethernet-phy@0 {
63 reg = <0>; 86 reg = <0>;
64 }; 87 };
@@ -74,6 +97,8 @@
74 phy-mode = "sgmii"; 97 phy-mode = "sgmii";
75 }; 98 };
76 ethernet@74000 { 99 ethernet@74000 {
100 pinctrl-0 = <&ge1_rgmii_pins>;
101 pinctrl-names = "default";
77 status = "okay"; 102 status = "okay";
78 phy = <&phy1>; 103 phy = <&phy1>;
79 phy-mode = "rgmii-id"; 104 phy-mode = "rgmii-id";
@@ -106,6 +131,26 @@
106 }; 131 };
107 }; 132 };
108 133
134 gpio-fan {
135 compatible = "gpio-fan";
136 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
137 gpio-fan,speed-map = <0 0 3000 1>;
138 pinctrl-0 = <&fan_pins>;
139 pinctrl-names = "default";
140 };
141
142 gpio_leds {
143 compatible = "gpio-leds";
144 pinctrl-names = "default";
145 pinctrl-0 = <&led_pins>;
146
147 sw_led {
148 label = "370rd:green:sw";
149 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
150 default-state = "keep";
151 };
152 };
153
109 nand@d0000 { 154 nand@d0000 {
110 status = "okay"; 155 status = "okay";
111 num-cs = <1>; 156 num-cs = <1>;
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 23227e0027ec..83286ec9702c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -110,7 +110,7 @@
110 }; 110 };
111 111
112 spi0: spi@10600 { 112 spi0: spi@10600 {
113 compatible = "marvell,orion-spi"; 113 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
114 reg = <0x10600 0x28>; 114 reg = <0x10600 0x28>;
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <0>; 116 #size-cells = <0>;
@@ -121,7 +121,7 @@
121 }; 121 };
122 122
123 spi1: spi@10680 { 123 spi1: spi@10680 {
124 compatible = "marvell,orion-spi"; 124 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
125 reg = <0x10680 0x28>; 125 reg = <0x10680 0x28>;
126 #address-cells = <1>; 126 #address-cells = <1>;
127 #size-cells = <0>; 127 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 21b588b6f6bd..6b3c23b1e138 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -151,6 +151,25 @@
151 "mpp62", "mpp60", "mpp58"; 151 "mpp62", "mpp60", "mpp58";
152 marvell,function = "audio"; 152 marvell,function = "audio";
153 }; 153 };
154
155 mdio_pins: mdio-pins {
156 marvell,pins = "mpp17", "mpp18";
157 marvell,function = "ge";
158 };
159
160 ge0_rgmii_pins: ge0-rgmii-pins {
161 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
162 "mpp9", "mpp10", "mpp11", "mpp12",
163 "mpp13", "mpp14", "mpp15", "mpp16";
164 marvell,function = "ge0";
165 };
166
167 ge1_rgmii_pins: ge1-rgmii-pins {
168 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
169 "mpp23", "mpp24", "mpp25", "mpp26",
170 "mpp27", "mpp28", "mpp29", "mpp30";
171 marvell,function = "ge1";
172 };
154 }; 173 };
155 174
156 gpio0: gpio@18100 { 175 gpio0: gpio@18100 {
@@ -206,6 +225,10 @@
206 status = "okay"; 225 status = "okay";
207 }; 226 };
208 227
228 sscg@18330 {
229 reg = <0x18330 0x4>;
230 };
231
209 interrupt-controller@20000 { 232 interrupt-controller@20000 {
210 reg = <0x20a00 0x1d0>, <0x21870 0x58>; 233 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
211 }; 234 };
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index c1e49e7bf0fa..de6571445cef 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -185,6 +185,12 @@
185 }; 185 };
186 }; 186 };
187 187
188 rtc@10300 {
189 compatible = "marvell,orion-rtc";
190 reg = <0x10300 0x20>;
191 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
192 };
193
188 spi0: spi@10600 { 194 spi0: spi@10600 {
189 compatible = "marvell,orion-spi"; 195 compatible = "marvell,orion-spi";
190 reg = <0x10600 0x50>; 196 reg = <0x10600 0x50>;
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index c5ed85a70ed9..7d8f32873e82 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -174,7 +174,7 @@
174 status = "okay"; 174 status = "okay";
175 175
176 isl12057: isl12057@68 { 176 isl12057: isl12057@68 {
177 compatible = "isl,isl12057"; 177 compatible = "isil,isl12057";
178 reg = <0x68>; 178 reg = <0x68>;
179 }; 179 };
180 180
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 5e95a8053445..d68b3c4862bc 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -345,10 +345,14 @@
345 }; 345 };
346 }; 346 };
347 347
348 ramc: ramc@ffffe200 { 348 ramc0: ramc@ffffe200 {
349 compatible = "atmel,at91sam9260-sdramc"; 349 compatible = "atmel,at91sam9260-sdramc";
350 reg = <0xffffe200 0x200 350 reg = <0xffffe200 0x200>;
351 0xffffe800 0x200>; 351 };
352
353 ramc1: ramc@ffffe800 {
354 compatible = "atmel,at91sam9260-sdramc";
355 reg = <0xffffe800 0x200>;
352 }; 356 };
353 357
354 pit: timer@fffffd30 { 358 pit: timer@fffffd30 {
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 4e0abbd9d655..a50ee587a7af 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -22,6 +22,10 @@
22 compatible = "atmel,at91sam9g20-i2c"; 22 compatible = "atmel,at91sam9g20-i2c";
23 }; 23 };
24 24
25 ssc0: ssc@fffbc000 {
26 compatible = "atmel,at91sam9rl-ssc";
27 };
28
25 adc0: adc@fffe0000 { 29 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>; 30 atmel,adc-startup-time = <40>;
27 }; 31 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 932a669156af..d3f65130a1f8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -96,8 +96,14 @@
96 96
97 ramc0: ramc@ffffe400 { 97 ramc0: ramc@ffffe400 {
98 compatible = "atmel,at91sam9g45-ddramc"; 98 compatible = "atmel,at91sam9g45-ddramc";
99 reg = <0xffffe400 0x200 99 reg = <0xffffe400 0x200>;
100 0xffffe600 0x200>; 100 clocks = <&ddrck>;
101 clock-names = "ddrck";
102 };
103
104 ramc1: ramc@ffffe600 {
105 compatible = "atmel,at91sam9g45-ddramc";
106 reg = <0xffffe600 0x200>;
101 clocks = <&ddrck>; 107 clocks = <&ddrck>;
102 clock-names = "ddrck"; 108 clock-names = "ddrck";
103 }; 109 };
@@ -159,7 +165,7 @@
159 compatible = "atmel,at91rm9200-clk-master"; 165 compatible = "atmel,at91rm9200-clk-master";
160 #clock-cells = <0>; 166 #clock-cells = <0>;
161 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 167 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
162 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; 168 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
163 atmel,clk-output-range = <0 133333333>; 169 atmel,clk-output-range = <0 133333333>;
164 atmel,clk-divisors = <1 2 4 3>; 170 atmel,clk-divisors = <1 2 4 3>;
165 }; 171 };
@@ -175,7 +181,7 @@
175 #address-cells = <1>; 181 #address-cells = <1>;
176 #size-cells = <0>; 182 #size-cells = <0>;
177 interrupt-parent = <&pmc>; 183 interrupt-parent = <&pmc>;
178 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; 184 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
179 185
180 prog0: prog0 { 186 prog0: prog0 {
181 #clock-cells = <0>; 187 #clock-cells = <0>;
@@ -1159,6 +1165,39 @@
1159 atmel,can-isoc; 1165 atmel,can-isoc;
1160 }; 1166 };
1161 }; 1167 };
1168
1169 sckc@fffffd50 {
1170 compatible = "atmel,at91sam9x5-sckc";
1171 reg = <0xfffffd50 0x4>;
1172
1173 slow_osc: slow_osc {
1174 compatible = "atmel,at91sam9x5-clk-slow-osc";
1175 #clock-cells = <0>;
1176 atmel,startup-time-usec = <1200000>;
1177 clocks = <&slow_xtal>;
1178 };
1179
1180 slow_rc_osc: slow_rc_osc {
1181 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1182 #clock-cells = <0>;
1183 atmel,startup-time-usec = <75>;
1184 clock-frequency = <32768>;
1185 clock-accuracy = <50000000>;
1186 };
1187
1188 clk32k: slck {
1189 compatible = "atmel,at91sam9x5-clk-slow";
1190 #clock-cells = <0>;
1191 clocks = <&slow_rc_osc &slow_osc>;
1192 };
1193 };
1194
1195 rtc@fffffdb0 {
1196 compatible = "atmel,at91rm9200-rtc";
1197 reg = <0xfffffdb0 0x30>;
1198 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1199 status = "disabled";
1200 };
1162 }; 1201 };
1163 1202
1164 fb0: fb@0x00500000 { 1203 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 96ccc7de4f0a..d8dd22651090 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -160,6 +160,10 @@
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_pwm_leds>; 161 pinctrl-0 = <&pinctrl_pwm_leds>;
162 }; 162 };
163
164 rtc@fffffdb0 {
165 status = "okay";
166 };
163 }; 167 };
164 168
165 fb0: fb@0x00500000 { 169 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 2bfac310dbec..68eb9aded164 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -87,6 +87,8 @@
87 ramc0: ramc@ffffe800 { 87 ramc0: ramc@ffffe800 {
88 compatible = "atmel,at91sam9g45-ddramc"; 88 compatible = "atmel,at91sam9g45-ddramc";
89 reg = <0xffffe800 0x200>; 89 reg = <0xffffe800 0x200>;
90 clocks = <&ddrck>;
91 clock-names = "ddrck";
90 }; 92 };
91 93
92 pmc: pmc@fffffc00 { 94 pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 83d723711ae1..13bb24ea971a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -136,6 +136,8 @@
136 }; 136 };
137 137
138 usb0: ohci@00500000 { 138 usb0: ohci@00500000 {
139 num-ports = <1>;
140 atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
139 status = "okay"; 141 status = "okay";
140 }; 142 };
141 }; 143 };
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index ab56c8b81dfa..f0b4352650ed 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -204,7 +204,7 @@
204 }; 204 };
205 205
206 ssc0: ssc@fffc0000 { 206 ssc0: ssc@fffc0000 {
207 compatible = "atmel,at91rm9200-ssc"; 207 compatible = "atmel,at91sam9rl-ssc";
208 reg = <0xfffc0000 0x4000>; 208 reg = <0xfffc0000 0x4000>;
209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
210 pinctrl-names = "default"; 210 pinctrl-names = "default";
@@ -213,7 +213,7 @@
213 }; 213 };
214 214
215 ssc1: ssc@fffc4000 { 215 ssc1: ssc@fffc4000 {
216 compatible = "atmel,at91rm9200-ssc"; 216 compatible = "atmel,at91sam9rl-ssc";
217 reg = <0xfffc4000 0x4000>; 217 reg = <0xfffc4000 0x4000>;
218 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 218 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
219 pinctrl-names = "default"; 219 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e1a5c70b885c..726274f7959b 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -95,6 +95,8 @@
95 ramc0: ramc@ffffe800 { 95 ramc0: ramc@ffffe800 {
96 compatible = "atmel,at91sam9g45-ddramc"; 96 compatible = "atmel,at91sam9g45-ddramc";
97 reg = <0xffffe800 0x200>; 97 reg = <0xffffe800 0x200>;
98 clocks = <&ddrck>;
99 clock-names = "ddrck";
98 }; 100 };
99 101
100 pmc: pmc@fffffc00 { 102 pmc: pmc@fffffc00 {
@@ -966,7 +968,7 @@
966 adc0: adc@f804c000 { 968 adc0: adc@f804c000 {
967 #address-cells = <1>; 969 #address-cells = <1>;
968 #size-cells = <0>; 970 #size-cells = <0>;
969 compatible = "atmel,at91sam9260-adc"; 971 compatible = "atmel,at91sam9x5-adc";
970 reg = <0xf804c000 0x100>; 972 reg = <0xf804c000 0x100>;
971 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 973 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
972 clocks = <&adc_clk>, 974 clocks = <&adc_clk>,
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 2a3b1c1313a0..58a0d60b95f1 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -23,7 +23,7 @@
23 23
24&gpio { 24&gpio {
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&gpioout &alt0 &alt3>; 26 pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
27 27
28 gpioout: gpioout { 28 gpioout: gpioout {
29 brcm,pins = <6>; 29 brcm,pins = <6>;
@@ -39,6 +39,12 @@
39 brcm,pins = <48 49 50 51 52 53>; 39 brcm,pins = <48 49 50 51 52 53>;
40 brcm,function = <7>; /* alt3 */ 40 brcm,function = <7>; /* alt3 */
41 }; 41 };
42
43 /* I2S interface */
44 alt2: alt2 {
45 brcm,pins = <28 29 30 31>;
46 brcm,function = <6>; /* alt2 */
47 };
42}; 48};
43 49
44&i2c0 { 50&i2c0 {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index b8473c43e888..3342cb1407bc 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -99,6 +99,7 @@
99 dmas = <&dma 2>, 99 dmas = <&dma 2>,
100 <&dma 3>; 100 <&dma 3>;
101 dma-names = "tx", "rx"; 101 dma-names = "tx", "rx";
102 status = "disabled";
102 }; 103 };
103 104
104 spi: spi@7e204000 { 105 spi: spi@7e204000 {
diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
new file mode 100644
index 000000000000..acd4fe1833f2
--- /dev/null
+++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
@@ -0,0 +1,44 @@
1/*
2 * Thermistor dts fragment for devices that use Thermistors as
3 * children of the IIO based ADC.
4 *
5 * Currently, used by Exynos5420 based Peach PIT and
6 * Exynos5800 based Peach PI.
7 *
8 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15&adc {
16 ncp15wb473@3 {
17 compatible = "murata,ncp15wb473";
18 pullup-uv = <1800000>;
19 pullup-ohm = <47000>;
20 pulldown-ohm = <0>;
21 io-channels = <&adc 3>;
22 };
23 ncp15wb473@4 {
24 compatible = "murata,ncp15wb473";
25 pullup-uv = <1800000>;
26 pullup-ohm = <47000>;
27 pulldown-ohm = <0>;
28 io-channels = <&adc 4>;
29 };
30 ncp15wb473@5 {
31 compatible = "murata,ncp15wb473";
32 pullup-uv = <1800000>;
33 pullup-ohm = <47000>;
34 pulldown-ohm = <0>;
35 io-channels = <&adc 5>;
36 };
37 ncp15wb473@6 {
38 compatible = "murata,ncp15wb473";
39 pullup-uv = <1800000>;
40 pullup-ohm = <47000>;
41 pulldown-ohm = <0>;
42 io-channels = <&adc 6>;
43 };
44};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 1e11e5a5f723..4f935ad9f27b 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -17,6 +17,18 @@
17 soc { 17 soc {
18 pmx_core: pinmux@1c14120 { 18 pmx_core: pinmux@1c14120 {
19 status = "okay"; 19 status = "okay";
20
21 mcasp0_pins: pinmux_mcasp0_pins {
22 pinctrl-single,bits = <
23 /*
24 * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
25 * AFSR, AMUTE
26 */
27 0x00 0x11111111 0xffffffff
28 /* AXR11, AXR12 */
29 0x04 0x00011000 0x000ff000
30 >;
31 };
20 }; 32 };
21 serial0: serial@1c42000 { 33 serial0: serial@1c42000 {
22 status = "okay"; 34 status = "okay";
@@ -39,6 +51,20 @@
39 tps: tps@48 { 51 tps: tps@48 {
40 reg = <0x48>; 52 reg = <0x48>;
41 }; 53 };
54 tlv320aic3106: tlv320aic3106@18 {
55 #sound-dai-cells = <0>;
56 compatible = "ti,tlv320aic3106";
57 reg = <0x18>;
58 status = "okay";
59
60 /* Regulators */
61 IOVDD-supply = <&vdcdc2_reg>;
62 /* Derived from VBAT: Baseboard 3.3V / 1.8V */
63 AVDD-supply = <&vbat>;
64 DRVDD-supply = <&vbat>;
65 DVDD-supply = <&vbat>;
66 };
67
42 }; 68 };
43 wdt: wdt@1c21000 { 69 wdt: wdt@1c21000 {
44 status = "okay"; 70 status = "okay";
@@ -117,6 +143,33 @@
117 regulator-max-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>;
118 regulator-boot-on; 144 regulator-boot-on;
119 }; 145 };
146
147 sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "DA850/OMAP-L138 EVM";
150 simple-audio-card,widgets =
151 "Line", "Line In",
152 "Line", "Line Out";
153 simple-audio-card,routing =
154 "LINE1L", "Line In",
155 "LINE1R", "Line In",
156 "Line Out", "LLOUT",
157 "Line Out", "RLOUT";
158 simple-audio-card,format = "dsp_b";
159 simple-audio-card,bitclock-master = <&link0_codec>;
160 simple-audio-card,frame-master = <&link0_codec>;
161 simple-audio-card,bitclock-inversion;
162
163 simple-audio-card,cpu {
164 sound-dai = <&mcasp0>;
165 system-clock-frequency = <24576000>;
166 };
167
168 link0_codec: simple-audio-card,codec {
169 sound-dai = <&tlv320aic3106>;
170 system-clock-frequency = <24576000>;
171 };
172 };
120}; 173};
121 174
122/include/ "tps6507x.dtsi" 175/include/ "tps6507x.dtsi"
@@ -170,3 +223,22 @@
170 }; 223 };
171 }; 224 };
172}; 225};
226
227&mcasp0 {
228 #sound-dai-cells = <0>;
229 status = "okay";
230 pinctrl-names = "default";
231 pinctrl-0 = <&mcasp0_pins>;
232
233 op-mode = <0>; /* MCASP_IIS_MODE */
234 tdm-slots = <2>;
235 /* 4 serializer */
236 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
237 0 0 0 0
238 0 0 0 0
239 0 0 0 1
240 2 0 0 0
241 >;
242 tx-num-evt = <32>;
243 rx-num-evt = <32>;
244};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index b695548dbb4e..0bd98cd00816 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -150,6 +150,12 @@
150 }; 150 };
151 151
152 }; 152 };
153 edma0: edma@01c00000 {
154 compatible = "ti,edma3";
155 reg = <0x0 0x10000>;
156 interrupts = <11 13 12>;
157 #dma-cells = <1>;
158 };
153 serial0: serial@1c42000 { 159 serial0: serial@1c42000 {
154 compatible = "ns16550a"; 160 compatible = "ns16550a";
155 reg = <0x42000 0x100>; 161 reg = <0x42000 0x100>;
@@ -270,6 +276,19 @@
270 ti,davinci-gpio-unbanked = <0>; 276 ti,davinci-gpio-unbanked = <0>;
271 status = "disabled"; 277 status = "disabled";
272 }; 278 };
279
280 mcasp0: mcasp@01d00000 {
281 compatible = "ti,da830-mcasp-audio";
282 reg = <0x100000 0x2000>,
283 <0x102000 0x400000>;
284 reg-names = "mpu", "dat";
285 interrupts = <54>;
286 interrupt-names = "common";
287 status = "disabled";
288 dmas = <&edma0 1>,
289 <&edma0 0>;
290 dma-names = "tx", "rx";
291 };
273 }; 292 };
274 nand_cs3@62000000 { 293 nand_cs3@62000000 {
275 compatible = "ti,davinci-nand"; 294 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index b40cdadb1f87..c6ce6258434f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -323,6 +323,8 @@
323 status = "okay"; 323 status = "okay";
324 pinctrl-names = "default"; 324 pinctrl-names = "default";
325 pinctrl-0 = <&uart1_pins>; 325 pinctrl-0 = <&uart1_pins>;
326 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
327 <&dra7_pmx_core 0x3e0>;
326}; 328};
327 329
328&uart2 { 330&uart2 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e09b1afdaef2..9cc98436a982 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -218,10 +218,12 @@
218 }; 218 };
219 219
220 dra7_pmx_core: pinmux@4a003400 { 220 dra7_pmx_core: pinmux@4a003400 {
221 compatible = "pinctrl-single"; 221 compatible = "ti,dra7-padconf", "pinctrl-single";
222 reg = <0x4a003400 0x0464>; 222 reg = <0x4a003400 0x0464>;
223 #address-cells = <1>; 223 #address-cells = <1>;
224 #size-cells = <0>; 224 #size-cells = <0>;
225 #interrupt-cells = <1>;
226 interrupt-controller;
225 pinctrl-single,register-width = <32>; 227 pinctrl-single,register-width = <32>;
226 pinctrl-single,function-mask = <0x3fffffff>; 228 pinctrl-single,function-mask = <0x3fffffff>;
227 }; 229 };
@@ -329,7 +331,7 @@
329 uart1: serial@4806a000 { 331 uart1: serial@4806a000 {
330 compatible = "ti,omap4-uart"; 332 compatible = "ti,omap4-uart";
331 reg = <0x4806a000 0x100>; 333 reg = <0x4806a000 0x100>;
332 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 334 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
333 ti,hwmods = "uart1"; 335 ti,hwmods = "uart1";
334 clock-frequency = <48000000>; 336 clock-frequency = <48000000>;
335 status = "disabled"; 337 status = "disabled";
@@ -338,7 +340,7 @@
338 uart2: serial@4806c000 { 340 uart2: serial@4806c000 {
339 compatible = "ti,omap4-uart"; 341 compatible = "ti,omap4-uart";
340 reg = <0x4806c000 0x100>; 342 reg = <0x4806c000 0x100>;
341 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 343 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
342 ti,hwmods = "uart2"; 344 ti,hwmods = "uart2";
343 clock-frequency = <48000000>; 345 clock-frequency = <48000000>;
344 status = "disabled"; 346 status = "disabled";
@@ -347,7 +349,7 @@
347 uart3: serial@48020000 { 349 uart3: serial@48020000 {
348 compatible = "ti,omap4-uart"; 350 compatible = "ti,omap4-uart";
349 reg = <0x48020000 0x100>; 351 reg = <0x48020000 0x100>;
350 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "uart3"; 353 ti,hwmods = "uart3";
352 clock-frequency = <48000000>; 354 clock-frequency = <48000000>;
353 status = "disabled"; 355 status = "disabled";
@@ -356,7 +358,7 @@
356 uart4: serial@4806e000 { 358 uart4: serial@4806e000 {
357 compatible = "ti,omap4-uart"; 359 compatible = "ti,omap4-uart";
358 reg = <0x4806e000 0x100>; 360 reg = <0x4806e000 0x100>;
359 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 361 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 ti,hwmods = "uart4"; 362 ti,hwmods = "uart4";
361 clock-frequency = <48000000>; 363 clock-frequency = <48000000>;
362 status = "disabled"; 364 status = "disabled";
@@ -365,7 +367,7 @@
365 uart5: serial@48066000 { 367 uart5: serial@48066000 {
366 compatible = "ti,omap4-uart"; 368 compatible = "ti,omap4-uart";
367 reg = <0x48066000 0x100>; 369 reg = <0x48066000 0x100>;
368 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 370 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "uart5"; 371 ti,hwmods = "uart5";
370 clock-frequency = <48000000>; 372 clock-frequency = <48000000>;
371 status = "disabled"; 373 status = "disabled";
@@ -374,7 +376,7 @@
374 uart6: serial@48068000 { 376 uart6: serial@48068000 {
375 compatible = "ti,omap4-uart"; 377 compatible = "ti,omap4-uart";
376 reg = <0x48068000 0x100>; 378 reg = <0x48068000 0x100>;
377 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 379 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "uart6"; 380 ti,hwmods = "uart6";
379 clock-frequency = <48000000>; 381 clock-frequency = <48000000>;
380 status = "disabled"; 382 status = "disabled";
@@ -383,7 +385,7 @@
383 uart7: serial@48420000 { 385 uart7: serial@48420000 {
384 compatible = "ti,omap4-uart"; 386 compatible = "ti,omap4-uart";
385 reg = <0x48420000 0x100>; 387 reg = <0x48420000 0x100>;
386 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 388 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
387 ti,hwmods = "uart7"; 389 ti,hwmods = "uart7";
388 clock-frequency = <48000000>; 390 clock-frequency = <48000000>;
389 status = "disabled"; 391 status = "disabled";
@@ -392,7 +394,7 @@
392 uart8: serial@48422000 { 394 uart8: serial@48422000 {
393 compatible = "ti,omap4-uart"; 395 compatible = "ti,omap4-uart";
394 reg = <0x48422000 0x100>; 396 reg = <0x48422000 0x100>;
395 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
396 ti,hwmods = "uart8"; 398 ti,hwmods = "uart8";
397 clock-frequency = <48000000>; 399 clock-frequency = <48000000>;
398 status = "disabled"; 400 status = "disabled";
@@ -401,7 +403,7 @@
401 uart9: serial@48424000 { 403 uart9: serial@48424000 {
402 compatible = "ti,omap4-uart"; 404 compatible = "ti,omap4-uart";
403 reg = <0x48424000 0x100>; 405 reg = <0x48424000 0x100>;
404 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 406 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "uart9"; 407 ti,hwmods = "uart9";
406 clock-frequency = <48000000>; 408 clock-frequency = <48000000>;
407 status = "disabled"; 409 status = "disabled";
@@ -410,7 +412,7 @@
410 uart10: serial@4ae2b000 { 412 uart10: serial@4ae2b000 {
411 compatible = "ti,omap4-uart"; 413 compatible = "ti,omap4-uart";
412 reg = <0x4ae2b000 0x100>; 414 reg = <0x4ae2b000 0x100>;
413 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 415 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "uart10"; 416 ti,hwmods = "uart10";
415 clock-frequency = <48000000>; 417 clock-frequency = <48000000>;
416 status = "disabled"; 418 status = "disabled";
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 514702348818..41074288adfa 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -19,6 +19,126 @@
19 }; 19 };
20}; 20};
21 21
22&dra7_pmx_core {
23 i2c1_pins: pinmux_i2c1_pins {
24 pinctrl-single,pins = <
25 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
26 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
27 >;
28 };
29};
30
31&i2c1 {
32 status = "okay";
33 pinctrl-names = "default";
34 pinctrl-0 = <&i2c1_pins>;
35 clock-frequency = <400000>;
36
37 tps65917: tps65917@58 {
38 compatible = "ti,tps65917";
39 reg = <0x58>;
40
41 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
42 interrupt-parent = <&gic>;
43 interrupt-controller;
44 #interrupt-cells = <2>;
45
46 ti,system-power-controller;
47
48 tps65917_pmic {
49 compatible = "ti,tps65917-pmic";
50
51 regulators {
52 smps1_reg: smps1 {
53 /* VDD_MPU */
54 regulator-name = "smps1";
55 regulator-min-microvolt = <850000>;
56 regulator-max-microvolt = <1250000>;
57 regulator-always-on;
58 regulator-boot-on;
59 };
60
61 smps2_reg: smps2 {
62 /* VDD_CORE */
63 regulator-name = "smps2";
64 regulator-min-microvolt = <850000>;
65 regulator-max-microvolt = <1030000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69
70 smps3_reg: smps3 {
71 /* VDD_GPU IVA DSPEVE */
72 regulator-name = "smps3";
73 regulator-min-microvolt = <850000>;
74 regulator-max-microvolt = <1250000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 smps4_reg: smps4 {
80 /* VDDS1V8 */
81 regulator-name = "smps4";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-always-on;
85 regulator-boot-on;
86 };
87
88 smps5_reg: smps5 {
89 /* VDD_DDR */
90 regulator-name = "smps5";
91 regulator-min-microvolt = <1350000>;
92 regulator-max-microvolt = <1350000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96
97 ldo1_reg: ldo1 {
98 /* LDO1_OUT --> SDIO */
99 regulator-name = "ldo1";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-boot-on;
103 };
104
105 ldo2_reg: ldo2 {
106 /* LDO2_OUT --> TP1017 (UNUSED) */
107 regulator-name = "ldo2";
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <3300000>;
110 };
111
112 ldo3_reg: ldo3 {
113 /* VDDA_1V8_PHY */
114 regulator-name = "ldo3";
115 regulator-min-microvolt = <1800000>;
116 regulator-max-microvolt = <1800000>;
117 regulator-boot-on;
118 regulator-always-on;
119 };
120
121 ldo5_reg: ldo5 {
122 /* VDDA_1V8_PLL */
123 regulator-name = "ldo5";
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 regulator-always-on;
127 regulator-boot-on;
128 };
129
130 ldo4_reg: ldo4 {
131 /* VDDA_3V_USB: VDDA_USBHS33 */
132 regulator-name = "ldo4";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-boot-on;
136 };
137 };
138 };
139 };
140};
141
22&uart1 { 142&uart1 {
23 status = "okay"; 143 status = "okay";
24}; 144};
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f1ec22f6ebf4..e5a3d23a3df1 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -22,4 +22,9 @@
22 reg = <0>; 22 reg = <0>;
23 }; 23 };
24 }; 24 };
25
26 pmu {
27 compatible = "arm,cortex-a15-pmu";
28 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
29 };
25}; 30};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index a4e8bb9f95c0..3be544c4891f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -38,4 +38,10 @@
38 reg = <1>; 38 reg = <1>;
39 }; 39 };
40 }; 40 };
41
42 pmu {
43 compatible = "arm,cortex-a15-pmu";
44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
46 };
41}; 47};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index adadaf97ac01..c697ff01ae8d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -54,17 +54,13 @@
54 status = "okay"; 54 status = "okay";
55 55
56 num-slots = <1>; 56 num-slots = <1>;
57 supports-highspeed;
58 broken-cd; 57 broken-cd;
59 card-detect-delay = <200>; 58 card-detect-delay = <200>;
60 samsung,dw-mshc-ciu-div = <3>; 59 samsung,dw-mshc-ciu-div = <3>;
61 samsung,dw-mshc-sdr-timing = <2 3>; 60 samsung,dw-mshc-sdr-timing = <2 3>;
62 samsung,dw-mshc-ddr-timing = <1 2>; 61 samsung,dw-mshc-ddr-timing = <1 2>;
63 62 bus-width = <8>;
64 slot@0 { 63 cap-mmc-highspeed;
65 reg = <0>;
66 bus-width = <8>;
67 };
68 }; 64 };
69 65
70 watchdog@10060000 { 66 watchdog@10060000 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9fbfb07..de15114fd07c 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
137 status = "okay"; 137 status = "okay";
138 138
139 num-slots = <1>; 139 num-slots = <1>;
140 supports-highspeed;
141 broken-cd; 140 broken-cd;
142 card-detect-delay = <200>; 141 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>; 142 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3>; 143 samsung,dw-mshc-sdr-timing = <2 3>;
145 samsung,dw-mshc-ddr-timing = <1 2>; 144 samsung,dw-mshc-ddr-timing = <1 2>;
146 145 bus-width = <8>;
147 slot@0 { 146 cap-mmc-highspeed;
148 reg = <0>;
149 bus-width = <8>;
150 };
151 }; 147 };
152 148
153 codec@13400000 { 149 codec@13400000 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4561e0..5e066cd87f66 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
520 520
521 mmc@12550000 { 521 mmc@12550000 {
522 num-slots = <1>; 522 num-slots = <1>;
523 supports-highspeed;
524 broken-cd; 523 broken-cd;
525 non-removable; 524 non-removable;
526 card-detect-delay = <200>; 525 card-detect-delay = <200>;
@@ -532,11 +531,8 @@
532 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 531 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
533 pinctrl-names = "default"; 532 pinctrl-names = "default";
534 status = "okay"; 533 status = "okay";
535 534 bus-width = <8>;
536 slot@0 { 535 cap-mmc-highspeed;
537 reg = <0>;
538 bus-width = <8>;
539 };
540 }; 536 };
541 537
542 serial@13800000 { 538 serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f50d15b..3acd97eb6630 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
401 mmc_0: mmc@12200000 { 401 mmc_0: mmc@12200000 {
402 status = "okay"; 402 status = "okay";
403 num-slots = <1>; 403 num-slots = <1>;
404 supports-highspeed;
405 broken-cd; 404 broken-cd;
406 card-detect-delay = <200>; 405 card-detect-delay = <200>;
407 samsung,dw-mshc-ciu-div = <3>; 406 samsung,dw-mshc-ciu-div = <3>;
@@ -410,17 +409,13 @@
410 vmmc-supply = <&mmc_reg>; 409 vmmc-supply = <&mmc_reg>;
411 pinctrl-names = "default"; 410 pinctrl-names = "default";
412 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 411 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
413 412 bus-width = <8>;
414 slot@0 { 413 cap-mmc-highspeed;
415 reg = <0>;
416 bus-width = <8>;
417 };
418 }; 414 };
419 415
420 mmc_2: mmc@12220000 { 416 mmc_2: mmc@12220000 {
421 status = "okay"; 417 status = "okay";
422 num-slots = <1>; 418 num-slots = <1>;
423 supports-highspeed;
424 card-detect-delay = <200>; 419 card-detect-delay = <200>;
425 samsung,dw-mshc-ciu-div = <3>; 420 samsung,dw-mshc-ciu-div = <3>;
426 samsung,dw-mshc-sdr-timing = <2 3>; 421 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -428,12 +423,9 @@
428 vmmc-supply = <&mmc_reg>; 423 vmmc-supply = <&mmc_reg>;
429 pinctrl-names = "default"; 424 pinctrl-names = "default";
430 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 425 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
431 426 bus-width = <4>;
432 slot@0 { 427 disable-wp;
433 reg = <0>; 428 cap-sd-highspeed;
434 bus-width = <4>;
435 disable-wp;
436 };
437 }; 429 };
438 430
439 i2s0: i2s@03830000 { 431 i2s0: i2s@03830000 {
@@ -570,8 +562,4 @@
570 connect-gpios = <&gpd1 7 1>; 562 connect-gpios = <&gpd1 7 1>;
571 }; 563 };
572 }; 564 };
573
574 usb@12110000 {
575 usb-phy = <&usb2_phy>;
576 };
577}; 565};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
deleted file mode 100644
index e603e9c70142..000000000000
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Common device tree include for all Exynos 5250 boards based off of Daisy.
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/ {
12 aliases {
13 };
14
15 memory {
16 reg = <0x40000000 0x80000000>;
17 };
18
19 chosen {
20 };
21
22 pinctrl@11400000 {
23 /*
24 * Disabled pullups since external part has its own pullups and
25 * double-pulling gets us out of spec in some cases.
26 */
27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>;
29 };
30 };
31
32 i2c@12C60000 {
33 status = "okay";
34 samsung,i2c-sda-delay = <100>;
35 samsung,i2c-max-bus-freq = <378000>;
36 };
37
38 i2c@12C70000 {
39 status = "okay";
40 samsung,i2c-sda-delay = <100>;
41 samsung,i2c-max-bus-freq = <378000>;
42 };
43
44 i2c@12C80000 {
45 status = "okay";
46 samsung,i2c-sda-delay = <100>;
47 samsung,i2c-max-bus-freq = <66000>;
48
49 hdmiddc@50 {
50 compatible = "samsung,exynos4210-hdmiddc";
51 reg = <0x50>;
52 };
53 };
54
55 i2c@12C90000 {
56 status = "okay";
57 samsung,i2c-sda-delay = <100>;
58 samsung,i2c-max-bus-freq = <66000>;
59 };
60
61 i2c@12CA0000 {
62 status = "okay";
63 samsung,i2c-sda-delay = <100>;
64 samsung,i2c-max-bus-freq = <66000>;
65 };
66
67 i2c@12CB0000 {
68 status = "okay";
69 samsung,i2c-sda-delay = <100>;
70 samsung,i2c-max-bus-freq = <66000>;
71 };
72
73 i2c@12CD0000 {
74 status = "okay";
75 samsung,i2c-sda-delay = <100>;
76 samsung,i2c-max-bus-freq = <66000>;
77 };
78
79 i2c@12CE0000 {
80 status = "okay";
81 samsung,i2c-sda-delay = <100>;
82 samsung,i2c-max-bus-freq = <378000>;
83
84 hdmiphy: hdmiphy@38 {
85 compatible = "samsung,exynos4212-hdmiphy";
86 reg = <0x38>;
87 };
88 };
89
90 mmc@12200000 {
91 num-slots = <1>;
92 supports-highspeed;
93 broken-cd;
94 card-detect-delay = <200>;
95 samsung,dw-mshc-ciu-div = <3>;
96 samsung,dw-mshc-sdr-timing = <2 3>;
97 samsung,dw-mshc-ddr-timing = <1 2>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
100
101 slot@0 {
102 reg = <0>;
103 bus-width = <8>;
104 };
105 };
106
107 mmc@12220000 {
108 num-slots = <1>;
109 supports-highspeed;
110 card-detect-delay = <200>;
111 samsung,dw-mshc-ciu-div = <3>;
112 samsung,dw-mshc-sdr-timing = <2 3>;
113 samsung,dw-mshc-ddr-timing = <1 2>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
116
117 slot@0 {
118 reg = <0>;
119 bus-width = <4>;
120 wp-gpios = <&gpc2 1 0>;
121 };
122 };
123
124 mmc@12230000 {
125 num-slots = <1>;
126 supports-highspeed;
127 broken-cd;
128 card-detect-delay = <200>;
129 samsung,dw-mshc-ciu-div = <3>;
130 samsung,dw-mshc-sdr-timing = <2 3>;
131 samsung,dw-mshc-ddr-timing = <1 2>;
132 /* See board-specific dts files for pin setup */
133
134 slot@0 {
135 reg = <0>;
136 bus-width = <4>;
137 };
138 };
139
140 spi_1: spi@12d30000 {
141 status = "okay";
142 samsung,spi-src-clk = <0>;
143 num-cs = <1>;
144 };
145
146 hdmi {
147 hpd-gpio = <&gpx3 7 0>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&hdmi_hpd_irq>;
150 phy = <&hdmiphy>;
151 ddc = <&i2c_2>;
152 };
153
154 gpio-keys {
155 compatible = "gpio-keys";
156
157 power {
158 label = "Power";
159 gpios = <&gpx1 3 1>;
160 linux,code = <116>; /* KEY_POWER */
161 gpio-key,wakeup;
162 };
163 };
164};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35adae565..6a0f4c0ff763 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -284,7 +284,6 @@
284 mmc@12200000 { 284 mmc@12200000 {
285 status = "okay"; 285 status = "okay";
286 num-slots = <1>; 286 num-slots = <1>;
287 supports-highspeed;
288 broken-cd; 287 broken-cd;
289 card-detect-delay = <200>; 288 card-detect-delay = <200>;
290 samsung,dw-mshc-ciu-div = <3>; 289 samsung,dw-mshc-ciu-div = <3>;
@@ -292,29 +291,22 @@
292 samsung,dw-mshc-ddr-timing = <1 2>; 291 samsung,dw-mshc-ddr-timing = <1 2>;
293 pinctrl-names = "default"; 292 pinctrl-names = "default";
294 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 293 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
295 294 bus-width = <8>;
296 slot@0 { 295 cap-mmc-highspeed;
297 reg = <0>;
298 bus-width = <8>;
299 };
300 }; 296 };
301 297
302 mmc@12220000 { 298 mmc@12220000 {
303 status = "okay"; 299 status = "okay";
304 num-slots = <1>; 300 num-slots = <1>;
305 supports-highspeed;
306 card-detect-delay = <200>; 301 card-detect-delay = <200>;
307 samsung,dw-mshc-ciu-div = <3>; 302 samsung,dw-mshc-ciu-div = <3>;
308 samsung,dw-mshc-sdr-timing = <2 3>; 303 samsung,dw-mshc-sdr-timing = <2 3>;
309 samsung,dw-mshc-ddr-timing = <1 2>; 304 samsung,dw-mshc-ddr-timing = <1 2>;
310 pinctrl-names = "default"; 305 pinctrl-names = "default";
311 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 306 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
312 307 bus-width = <4>;
313 slot@0 { 308 disable-wp;
314 reg = <0>; 309 cap-sd-highspeed;
315 bus-width = <4>;
316 disable-wp;
317 };
318 }; 310 };
319 311
320 spi_1: spi@12d30000 { 312 spi_1: spi@12d30000 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c4116541..e51fcef884a4 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
9*/ 9*/
10 10
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/gpio/gpio.h>
12#include "exynos5250.dtsi" 13#include "exynos5250.dtsi"
13#include "exynos5250-cros-common.dtsi"
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
@@ -20,6 +20,13 @@
20 i2c104 = &i2c_104; 20 i2c104 = &i2c_104;
21 }; 21 };
22 22
23 memory {
24 reg = <0x40000000 0x80000000>;
25 };
26
27 chosen {
28 };
29
23 rtc@101E0000 { 30 rtc@101E0000 {
24 status = "okay"; 31 status = "okay";
25 }; 32 };
@@ -93,6 +100,13 @@
93 gpio-keys { 100 gpio-keys {
94 compatible = "gpio-keys"; 101 compatible = "gpio-keys";
95 102
103 power {
104 label = "Power";
105 gpios = <&gpx1 3 1>;
106 linux,code = <116>; /* KEY_POWER */
107 gpio-key,wakeup;
108 };
109
96 lid-switch { 110 lid-switch {
97 label = "Lid"; 111 label = "Lid";
98 gpios = <&gpx3 5 1>; 112 gpios = <&gpx3 5 1>;
@@ -181,7 +195,7 @@
181 dcdc3 { 195 dcdc3 {
182 ti,enable-ext-control; 196 ti,enable-ext-control;
183 }; 197 };
184 fet1 { 198 fet1: fet1 {
185 regulator-name = "vcd_led"; 199 regulator-name = "vcd_led";
186 ti,overcurrent-wait = <3>; 200 ti,overcurrent-wait = <3>;
187 }; 201 };
@@ -204,7 +218,7 @@
204 regulator-always-on; 218 regulator-always-on;
205 ti,overcurrent-wait = <3>; 219 ti,overcurrent-wait = <3>;
206 }; 220 };
207 fet6 { 221 fet6: fet6 {
208 regulator-name = "lcd_vdd"; 222 regulator-name = "lcd_vdd";
209 ti,overcurrent-wait = <3>; 223 ti,overcurrent-wait = <3>;
210 }; 224 };
@@ -226,26 +240,6 @@
226 }; 240 };
227 }; 241 };
228 242
229 mmc@12200000 {
230 status = "okay";
231 };
232
233 mmc@12220000 {
234 status = "okay";
235 };
236
237 /*
238 * On Snow we've got SIP WiFi and so can keep drive strengths low to
239 * reduce EMI.
240 */
241 mmc@12230000 {
242 status = "okay";
243 slot@0 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
246 };
247 };
248
249 i2c@12CD0000 { 243 i2c@12CD0000 {
250 max98095: codec@11 { 244 max98095: codec@11 {
251 compatible = "maxim,max98095"; 245 compatible = "maxim,max98095";
@@ -253,6 +247,15 @@
253 pinctrl-0 = <&max98095_en>; 247 pinctrl-0 = <&max98095_en>;
254 pinctrl-names = "default"; 248 pinctrl-names = "default";
255 }; 249 };
250
251 ptn3460: lvds-bridge@20 {
252 compatible = "nxp,ptn3460";
253 reg = <0x20>;
254 powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
255 reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
256 edid-emulation = <5>;
257 panel = <&panel>;
258 };
256 }; 259 };
257 260
258 i2s0: i2s@03830000 { 261 i2s0: i2s@03830000 {
@@ -294,17 +297,24 @@
294 }; 297 };
295 298
296 hdmi { 299 hdmi {
300 hpd-gpio = <&gpx3 7 0>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&hdmi_hpd_irq>;
303 phy = <&hdmiphy>;
304 ddc = <&i2c_2>;
297 hdmi-en-supply = <&tps65090_fet7>; 305 hdmi-en-supply = <&tps65090_fet7>;
298 vdd-supply = <&ldo8_reg>; 306 vdd-supply = <&ldo8_reg>;
299 vdd_osc-supply = <&ldo10_reg>; 307 vdd_osc-supply = <&ldo10_reg>;
300 vdd_pll-supply = <&ldo8_reg>; 308 vdd_pll-supply = <&ldo8_reg>;
301 }; 309 };
302 310
303 backlight { 311 backlight: backlight {
304 compatible = "pwm-backlight"; 312 compatible = "pwm-backlight";
305 pwms = <&pwm 0 1000000 0>; 313 pwms = <&pwm 0 1000000 0>;
306 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 314 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
307 default-brightness-level = <7>; 315 default-brightness-level = <7>;
316 enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
317 power-supply = <&fet1>;
308 pinctrl-0 = <&pwm0_out>; 318 pinctrl-0 = <&pwm0_out>;
309 pinctrl-names = "default"; 319 pinctrl-names = "default";
310 }; 320 };
@@ -314,6 +324,12 @@
314 samsung,invert-vclk; 324 samsung,invert-vclk;
315 }; 325 };
316 326
327 panel: panel {
328 compatible = "auo,b116xw03";
329 power-supply = <&fet6>;
330 backlight = <&backlight>;
331 };
332
317 dp-controller@145B0000 { 333 dp-controller@145B0000 {
318 status = "okay"; 334 status = "okay";
319 pinctrl-names = "default"; 335 pinctrl-names = "default";
@@ -325,26 +341,15 @@
325 samsung,link-rate = <0x0a>; 341 samsung,link-rate = <0x0a>;
326 samsung,lane-count = <2>; 342 samsung,lane-count = <2>;
327 samsung,hpd-gpio = <&gpx0 7 0>; 343 samsung,hpd-gpio = <&gpx0 7 0>;
328 344 bridge = <&ptn3460>;
329 display-timings {
330 native-mode = <&timing1>;
331
332 timing1: timing@1 {
333 clock-frequency = <70589280>;
334 hactive = <1366>;
335 vactive = <768>;
336 hfront-porch = <40>;
337 hback-porch = <40>;
338 hsync-len = <32>;
339 vback-porch = <10>;
340 vfront-porch = <12>;
341 vsync-len = <6>;
342 };
343 };
344 }; 345 };
345}; 346};
346 347
347&i2c_0 { 348&i2c_0 {
349 status = "okay";
350 samsung,i2c-sda-delay = <100>;
351 samsung,i2c-max-bus-freq = <378000>;
352
348 max77686@09 { 353 max77686@09 {
349 compatible = "maxim,max77686"; 354 compatible = "maxim,max77686";
350 interrupt-parent = <&gpx3>; 355 interrupt-parent = <&gpx3>;
@@ -491,6 +496,10 @@
491}; 496};
492 497
493&i2c_1 { 498&i2c_1 {
499 status = "okay";
500 samsung,i2c-sda-delay = <100>;
501 samsung,i2c-max-bus-freq = <378000>;
502
494 trackpad { 503 trackpad {
495 reg = <0x67>; 504 reg = <0x67>;
496 compatible = "cypress,cyapa"; 505 compatible = "cypress,cyapa";
@@ -500,6 +509,106 @@
500 }; 509 };
501}; 510};
502 511
512/*
513 * Disabled pullups since external part has its own pullups and
514 * double-pulling gets us out of spec in some cases.
515 */
516&i2c2_bus {
517 samsung,pin-pud = <0>;
518};
519
520&i2c_2 {
521 status = "okay";
522 samsung,i2c-sda-delay = <100>;
523 samsung,i2c-max-bus-freq = <66000>;
524
525 hdmiddc@50 {
526 compatible = "samsung,exynos4210-hdmiddc";
527 reg = <0x50>;
528 };
529};
530
531&i2c_3 {
532 status = "okay";
533 samsung,i2c-sda-delay = <100>;
534 samsung,i2c-max-bus-freq = <66000>;
535};
536
537&i2c_4 {
538 status = "okay";
539 samsung,i2c-sda-delay = <100>;
540 samsung,i2c-max-bus-freq = <66000>;
541};
542
543&i2c_5 {
544 status = "okay";
545 samsung,i2c-sda-delay = <100>;
546 samsung,i2c-max-bus-freq = <66000>;
547};
548
549&i2c_7 {
550 status = "okay";
551 samsung,i2c-sda-delay = <100>;
552 samsung,i2c-max-bus-freq = <66000>;
553};
554
555&i2c_8 {
556 status = "okay";
557 samsung,i2c-sda-delay = <100>;
558 samsung,i2c-max-bus-freq = <378000>;
559
560 hdmiphy: hdmiphy@38 {
561 compatible = "samsung,exynos4212-hdmiphy";
562 reg = <0x38>;
563 };
564};
565
566&mmc_0 {
567 status = "okay";
568 num-slots = <1>;
569 broken-cd;
570 card-detect-delay = <200>;
571 samsung,dw-mshc-ciu-div = <3>;
572 samsung,dw-mshc-sdr-timing = <2 3>;
573 samsung,dw-mshc-ddr-timing = <1 2>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
576 bus-width = <8>;
577 cap-mmc-highspeed;
578};
579
580&mmc_2 {
581 status = "okay";
582 num-slots = <1>;
583 card-detect-delay = <200>;
584 samsung,dw-mshc-ciu-div = <3>;
585 samsung,dw-mshc-sdr-timing = <2 3>;
586 samsung,dw-mshc-ddr-timing = <1 2>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
589 bus-width = <4>;
590 wp-gpios = <&gpc2 1 0>;
591 cap-sd-highspeed;
592};
593
594/*
595 * On Snow we've got SIP WiFi and so can keep drive strengths low to
596 * reduce EMI.
597 */
598&mmc_3 {
599 status = "okay";
600 num-slots = <1>;
601 broken-cd;
602 card-detect-delay = <200>;
603 samsung,dw-mshc-ciu-div = <3>;
604 samsung,dw-mshc-sdr-timing = <2 3>;
605 samsung,dw-mshc-ddr-timing = <1 2>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
608 bus-width = <4>;
609 cap-sd-highspeed;
610};
611
503&pinctrl_0 { 612&pinctrl_0 {
504 max77686_irq: max77686-irq { 613 max77686_irq: max77686-irq {
505 samsung,pins = "gpx3-2"; 614 samsung,pins = "gpx3-2";
@@ -509,4 +618,10 @@
509 }; 618 };
510}; 619};
511 620
621&spi_1 {
622 status = "okay";
623 samsung,spi-src-clk = <0>;
624 num-cs = <1>;
625};
626
512#include "cros-ec-keyboard.dtsi" 627#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1eff37bd..f21b9aa00fbb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -603,21 +603,6 @@
603 }; 603 };
604 }; 604 };
605 605
606 usb2_phy: usbphy@12130000 {
607 compatible = "samsung,exynos5250-usb2phy";
608 reg = <0x12130000 0x100>;
609 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
610 clock-names = "ext_xtal", "usbhost";
611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges;
614
615 usbphy-sys {
616 reg = <0x10040704 0x8>,
617 <0x10050230 0x4>;
618 };
619 };
620
621 usb2_phy_gen: phy@12130000 { 606 usb2_phy_gen: phy@12130000 {
622 compatible = "samsung,exynos5250-usb2-phy"; 607 compatible = "samsung,exynos5250-usb2-phy";
623 reg = <0x12130000 0x100>; 608 reg = <0x12130000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 8c84ab27c19b..a803b605051b 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -69,7 +69,7 @@
69 num-slots = <1>; 69 num-slots = <1>;
70 broken-cd; 70 broken-cd;
71 bypass-smu; 71 bypass-smu;
72 supports-highspeed; 72 cap-mmc-highspeed;
73 supports-hs200-mode; /* 200 Mhz */ 73 supports-hs200-mode; /* 200 Mhz */
74 card-detect-delay = <200>; 74 card-detect-delay = <200>;
75 samsung,dw-mshc-ciu-div = <3>; 75 samsung,dw-mshc-ciu-div = <3>;
@@ -77,27 +77,19 @@
77 samsung,dw-mshc-ddr-timing = <0 2>; 77 samsung,dw-mshc-ddr-timing = <0 2>;
78 pinctrl-names = "default"; 78 pinctrl-names = "default";
79 pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; 79 pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
80 80 bus-width = <8>;
81 slot@0 {
82 reg = <0>;
83 bus-width = <8>;
84 };
85}; 81};
86 82
87&mmc_2 { 83&mmc_2 {
88 status = "okay"; 84 status = "okay";
89 num-slots = <1>; 85 num-slots = <1>;
90 supports-highspeed; 86 cap-sd-highspeed;
91 card-detect-delay = <200>; 87 card-detect-delay = <200>;
92 samsung,dw-mshc-ciu-div = <3>; 88 samsung,dw-mshc-ciu-div = <3>;
93 samsung,dw-mshc-sdr-timing = <2 3>; 89 samsung,dw-mshc-sdr-timing = <2 3>;
94 samsung,dw-mshc-ddr-timing = <1 2>; 90 samsung,dw-mshc-ddr-timing = <1 2>;
95 pinctrl-names = "default"; 91 pinctrl-names = "default";
96 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; 92 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
97 93 bus-width = <4>;
98 slot@0 { 94 disable-wp;
99 reg = <0>;
100 bus-width = <4>;
101 disable-wp;
102 };
103}; 95};
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 7275bbd6fc4b..be3e02530b42 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -40,33 +40,25 @@
40&mmc_0 { 40&mmc_0 {
41 status = "okay"; 41 status = "okay";
42 num-slots = <1>; 42 num-slots = <1>;
43 supports-highspeed; 43 cap-mmc-highspeed;
44 broken-cd; 44 broken-cd;
45 card-detect-delay = <200>; 45 card-detect-delay = <200>;
46 samsung,dw-mshc-ciu-div = <3>; 46 samsung,dw-mshc-ciu-div = <3>;
47 samsung,dw-mshc-sdr-timing = <2 3>; 47 samsung,dw-mshc-sdr-timing = <2 3>;
48 samsung,dw-mshc-ddr-timing = <1 2>; 48 samsung,dw-mshc-ddr-timing = <1 2>;
49 49 bus-width = <8>;
50 slot@0 {
51 reg = <0>;
52 bus-width = <8>;
53 };
54}; 50};
55 51
56&mmc_2 { 52&mmc_2 {
57 status = "okay"; 53 status = "okay";
58 num-slots = <1>; 54 num-slots = <1>;
59 supports-highspeed; 55 cap-sd-highspeed;
60 card-detect-delay = <200>; 56 card-detect-delay = <200>;
61 samsung,dw-mshc-ciu-div = <3>; 57 samsung,dw-mshc-ciu-div = <3>;
62 samsung,dw-mshc-sdr-timing = <2 3>; 58 samsung,dw-mshc-sdr-timing = <2 3>;
63 samsung,dw-mshc-ddr-timing = <1 2>; 59 samsung,dw-mshc-ddr-timing = <1 2>;
64 60 bus-width = <4>;
65 slot@0 { 61 disable-wp;
66 reg = <0>;
67 bus-width = <4>;
68 disable-wp;
69 };
70}; 62};
71 63
72&uart0 { 64&uart0 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 434fd9d3e09d..70a559cf1a3d 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -50,7 +50,6 @@
50 mmc@12200000 { 50 mmc@12200000 {
51 status = "okay"; 51 status = "okay";
52 broken-cd; 52 broken-cd;
53 supports-highspeed;
54 card-detect-delay = <200>; 53 card-detect-delay = <200>;
55 samsung,dw-mshc-ciu-div = <3>; 54 samsung,dw-mshc-ciu-div = <3>;
56 samsung,dw-mshc-sdr-timing = <0 4>; 55 samsung,dw-mshc-sdr-timing = <0 4>;
@@ -58,16 +57,12 @@
58 pinctrl-names = "default"; 57 pinctrl-names = "default";
59 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 58 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
60 vmmc-supply = <&ldo10_reg>; 59 vmmc-supply = <&ldo10_reg>;
61 60 bus-width = <8>;
62 slot@0 { 61 cap-mmc-highspeed;
63 reg = <0>;
64 bus-width = <8>;
65 };
66 }; 62 };
67 63
68 mmc@12220000 { 64 mmc@12220000 {
69 status = "okay"; 65 status = "okay";
70 supports-highspeed;
71 card-detect-delay = <200>; 66 card-detect-delay = <200>;
72 samsung,dw-mshc-ciu-div = <3>; 67 samsung,dw-mshc-ciu-div = <3>;
73 samsung,dw-mshc-sdr-timing = <2 3>; 68 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -75,11 +70,8 @@
75 pinctrl-names = "default"; 70 pinctrl-names = "default";
76 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 71 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
77 vmmc-supply = <&ldo10_reg>; 72 vmmc-supply = <&ldo10_reg>;
78 73 bus-width = <4>;
79 slot@0 { 74 cap-sd-highspeed;
80 reg = <0>;
81 bus-width = <4>;
82 };
83 }; 75 };
84 76
85 hsi2c_4: i2c@12CA0000 { 77 hsi2c_4: i2c@12CA0000 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 228a6b1e0aa1..9a233828539c 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
14#include "exynos5420.dtsi" 15#include "exynos5420.dtsi"
15 16
16/ { 17/ {
@@ -30,11 +31,12 @@
30 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; 31 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
31 }; 32 };
32 33
33 backlight { 34 backlight: backlight {
34 compatible = "pwm-backlight"; 35 compatible = "pwm-backlight";
35 pwms = <&pwm 0 1000000 0>; 36 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 37 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
37 default-brightness-level = <7>; 38 default-brightness-level = <7>;
39 power-supply = <&tps65090_fet1>;
38 pinctrl-0 = <&pwm0_out>; 40 pinctrl-0 = <&pwm0_out>;
39 pinctrl-names = "default"; 41 pinctrl-names = "default";
40 }; 42 };
@@ -100,6 +102,17 @@
100 regulator-boot-on; 102 regulator-boot-on;
101 regulator-always-on; 103 regulator-always-on;
102 }; 104 };
105
106 panel: panel {
107 compatible = "auo,b116xw03";
108 power-supply = <&tps65090_fet6>;
109 backlight = <&backlight>;
110 };
111};
112
113&adc {
114 status = "okay";
115 vdd-supply = <&ldo9_reg>;
103}; 116};
104 117
105&dp { 118&dp {
@@ -113,22 +126,7 @@
113 samsung,link-rate = <0x06>; 126 samsung,link-rate = <0x06>;
114 samsung,lane-count = <2>; 127 samsung,lane-count = <2>;
115 samsung,hpd-gpio = <&gpx2 6 0>; 128 samsung,hpd-gpio = <&gpx2 6 0>;
116 129 bridge = <&ps8625>;
117 display-timings {
118 native-mode = <&timing1>;
119
120 timing1: timing@1 {
121 clock-frequency = <70589280>;
122 hactive = <1366>;
123 vactive = <768>;
124 hfront-porch = <40>;
125 hback-porch = <40>;
126 hsync-len = <32>;
127 vback-porch = <10>;
128 vfront-porch = <12>;
129 vsync-len = <6>;
130 };
131 };
132}; 130};
133 131
134&fimd { 132&fimd {
@@ -142,10 +140,348 @@
142 pinctrl-names = "default"; 140 pinctrl-names = "default";
143 pinctrl-0 = <&hdmi_hpd_irq>; 141 pinctrl-0 = <&hdmi_hpd_irq>;
144 ddc = <&i2c_2>; 142 ddc = <&i2c_2>;
143
144 hdmi-en-supply = <&tps65090_fet7>;
145 vdd-supply = <&ldo8_reg>;
146 vdd_osc-supply = <&ldo10_reg>;
147 vdd_pll-supply = <&ldo8_reg>;
148};
149
150&hsi2c_4 {
151 status = "okay";
152 clock-frequency = <400000>;
153
154 max77802-pmic@9 {
155 compatible = "maxim,max77802";
156 interrupt-parent = <&gpx3>;
157 interrupts = <1 IRQ_TYPE_NONE>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
160 <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
161 wakeup-source;
162 reg = <0x9>;
163 #clock-cells = <1>;
164
165 inb1-supply = <&tps65090_dcdc2>;
166 inb2-supply = <&tps65090_dcdc1>;
167 inb3-supply = <&tps65090_dcdc2>;
168 inb4-supply = <&tps65090_dcdc2>;
169 inb5-supply = <&tps65090_dcdc1>;
170 inb6-supply = <&tps65090_dcdc2>;
171 inb7-supply = <&tps65090_dcdc1>;
172 inb8-supply = <&tps65090_dcdc1>;
173 inb9-supply = <&tps65090_dcdc1>;
174 inb10-supply = <&tps65090_dcdc1>;
175
176 inl1-supply = <&buck5_reg>;
177 inl2-supply = <&buck7_reg>;
178 inl3-supply = <&buck9_reg>;
179 inl4-supply = <&buck9_reg>;
180 inl5-supply = <&buck9_reg>;
181 inl6-supply = <&tps65090_dcdc2>;
182 inl7-supply = <&buck9_reg>;
183 inl9-supply = <&tps65090_dcdc2>;
184 inl10-supply = <&buck7_reg>;
185
186 regulators {
187 buck1_reg: BUCK1 {
188 regulator-name = "vdd_mif";
189 regulator-min-microvolt = <800000>;
190 regulator-max-microvolt = <1300000>;
191 regulator-always-on;
192 regulator-boot-on;
193 regulator-ramp-delay = <12500>;
194 };
195
196 buck2_reg: BUCK2 {
197 regulator-name = "vdd_arm";
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <1500000>;
200 regulator-always-on;
201 regulator-boot-on;
202 regulator-ramp-delay = <12500>;
203 };
204
205 buck3_reg: BUCK3 {
206 regulator-name = "vdd_int";
207 regulator-min-microvolt = <800000>;
208 regulator-max-microvolt = <1400000>;
209 regulator-always-on;
210 regulator-boot-on;
211 regulator-ramp-delay = <12500>;
212 };
213
214 buck4_reg: BUCK4 {
215 regulator-name = "vdd_g3d";
216 regulator-min-microvolt = <700000>;
217 regulator-max-microvolt = <1400000>;
218 regulator-always-on;
219 regulator-boot-on;
220 regulator-ramp-delay = <12500>;
221 };
222
223 buck5_reg: BUCK5 {
224 regulator-name = "vdd_1v2";
225 regulator-min-microvolt = <1200000>;
226 regulator-max-microvolt = <1200000>;
227 regulator-always-on;
228 regulator-boot-on;
229 };
230
231 buck6_reg: BUCK6 {
232 regulator-name = "vdd_kfc";
233 regulator-min-microvolt = <800000>;
234 regulator-max-microvolt = <1500000>;
235 regulator-always-on;
236 regulator-boot-on;
237 regulator-ramp-delay = <12500>;
238 };
239
240 buck7_reg: BUCK7 {
241 regulator-name = "vdd_1v35";
242 regulator-min-microvolt = <1350000>;
243 regulator-max-microvolt = <1350000>;
244 regulator-always-on;
245 regulator-boot-on;
246 };
247
248 buck8_reg: BUCK8 {
249 regulator-name = "vdd_emmc";
250 regulator-min-microvolt = <2850000>;
251 regulator-max-microvolt = <2850000>;
252 regulator-always-on;
253 regulator-boot-on;
254 };
255
256 buck9_reg: BUCK9 {
257 regulator-name = "vdd_2v";
258 regulator-min-microvolt = <2000000>;
259 regulator-max-microvolt = <2000000>;
260 regulator-always-on;
261 regulator-boot-on;
262 };
263
264 buck10_reg: BUCK10 {
265 regulator-name = "vdd_1v8";
266 regulator-min-microvolt = <1800000>;
267 regulator-max-microvolt = <1800000>;
268 regulator-always-on;
269 regulator-boot-on;
270 };
271
272 ldo1_reg: LDO1 {
273 regulator-name = "vdd_1v0";
274 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <1000000>;
276 regulator-always-on;
277 };
278
279 ldo2_reg: LDO2 {
280 regulator-name = "vdd_1v2_2";
281 regulator-min-microvolt = <1200000>;
282 regulator-max-microvolt = <1200000>;
283 };
284
285 ldo3_reg: LDO3 {
286 regulator-name = "vdd_1v8_3";
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <1800000>;
289 regulator-always-on;
290 };
291
292 vqmmc_sdcard: ldo4_reg: LDO4 {
293 regulator-name = "vdd_sd";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <2800000>;
296 regulator-always-on;
297 };
298
299 ldo5_reg: LDO5 {
300 regulator-name = "vdd_1v8_5";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
303 regulator-always-on;
304 };
305
306 ldo6_reg: LDO6 {
307 regulator-name = "vdd_1v8_6";
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-always-on;
311 };
312
313 ldo7_reg: LDO7 {
314 regulator-name = "vdd_1v8_7";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 };
318
319 ldo8_reg: LDO8 {
320 regulator-name = "vdd_ldo8";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
323 regulator-always-on;
324 };
325
326 ldo9_reg: LDO9 {
327 regulator-name = "vdd_ldo9";
328 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <1800000>;
330 regulator-always-on;
331 };
332
333 ldo10_reg: LDO10 {
334 regulator-name = "vdd_ldo10";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 };
339
340 ldo11_reg: LDO11 {
341 regulator-name = "vdd_ldo11";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>;
344 regulator-always-on;
345 };
346
347 ldo12_reg: LDO12 {
348 regulator-name = "vdd_ldo12";
349 regulator-min-microvolt = <3000000>;
350 regulator-max-microvolt = <3000000>;
351 regulator-always-on;
352 };
353
354 ldo13_reg: LDO13 {
355 regulator-name = "vdd_ldo13";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-always-on;
359 };
360
361 ldo14_reg: LDO14 {
362 regulator-name = "vdd_ldo14";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 };
367
368 ldo15_reg: LDO15 {
369 regulator-name = "vdd_ldo15";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 regulator-always-on;
373 };
374
375 ldo17_reg: LDO17 {
376 regulator-name = "vdd_g3ds";
377 regulator-min-microvolt = <900000>;
378 regulator-max-microvolt = <1400000>;
379 regulator-always-on;
380 };
381
382 ldo18_reg: LDO18 {
383 regulator-name = "ldo_18";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 };
387
388 ldo19_reg: LDO19 {
389 regulator-name = "ldo_19";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 };
393
394 ldo20_reg: LDO20 {
395 regulator-name = "ldo_20";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <1800000>;
398 regulator-always-on;
399 };
400
401 ldo21_reg: LDO21 {
402 regulator-name = "ldo_21";
403 regulator-min-microvolt = <2800000>;
404 regulator-max-microvolt = <2800000>;
405 };
406
407 ldo23_reg: LDO23 {
408 regulator-name = "ldo_23";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411 };
412 ldo24_reg: LDO24 {
413 regulator-name = "ldo_24";
414 regulator-min-microvolt = <2800000>;
415 regulator-max-microvolt = <2800000>;
416 };
417
418 ldo25_reg: LDO25 {
419 regulator-name = "ldo_25";
420 regulator-min-microvolt = <3300000>;
421 regulator-max-microvolt = <3300000>;
422 };
423
424 ldo26_reg: LDO26 {
425 regulator-name = "ldo_26";
426 regulator-min-microvolt = <1200000>;
427 regulator-max-microvolt = <1200000>;
428 };
429
430 ldo27_reg: LDO27 {
431 regulator-name = "ldo_27";
432 regulator-min-microvolt = <1200000>;
433 regulator-max-microvolt = <1200000>;
434 };
435
436 ldo28_reg: LDO28 {
437 regulator-name = "ldo_28";
438 regulator-min-microvolt = <1800000>;
439 regulator-max-microvolt = <1800000>;
440 };
441
442 ldo29_reg: LDO29 {
443 regulator-name = "ldo_29";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446 };
447
448 ldo30_reg: LDO30 {
449 regulator-name = "vdd_mifs";
450 regulator-min-microvolt = <1000000>;
451 regulator-max-microvolt = <1000000>;
452 regulator-always-on;
453 };
454
455 ldo32_reg: LDO32 {
456 regulator-name = "ldo_32";
457 regulator-min-microvolt = <3000000>;
458 regulator-max-microvolt = <3000000>;
459 };
460
461 ldo33_reg: LDO33 {
462 regulator-name = "ldo_33";
463 regulator-min-microvolt = <2800000>;
464 regulator-max-microvolt = <2800000>;
465 };
466
467 ldo34_reg: LDO34 {
468 regulator-name = "ldo_34";
469 regulator-min-microvolt = <3000000>;
470 regulator-max-microvolt = <3000000>;
471 };
472
473 ldo35_reg: LDO35 {
474 regulator-name = "ldo_35";
475 regulator-min-microvolt = <1200000>;
476 regulator-max-microvolt = <1200000>;
477 };
478 };
479 };
145}; 480};
146 481
147&hsi2c_7 { 482&hsi2c_7 {
148 status = "okay"; 483 status = "okay";
484 clock-frequency = <400000>;
149 485
150 max98090: codec@10 { 486 max98090: codec@10 {
151 compatible = "maxim,max98090"; 487 compatible = "maxim,max98090";
@@ -155,6 +491,44 @@
155 pinctrl-names = "default"; 491 pinctrl-names = "default";
156 pinctrl-0 = <&max98090_irq>; 492 pinctrl-0 = <&max98090_irq>;
157 }; 493 };
494
495 light-sensor@44 {
496 compatible = "isil,isl29018";
497 reg = <0x44>;
498 vcc-supply = <&tps65090_fet5>;
499 };
500
501 ps8625: lvds-bridge@48 {
502 compatible = "parade,ps8625";
503 reg = <0x48>;
504 sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
505 reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
506 lane-count = <2>;
507 panel = <&panel>;
508 use-external-pwm;
509 };
510};
511
512&hsi2c_8 {
513 status = "okay";
514 clock-frequency = <333000>;
515
516 /* Atmel mXT336S */
517 trackpad@4b {
518 compatible = "atmel,maxtouch";
519 reg = <0x4b>;
520 interrupt-parent = <&gpx1>;
521 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
522 wakeup-source;
523 pinctrl-names = "default";
524 pinctrl-0 = <&trackpad_irq>;
525 linux,gpio-keymap = <KEY_RESERVED
526 KEY_RESERVED
527 KEY_RESERVED /* GPIO0 */
528 KEY_RESERVED /* GPIO1 */
529 KEY_RESERVED /* GPIO2 */
530 BTN_LEFT>; /* GPIO3 */
531 };
158}; 532};
159 533
160&hsi2c_9 { 534&hsi2c_9 {
@@ -187,7 +561,7 @@
187 num-slots = <1>; 561 num-slots = <1>;
188 broken-cd; 562 broken-cd;
189 caps2-mmc-hs200-1_8v; 563 caps2-mmc-hs200-1_8v;
190 supports-highspeed; 564 cap-mmc-highspeed;
191 non-removable; 565 non-removable;
192 card-detect-delay = <200>; 566 card-detect-delay = <200>;
193 clock-frequency = <400000000>; 567 clock-frequency = <400000000>;
@@ -196,17 +570,13 @@
196 samsung,dw-mshc-ddr-timing = <0 2>; 570 samsung,dw-mshc-ddr-timing = <0 2>;
197 pinctrl-names = "default"; 571 pinctrl-names = "default";
198 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 572 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
199 573 bus-width = <8>;
200 slot@0 {
201 reg = <0>;
202 bus-width = <8>;
203 };
204}; 574};
205 575
206&mmc_2 { 576&mmc_2 {
207 status = "okay"; 577 status = "okay";
208 num-slots = <1>; 578 num-slots = <1>;
209 supports-highspeed; 579 cap-sd-highspeed;
210 card-detect-delay = <200>; 580 card-detect-delay = <200>;
211 clock-frequency = <400000000>; 581 clock-frequency = <400000000>;
212 samsung,dw-mshc-ciu-div = <3>; 582 samsung,dw-mshc-ciu-div = <3>;
@@ -214,11 +584,7 @@
214 samsung,dw-mshc-ddr-timing = <1 2>; 584 samsung,dw-mshc-ddr-timing = <1 2>;
215 pinctrl-names = "default"; 585 pinctrl-names = "default";
216 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 586 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
217 587 bus-width = <4>;
218 slot@0 {
219 reg = <0>;
220 bus-width = <4>;
221 };
222}; 588};
223 589
224 590
@@ -249,6 +615,13 @@
249 samsung,pin-drv = <0>; 615 samsung,pin-drv = <0>;
250 }; 616 };
251 617
618 trackpad_irq: trackpad-irq {
619 samsung,pins = "gpx1-1";
620 samsung,pin-function = <0xf>;
621 samsung,pin-pud = <0>;
622 samsung,pin-drv = <0>;
623 };
624
252 power_key_irq: power-key-irq { 625 power_key_irq: power-key-irq {
253 samsung,pins = "gpx1-2"; 626 samsung,pins = "gpx1-2";
254 samsung,pin-function = <0>; 627 samsung,pin-function = <0>;
@@ -277,12 +650,42 @@
277 samsung,pin-drv = <0>; 650 samsung,pin-drv = <0>;
278 }; 651 };
279 652
653 max77802_irq: max77802-irq {
654 samsung,pins = "gpx3-1";
655 samsung,pin-function = <0>;
656 samsung,pin-pud = <0>;
657 samsung,pin-drv = <0>;
658 };
659
280 hdmi_hpd_irq: hdmi-hpd-irq { 660 hdmi_hpd_irq: hdmi-hpd-irq {
281 samsung,pins = "gpx3-7"; 661 samsung,pins = "gpx3-7";
282 samsung,pin-function = <0>; 662 samsung,pin-function = <0>;
283 samsung,pin-pud = <1>; 663 samsung,pin-pud = <1>;
284 samsung,pin-drv = <0>; 664 samsung,pin-drv = <0>;
285 }; 665 };
666
667 pmic_dvs_1: pmic-dvs-1 {
668 samsung,pins = "gpy7-6";
669 samsung,pin-function = <1>;
670 samsung,pin-pud = <0>;
671 samsung,pin-drv = <0>;
672 };
673};
674
675&pinctrl_2 {
676 pmic_dvs_2: pmic-dvs-2 {
677 samsung,pins = "gpj4-2";
678 samsung,pin-function = <1>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <0>;
681 };
682
683 pmic_dvs_3: pmic-dvs-3 {
684 samsung,pins = "gpj4-3";
685 samsung,pin-function = <1>;
686 samsung,pin-pud = <0>;
687 samsung,pin-drv = <0>;
688 };
286}; 689};
287 690
288&pinctrl_3 { 691&pinctrl_3 {
@@ -312,6 +715,14 @@
312 samsung,pin-pud = <0>; 715 samsung,pin-pud = <0>;
313 samsung,pin-drv = <0>; 716 samsung,pin-drv = <0>;
314 }; 717 };
718
719 pmic_selb: pmic-selb {
720 samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
721 "gph0-6";
722 samsung,pin-function = <1>;
723 samsung,pin-pud = <0>;
724 samsung,pin-drv = <0>;
725 };
315}; 726};
316 727
317&rtc { 728&rtc {
@@ -365,12 +776,12 @@
365 vsys2-supply = <&vbat>; 776 vsys2-supply = <&vbat>;
366 vsys3-supply = <&vbat>; 777 vsys3-supply = <&vbat>;
367 infet1-supply = <&vbat>; 778 infet1-supply = <&vbat>;
368 infet2-supply = <&vbat>; 779 infet2-supply = <&tps65090_dcdc1>;
369 infet3-supply = <&vbat>; 780 infet3-supply = <&tps65090_dcdc2>;
370 infet4-supply = <&vbat>; 781 infet4-supply = <&tps65090_dcdc2>;
371 infet5-supply = <&vbat>; 782 infet5-supply = <&tps65090_dcdc2>;
372 infet6-supply = <&vbat>; 783 infet6-supply = <&tps65090_dcdc2>;
373 infet7-supply = <&vbat>; 784 infet7-supply = <&tps65090_dcdc1>;
374 vsys-l1-supply = <&vbat>; 785 vsys-l1-supply = <&vbat>;
375 vsys-l2-supply = <&vbat>; 786 vsys-l2-supply = <&vbat>;
376 787
@@ -445,3 +856,4 @@
445}; 856};
446 857
447#include "cros-ec-keyboard.dtsi" 858#include "cros-ec-keyboard.dtsi"
859#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6052aa9c5659..8be3d7b489ff 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -76,34 +76,26 @@
76 mmc@12200000 { 76 mmc@12200000 {
77 status = "okay"; 77 status = "okay";
78 broken-cd; 78 broken-cd;
79 supports-highspeed;
80 card-detect-delay = <200>; 79 card-detect-delay = <200>;
81 samsung,dw-mshc-ciu-div = <3>; 80 samsung,dw-mshc-ciu-div = <3>;
82 samsung,dw-mshc-sdr-timing = <0 4>; 81 samsung,dw-mshc-sdr-timing = <0 4>;
83 samsung,dw-mshc-ddr-timing = <0 2>; 82 samsung,dw-mshc-ddr-timing = <0 2>;
84 pinctrl-names = "default"; 83 pinctrl-names = "default";
85 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 84 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
86 85 bus-width = <8>;
87 slot@0 { 86 cap-mmc-highspeed;
88 reg = <0>;
89 bus-width = <8>;
90 };
91 }; 87 };
92 88
93 mmc@12220000 { 89 mmc@12220000 {
94 status = "okay"; 90 status = "okay";
95 supports-highspeed;
96 card-detect-delay = <200>; 91 card-detect-delay = <200>;
97 samsung,dw-mshc-ciu-div = <3>; 92 samsung,dw-mshc-ciu-div = <3>;
98 samsung,dw-mshc-sdr-timing = <2 3>; 93 samsung,dw-mshc-sdr-timing = <2 3>;
99 samsung,dw-mshc-ddr-timing = <1 2>; 94 samsung,dw-mshc-ddr-timing = <1 2>;
100 pinctrl-names = "default"; 95 pinctrl-names = "default";
101 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 96 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
102 97 bus-width = <4>;
103 slot@0 { 98 cap-sd-highspeed;
104 reg = <0>;
105 bus-width = <4>;
106 };
107 }; 99 };
108 100
109 dp-controller@145B0000 { 101 dp-controller@145B0000 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3ee48bbe05f..1d31c8132558 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
14#include "exynos5800.dtsi" 15#include "exynos5800.dtsi"
15 16
16/ { 17/ {
@@ -28,11 +29,13 @@
28 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; 29 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
29 }; 30 };
30 31
31 backlight { 32 backlight: backlight {
32 compatible = "pwm-backlight"; 33 compatible = "pwm-backlight";
33 pwms = <&pwm 0 1000000 0>; 34 pwms = <&pwm 0 1000000 0>;
34 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 35 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
35 default-brightness-level = <7>; 36 default-brightness-level = <7>;
37 enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
38 power-supply = <&tps65090_fet1>;
36 pinctrl-0 = <&pwm0_out>; 39 pinctrl-0 = <&pwm0_out>;
37 pinctrl-names = "default"; 40 pinctrl-names = "default";
38 }; 41 };
@@ -98,6 +101,17 @@
98 regulator-boot-on; 101 regulator-boot-on;
99 regulator-always-on; 102 regulator-always-on;
100 }; 103 };
104
105 panel: panel {
106 compatible = "auo,b133htn01";
107 power-supply = <&tps65090_fet6>;
108 backlight = <&backlight>;
109 };
110};
111
112&adc {
113 status = "okay";
114 vdd-supply = <&ldo9_reg>;
101}; 115};
102 116
103&dp { 117&dp {
@@ -111,22 +125,7 @@
111 samsung,link-rate = <0x0a>; 125 samsung,link-rate = <0x0a>;
112 samsung,lane-count = <2>; 126 samsung,lane-count = <2>;
113 samsung,hpd-gpio = <&gpx2 6 0>; 127 samsung,hpd-gpio = <&gpx2 6 0>;
114 128 panel = <&panel>;
115 display-timings {
116 native-mode = <&timing1>;
117
118 timing1: timing@1 {
119 clock-frequency = <150660000>;
120 hactive = <1920>;
121 vactive = <1080>;
122 hfront-porch = <60>;
123 hback-porch = <172>;
124 hsync-len = <80>;
125 vback-porch = <25>;
126 vfront-porch = <10>;
127 vsync-len = <10>;
128 };
129 };
130}; 129};
131 130
132&fimd { 131&fimd {
@@ -140,10 +139,348 @@
140 pinctrl-names = "default"; 139 pinctrl-names = "default";
141 pinctrl-0 = <&hdmi_hpd_irq>; 140 pinctrl-0 = <&hdmi_hpd_irq>;
142 ddc = <&i2c_2>; 141 ddc = <&i2c_2>;
142
143 hdmi-en-supply = <&tps65090_fet7>;
144 vdd-supply = <&ldo8_reg>;
145 vdd_osc-supply = <&ldo10_reg>;
146 vdd_pll-supply = <&ldo8_reg>;
147};
148
149&hsi2c_4 {
150 status = "okay";
151 clock-frequency = <400000>;
152
153 max77802-pmic@9 {
154 compatible = "maxim,max77802";
155 interrupt-parent = <&gpx3>;
156 interrupts = <1 IRQ_TYPE_NONE>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
159 <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
160 wakeup-source;
161 reg = <0x9>;
162 #clock-cells = <1>;
163
164 inb1-supply = <&tps65090_dcdc2>;
165 inb2-supply = <&tps65090_dcdc1>;
166 inb3-supply = <&tps65090_dcdc2>;
167 inb4-supply = <&tps65090_dcdc2>;
168 inb5-supply = <&tps65090_dcdc1>;
169 inb6-supply = <&tps65090_dcdc2>;
170 inb7-supply = <&tps65090_dcdc1>;
171 inb8-supply = <&tps65090_dcdc1>;
172 inb9-supply = <&tps65090_dcdc1>;
173 inb10-supply = <&tps65090_dcdc1>;
174
175 inl1-supply = <&buck5_reg>;
176 inl2-supply = <&buck7_reg>;
177 inl3-supply = <&buck9_reg>;
178 inl4-supply = <&buck9_reg>;
179 inl5-supply = <&buck9_reg>;
180 inl6-supply = <&tps65090_dcdc2>;
181 inl7-supply = <&buck9_reg>;
182 inl9-supply = <&tps65090_dcdc2>;
183 inl10-supply = <&buck7_reg>;
184
185 regulators {
186 buck1_reg: BUCK1 {
187 regulator-name = "vdd_mif";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1300000>;
190 regulator-always-on;
191 regulator-boot-on;
192 regulator-ramp-delay = <12500>;
193 };
194
195 buck2_reg: BUCK2 {
196 regulator-name = "vdd_arm";
197 regulator-min-microvolt = <800000>;
198 regulator-max-microvolt = <1500000>;
199 regulator-always-on;
200 regulator-boot-on;
201 regulator-ramp-delay = <12500>;
202 };
203
204 buck3_reg: BUCK3 {
205 regulator-name = "vdd_int";
206 regulator-min-microvolt = <800000>;
207 regulator-max-microvolt = <1400000>;
208 regulator-always-on;
209 regulator-boot-on;
210 regulator-ramp-delay = <12500>;
211 };
212
213 buck4_reg: BUCK4 {
214 regulator-name = "vdd_g3d";
215 regulator-min-microvolt = <700000>;
216 regulator-max-microvolt = <1400000>;
217 regulator-always-on;
218 regulator-boot-on;
219 regulator-ramp-delay = <12500>;
220 };
221
222 buck5_reg: BUCK5 {
223 regulator-name = "vdd_1v2";
224 regulator-min-microvolt = <1200000>;
225 regulator-max-microvolt = <1200000>;
226 regulator-always-on;
227 regulator-boot-on;
228 };
229
230 buck6_reg: BUCK6 {
231 regulator-name = "vdd_kfc";
232 regulator-min-microvolt = <800000>;
233 regulator-max-microvolt = <1500000>;
234 regulator-always-on;
235 regulator-boot-on;
236 regulator-ramp-delay = <12500>;
237 };
238
239 buck7_reg: BUCK7 {
240 regulator-name = "vdd_1v35";
241 regulator-min-microvolt = <1350000>;
242 regulator-max-microvolt = <1350000>;
243 regulator-always-on;
244 regulator-boot-on;
245 };
246
247 buck8_reg: BUCK8 {
248 regulator-name = "vdd_emmc";
249 regulator-min-microvolt = <2850000>;
250 regulator-max-microvolt = <2850000>;
251 regulator-always-on;
252 regulator-boot-on;
253 };
254
255 buck9_reg: BUCK9 {
256 regulator-name = "vdd_2v";
257 regulator-min-microvolt = <2000000>;
258 regulator-max-microvolt = <2000000>;
259 regulator-always-on;
260 regulator-boot-on;
261 };
262
263 buck10_reg: BUCK10 {
264 regulator-name = "vdd_1v8";
265 regulator-min-microvolt = <1800000>;
266 regulator-max-microvolt = <1800000>;
267 regulator-always-on;
268 regulator-boot-on;
269 };
270
271 ldo1_reg: LDO1 {
272 regulator-name = "vdd_1v0";
273 regulator-min-microvolt = <1000000>;
274 regulator-max-microvolt = <1000000>;
275 regulator-always-on;
276 };
277
278 ldo2_reg: LDO2 {
279 regulator-name = "vdd_1v2_2";
280 regulator-min-microvolt = <1200000>;
281 regulator-max-microvolt = <1200000>;
282 };
283
284 ldo3_reg: LDO3 {
285 regulator-name = "vdd_1v8_3";
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <1800000>;
288 regulator-always-on;
289 };
290
291 vqmmc_sdcard: ldo4_reg: LDO4 {
292 regulator-name = "vdd_sd";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <2800000>;
295 regulator-always-on;
296 };
297
298 ldo5_reg: LDO5 {
299 regulator-name = "vdd_1v8_5";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 regulator-always-on;
303 };
304
305 ldo6_reg: LDO6 {
306 regulator-name = "vdd_1v8_6";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
309 regulator-always-on;
310 };
311
312 ldo7_reg: LDO7 {
313 regulator-name = "vdd_1v8_7";
314 regulator-min-microvolt = <1800000>;
315 regulator-max-microvolt = <1800000>;
316 };
317
318 ldo8_reg: LDO8 {
319 regulator-name = "vdd_ldo8";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-always-on;
323 };
324
325 ldo9_reg: LDO9 {
326 regulator-name = "vdd_ldo9";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-always-on;
330 };
331
332 ldo10_reg: LDO10 {
333 regulator-name = "vdd_ldo10";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-always-on;
337 };
338
339 ldo11_reg: LDO11 {
340 regulator-name = "vdd_ldo11";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-always-on;
344 };
345
346 ldo12_reg: LDO12 {
347 regulator-name = "vdd_ldo12";
348 regulator-min-microvolt = <3000000>;
349 regulator-max-microvolt = <3000000>;
350 regulator-always-on;
351 };
352
353 ldo13_reg: LDO13 {
354 regulator-name = "vdd_ldo13";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>;
357 regulator-always-on;
358 };
359
360 ldo14_reg: LDO14 {
361 regulator-name = "vdd_ldo14";
362 regulator-min-microvolt = <1800000>;
363 regulator-max-microvolt = <1800000>;
364 regulator-always-on;
365 };
366
367 ldo15_reg: LDO15 {
368 regulator-name = "vdd_ldo15";
369 regulator-min-microvolt = <1000000>;
370 regulator-max-microvolt = <1000000>;
371 regulator-always-on;
372 };
373
374 ldo17_reg: LDO17 {
375 regulator-name = "vdd_g3ds";
376 regulator-min-microvolt = <900000>;
377 regulator-max-microvolt = <1400000>;
378 regulator-always-on;
379 };
380
381 ldo18_reg: LDO18 {
382 regulator-name = "ldo_18";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385 };
386
387 ldo19_reg: LDO19 {
388 regulator-name = "ldo_19";
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 };
392
393 ldo20_reg: LDO20 {
394 regulator-name = "ldo_20";
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397 regulator-always-on;
398 };
399
400 ldo21_reg: LDO21 {
401 regulator-name = "ldo_21";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <2800000>;
404 };
405
406 ldo23_reg: LDO23 {
407 regulator-name = "ldo_23";
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 };
411 ldo24_reg: LDO24 {
412 regulator-name = "ldo_24";
413 regulator-min-microvolt = <2800000>;
414 regulator-max-microvolt = <2800000>;
415 };
416
417 ldo25_reg: LDO25 {
418 regulator-name = "ldo_25";
419 regulator-min-microvolt = <3300000>;
420 regulator-max-microvolt = <3300000>;
421 };
422
423 ldo26_reg: LDO26 {
424 regulator-name = "ldo_26";
425 regulator-min-microvolt = <1200000>;
426 regulator-max-microvolt = <1200000>;
427 };
428
429 ldo27_reg: LDO27 {
430 regulator-name = "ldo_27";
431 regulator-min-microvolt = <1200000>;
432 regulator-max-microvolt = <1200000>;
433 };
434
435 ldo28_reg: LDO28 {
436 regulator-name = "ldo_28";
437 regulator-min-microvolt = <1800000>;
438 regulator-max-microvolt = <1800000>;
439 };
440
441 ldo29_reg: LDO29 {
442 regulator-name = "ldo_29";
443 regulator-min-microvolt = <1800000>;
444 regulator-max-microvolt = <1800000>;
445 };
446
447 ldo30_reg: LDO30 {
448 regulator-name = "vdd_mifs";
449 regulator-min-microvolt = <1000000>;
450 regulator-max-microvolt = <1000000>;
451 regulator-always-on;
452 };
453
454 ldo32_reg: LDO32 {
455 regulator-name = "ldo_32";
456 regulator-min-microvolt = <3000000>;
457 regulator-max-microvolt = <3000000>;
458 };
459
460 ldo33_reg: LDO33 {
461 regulator-name = "ldo_33";
462 regulator-min-microvolt = <2800000>;
463 regulator-max-microvolt = <2800000>;
464 };
465
466 ldo34_reg: LDO34 {
467 regulator-name = "ldo_34";
468 regulator-min-microvolt = <3000000>;
469 regulator-max-microvolt = <3000000>;
470 };
471
472 ldo35_reg: LDO35 {
473 regulator-name = "ldo_35";
474 regulator-min-microvolt = <1200000>;
475 regulator-max-microvolt = <1200000>;
476 };
477 };
478 };
143}; 479};
144 480
145&hsi2c_7 { 481&hsi2c_7 {
146 status = "okay"; 482 status = "okay";
483 clock-frequency = <400000>;
147 484
148 max98091: codec@10 { 485 max98091: codec@10 {
149 compatible = "maxim,max98091"; 486 compatible = "maxim,max98091";
@@ -153,6 +490,33 @@
153 pinctrl-names = "default"; 490 pinctrl-names = "default";
154 pinctrl-0 = <&max98091_irq>; 491 pinctrl-0 = <&max98091_irq>;
155 }; 492 };
493
494 light-sensor@44 {
495 compatible = "isil,isl29018";
496 reg = <0x44>;
497 vcc-supply = <&tps65090_fet5>;
498 };
499};
500
501&hsi2c_8 {
502 status = "okay";
503 clock-frequency = <333000>;
504 /* Atmel mXT540S */
505 trackpad@4b {
506 compatible = "atmel,maxtouch";
507 reg = <0x4b>;
508 interrupt-parent = <&gpx1>;
509 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
510 wakeup-source;
511 pinctrl-names = "default";
512 pinctrl-0 = <&trackpad_irq>;
513 linux,gpio-keymap = <KEY_RESERVED
514 KEY_RESERVED
515 KEY_RESERVED /* GPIO 0 */
516 KEY_RESERVED /* GPIO 1 */
517 BTN_LEFT /* GPIO 2 */
518 KEY_RESERVED>; /* GPIO 3 */
519 };
156}; 520};
157 521
158&hsi2c_9 { 522&hsi2c_9 {
@@ -185,7 +549,7 @@
185 num-slots = <1>; 549 num-slots = <1>;
186 broken-cd; 550 broken-cd;
187 caps2-mmc-hs200-1_8v; 551 caps2-mmc-hs200-1_8v;
188 supports-highspeed; 552 cap-mmc-highspeed;
189 non-removable; 553 non-removable;
190 card-detect-delay = <200>; 554 card-detect-delay = <200>;
191 clock-frequency = <400000000>; 555 clock-frequency = <400000000>;
@@ -194,17 +558,13 @@
194 samsung,dw-mshc-ddr-timing = <0 2>; 558 samsung,dw-mshc-ddr-timing = <0 2>;
195 pinctrl-names = "default"; 559 pinctrl-names = "default";
196 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 560 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
197 561 bus-width = <8>;
198 slot@0 {
199 reg = <0>;
200 bus-width = <8>;
201 };
202}; 562};
203 563
204&mmc_2 { 564&mmc_2 {
205 status = "okay"; 565 status = "okay";
206 num-slots = <1>; 566 num-slots = <1>;
207 supports-highspeed; 567 cap-sd-highspeed;
208 card-detect-delay = <200>; 568 card-detect-delay = <200>;
209 clock-frequency = <400000000>; 569 clock-frequency = <400000000>;
210 samsung,dw-mshc-ciu-div = <3>; 570 samsung,dw-mshc-ciu-div = <3>;
@@ -212,11 +572,7 @@
212 samsung,dw-mshc-ddr-timing = <1 2>; 572 samsung,dw-mshc-ddr-timing = <1 2>;
213 pinctrl-names = "default"; 573 pinctrl-names = "default";
214 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 574 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
215 575 bus-width = <4>;
216 slot@0 {
217 reg = <0>;
218 bus-width = <4>;
219 };
220}; 576};
221 577
222 578
@@ -247,6 +603,13 @@
247 samsung,pin-drv = <0>; 603 samsung,pin-drv = <0>;
248 }; 604 };
249 605
606 trackpad_irq: trackpad-irq {
607 samsung,pins = "gpx1-1";
608 samsung,pin-function = <0xf>;
609 samsung,pin-pud = <0>;
610 samsung,pin-drv = <0>;
611 };
612
250 power_key_irq: power-key-irq { 613 power_key_irq: power-key-irq {
251 samsung,pins = "gpx1-2"; 614 samsung,pins = "gpx1-2";
252 samsung,pin-function = <0>; 615 samsung,pin-function = <0>;
@@ -275,12 +638,42 @@
275 samsung,pin-drv = <0>; 638 samsung,pin-drv = <0>;
276 }; 639 };
277 640
641 max77802_irq: max77802-irq {
642 samsung,pins = "gpx3-1";
643 samsung,pin-function = <0>;
644 samsung,pin-pud = <0>;
645 samsung,pin-drv = <0>;
646 };
647
278 hdmi_hpd_irq: hdmi-hpd-irq { 648 hdmi_hpd_irq: hdmi-hpd-irq {
279 samsung,pins = "gpx3-7"; 649 samsung,pins = "gpx3-7";
280 samsung,pin-function = <0>; 650 samsung,pin-function = <0>;
281 samsung,pin-pud = <1>; 651 samsung,pin-pud = <1>;
282 samsung,pin-drv = <0>; 652 samsung,pin-drv = <0>;
283 }; 653 };
654
655 pmic_dvs_1: pmic-dvs-1 {
656 samsung,pins = "gpy7-6";
657 samsung,pin-function = <1>;
658 samsung,pin-pud = <0>;
659 samsung,pin-drv = <0>;
660 };
661};
662
663&pinctrl_2 {
664 pmic_dvs_2: pmic-dvs-2 {
665 samsung,pins = "gpj4-2";
666 samsung,pin-function = <1>;
667 samsung,pin-pud = <0>;
668 samsung,pin-drv = <0>;
669 };
670
671 pmic_dvs_3: pmic-dvs-3 {
672 samsung,pins = "gpj4-3";
673 samsung,pin-function = <1>;
674 samsung,pin-pud = <0>;
675 samsung,pin-drv = <0>;
676 };
284}; 677};
285 678
286&pinctrl_3 { 679&pinctrl_3 {
@@ -310,6 +703,14 @@
310 samsung,pin-pud = <0>; 703 samsung,pin-pud = <0>;
311 samsung,pin-drv = <0>; 704 samsung,pin-drv = <0>;
312 }; 705 };
706
707 pmic_selb: pmic-selb {
708 samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
709 "gph0-6";
710 samsung,pin-function = <1>;
711 samsung,pin-pud = <0>;
712 samsung,pin-drv = <0>;
713 };
313}; 714};
314 715
315&rtc { 716&rtc {
@@ -363,12 +764,12 @@
363 vsys2-supply = <&vbat>; 764 vsys2-supply = <&vbat>;
364 vsys3-supply = <&vbat>; 765 vsys3-supply = <&vbat>;
365 infet1-supply = <&vbat>; 766 infet1-supply = <&vbat>;
366 infet2-supply = <&vbat>; 767 infet2-supply = <&tps65090_dcdc1>;
367 infet3-supply = <&vbat>; 768 infet3-supply = <&tps65090_dcdc2>;
368 infet4-supply = <&vbat>; 769 infet4-supply = <&tps65090_dcdc2>;
369 infet5-supply = <&vbat>; 770 infet5-supply = <&tps65090_dcdc2>;
370 infet6-supply = <&vbat>; 771 infet6-supply = <&tps65090_dcdc2>;
371 infet7-supply = <&vbat>; 772 infet7-supply = <&tps65090_dcdc1>;
372 vsys-l1-supply = <&vbat>; 773 vsys-l1-supply = <&vbat>;
373 vsys-l2-supply = <&vbat>; 774 vsys-l2-supply = <&vbat>;
374 775
@@ -443,3 +844,4 @@
443}; 844};
444 845
445#include "cros-ec-keyboard.dtsi" 846#include "cros-ec-keyboard.dtsi"
847#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
new file mode 100644
index 000000000000..af4eee5794aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -0,0 +1,152 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16 model = "Freescale MX1 ADS";
17 compatible = "fsl,imx1ads", "fsl,imx1";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x08000000 0x04000000>;
25 };
26
27 clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 clk32 {
32 compatible = "fsl,imx-clk32", "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32000>;
35 };
36 };
37};
38
39&cspi1 {
40 pinctrl-0 = <&pinctrl_cspi1>;
41 fsl,spi-num-chipselects = <1>;
42 cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
43 status = "okay";
44};
45
46&i2c {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_i2c>;
49 status = "okay";
50
51 extgpio0: pcf8575@22 {
52 compatible = "nxp,pcf8575";
53 reg = <0x22>;
54 gpio-controller;
55 #gpio-cells = <2>;
56 };
57
58 extgpio1: pcf8575@24 {
59 compatible = "nxp,pcf8575";
60 reg = <0x24>;
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64};
65
66&uart1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_uart1>;
69 fsl,uart-has-rtscts;
70 status = "okay";
71};
72
73&uart2 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart2>;
76 fsl,uart-has-rtscts;
77 status = "okay";
78};
79
80&weim {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_weim>;
83 status = "okay";
84
85 nor: nor@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0x00000000 0x02000000>;
88 bank-width = <4>;
89 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 };
93};
94
95&iomuxc {
96 imx1-ads {
97 pinctrl_cspi1: cspi1grp {
98 fsl,pins = <
99 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
100 MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
101 MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
102 MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
103 MX1_PAD_SPI1_SS__GPIO3_15 0x0
104 >;
105 };
106
107 pinctrl_i2c: i2cgrp {
108 fsl,pins = <
109 MX1_PAD_I2C_SCL__I2C_SCL 0x0
110 MX1_PAD_I2C_SDA__I2C_SDA 0x0
111 >;
112 };
113
114 pinctrl_uart1: uart1grp {
115 fsl,pins = <
116 MX1_PAD_UART1_TXD__UART1_TXD 0x0
117 MX1_PAD_UART1_RXD__UART1_RXD 0x0
118 MX1_PAD_UART1_CTS__UART1_CTS 0x0
119 MX1_PAD_UART1_RTS__UART1_RTS 0x0
120 >;
121 };
122
123 pinctrl_uart2: uart2grp {
124 fsl,pins = <
125 MX1_PAD_UART2_TXD__UART2_TXD 0x0
126 MX1_PAD_UART2_RXD__UART2_RXD 0x0
127 MX1_PAD_UART2_CTS__UART2_CTS 0x0
128 MX1_PAD_UART2_RTS__UART2_RTS 0x0
129 >;
130 };
131
132 pinctrl_weim: weimgrp {
133 fsl,pins = <
134 MX1_PAD_A0__A0 0x0
135 MX1_PAD_A16__A16 0x0
136 MX1_PAD_A17__A17 0x0
137 MX1_PAD_A18__A18 0x0
138 MX1_PAD_A19__A19 0x0
139 MX1_PAD_A20__A20 0x0
140 MX1_PAD_A21__A21 0x0
141 MX1_PAD_A22__A22 0x0
142 MX1_PAD_A23__A23 0x0
143 MX1_PAD_A24__A24 0x0
144 MX1_PAD_BCLK__BCLK 0x0
145 MX1_PAD_CS4__CS4 0x0
146 MX1_PAD_DTACK__DTACK 0x0
147 MX1_PAD_ECB__ECB 0x0
148 MX1_PAD_LBA__LBA 0x0
149 >;
150 };
151 };
152};
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
new file mode 100644
index 000000000000..07d92fb40e6f
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16 model = "Armadeus APF9328";
17 compatible = "armadeus,imx1-apf9328", "fsl,imx1";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x08000000 0x00800000>;
25 };
26};
27
28&i2c {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2c>;
31 status = "okay";
32};
33
34&uart1 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_uart1>;
37 fsl,uart-has-rtscts;
38 status = "okay";
39};
40
41&uart2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart2>;
44 fsl,uart-has-rtscts;
45 status = "okay";
46};
47
48&weim {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_weim>;
51 status = "okay";
52
53 nor: nor@0,0 {
54 compatible = "cfi-flash";
55 reg = <0 0x00000000 0x02000000>;
56 bank-width = <2>;
57 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 };
61
62 eth: eth@4,c00000 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_eth>;
65 compatible = "davicom,dm9000";
66 reg = <
67 4 0x00c00000 0x2
68 4 0x00c00002 0x2
69 >;
70 interrupt-parent = <&gpio2>;
71 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
72 fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
73 };
74};
75
76&iomuxc {
77 imx1-apf9328 {
78 pinctrl_eth: ethgrp {
79 fsl,pins = <
80 MX1_PAD_SIM_SVEN__GPIO2_14 0x0
81 >;
82 };
83
84 pinctrl_i2c: i2cgrp {
85 fsl,pins = <
86 MX1_PAD_I2C_SCL__I2C_SCL 0x0
87 MX1_PAD_I2C_SDA__I2C_SDA 0x0
88 >;
89 };
90
91 pinctrl_uart1: uart1grp {
92 fsl,pins = <
93 MX1_PAD_UART1_TXD__UART1_TXD 0x0
94 MX1_PAD_UART1_RXD__UART1_RXD 0x0
95 MX1_PAD_UART1_CTS__UART1_CTS 0x0
96 MX1_PAD_UART1_RTS__UART1_RTS 0x0
97 >;
98 };
99
100 pinctrl_uart2: uart2grp {
101 fsl,pins = <
102 MX1_PAD_UART2_TXD__UART2_TXD 0x0
103 MX1_PAD_UART2_RXD__UART2_RXD 0x0
104 MX1_PAD_UART2_CTS__UART2_CTS 0x0
105 MX1_PAD_UART2_RTS__UART2_RTS 0x0
106 >;
107 };
108
109 pinctrl_weim: weimgrp {
110 fsl,pins = <
111 MX1_PAD_A0__A0 0x0
112 MX1_PAD_A16__A16 0x0
113 MX1_PAD_A17__A17 0x0
114 MX1_PAD_A18__A18 0x0
115 MX1_PAD_A19__A19 0x0
116 MX1_PAD_A20__A20 0x0
117 MX1_PAD_A21__A21 0x0
118 MX1_PAD_A22__A22 0x0
119 MX1_PAD_A23__A23 0x0
120 MX1_PAD_A24__A24 0x0
121 MX1_PAD_BCLK__BCLK 0x0
122 MX1_PAD_CS4__CS4 0x0
123 MX1_PAD_DTACK__DTACK 0x0
124 MX1_PAD_ECB__ECB 0x0
125 MX1_PAD_LBA__LBA 0x0
126 >;
127 };
128 };
129};
diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h
new file mode 100644
index 000000000000..22bec8b87680
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-pinfunc.h
@@ -0,0 +1,302 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __DTS_IMX1_PINFUNC_H
13#define __DTS_IMX1_PINFUNC_H
14
15/*
16 * The pin function ID is a tuple of
17 * <pin mux_id>
18 * mux_id consists of
19 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
20 *
21 * function: 0 - Primary function
22 * 1 - Alternate function
23 * 2 - GPIO
24 * direction: 0 - Input
25 * 1 - Output
26 * gpio_oconf: 0 - A_IN
27 * 1 - B_IN
28 * 2 - A_OUT
29 * 3 - Data Register
30 * gpio_iconfa/b: 0 - GPIO_IN
31 * 1 - Interrupt Status Register
32 * 2 - 0
33 * 3 - 1
34 *
35 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
36 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
37 * number on the specific port (between 0 and 31).
38 */
39
40#define MX1_PAD_A24__A24 0x00 0x004
41#define MX1_PAD_A24__GPIO1_0 0x00 0x032
42#define MX1_PAD_A24__SPI2_CLK 0x00 0x006
43#define MX1_PAD_TIN__TIN 0x01 0x000
44#define MX1_PAD_TIN__GPIO1_1 0x01 0x032
45#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022
46#define MX1_PAD_PWMO__PWMO 0x02 0x004
47#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032
48#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004
49#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032
50#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000
51#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032
52#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000
53#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032
54#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000
55#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032
56#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000
57#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032
58#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000
59#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032
60#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000
61#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032
62#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000
63#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032
64#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000
65#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032
66#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000
67#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032
68#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000
69#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032
70#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000
71#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032
72#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000
73#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032
74#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004
75#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032
76#define MX1_PAD_DTACK__DTACK 0x11 0x000
77#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032
78#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002
79#define MX1_PAD_DTACK__A25 0x11 0x016
80#define MX1_PAD_BCLK__BCLK 0x12 0x004
81#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032
82#define MX1_PAD_LBA__LBA 0x13 0x004
83#define MX1_PAD_LBA__GPIO1_19 0x13 0x032
84#define MX1_PAD_ECB__ECB 0x14 0x000
85#define MX1_PAD_ECB__GPIO1_20 0x14 0x032
86#define MX1_PAD_A0__A0 0x15 0x004
87#define MX1_PAD_A0__GPIO1_21 0x15 0x032
88#define MX1_PAD_CS4__CS4 0x16 0x004
89#define MX1_PAD_CS4__GPIO1_22 0x16 0x032
90#define MX1_PAD_CS5__CS5 0x17 0x004
91#define MX1_PAD_CS5__GPIO1_23 0x17 0x032
92#define MX1_PAD_A16__A16 0x18 0x004
93#define MX1_PAD_A16__GPIO1_24 0x18 0x032
94#define MX1_PAD_A17__A17 0x19 0x004
95#define MX1_PAD_A17__GPIO1_25 0x19 0x032
96#define MX1_PAD_A18__A18 0x1a 0x004
97#define MX1_PAD_A18__GPIO1_26 0x1a 0x032
98#define MX1_PAD_A19__A19 0x1b 0x004
99#define MX1_PAD_A19__GPIO1_27 0x1b 0x032
100#define MX1_PAD_A20__A20 0x1c 0x004
101#define MX1_PAD_A20__GPIO1_28 0x1c 0x032
102#define MX1_PAD_A21__A21 0x1d 0x004
103#define MX1_PAD_A21__GPIO1_29 0x1d 0x032
104#define MX1_PAD_A22__A22 0x1e 0x004
105#define MX1_PAD_A22__GPIO1_30 0x1e 0x032
106#define MX1_PAD_A23__A23 0x1f 0x004
107#define MX1_PAD_A23__GPIO1_31 0x1f 0x032
108#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000
109#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001
110#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032
111#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000
112#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001
113#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032
114#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000
115#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001
116#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032
117#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000
118#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001
119#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032
120#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004
121#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005
122#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032
123#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000
124#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005
125#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032
126#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004
127#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001
128#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032
129#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000
130#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001
131#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032
132#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000
133#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001
134#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032
135#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000
136#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005
137#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032
138#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004
139#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001
140#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032
141#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004
142#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001
143#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032
144#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004
145#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032
146#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004
147#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032
148#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000
149#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032
150#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004
151#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032
152#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000
153#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032
154#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000
155#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032
156#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004
157#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032
158#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004
159#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032
160#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004
161#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032
162#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000
163#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032
164#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004
165#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032
166#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000
167#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032
168#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000
169#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032
170#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000
171#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032
172#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000
173#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032
174#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004
175#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032
176#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000
177#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032
178#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000
179#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032
180#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004
181#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032
182#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000
183#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032
184#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004
185#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032
186#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000
187#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032
188#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000
189#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032
190#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004
191#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032
192#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000
193#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032
194#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000
195#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032
196#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004
197#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032
198#define MX1_PAD_BT13__BT13 0x53 0x004
199#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001
200#define MX1_PAD_BT13__GPIO3_19 0x53 0x032
201#define MX1_PAD_BT12__BT12 0x54 0x004
202#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001
203#define MX1_PAD_BT12__GPIO3_20 0x54 0x032
204#define MX1_PAD_BT11__BT11 0x55 0x004
205#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001
206#define MX1_PAD_BT11__GPIO3_21 0x55 0x032
207#define MX1_PAD_BT10__BT10 0x56 0x004
208#define MX1_PAD_BT10__SSI2_TX 0x56 0x001
209#define MX1_PAD_BT10__GPIO3_22 0x56 0x032
210#define MX1_PAD_BT9__BT9 0x57 0x004
211#define MX1_PAD_BT9__SSI2_RX 0x57 0x001
212#define MX1_PAD_BT9__GPIO3_23 0x57 0x032
213#define MX1_PAD_BT8__BT8 0x58 0x004
214#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001
215#define MX1_PAD_BT8__GPIO3_24 0x58 0x032
216#define MX1_PAD_BT8__UART3_RI 0x58 0x016
217#define MX1_PAD_BT7__BT7 0x59 0x004
218#define MX1_PAD_BT7__GPIO3_25 0x59 0x032
219#define MX1_PAD_BT7__UART3_DSR 0x59 0x016
220#define MX1_PAD_BT6__BT6 0x5a 0x004
221#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032
222#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016
223#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022
224#define MX1_PAD_BT5__BT5 0x5b 0x000
225#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032
226#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016
227#define MX1_PAD_BT4__BT4 0x5c 0x000
228#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032
229#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016
230#define MX1_PAD_BT3__BT3 0x5d 0x000
231#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032
232#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022
233#define MX1_PAD_BT2__BT2 0x5e 0x004
234#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032
235#define MX1_PAD_BT2__UART3_TX 0x5e 0x016
236#define MX1_PAD_BT1__BT1 0x5f 0x000
237#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032
238#define MX1_PAD_BT1__UART3_RX 0x5f 0x022
239#define MX1_PAD_LSCLK__LSCLK 0x66 0x004
240#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032
241#define MX1_PAD_REV__REV 0x67 0x004
242#define MX1_PAD_REV__UART2_DTR 0x67 0x001
243#define MX1_PAD_REV__GPIO4_7 0x67 0x032
244#define MX1_PAD_REV__SPI2_CLK 0x67 0x006
245#define MX1_PAD_CLS__CLS 0x68 0x004
246#define MX1_PAD_CLS__UART2_DCD 0x68 0x005
247#define MX1_PAD_CLS__GPIO4_8 0x68 0x032
248#define MX1_PAD_CLS__SPI2_SS 0x68 0x002
249#define MX1_PAD_PS__PS 0x69 0x004
250#define MX1_PAD_PS__UART2_RI 0x69 0x005
251#define MX1_PAD_PS__GPIO4_9 0x69 0x032
252#define MX1_PAD_PS__SPI2_RXD 0x69 0x022
253#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004
254#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005
255#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032
256#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006
257#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004
258#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032
259#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012
260#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004
261#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032
262#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004
263#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032
264#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004
265#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032
266#define MX1_PAD_LD0__LD0 0x6f 0x004
267#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032
268#define MX1_PAD_LD1__LD1 0x70 0x004
269#define MX1_PAD_LD1__GPIO4_16 0x70 0x032
270#define MX1_PAD_LD2__LD2 0x71 0x004
271#define MX1_PAD_LD2__GPIO4_17 0x71 0x032
272#define MX1_PAD_LD3__LD3 0x72 0x004
273#define MX1_PAD_LD3__GPIO4_18 0x72 0x032
274#define MX1_PAD_LD4__LD4 0x73 0x004
275#define MX1_PAD_LD4__GPIO4_19 0x73 0x032
276#define MX1_PAD_LD5__LD5 0x74 0x004
277#define MX1_PAD_LD5__GPIO4_20 0x74 0x032
278#define MX1_PAD_LD6__LD6 0x75 0x004
279#define MX1_PAD_LD6__GPIO4_21 0x75 0x032
280#define MX1_PAD_LD7__LD7 0x76 0x004
281#define MX1_PAD_LD7__GPIO4_22 0x76 0x032
282#define MX1_PAD_LD8__LD8 0x77 0x004
283#define MX1_PAD_LD8__GPIO4_23 0x77 0x032
284#define MX1_PAD_LD9__LD9 0x78 0x004
285#define MX1_PAD_LD9__GPIO4_24 0x78 0x032
286#define MX1_PAD_LD10__LD10 0x79 0x004
287#define MX1_PAD_LD10__GPIO4_25 0x79 0x032
288#define MX1_PAD_LD11__LD11 0x7a 0x004
289#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032
290#define MX1_PAD_LD12__LD12 0x7b 0x004
291#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032
292#define MX1_PAD_LD13__LD13 0x7c 0x004
293#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032
294#define MX1_PAD_LD14__LD14 0x7d 0x004
295#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032
296#define MX1_PAD_LD15__LD15 0x7e 0x004
297#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032
298#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000
299#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032
300#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006
301
302#endif
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
new file mode 100644
index 000000000000..22f5d1db5b31
--- /dev/null
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -0,0 +1,266 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13#include "imx1-pinfunc.h"
14
15#include <dt-bindings/clock/imx1-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19/ {
20 aliases {
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 i2c0 = &i2c;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 spi0 = &cspi1;
30 spi1 = &cspi2;
31 };
32
33 aitc: aitc-interrupt-controller@00223000 {
34 compatible = "fsl,imx1-aitc", "fsl,avic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x00223000 0x1000>;
38 };
39
40 cpus {
41 #size-cells = <0>;
42 #address-cells = <1>;
43
44 cpu: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,arm920t";
47 operating-points = <200000 1900000>;
48 clock-latency = <62500>;
49 clocks = <&clks IMX1_CLK_MCU>;
50 voltage-tolerance = <5>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&aitc>;
59 ranges;
60
61 aipi@00200000 {
62 compatible = "fsl,aipi-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x00200000 0x10000>;
66 ranges;
67
68 gpt1: timer@00202000 {
69 compatible = "fsl,imx1-gpt";
70 reg = <0x00202000 0x1000>;
71 interrupts = <59>;
72 clocks = <&clks IMX1_CLK_HCLK>,
73 <&clks IMX1_CLK_PER1>;
74 clock-names = "ipg", "per";
75 };
76
77 gpt2: timer@00203000 {
78 compatible = "fsl,imx1-gpt";
79 reg = <0x00203000 0x1000>;
80 interrupts = <58>;
81 clocks = <&clks IMX1_CLK_HCLK>,
82 <&clks IMX1_CLK_PER1>;
83 clock-names = "ipg", "per";
84 };
85
86 fb: fb@00205000 {
87 compatible = "fsl,imx1-fb";
88 reg = <0x00205000 0x1000>;
89 interrupts = <14>;
90 clocks = <&clks IMX1_CLK_DUMMY>,
91 <&clks IMX1_CLK_DUMMY>,
92 <&clks IMX1_CLK_PER2>;
93 clock-names = "ipg", "ahb", "per";
94 status = "disabled";
95 };
96
97 uart1: serial@00206000 {
98 compatible = "fsl,imx1-uart";
99 reg = <0x00206000 0x1000>;
100 interrupts = <30 29 26>;
101 clocks = <&clks IMX1_CLK_HCLK>,
102 <&clks IMX1_CLK_PER1>;
103 clock-names = "ipg", "per";
104 status = "disabled";
105 };
106
107 uart2: serial@00207000 {
108 compatible = "fsl,imx1-uart";
109 reg = <0x00207000 0x1000>;
110 interrupts = <24 23 20>;
111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clks IMX1_CLK_PER1>;
113 clock-names = "ipg", "per";
114 status = "disabled";
115 };
116
117 pwm: pwm@00208000 {
118 #pwm-cells = <2>;
119 compatible = "fsl,imx1-pwm";
120 reg = <0x00208000 0x1000>;
121 interrupts = <34>;
122 clocks = <&clks IMX1_CLK_DUMMY>,
123 <&clks IMX1_CLK_PER1>;
124 clock-names = "ipg", "per";
125 };
126
127 dma: dma@00209000 {
128 compatible = "fsl,imx1-dma";
129 reg = <0x00209000 0x1000>;
130 interrupts = <61 60>;
131 clocks = <&clks IMX1_CLK_HCLK>,
132 <&clks IMX1_CLK_DMA_GATE>;
133 clock-names = "ipg", "ahb";
134 #dma-cells = <1>;
135 };
136
137 uart3: serial@0020a000 {
138 compatible = "fsl,imx1-uart";
139 reg = <0x0020a000 0x1000>;
140 interrupts = <54 4 1>;
141 clocks = <&clks IMX1_CLK_UART3_GATE>,
142 <&clks IMX1_CLK_PER1>;
143 clock-names = "ipg", "per";
144 status = "disabled";
145 };
146 };
147
148 aipi@00210000 {
149 compatible = "fsl,aipi-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x00210000 0x10000>;
153 ranges;
154
155 cspi1: cspi@00213000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,imx1-cspi";
159 reg = <0x00213000 0x1000>;
160 interrupts = <41>;
161 clocks = <&clks IMX1_CLK_DUMMY>,
162 <&clks IMX1_CLK_PER1>;
163 clock-names = "ipg", "per";
164 status = "disabled";
165 };
166
167 i2c: i2c@00217000 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 compatible = "fsl,imx1-i2c";
171 reg = <0x00217000 0x1000>;
172 interrupts = <39>;
173 clocks = <&clks IMX1_CLK_HCLK>;
174 status = "disabled";
175 };
176
177 cspi2: cspi@00219000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx1-cspi";
181 reg = <0x00219000 0x1000>;
182 interrupts = <40>;
183 clocks = <&clks IMX1_CLK_DUMMY>,
184 <&clks IMX1_CLK_PER1>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 clks: ccm@0021b000 {
190 compatible = "fsl,imx1-ccm";
191 reg = <0x0021b000 0x1000>;
192 #clock-cells = <1>;
193 };
194
195 iomuxc: iomuxc@0021c000 {
196 compatible = "fsl,imx1-iomuxc";
197 reg = <0x0021c000 0x1000>;
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges;
201
202 gpio1: gpio@0021c000 {
203 compatible = "fsl,imx1-gpio";
204 reg = <0x0021c000 0x100>;
205 interrupts = <11>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 gpio2: gpio@0021c100 {
213 compatible = "fsl,imx1-gpio";
214 reg = <0x0021c100 0x100>;
215 interrupts = <12>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 };
221
222 gpio3: gpio@0021c200 {
223 compatible = "fsl,imx1-gpio";
224 reg = <0x0021c200 0x100>;
225 interrupts = <13>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 gpio4: gpio@0021c300 {
233 compatible = "fsl,imx1-gpio";
234 reg = <0x0021c300 0x100>;
235 interrupts = <62>;
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241 };
242 };
243
244 weim: weim@00220000 {
245 #address-cells = <2>;
246 #size-cells = <1>;
247 compatible = "fsl,imx1-weim";
248 reg = <0x00220000 0x1000>;
249 clocks = <&clks IMX1_CLK_DUMMY>;
250 ranges = <
251 0 0 0x10000000 0x02000000
252 1 0 0x12000000 0x01000000
253 2 0 0x13000000 0x01000000
254 3 0 0x14000000 0x01000000
255 4 0 0x15000000 0x01000000
256 5 0 0x16000000 0x01000000
257 >;
258 status = "disabled";
259 };
260
261 esram: esram@00300000 {
262 compatible = "mmio-sram";
263 reg = <0x00300000 0x20000>;
264 };
265 };
266};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index a33f66c11b73..57e29977ba06 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -60,10 +60,10 @@
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
61 pinctrl-0 = <&lcdif_24bit_pins_a>; 61 pinctrl-0 = <&lcdif_24bit_pins_a>;
62 lcd-supply = <&reg_lcd_3v3>; 62 lcd-supply = <&reg_lcd_3v3>;
63 display = <&display>; 63 display = <&display0>;
64 status = "okay"; 64 status = "okay";
65 65
66 display: display { 66 display0: display0 {
67 bits-per-pixel = <32>; 67 bits-per-pixel = <32>;
68 bus-width = <24>; 68 bus-width = <24>;
69 69
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 9238a95d8e62..88eebb15da6a 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -247,6 +247,7 @@
247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
248 248
249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
250#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
250#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 251#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
251#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 252#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
252 253
@@ -260,6 +261,7 @@
260#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 261#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
261 262
262#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 263#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
264#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
263#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 265#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
264#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 266#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
265 267
@@ -269,31 +271,46 @@
269#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 271#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
270 272
271#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 273#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
274#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
272#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 275#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
273#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 276#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
274 277
275#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 278#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
279#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
276#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 280#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
277 281
278#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 282#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
283#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
279#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 284#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
280 285
281#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 286#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
287#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
282#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 288#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
289#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
283 290
284#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 291#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
292#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
285#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 293#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
294#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
286 295
287#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 296#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
297#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
298#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
288#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 299#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
289 300
290#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 301#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
302#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
303#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
291#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 304#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
292 305
293#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 306#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
307#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
308#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
294#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 309#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
295 310
296#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 311#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
312#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
313#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
297#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 314#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
298 315
299#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 316#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
@@ -303,18 +320,24 @@
303#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 320#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
304 321
305#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 322#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
323#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
306#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 324#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
307 325
308#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 326#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
327#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
309#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 328#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
310 329
311#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 330#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
331#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
312#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 332#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
313 333
314#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 334#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
335#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
336#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
315#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 337#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
316 338
317#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 339#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
340#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
318#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 341#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
319 342
320#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 343#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
@@ -328,6 +351,7 @@
328 351
329#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 352#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
330#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 353#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
354#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
331#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 355#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
332 356
333#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 357#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
@@ -342,6 +366,7 @@
342 366
343#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 367#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
344#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 368#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
369#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
345#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 370#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
346 371
347#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 372#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
@@ -349,14 +374,17 @@
349#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 374#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
350 375
351#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 376#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
377#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
352#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 378#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
353#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 379#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
354 380
355#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 381#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
382#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
356#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 383#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
357#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 384#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
358 385
359#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 386#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
387#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
360#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 388#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
361 389
362#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 390#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
@@ -457,14 +485,15 @@
457#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 485#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
458 486
459#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 487#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
460#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
461#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 488#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
462 489
463#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 490#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
464#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 491#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
492#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
465#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 493#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
466 494
467#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 495#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
496#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
468#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 497#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
469 498
470#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 499#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index c1740396b2c9..58d3c3cf2923 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -239,6 +239,7 @@
239 }; 239 };
240 240
241 ssi2: ssi@50014000 { 241 ssi2: ssi@50014000 {
242 #sound-dai-cells = <0>;
242 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 243 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
243 reg = <0x50014000 0x4000>; 244 reg = <0x50014000 0x4000>;
244 interrupts = <11>; 245 interrupts = <11>;
@@ -274,6 +275,7 @@
274 }; 275 };
275 276
276 ssi1: ssi@50034000 { 277 ssi1: ssi@50034000 {
278 #sound-dai-cells = <0>;
277 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 279 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
278 reg = <0x50034000 0x4000>; 280 reg = <0x50034000 0x4000>;
279 interrupts = <12>; 281 interrupts = <12>;
@@ -453,7 +455,7 @@
453 }; 455 };
454 456
455 sdma: sdma@53fd4000 { 457 sdma: sdma@53fd4000 {
456 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; 458 compatible = "fsl,imx25-sdma";
457 reg = <0x53fd4000 0x4000>; 459 reg = <0x53fd4000 0x4000>;
458 clocks = <&clks 112>, <&clks 68>; 460 clocks = <&clks 112>, <&clks 68>;
459 clock-names = "ipg", "ahb"; 461 clock-names = "ipg", "ahb";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 2b6d489dae69..da306c5dd678 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -67,6 +67,16 @@
67 pinctrl-names = "default"; 67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; 68 pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
69 status = "okay"; 69 status = "okay";
70
71 adc@0 {
72 compatible = "maxim,max1027";
73 reg = <0>;
74 interrupt-parent = <&gpio5>;
75 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_max1027>;
78 spi-max-frequency = <10000000>;
79 };
70}; 80};
71 81
72&cspi2 { 82&cspi2 {
@@ -189,6 +199,13 @@
189 >; 199 >;
190 }; 200 };
191 201
202 pinctrl_max1027: max1027 {
203 fsl,pins = <
204 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
205 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
206 >;
207 };
208
192 pinctrl_pwm: pwmgrp { 209 pinctrl_pwm: pwmgrp {
193 fsl,pins = < 210 fsl,pins = <
194 MX27_PAD_PWMO__PWMO 0x0 211 MX27_PAD_PWMO__PWMO 0x0
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 221cac4fb2cd..1f38a052ad4b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -83,10 +83,10 @@
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 pinctrl-0 = <&lcdif_16bit_pins_a 84 pinctrl-0 = <&lcdif_16bit_pins_a
85 &lcdif_pins_apf28dev>; 85 &lcdif_pins_apf28dev>;
86 display = <&display>; 86 display = <&display0>;
87 status = "okay"; 87 status = "okay";
88 88
89 display: display { 89 display0: display0 {
90 bits-per-pixel = <16>; 90 bits-per-pixel = <16>;
91 bus-width = <16>; 91 bus-width = <16>;
92 92
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index e1ce9179db63..1092b761d7ac 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -94,10 +94,10 @@
94 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 pinctrl-0 = <&lcdif_24bit_pins_a 95 pinctrl-0 = <&lcdif_24bit_pins_a
96 &lcdif_pins_apx4>; 96 &lcdif_pins_apx4>;
97 display = <&display>; 97 display = <&display0>;
98 status = "okay"; 98 status = "okay";
99 99
100 display: display { 100 display0: display0 {
101 bits-per-pixel = <32>; 101 bits-per-pixel = <32>;
102 bus-width = <24>; 102 bus-width = <24>;
103 103
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 7d51459de5e8..ef944b6d4f01 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -177,10 +177,10 @@
177 pinctrl-0 = <&lcdif_18bit_pins_cfa10049 177 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
178 &lcdif_pins_cfa10049 178 &lcdif_pins_cfa10049
179 &lcdif_pins_cfa10049_pullup>; 179 &lcdif_pins_cfa10049_pullup>;
180 display = <&display>; 180 display = <&display0>;
181 status = "okay"; 181 status = "okay";
182 182
183 display: display { 183 display0: display0 {
184 bits-per-pixel = <32>; 184 bits-per-pixel = <32>;
185 bus-width = <18>; 185 bus-width = <18>;
186 186
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index c3900e7ba331..6a34114bec29 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -92,10 +92,10 @@
92 pinctrl-0 = <&lcdif_18bit_pins_cfa10055 92 pinctrl-0 = <&lcdif_18bit_pins_cfa10055
93 &lcdif_pins_cfa10055 93 &lcdif_pins_cfa10055
94 &lcdif_pins_cfa10055_pullup>; 94 &lcdif_pins_cfa10055_pullup>;
95 display = <&display>; 95 display = <&display0>;
96 status = "okay"; 96 status = "okay";
97 97
98 display: display { 98 display0: display0 {
99 bits-per-pixel = <32>; 99 bits-per-pixel = <32>;
100 bus-width = <18>; 100 bus-width = <18>;
101 101
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index cef959a97219..ba6495ca44d2 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -64,10 +64,10 @@
64 pinctrl-0 = <&lcdif_24bit_pins_a 64 pinctrl-0 = <&lcdif_24bit_pins_a
65 &lcdif_pins_cfa10056 65 &lcdif_pins_cfa10056
66 &lcdif_pins_cfa10056_pullup >; 66 &lcdif_pins_cfa10056_pullup >;
67 display = <&display>; 67 display = <&display0>;
68 status = "okay"; 68 status = "okay";
69 69
70 display: display { 70 display0: display0 {
71 bits-per-pixel = <32>; 71 bits-per-pixel = <32>;
72 bus-width = <24>; 72 bus-width = <24>;
73 73
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index c4e00ce4b6da..5df0b24eaf59 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -78,10 +78,10 @@
78 pinctrl-names = "default"; 78 pinctrl-names = "default";
79 pinctrl-0 = <&lcdif_18bit_pins_cfa10057 79 pinctrl-0 = <&lcdif_18bit_pins_cfa10057
80 &lcdif_pins_cfa10057>; 80 &lcdif_pins_cfa10057>;
81 display = <&display>; 81 display = <&display0>;
82 status = "okay"; 82 status = "okay";
83 83
84 display: display { 84 display0: display0 {
85 bits-per-pixel = <32>; 85 bits-per-pixel = <32>;
86 bus-width = <18>; 86 bus-width = <18>;
87 87
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 7c9cc783f0d1..f5c6dce34abe 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -51,10 +51,10 @@
51 pinctrl-names = "default"; 51 pinctrl-names = "default";
52 pinctrl-0 = <&lcdif_24bit_pins_a 52 pinctrl-0 = <&lcdif_24bit_pins_a
53 &lcdif_pins_cfa10058>; 53 &lcdif_pins_cfa10058>;
54 display = <&display>; 54 display = <&display0>;
55 status = "okay"; 55 status = "okay";
56 56
57 display: display { 57 display0: display0 {
58 bits-per-pixel = <32>; 58 bits-per-pixel = <32>;
59 bus-width = <24>; 59 bus-width = <24>;
60 60
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index e4cc44c98585..09664fcf5afb 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -124,10 +124,10 @@
124 pinctrl-0 = <&lcdif_24bit_pins_a 124 pinctrl-0 = <&lcdif_24bit_pins_a
125 &lcdif_pins_evk>; 125 &lcdif_pins_evk>;
126 lcd-supply = <&reg_lcd_3v3>; 126 lcd-supply = <&reg_lcd_3v3>;
127 display = <&display>; 127 display = <&display0>;
128 status = "okay"; 128 status = "okay";
129 129
130 display: display { 130 display0: display0 {
131 bits-per-pixel = <32>; 131 bits-per-pixel = <32>;
132 bus-width = <24>; 132 bus-width = <24>;
133 133
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9348ce59dda4..2df63bee6f4e 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -115,10 +115,10 @@
115 pinctrl-names = "default"; 115 pinctrl-names = "default";
116 pinctrl-0 = <&lcdif_24bit_pins_a 116 pinctrl-0 = <&lcdif_24bit_pins_a
117 &lcdif_pins_m28>; 117 &lcdif_pins_m28>;
118 display = <&display>; 118 display = <&display0>;
119 status = "okay"; 119 status = "okay";
120 120
121 display: display0 { 121 display0: display0 {
122 bits-per-pixel = <32>; 122 bits-per-pixel = <32>;
123 bus-width = <24>; 123 bus-width = <24>;
124 124
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index b3c09ae3b928..e35cc6ba3ca6 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -81,10 +81,10 @@
81 pinctrl-names = "default"; 81 pinctrl-names = "default";
82 pinctrl-0 = <&lcdif_24bit_pins_a 82 pinctrl-0 = <&lcdif_24bit_pins_a
83 &lcdif_pins_m28>; 83 &lcdif_pins_m28>;
84 display = <&display>; 84 display = <&display0>;
85 status = "okay"; 85 status = "okay";
86 86
87 display: display { 87 display0: display0 {
88 bits-per-pixel = <16>; 88 bits-per-pixel = <16>;
89 bus-width = <18>; 89 bus-width = <18>;
90 90
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index e14bd86f3e99..a5b27c85a91c 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -21,12 +21,15 @@
21 aliases { 21 aliases {
22 can0 = &can0; 22 can0 = &can0;
23 can1 = &can1; 23 can1 = &can1;
24 display = &display; 24 display = &display0;
25 ds1339 = &ds1339; 25 ds1339 = &ds1339;
26 gpio5 = &gpio5; 26 gpio5 = &gpio5;
27 lcdif = &lcdif; 27 lcdif = &lcdif;
28 lcdif_23bit_pins = &tx28_lcdif_23bit_pins; 28 lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
29 lcdif_24bit_pins = &lcdif_24bit_pins_a; 29 lcdif_24bit_pins = &lcdif_24bit_pins_a;
30 reg_can_xcvr = &reg_can_xcvr;
31 spi_gpio = &spi_gpio;
32 spi_mxs = &ssp3;
30 stk5led = &user_led; 33 stk5led = &user_led;
31 usbotg = &usb0; 34 usbotg = &usb0;
32 }; 35 };
@@ -37,7 +40,7 @@
37 40
38 onewire { 41 onewire {
39 compatible = "w1-gpio"; 42 compatible = "w1-gpio";
40 gpios = <&gpio2 7 0>; 43 gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
41 status = "disabled"; 44 status = "disabled";
42 }; 45 };
43 46
@@ -52,7 +55,7 @@
52 regulator-name = "usb0_vbus"; 55 regulator-name = "usb0_vbus";
53 regulator-min-microvolt = <5000000>; 56 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>;
55 gpio = <&gpio0 18 0>; 58 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
56 enable-active-high; 59 enable-active-high;
57 }; 60 };
58 61
@@ -62,7 +65,7 @@
62 regulator-name = "usb1_vbus"; 65 regulator-name = "usb1_vbus";
63 regulator-min-microvolt = <5000000>; 66 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>;
65 gpio = <&gpio3 27 0>; 68 gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
66 enable-active-high; 69 enable-active-high;
67 }; 70 };
68 71
@@ -90,7 +93,7 @@
90 regulator-name = "CAN XCVR"; 93 regulator-name = "CAN XCVR";
91 regulator-min-microvolt = <3300000>; 94 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>; 95 regulator-max-microvolt = <3300000>;
93 gpio = <&gpio1 0 0>; 96 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
94 pinctrl-names = "default"; 97 pinctrl-names = "default";
95 pinctrl-0 = <&tx28_flexcan_xcvr_pins>; 98 pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
96 }; 99 };
@@ -101,7 +104,7 @@
101 regulator-name = "LCD POWER"; 104 regulator-name = "LCD POWER";
102 regulator-min-microvolt = <3300000>; 105 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>;
104 gpio = <&gpio1 31 0>; 107 gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
105 enable-active-high; 108 enable-active-high;
106 }; 109 };
107 110
@@ -111,7 +114,7 @@
111 regulator-name = "LCD RESET"; 114 regulator-name = "LCD RESET";
112 regulator-min-microvolt = <3300000>; 115 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>;
114 gpio = <&gpio3 30 0>; 117 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
115 startup-delay-us = <300000>; 118 startup-delay-us = <300000>;
116 enable-active-high; 119 enable-active-high;
117 regulator-always-on; 120 regulator-always-on;
@@ -143,7 +146,7 @@
143 146
144 user_led: user { 147 user_led: user {
145 label = "Heartbeat"; 148 label = "Heartbeat";
146 gpios = <&gpio4 10 0>; 149 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
147 linux,default-trigger = "heartbeat"; 150 linux,default-trigger = "heartbeat";
148 }; 151 };
149 }; 152 };
@@ -172,16 +175,16 @@
172 matrix_keypad: matrix-keypad@0 { 175 matrix_keypad: matrix-keypad@0 {
173 compatible = "gpio-matrix-keypad"; 176 compatible = "gpio-matrix-keypad";
174 col-gpios = < 177 col-gpios = <
175 &gpio5 0 0 178 &gpio5 0 GPIO_ACTIVE_HIGH
176 &gpio5 1 0 179 &gpio5 1 GPIO_ACTIVE_HIGH
177 &gpio5 2 0 180 &gpio5 2 GPIO_ACTIVE_HIGH
178 &gpio5 3 0 181 &gpio5 3 GPIO_ACTIVE_HIGH
179 >; 182 >;
180 row-gpios = < 183 row-gpios = <
181 &gpio5 4 0 184 &gpio5 4 GPIO_ACTIVE_HIGH
182 &gpio5 5 0 185 &gpio5 5 GPIO_ACTIVE_HIGH
183 &gpio5 6 0 186 &gpio5 6 GPIO_ACTIVE_HIGH
184 &gpio5 7 0 187 &gpio5 7 GPIO_ACTIVE_HIGH
185 >; 188 >;
186 /* sample keymap */ 189 /* sample keymap */
187 linux,keymap = < 190 linux,keymap = <
@@ -203,6 +206,44 @@
203 col-scan-delay-us = <5000>; 206 col-scan-delay-us = <5000>;
204 linux,no-autorepeat; 207 linux,no-autorepeat;
205 }; 208 };
209
210 spi_gpio: spi-gpio {
211 compatible = "spi-gpio";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&tx28_spi_gpio_pins>;
216
217 gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
218 gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
219 gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
220 num-chipselects = <3>;
221 cs-gpios = <
222 &gpio2 27 GPIO_ACTIVE_LOW
223 &gpio3 8 GPIO_ACTIVE_LOW
224 &gpio3 9 GPIO_ACTIVE_LOW
225 >;
226 /* enable this and disable ssp3 below, if you need full duplex SPI transfer */
227 status = "disabled";
228
229 spi@0 {
230 compatible = "spidev";
231 reg = <0>;
232 spi-max-frequency = <57600000>;
233 };
234
235 spi@1 {
236 compatible = "spidev";
237 reg = <1>;
238 spi-max-frequency = <57600000>;
239 };
240
241 spi@2 {
242 compatible = "spidev";
243 reg = <2>;
244 spi-max-frequency = <57600000>;
245 };
246 };
206}; 247};
207 248
208/* 2nd TX-Std UART - (A)UART1 */ 249/* 2nd TX-Std UART - (A)UART1 */
@@ -284,8 +325,8 @@
284 pinctrl-0 = <&tx28_edt_ft5x06_pins>; 325 pinctrl-0 = <&tx28_edt_ft5x06_pins>;
285 interrupt-parent = <&gpio2>; 326 interrupt-parent = <&gpio2>;
286 interrupts = <5 0>; 327 interrupts = <5 0>;
287 reset-gpios = <&gpio2 6 1>; 328 reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
288 wake-gpios = <&gpio4 9 0>; 329 wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
289 }; 330 };
290 331
291 touchscreen: tsc2007@48 { 332 touchscreen: tsc2007@48 {
@@ -295,7 +336,7 @@
295 pinctrl-0 = <&tx28_tsc2007_pins>; 336 pinctrl-0 = <&tx28_tsc2007_pins>;
296 interrupt-parent = <&gpio3>; 337 interrupt-parent = <&gpio3>;
297 interrupts = <20 0>; 338 interrupts = <20 0>;
298 pendown-gpio = <&gpio3 20 1>; 339 pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
299 ti,x-plate-ohms = /bits/ 16 <660>; 340 ti,x-plate-ohms = /bits/ 16 <660>;
300 }; 341 };
301 342
@@ -309,10 +350,10 @@
309 pinctrl-names = "default"; 350 pinctrl-names = "default";
310 pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; 351 pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
311 lcd-supply = <&reg_lcd>; 352 lcd-supply = <&reg_lcd>;
312 display = <&display>; 353 display = <&display0>;
313 status = "okay"; 354 status = "okay";
314 355
315 display: display@0 { 356 display0: display0 {
316 bits-per-pixel = <32>; 357 bits-per-pixel = <32>;
317 bus-width = <24>; 358 bus-width = <24>;
318 display-timings { 359 display-timings {
@@ -558,6 +599,20 @@
558 fsl,pull-up = <MXS_PULL_DISABLE>; 599 fsl,pull-up = <MXS_PULL_DISABLE>;
559 }; 600 };
560 601
602 tx28_spi_gpio_pins: spi-gpiogrp {
603 fsl,pinmux-ids = <
604 MX28_PAD_AUART2_RX__GPIO_3_8
605 MX28_PAD_AUART2_TX__GPIO_3_9
606 MX28_PAD_SSP3_SCK__GPIO_2_24
607 MX28_PAD_SSP3_MOSI__GPIO_2_25
608 MX28_PAD_SSP3_MISO__GPIO_2_26
609 MX28_PAD_SSP3_SS0__GPIO_2_27
610 >;
611 fsl,drive-strength = <MXS_DRIVE_8mA>;
612 fsl,voltage = <MXS_VOLTAGE_HIGH>;
613 fsl,pull-up = <MXS_PULL_DISABLE>;
614 };
615
561 tx28_tsc2007_pins: tx28-tsc2007-pins { 616 tx28_tsc2007_pins: tx28-tsc2007-pins {
562 fsl,pinmux-ids = < 617 fsl,pinmux-ids = <
563 MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ 618 MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
@@ -619,17 +674,23 @@
619 clock-frequency = <57600000>; 674 clock-frequency = <57600000>;
620 status = "okay"; 675 status = "okay";
621 676
622 spidev0: spi@0 { 677 spi@0 {
623 compatible = "spidev"; 678 compatible = "spidev";
624 reg = <0>; 679 reg = <0>;
625 spi-max-frequency = <57600000>; 680 spi-max-frequency = <57600000>;
626 }; 681 };
627 682
628 spidev1: spi@1 { 683 spi@1 {
629 compatible = "spidev"; 684 compatible = "spidev";
630 reg = <1>; 685 reg = <1>;
631 spi-max-frequency = <57600000>; 686 spi-max-frequency = <57600000>;
632 }; 687 };
688
689 spi@2 {
690 compatible = "spidev";
691 reg = <2>;
692 spi-max-frequency = <57600000>;
693 };
633}; 694};
634 695
635&usb0 { 696&usb0 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index a95cc5358ff4..47f68ac868d4 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -489,6 +489,38 @@
489 fsl,pull-up = <MXS_PULL_DISABLE>; 489 fsl,pull-up = <MXS_PULL_DISABLE>;
490 }; 490 };
491 491
492 mmc1_4bit_pins_a: mmc1-4bit@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 MX28_PAD_GPMI_D00__SSP1_D0
496 MX28_PAD_GPMI_D01__SSP1_D1
497 MX28_PAD_GPMI_D02__SSP1_D2
498 MX28_PAD_GPMI_D03__SSP1_D3
499 MX28_PAD_GPMI_RDY1__SSP1_CMD
500 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
501 MX28_PAD_GPMI_WRN__SSP1_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
506 };
507
508 mmc1_cd_cfg: mmc1-cd-cfg {
509 fsl,pinmux-ids = <
510 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
511 >;
512 fsl,pull-up = <MXS_PULL_DISABLE>;
513 };
514
515 mmc1_sck_cfg: mmc1-sck-cfg {
516 fsl,pinmux-ids = <
517 MX28_PAD_GPMI_WRN__SSP1_SCK
518 >;
519 fsl,drive-strength = <MXS_DRIVE_12mA>;
520 fsl,pull-up = <MXS_PULL_DISABLE>;
521 };
522
523
492 mmc2_4bit_pins_a: mmc2-4bit@0 { 524 mmc2_4bit_pins_a: mmc2-4bit@0 {
493 reg = <0>; 525 reg = <0>;
494 fsl,pinmux-ids = < 526 fsl,pinmux-ids = <
@@ -553,6 +585,17 @@
553 fsl,pull-up = <MXS_PULL_ENABLE>; 585 fsl,pull-up = <MXS_PULL_ENABLE>;
554 }; 586 };
555 587
588 i2c1_pins_b: i2c1@1 {
589 reg = <1>;
590 fsl,pinmux-ids = <
591 MX28_PAD_AUART2_CTS__I2C1_SCL
592 MX28_PAD_AUART2_RTS__I2C1_SDA
593 >;
594 fsl,drive-strength = <MXS_DRIVE_8mA>;
595 fsl,voltage = <MXS_VOLTAGE_HIGH>;
596 fsl,pull-up = <MXS_PULL_ENABLE>;
597 };
598
556 saif0_pins_a: saif0@0 { 599 saif0_pins_a: saif0@0 {
557 reg = <0>; 600 reg = <0>;
558 fsl,pinmux-ids = < 601 fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 442e216ca9d9..6932928f3b45 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -114,6 +114,7 @@
114 }; 114 };
115 115
116 ssi1: ssi@43fa0000 { 116 ssi1: ssi@43fa0000 {
117 #sound-dai-cells = <0>;
117 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; 118 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
118 reg = <0x43fa0000 0x4000>; 119 reg = <0x43fa0000 0x4000>;
119 interrupts = <11>; 120 interrupts = <11>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index c0e0f60ab6b2..620b0f030591 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -145,6 +145,7 @@
145 }; 145 };
146 146
147 ssi2: ssi@50014000 { 147 ssi2: ssi@50014000 {
148 #sound-dai-cells = <0>;
148 compatible = "fsl,imx50-ssi", 149 compatible = "fsl,imx50-ssi",
149 "fsl,imx51-ssi", 150 "fsl,imx51-ssi",
150 "fsl,imx21-ssi"; 151 "fsl,imx21-ssi";
@@ -454,6 +455,7 @@
454 }; 455 };
455 456
456 ssi1: ssi@63fcc000 { 457 ssi1: ssi@63fcc000 {
458 #sound-dai-cells = <0>;
457 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", 459 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
458 "fsl,imx21-ssi"; 460 "fsl,imx21-ssi";
459 reg = <0x63fcc000 0x4000>; 461 reg = <0x63fcc000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 17c05a6fa776..92660e1fe1fc 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -210,6 +210,7 @@
210 }; 210 };
211 211
212 ssi2: ssi@70014000 { 212 ssi2: ssi@70014000 {
213 #sound-dai-cells = <0>;
213 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
214 reg = <0x70014000 0x4000>; 215 reg = <0x70014000 0x4000>;
215 interrupts = <30>; 216 interrupts = <30>;
@@ -499,6 +500,7 @@
499 }; 500 };
500 501
501 ssi1: ssi@83fcc000 { 502 ssi1: ssi@83fcc000 {
503 #sound-dai-cells = <0>;
502 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
503 reg = <0x83fcc000 0x4000>; 505 reg = <0x83fcc000 0x4000>;
504 interrupts = <29>; 506 interrupts = <29>;
@@ -554,6 +556,7 @@
554 }; 556 };
555 557
556 ssi3: ssi@83fe8000 { 558 ssi3: ssi@83fe8000 {
559 #sound-dai-cells = <0>;
557 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
558 reg = <0x83fe8000 0x4000>; 561 reg = <0x83fe8000 0x4000>;
559 interrupts = <96>; 562 interrupts = <96>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 5ec1590ff7bc..1d325576bcc0 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -265,7 +265,7 @@
265 }; 265 };
266 266
267 pmic: dialog@48 { 267 pmic: dialog@48 {
268 compatible = "dialog,da9053", "dialog,da9052"; 268 compatible = "dlg,da9053", "dlg,da9052";
269 reg = <0x48>; 269 reg = <0x48>;
270 }; 270 };
271}; 271};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 6b675a02066f..f91725b2e8ab 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -221,6 +221,7 @@
221 }; 221 };
222 222
223 ssi2: ssi@50014000 { 223 ssi2: ssi@50014000 {
224 #sound-dai-cells = <0>;
224 compatible = "fsl,imx53-ssi", 225 compatible = "fsl,imx53-ssi",
225 "fsl,imx51-ssi", 226 "fsl,imx51-ssi",
226 "fsl,imx21-ssi"; 227 "fsl,imx21-ssi";
@@ -669,6 +670,7 @@
669 }; 670 };
670 671
671 ssi1: ssi@63fcc000 { 672 ssi1: ssi@63fcc000 {
673 #sound-dai-cells = <0>;
672 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 674 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
673 "fsl,imx21-ssi"; 675 "fsl,imx21-ssi";
674 reg = <0x63fcc000 0x4000>; 676 reg = <0x63fcc000 0x4000>;
@@ -696,6 +698,7 @@
696 }; 698 };
697 699
698 ssi3: ssi@63fe8000 { 700 ssi3: ssi@63fe8000 {
701 #sound-dai-cells = <0>;
699 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 702 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
700 "fsl,imx21-ssi"; 703 "fsl,imx21-ssi";
701 reg = <0x63fe8000 0x4000>; 704 reg = <0x63fe8000 0x4000>;
@@ -752,5 +755,10 @@
752 reg = <0xf8000000 0x20000>; 755 reg = <0xf8000000 0x20000>;
753 clocks = <&clks IMX5_CLK_OCRAM>; 756 clocks = <&clks IMX5_CLK_OCRAM>;
754 }; 757 };
758
759 pmu {
760 compatible = "arm,cortex-a8-pmu";
761 interrupts = <77>;
762 };
755 }; 763 };
756}; 764};
diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts
new file mode 100644
index 000000000000..a4b700cef188
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw552x.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6dl.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
19 compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
20};
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 71598546087f..44a0e6736bb1 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,206 +1,13 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King
3 */ 4 */
4/dts-v1/; 5/dts-v1/;
5 6
6#include "imx6dl.dtsi" 7#include "imx6dl.dtsi"
7#include "imx6qdl-microsom.dtsi" 8#include "imx6qdl-hummingboard.dtsi"
8#include "imx6qdl-microsom-ar8035.dtsi"
9 9
10/ { 10/ {
11 model = "SolidRun HummingBoard DL/Solo"; 11 model = "SolidRun HummingBoard Solo/DualLite";
12 compatible = "solidrun,hummingboard", "fsl,imx6dl"; 12 compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 ir_recv: ir-receiver {
19 compatible = "gpio-ir-receiver";
20 gpios = <&gpio1 2 1>;
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
27
28 reg_3p3v: 3p3v {
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
34 };
35
36 reg_usbh1_vbus: usb-h1-vbus {
37 compatible = "regulator-fixed";
38 enable-active-high;
39 gpio = <&gpio1 0 0>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
42 regulator-name = "usb_h1_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 };
46
47 reg_usbotg_vbus: usb-otg-vbus {
48 compatible = "regulator-fixed";
49 enable-active-high;
50 gpio = <&gpio3 22 0>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
53 regulator-name = "usb_otg_vbus";
54 regulator-min-microvolt = <5000000>;
55 regulator-max-microvolt = <5000000>;
56 };
57 };
58
59 sound-spdif {
60 compatible = "fsl,imx-audio-spdif";
61 model = "On-board SPDIF";
62 /* IMX6 doesn't implement this yet */
63 spdif-controller = <&spdif>;
64 spdif-out;
65 };
66};
67
68&can1 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
71 status = "okay";
72};
73
74&hdmi {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
77 ddc-i2c-bus = <&i2c2>;
78 status = "okay";
79};
80
81&i2c1 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
84
85 /*
86 * Not fitted on Carrier-1 board... yet
87 status = "okay";
88
89 rtc: pcf8523@68 {
90 compatible = "nxp,pcf8523";
91 reg = <0x68>;
92 };
93 */
94};
95
96&i2c2 {
97 clock-frequency = <100000>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
100 status = "okay";
101};
102
103&iomuxc {
104 hummingboard {
105 pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
106 fsl,pins = <
107 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
108 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
109 >;
110 };
111
112 pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
113 fsl,pins = <
114 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
115 >;
116 };
117
118 pinctrl_hummingboard_hdmi: hummingboard-hdmi {
119 fsl,pins = <
120 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
121 >;
122 };
123
124 pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
125 fsl,pins = <
126 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
127 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
128 >;
129 };
130
131 pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
132 fsl,pins = <
133 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
134 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
135 >;
136 };
137
138 pinctrl_hummingboard_spdif: hummingboard-spdif {
139 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
140 };
141
142 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
143 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
144 };
145
146 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
147 /*
148 * Similar to pinctrl_usbotg_2, but we want it
149 * pulled down for a fixed host connection.
150 */
151 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
152 };
153
154 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
155 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
156 };
157
158 pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
159 fsl,pins = <
160 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
161 >;
162 };
163
164 pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
165 fsl,pins = <
166 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
167 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
168 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
169 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
170 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
171 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
172 >;
173 };
174 };
175};
176
177&spdif {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
180 status = "okay";
181};
182
183&usbh1 {
184 disable-over-current;
185 vbus-supply = <&reg_usbh1_vbus>;
186 status = "okay";
187};
188
189&usbotg {
190 disable-over-current;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
193 vbus-supply = <&reg_usbotg_vbus>;
194 status = "okay";
195};
196
197&usdhc2 {
198 pinctrl-names = "default";
199 pinctrl-0 = <
200 &pinctrl_hummingboard_usdhc2_aux
201 &pinctrl_hummingboard_usdhc2
202 >;
203 vmmc-supply = <&reg_3p3v>;
204 cd-gpios = <&gpio1 4 0>;
205 status = "okay";
206}; 13};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 22e6f8e657d2..822ffb231c57 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include <dt-bindings/gpio/gpio.h>
13#include "imx6q.dtsi" 14#include "imx6q.dtsi"
14 15
15/ { 16/ {
@@ -18,7 +19,6 @@
18 19
19 /* these are used by bootloader for disabling nodes */ 20 /* these are used by bootloader for disabling nodes */
20 aliases { 21 aliases {
21 ethernet0 = &fec;
22 ethernet1 = &eth1; 22 ethernet1 = &eth1;
23 i2c0 = &i2c1; 23 i2c0 = &i2c1;
24 i2c1 = &i2c2; 24 i2c1 = &i2c2;
@@ -26,12 +26,10 @@
26 led0 = &led0; 26 led0 = &led0;
27 led1 = &led1; 27 led1 = &led1;
28 led2 = &led2; 28 led2 = &led2;
29 sky2 = &eth1;
30 ssi0 = &ssi1; 29 ssi0 = &ssi1;
31 spi0 = &ecspi1; 30 spi0 = &ecspi1;
32 usb0 = &usbh1; 31 usb0 = &usbh1;
33 usb1 = &usbotg; 32 usb1 = &usbotg;
34 usdhc2 = &usdhc3;
35 }; 33 };
36 34
37 chosen { 35 chosen {
@@ -40,23 +38,25 @@
40 38
41 leds { 39 leds {
42 compatible = "gpio-leds"; 40 compatible = "gpio-leds";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpio_leds>;
43 43
44 led0: user1 { 44 led0: user1 {
45 label = "user1"; 45 label = "user1";
46 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 46 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */
47 default-state = "on"; 47 default-state = "on";
48 linux,default-trigger = "heartbeat"; 48 linux,default-trigger = "heartbeat";
49 }; 49 };
50 50
51 led1: user2 { 51 led1: user2 {
52 label = "user2"; 52 label = "user2";
53 gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ 53 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */
54 default-state = "off"; 54 default-state = "off";
55 }; 55 };
56 56
57 led2: user3 { 57 led2: user3 {
58 label = "user3"; 58 label = "user3";
59 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 59 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */
60 default-state = "off"; 60 default-state = "off";
61 }; 61 };
62 }; 62 };
@@ -67,7 +67,9 @@
67 67
68 pps { 68 pps {
69 compatible = "pps-gpio"; 69 compatible = "pps-gpio";
70 gpios = <&gpio1 5 0>; 70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_gpio_leds>;
72 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
71 status = "okay"; 73 status = "okay";
72 }; 74 };
73 75
@@ -109,7 +111,7 @@
109 regulator-name = "usb_otg_vbus"; 111 regulator-name = "usb_otg_vbus";
110 regulator-min-microvolt = <5000000>; 112 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>;
112 gpio = <&gpio3 22 0>; 114 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
113 enable-active-high; 115 enable-active-high;
114 }; 116 };
115 }; 117 };
@@ -137,7 +139,7 @@
137 139
138&ecspi1 { 140&ecspi1 {
139 fsl,spi-num-chipselects = <1>; 141 fsl,spi-num-chipselects = <1>;
140 cs-gpios = <&gpio3 19 0>; 142 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
141 pinctrl-names = "default"; 143 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_ecspi1>; 144 pinctrl-0 = <&pinctrl_ecspi1>;
143 status = "okay"; 145 status = "okay";
@@ -153,7 +155,7 @@
153 pinctrl-names = "default"; 155 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
155 phy-mode = "rgmii"; 157 phy-mode = "rgmii";
156 phy-reset-gpios = <&gpio1 30 0>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
157 status = "okay"; 159 status = "okay";
158}; 160};
159 161
@@ -199,11 +201,6 @@
199 #gpio-cells = <2>; 201 #gpio-cells = <2>;
200 }; 202 };
201 203
202 hwmon: gsc@29 {
203 compatible = "gw,gsp";
204 reg = <0x29>;
205 };
206
207 rtc: ds1672@68 { 204 rtc: ds1672@68 {
208 compatible = "dallas,ds1672"; 205 compatible = "dallas,ds1672";
209 reg = <0x68>; 206 reg = <0x68>;
@@ -314,16 +311,6 @@
314 }; 311 };
315 }; 312 };
316 }; 313 };
317
318 pciswitch: pex8609@3f {
319 compatible = "plx,pex8609";
320 reg = <0x3f>;
321 };
322
323 pciclkgen: si52147@6b {
324 compatible = "sil,si52147";
325 reg = <0x6b>;
326 };
327}; 314};
328 315
329&i2c3 { 316&i2c3 {
@@ -345,51 +332,73 @@
345 VDDIO-supply = <&reg_3p3v>; 332 VDDIO-supply = <&reg_3p3v>;
346 }; 333 };
347 334
348 hdmiin: adv7611@4c {
349 compatible = "adi,adv7611";
350 reg = <0x4c>;
351 };
352
353 touchscreen: egalax_ts@04 { 335 touchscreen: egalax_ts@04 {
354 compatible = "eeti,egalax_ts"; 336 compatible = "eeti,egalax_ts";
355 reg = <0x04>; 337 reg = <0x04>;
356 interrupt-parent = <&gpio7>; 338 interrupt-parent = <&gpio7>;
357 interrupts = <12 2>; /* gpio7_12 active low */ 339 interrupts = <12 2>;
358 wakeup-gpios = <&gpio7 12 0>; 340 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
359 }; 341 };
342};
360 343
361 videoout: adv7393@2a { 344&ldb {
362 compatible = "adi,adv7393"; 345 status = "okay";
363 reg = <0x2a>; 346};
364 }; 347
348&pcie {
349 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
350 status = "okay";
365 351
366 videoin: adv7180@20 { 352 eth1: sky2@8 { /* MAC/PHY on bus 8 */
367 compatible = "adi,adv7180"; 353 compatible = "marvell,sky2";
368 reg = <0x20>;
369 }; 354 };
370}; 355};
371 356
372&iomuxc { 357&ssi1 {
358 status = "okay";
359};
360
361&uart1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_uart1>;
364 status = "okay";
365};
366
367&uart2 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_uart2>;
370 status = "okay";
371};
372
373&uart5 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart5>;
376 status = "okay";
377};
378
379&usbotg {
380 vbus-supply = <&reg_usb_otg_vbus>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_usbotg>;
383 disable-over-current;
384 status = "okay";
385};
386
387&usbh1 {
388 vbus-supply = <&reg_usb_h1_vbus>;
389 status = "okay";
390};
391
392&usdhc3 {
373 pinctrl-names = "default"; 393 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_hog>; 394 pinctrl-0 = <&pinctrl_usdhc3>;
395 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
396 vmmc-supply = <&reg_3p3v>;
397 status = "okay";
398};
375 399
400&iomuxc {
376 imx6q-gw5400-a { 401 imx6q-gw5400-a {
377 pinctrl_hog: hoggrp {
378 fsl,pins = <
379 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
380 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
381 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
382 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
383 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
384 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */
385 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
386 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
387 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */
388 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
389 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
390 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
391 >;
392 };
393 402
394 pinctrl_audmux: audmuxgrp { 403 pinctrl_audmux: audmuxgrp {
395 fsl,pins = < 404 fsl,pins = <
@@ -397,6 +406,7 @@
397 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 406 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
398 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 407 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
399 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 408 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
409 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
400 >; 410 >;
401 }; 411 };
402 412
@@ -405,6 +415,7 @@
405 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 415 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
406 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 416 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
407 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 417 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
408 >; 419 >;
409 }; 420 };
410 421
@@ -429,6 +440,14 @@
429 >; 440 >;
430 }; 441 };
431 442
443 pinctrl_gpio_leds: gpioledsgrp {
444 fsl,pins = <
445 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */
446 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */
447 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */
448 >;
449 };
450
432 pinctrl_i2c1: i2c1grp { 451 pinctrl_i2c1: i2c1grp {
433 fsl,pins = < 452 fsl,pins = <
434 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 453 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@@ -450,6 +469,19 @@
450 >; 469 >;
451 }; 470 };
452 471
472 pinctrl_pcie: pciegrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
475 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
476 >;
477 };
478
479 pinctrl_pps: ppsgrp {
480 fsl,pins = <
481 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */
482 >;
483 };
484
453 pinctrl_uart1: uart1grp { 485 pinctrl_uart1: uart1grp {
454 fsl,pins = < 486 fsl,pins = <
455 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 487 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -474,6 +506,7 @@
474 pinctrl_usbotg: usbotggrp { 506 pinctrl_usbotg: usbotggrp {
475 fsl,pins = < 507 fsl,pins = <
476 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 508 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
509 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
477 >; 510 >;
478 }; 511 };
479 512
@@ -489,59 +522,3 @@
489 }; 522 };
490 }; 523 };
491}; 524};
492
493&ldb {
494 status = "okay";
495};
496
497&pcie {
498 reset-gpio = <&gpio1 29 0>;
499 status = "okay";
500
501 eth1: sky2@8 { /* MAC/PHY on bus 8 */
502 compatible = "marvell,sky2";
503 };
504};
505
506&ssi1 {
507 status = "okay";
508};
509
510&uart1 {
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_uart1>;
513 status = "okay";
514};
515
516&uart2 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_uart2>;
519 status = "okay";
520};
521
522&uart5 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_uart5>;
525 status = "okay";
526};
527
528&usbotg {
529 vbus-supply = <&reg_usb_otg_vbus>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_usbotg>;
532 disable-over-current;
533 status = "okay";
534};
535
536&usbh1 {
537 vbus-supply = <&reg_usb_h1_vbus>;
538 status = "okay";
539};
540
541&usdhc3 {
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_usdhc3>;
544 cd-gpios = <&gpio7 0 0>;
545 vmmc-supply = <&reg_3p3v>;
546 status = "okay";
547};
diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts
new file mode 100644
index 000000000000..f87a8fa6e04d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw552x.dts
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6q.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
19 compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
20};
21
22&sata {
23 status = "okay";
24};
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
new file mode 100644
index 000000000000..c2bf8476ce45
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King
4 */
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include "imx6qdl-hummingboard.dtsi"
9
10/ {
11 model = "SolidRun HummingBoard Dual/Quad";
12 compatible = "solidrun,hummingboard/q", "fsl,imx6q";
13};
14
15&sata {
16 status = "okay";
17 fsl,transmit-level-mV = <1025>;
18 fsl,transmit-boost-mdB = <3330>;
19 fsl,transmit-atten-16ths = <9>;
20 fsl,receive-eq-mdB = <3000>;
21};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 0db15af41cb1..f2867c4b34a8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -9,11 +9,11 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 led0 = &led0; 17 led0 = &led0;
18 led1 = &led1; 18 led1 = &led1;
19 nand = &gpmi; 19 nand = &gpmi;
@@ -27,17 +27,19 @@
27 27
28 leds { 28 leds {
29 compatible = "gpio-leds"; 29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_leds>;
30 32
31 led0: user1 { 33 led0: user1 {
32 label = "user1"; 34 label = "user1";
33 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 35 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
34 default-state = "on"; 36 default-state = "on";
35 linux,default-trigger = "heartbeat"; 37 linux,default-trigger = "heartbeat";
36 }; 38 };
37 39
38 led1: user2 { 40 led1: user2 {
39 label = "user2"; 41 label = "user2";
40 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 42 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
41 default-state = "off"; 43 default-state = "off";
42 }; 44 };
43 }; 45 };
@@ -48,7 +50,9 @@
48 50
49 pps { 51 pps {
50 compatible = "pps-gpio"; 52 compatible = "pps-gpio";
51 gpios = <&gpio1 26 0>; 53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_pps>;
55 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
52 status = "okay"; 56 status = "okay";
53 }; 57 };
54 58
@@ -81,7 +85,7 @@
81 regulator-name = "usb_otg_vbus"; 85 regulator-name = "usb_otg_vbus";
82 regulator-min-microvolt = <5000000>; 86 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio3 22 0>; 88 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
85 enable-active-high; 89 enable-active-high;
86 }; 90 };
87 }; 91 };
@@ -91,7 +95,7 @@
91 pinctrl-names = "default"; 95 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_enet>; 96 pinctrl-0 = <&pinctrl_enet>;
93 phy-mode = "rgmii"; 97 phy-mode = "rgmii";
94 phy-reset-gpios = <&gpio1 30 0>; 98 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
95 status = "okay"; 99 status = "okay";
96}; 100};
97 101
@@ -143,11 +147,6 @@
143 #gpio-cells = <2>; 147 #gpio-cells = <2>;
144 }; 148 };
145 149
146 hwmon: gsc@29 {
147 compatible = "gw,gsp";
148 reg = <0x29>;
149 };
150
151 rtc: ds1672@68 { 150 rtc: ds1672@68 {
152 compatible = "dallas,ds1672"; 151 compatible = "dallas,ds1672";
153 reg = <0x68>; 152 reg = <0x68>;
@@ -159,53 +158,6 @@
159 pinctrl-names = "default"; 158 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c2>; 159 pinctrl-0 = <&pinctrl_i2c2>;
161 status = "okay"; 160 status = "okay";
162
163 pmic: ltc3676@3c {
164 compatible = "lltc,ltc3676";
165 reg = <0x3c>;
166
167 regulators {
168 sw1_reg: ltc3676__sw1 {
169 regulator-min-microvolt = <1175000>;
170 regulator-max-microvolt = <1175000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 sw2_reg: ltc3676__sw2 {
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <1800000>;
178 regulator-boot-on;
179 regulator-always-on;
180 };
181
182 sw3_reg: ltc3676__sw3 {
183 regulator-min-microvolt = <1175000>;
184 regulator-max-microvolt = <1175000>;
185 regulator-boot-on;
186 regulator-always-on;
187 };
188
189 sw4_reg: ltc3676__sw4 {
190 regulator-min-microvolt = <1500000>;
191 regulator-max-microvolt = <1500000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 ldo2_reg: ltc3676__ldo2 {
197 regulator-min-microvolt = <2500000>;
198 regulator-max-microvolt = <2500000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 ldo4_reg: ltc3676__ldo4 {
204 regulator-min-microvolt = <3000000>;
205 regulator-max-microvolt = <3000000>;
206 };
207 };
208 };
209}; 161};
210 162
211&i2c3 { 163&i2c3 {
@@ -213,31 +165,53 @@
213 pinctrl-names = "default"; 165 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c3>; 166 pinctrl-0 = <&pinctrl_i2c3>;
215 status = "okay"; 167 status = "okay";
168};
216 169
217 videoin: adv7180@20 { 170&pcie {
218 compatible = "adi,adv7180"; 171 pinctrl-names = "default";
219 reg = <0x20>; 172 pinctrl-0 = <&pinctrl_pcie>;
220 }; 173 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
174 status = "okay";
221}; 175};
222 176
223&iomuxc { 177&uart1 {
224 pinctrl-names = "default"; 178 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_hog>; 179 pinctrl-0 = <&pinctrl_uart1>;
180 status = "okay";
181};
226 182
227 imx6qdl-gw51xx { 183&uart2 {
228 pinctrl_hog: hoggrp { 184 pinctrl-names = "default";
229 fsl,pins = < 185 pinctrl-0 = <&pinctrl_uart2>;
230 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ 186 status = "okay";
231 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ 187};
232 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
233 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
234 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
235 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */
236 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
237 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
238 >;
239 };
240 188
189&uart3 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart3>;
192 status = "okay";
193};
194
195&uart5 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart5>;
198 status = "okay";
199};
200
201&usbotg {
202 vbus-supply = <&reg_usb_otg_vbus>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbotg>;
205 disable-over-current;
206 status = "okay";
207};
208
209&usbh1 {
210 status = "okay";
211};
212
213&iomuxc {
214 imx6qdl-gw51xx {
241 pinctrl_enet: enetgrp { 215 pinctrl_enet: enetgrp {
242 fsl,pins = < 216 fsl,pins = <
243 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 217 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
@@ -256,6 +230,14 @@
256 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 230 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
257 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 231 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
258 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 232 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
233 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
234 >;
235 };
236
237 pinctrl_gpio_leds: gpioledsgrp {
238 fsl,pins = <
239 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
240 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
259 >; 241 >;
260 }; 242 };
261 243
@@ -301,6 +283,18 @@
301 >; 283 >;
302 }; 284 };
303 285
286 pinctrl_pcie: pciegrp {
287 fsl,pins = <
288 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
289 >;
290 };
291
292 pinctrl_pps: ppsgrp {
293 fsl,pins = <
294 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
295 >;
296 };
297
304 pinctrl_uart1: uart1grp { 298 pinctrl_uart1: uart1grp {
305 fsl,pins = < 299 fsl,pins = <
306 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 300 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -332,48 +326,8 @@
332 pinctrl_usbotg: usbotggrp { 326 pinctrl_usbotg: usbotggrp {
333 fsl,pins = < 327 fsl,pins = <
334 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 328 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
329 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
335 >; 330 >;
336 }; 331 };
337 }; 332 };
338}; 333};
339
340&pcie {
341 reset-gpio = <&gpio1 0 0>;
342 status = "okay";
343};
344
345&uart1 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_uart1>;
348 status = "okay";
349};
350
351&uart2 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_uart2>;
354 status = "okay";
355};
356
357&uart3 {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_uart3>;
360 status = "okay";
361};
362
363&uart5 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart5>;
366 status = "okay";
367};
368
369&usbotg {
370 vbus-supply = <&reg_usb_otg_vbus>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usbotg>;
373 disable-over-current;
374 status = "okay";
375};
376
377&usbh1 {
378 status = "okay";
379};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 234e7b755232..d3c0bf5c84e3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -9,10 +9,11 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 ethernet0 = &fec;
16 led0 = &led0; 17 led0 = &led0;
17 led1 = &led1; 18 led1 = &led1;
18 led2 = &led2; 19 led2 = &led2;
@@ -20,7 +21,6 @@
20 ssi0 = &ssi1; 21 ssi0 = &ssi1;
21 usb0 = &usbh1; 22 usb0 = &usbh1;
22 usb1 = &usbotg; 23 usb1 = &usbotg;
23 usdhc2 = &usdhc3;
24 }; 24 };
25 25
26 chosen { 26 chosen {
@@ -36,23 +36,25 @@
36 36
37 leds { 37 leds {
38 compatible = "gpio-leds"; 38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
39 41
40 led0: user1 { 42 led0: user1 {
41 label = "user1"; 43 label = "user1";
42 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
43 default-state = "on"; 45 default-state = "on";
44 linux,default-trigger = "heartbeat"; 46 linux,default-trigger = "heartbeat";
45 }; 47 };
46 48
47 led1: user2 { 49 led1: user2 {
48 label = "user2"; 50 label = "user2";
49 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
50 default-state = "off"; 52 default-state = "off";
51 }; 53 };
52 54
53 led2: user3 { 55 led2: user3 {
54 label = "user3"; 56 label = "user3";
55 gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ 57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
56 default-state = "off"; 58 default-state = "off";
57 }; 59 };
58 }; 60 };
@@ -63,7 +65,9 @@
63 65
64 pps { 66 pps {
65 compatible = "pps-gpio"; 67 compatible = "pps-gpio";
66 gpios = <&gpio1 26 0>; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
67 status = "okay"; 71 status = "okay";
68 }; 72 };
69 73
@@ -115,7 +119,7 @@
115 regulator-name = "usb_otg_vbus"; 119 regulator-name = "usb_otg_vbus";
116 regulator-min-microvolt = <5000000>; 120 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>; 121 regulator-max-microvolt = <5000000>;
118 gpio = <&gpio3 22 0>; 122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
119 enable-active-high; 123 enable-active-high;
120 }; 124 };
121 }; 125 };
@@ -141,11 +145,17 @@
141 status = "okay"; 145 status = "okay";
142}; 146};
143 147
148&can1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_flexcan1>;
151 status = "okay";
152};
153
144&fec { 154&fec {
145 pinctrl-names = "default"; 155 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
147 phy-mode = "rgmii"; 157 phy-mode = "rgmii";
148 phy-reset-gpios = <&gpio1 30 0>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
149 status = "okay"; 159 status = "okay";
150}; 160};
151 161
@@ -197,11 +207,6 @@
197 #gpio-cells = <2>; 207 #gpio-cells = <2>;
198 }; 208 };
199 209
200 hwmon: gsc@29 {
201 compatible = "gw,gsp";
202 reg = <0x29>;
203 };
204
205 rtc: ds1672@68 { 210 rtc: ds1672@68 {
206 compatible = "dallas,ds1672"; 211 compatible = "dallas,ds1672";
207 reg = <0x68>; 212 reg = <0x68>;
@@ -213,65 +218,6 @@
213 pinctrl-names = "default"; 218 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c2>; 219 pinctrl-0 = <&pinctrl_i2c2>;
215 status = "okay"; 220 status = "okay";
216
217 pciswitch: pex8609@3f {
218 compatible = "plx,pex8609";
219 reg = <0x3f>;
220 };
221
222 pmic: ltc3676@3c {
223 compatible = "lltc,ltc3676";
224 reg = <0x3c>;
225
226 regulators {
227 sw1_reg: ltc3676__sw1 {
228 regulator-min-microvolt = <1175000>;
229 regulator-max-microvolt = <1175000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 sw2_reg: ltc3676__sw2 {
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 sw3_reg: ltc3676__sw3 {
242 regulator-min-microvolt = <1175000>;
243 regulator-max-microvolt = <1175000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247
248 sw4_reg: ltc3676__sw4 {
249 regulator-min-microvolt = <1500000>;
250 regulator-max-microvolt = <1500000>;
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 ldo2_reg: ltc3676__ldo2 {
256 regulator-min-microvolt = <2500000>;
257 regulator-max-microvolt = <2500000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 ldo3_reg: ltc3676__ldo3 {
263 regulator-min-microvolt = <1800000>;
264 regulator-max-microvolt = <1800000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 ldo4_reg: ltc3676__ldo4 {
270 regulator-min-microvolt = <3000000>;
271 regulator-max-microvolt = <3000000>;
272 };
273 };
274 };
275}; 221};
276 222
277&i2c3 { 223&i2c3 {
@@ -280,11 +226,6 @@
280 pinctrl-0 = <&pinctrl_i2c3>; 226 pinctrl-0 = <&pinctrl_i2c3>;
281 status = "okay"; 227 status = "okay";
282 228
283 accelerometer: fxos8700@1e {
284 compatible = "fsl,fxos8700";
285 reg = <0x13>;
286 };
287
288 codec: sgtl5000@0a { 229 codec: sgtl5000@0a {
289 compatible = "fsl,sgtl5000"; 230 compatible = "fsl,sgtl5000";
290 reg = <0x0a>; 231 reg = <0x0a>;
@@ -297,49 +238,101 @@
297 compatible = "eeti,egalax_ts"; 238 compatible = "eeti,egalax_ts";
298 reg = <0x04>; 239 reg = <0x04>;
299 interrupt-parent = <&gpio7>; 240 interrupt-parent = <&gpio7>;
300 interrupts = <12 2>; /* gpio7_12 active low */ 241 interrupts = <12 2>;
301 wakeup-gpios = <&gpio7 12 0>; 242 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
302 }; 243 };
244};
245
246&ldb {
247 status = "okay";
303 248
304 videoin: adv7180@20 { 249 lvds-channel@0 {
305 compatible = "adi,adv7180"; 250 fsl,data-mapping = "spwg";
306 reg = <0x20>; 251 fsl,data-width = <18>;
252 status = "okay";
253
254 display-timings {
255 native-mode = <&timing0>;
256 timing0: hsd100pxn1 {
257 clock-frequency = <65000000>;
258 hactive = <1024>;
259 vactive = <768>;
260 hback-porch = <220>;
261 hfront-porch = <40>;
262 vback-porch = <21>;
263 vfront-porch = <7>;
264 hsync-len = <60>;
265 vsync-len = <10>;
266 };
267 };
307 }; 268 };
308}; 269};
309 270
310&iomuxc { 271&pcie {
311 pinctrl-names = "default"; 272 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_hog>; 273 pinctrl-0 = <&pinctrl_pcie>;
274 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
275 status = "okay";
276};
313 277
314 imx6qdl-gw52xx { 278&pwm4 {
315 pinctrl_hog: hoggrp { 279 pinctrl-names = "default";
316 fsl,pins = < 280 pinctrl-0 = <&pinctrl_pwm4>;
317 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ 281 status = "okay";
318 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ 282};
319 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 283
320 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ 284&ssi1 {
321 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ 285 fsl,mode = "i2s-slave";
322 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ 286 status = "okay";
323 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ 287};
324 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 288
325 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 289&uart1 {
326 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ 290 pinctrl-names = "default";
327 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ 291 pinctrl-0 = <&pinctrl_uart1>;
328 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ 292 status = "okay";
329 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ 293};
330 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ 294
331 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ 295&uart2 {
332 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ 296 pinctrl-names = "default";
333 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ 297 pinctrl-0 = <&pinctrl_uart2>;
334 >; 298 status = "okay";
335 }; 299};
300
301&uart5 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_uart5>;
304 status = "okay";
305};
306
307&usbotg {
308 vbus-supply = <&reg_usb_otg_vbus>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_usbotg>;
311 disable-over-current;
312 status = "okay";
313};
314
315&usbh1 {
316 status = "okay";
317};
318
319&usdhc3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_usdhc3>;
322 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
323 vmmc-supply = <&reg_3p3v>;
324 status = "okay";
325};
336 326
327&iomuxc {
328 imx6qdl-gw52xx {
337 pinctrl_audmux: audmuxgrp { 329 pinctrl_audmux: audmuxgrp {
338 fsl,pins = < 330 fsl,pins = <
339 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 331 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
340 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 332 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
341 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 333 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
342 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 334 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
335 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
343 >; 336 >;
344 }; 337 };
345 338
@@ -361,6 +354,23 @@
361 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 354 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
362 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 355 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
363 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 356 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
357 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
358 >;
359 };
360
361 pinctrl_flexcan1: flexcan1grp {
362 fsl,pins = <
363 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
364 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
365 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
366 >;
367 };
368
369 pinctrl_gpio_leds: gpioledsgrp {
370 fsl,pins = <
371 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
372 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
373 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
364 >; 374 >;
365 }; 375 };
366 376
@@ -406,6 +416,18 @@
406 >; 416 >;
407 }; 417 };
408 418
419 pinctrl_pcie: pciegrp {
420 fsl,pins = <
421 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
422 >;
423 };
424
425 pinctrl_pps: ppsgrp {
426 fsl,pins = <
427 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
428 >;
429 };
430
409 pinctrl_pwm4: pwm4grp { 431 pinctrl_pwm4: pwm4grp {
410 fsl,pins = < 432 fsl,pins = <
411 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 433 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -436,6 +458,7 @@
436 pinctrl_usbotg: usbotggrp { 458 pinctrl_usbotg: usbotggrp {
437 fsl,pins = < 459 fsl,pins = <
438 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 460 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
461 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
439 >; 462 >;
440 }; 463 };
441 464
@@ -447,85 +470,8 @@
447 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 470 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
448 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 471 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
449 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 472 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
473 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
450 >; 474 >;
451 }; 475 };
452 }; 476 };
453}; 477};
454
455&ldb {
456 status = "okay";
457
458 lvds-channel@0 {
459 fsl,data-mapping = "spwg";
460 fsl,data-width = <18>;
461 status = "okay";
462
463 display-timings {
464 native-mode = <&timing0>;
465 timing0: hsd100pxn1 {
466 clock-frequency = <65000000>;
467 hactive = <1024>;
468 vactive = <768>;
469 hback-porch = <220>;
470 hfront-porch = <40>;
471 vback-porch = <21>;
472 vfront-porch = <7>;
473 hsync-len = <60>;
474 vsync-len = <10>;
475 };
476 };
477 };
478};
479
480&pcie {
481 reset-gpio = <&gpio1 29 0>;
482 status = "okay";
483};
484
485&pwm4 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_pwm4>;
488 status = "okay";
489};
490
491&ssi1 {
492 status = "okay";
493};
494
495&uart1 {
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart1>;
498 status = "okay";
499};
500
501&uart2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart2>;
504 status = "okay";
505};
506
507&uart5 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart5>;
510 status = "okay";
511};
512
513&usbotg {
514 vbus-supply = <&reg_usb_otg_vbus>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_usbotg>;
517 disable-over-current;
518 status = "okay";
519};
520
521&usbh1 {
522 status = "okay";
523};
524
525&usdhc3 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_usdhc3>;
528 cd-gpios = <&gpio7 0 0>;
529 vmmc-supply = <&reg_3p3v>;
530 status = "okay";
531};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 143f84f7812c..cade1bdc97e9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -9,21 +9,19 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1; 17 ethernet1 = &eth1;
18 led0 = &led0; 18 led0 = &led0;
19 led1 = &led1; 19 led1 = &led1;
20 led2 = &led2; 20 led2 = &led2;
21 nand = &gpmi; 21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1; 22 ssi0 = &ssi1;
24 usb0 = &usbh1; 23 usb0 = &usbh1;
25 usb1 = &usbotg; 24 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 }; 25 };
28 26
29 chosen { 27 chosen {
@@ -39,23 +37,25 @@
39 37
40 leds { 38 leds {
41 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
42 42
43 led0: user1 { 43 led0: user1 {
44 label = "user1"; 44 label = "user1";
45 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 45 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 default-state = "on"; 46 default-state = "on";
47 linux,default-trigger = "heartbeat"; 47 linux,default-trigger = "heartbeat";
48 }; 48 };
49 49
50 led1: user2 { 50 led1: user2 {
51 label = "user2"; 51 label = "user2";
52 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 52 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
53 default-state = "off"; 53 default-state = "off";
54 }; 54 };
55 55
56 led2: user3 { 56 led2: user3 {
57 label = "user3"; 57 label = "user3";
58 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 58 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
59 default-state = "off"; 59 default-state = "off";
60 }; 60 };
61 }; 61 };
@@ -66,7 +66,9 @@
66 66
67 pps { 67 pps {
68 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 gpios = <&gpio1 26 0>; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
70 status = "okay"; 72 status = "okay";
71 }; 73 };
72 74
@@ -118,7 +120,7 @@
118 regulator-name = "usb_otg_vbus"; 120 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 0>; 123 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
122 enable-active-high; 124 enable-active-high;
123 }; 125 };
124 }; 126 };
@@ -154,7 +156,7 @@
154 pinctrl-names = "default"; 156 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_enet>; 157 pinctrl-0 = <&pinctrl_enet>;
156 phy-mode = "rgmii"; 158 phy-mode = "rgmii";
157 phy-reset-gpios = <&gpio1 30 0>; 159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
158 status = "okay"; 160 status = "okay";
159}; 161};
160 162
@@ -206,11 +208,6 @@
206 #gpio-cells = <2>; 208 #gpio-cells = <2>;
207 }; 209 };
208 210
209 hwmon: gsc@29 {
210 compatible = "gw,gsp";
211 reg = <0x29>;
212 };
213
214 rtc: ds1672@68 { 211 rtc: ds1672@68 {
215 compatible = "dallas,ds1672"; 212 compatible = "dallas,ds1672";
216 reg = <0x68>; 213 reg = <0x68>;
@@ -222,77 +219,6 @@
222 pinctrl-names = "default"; 219 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c2>; 220 pinctrl-0 = <&pinctrl_i2c2>;
224 status = "okay"; 221 status = "okay";
225
226 pciclkgen: si53156@6b {
227 compatible = "sil,si53156";
228 reg = <0x6b>;
229 };
230
231 pciswitch: pex8606@3f {
232 compatible = "plx,pex8606";
233 reg = <0x3f>;
234 };
235
236 pmic: ltc3676@3c {
237 compatible = "lltc,ltc3676";
238 reg = <0x3c>;
239
240 regulators {
241 /* VDD_SOC */
242 sw1_reg: ltc3676__sw1 {
243 regulator-min-microvolt = <1175000>;
244 regulator-max-microvolt = <1175000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 /* VDD_1P8 */
250 sw2_reg: ltc3676__sw2 {
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 /* VDD_ARM */
258 sw3_reg: ltc3676__sw3 {
259 regulator-min-microvolt = <1175000>;
260 regulator-max-microvolt = <1175000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 /* VDD_DDR */
266 sw4_reg: ltc3676__sw4 {
267 regulator-min-microvolt = <1500000>;
268 regulator-max-microvolt = <1500000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272
273 /* VDD_2P5 */
274 ldo2_reg: ltc3676__ldo2 {
275 regulator-min-microvolt = <2500000>;
276 regulator-max-microvolt = <2500000>;
277 regulator-boot-on;
278 regulator-always-on;
279 };
280
281 /* VDD_1P8 */
282 ldo3_reg: ltc3676__ldo3 {
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <1800000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 /* VDD_HIGH */
290 ldo4_reg: ltc3676__ldo4 {
291 regulator-min-microvolt = <3000000>;
292 regulator-max-microvolt = <3000000>;
293 };
294 };
295 };
296}; 222};
297 223
298&i2c3 { 224&i2c3 {
@@ -301,11 +227,6 @@
301 pinctrl-0 = <&pinctrl_i2c3>; 227 pinctrl-0 = <&pinctrl_i2c3>;
302 status = "okay"; 228 status = "okay";
303 229
304 accelerometer: fxos8700@1e {
305 compatible = "fsl,fxos8700";
306 reg = <0x1e>;
307 };
308
309 codec: sgtl5000@0a { 230 codec: sgtl5000@0a {
310 compatible = "fsl,sgtl5000"; 231 compatible = "fsl,sgtl5000";
311 reg = <0x0a>; 232 reg = <0x0a>;
@@ -314,65 +235,110 @@
314 VDDIO-supply = <&reg_3p3v>; 235 VDDIO-supply = <&reg_3p3v>;
315 }; 236 };
316 237
317 hdmiin: adv7611@4c {
318 compatible = "adi,adv7611";
319 reg = <0x4c>;
320 };
321
322 touchscreen: egalax_ts@04 { 238 touchscreen: egalax_ts@04 {
323 compatible = "eeti,egalax_ts"; 239 compatible = "eeti,egalax_ts";
324 reg = <0x04>; 240 reg = <0x04>;
325 interrupt-parent = <&gpio1>; 241 interrupt-parent = <&gpio1>;
326 interrupts = <11 2>; /* gpio1_11 active low */ 242 interrupts = <11 2>;
327 wakeup-gpios = <&gpio1 11 0>; 243 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
328 }; 244 };
245};
329 246
330 videoout: adv7393@2a { 247&ldb {
331 compatible = "adi,adv7393"; 248 status = "okay";
332 reg = <0x2a>; 249
250 lvds-channel@1 {
251 fsl,data-mapping = "spwg";
252 fsl,data-width = <18>;
253 status = "okay";
254
255 display-timings {
256 native-mode = <&timing0>;
257 timing0: hsd100pxn1 {
258 clock-frequency = <65000000>;
259 hactive = <1024>;
260 vactive = <768>;
261 hback-porch = <220>;
262 hfront-porch = <40>;
263 vback-porch = <21>;
264 vfront-porch = <7>;
265 hsync-len = <60>;
266 vsync-len = <10>;
267 };
268 };
333 }; 269 };
270};
334 271
335 videoin: adv7180@20 { 272&pcie {
336 compatible = "adi,adv7180"; 273 pinctrl-names = "default";
337 reg = <0x20>; 274 pinctrl-0 = <&pinctrl_pcie>;
275 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
276 status = "okay";
277
278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
279 compatible = "marvell,sky2";
338 }; 280 };
339}; 281};
340 282
341&iomuxc { 283&pwm4 {
342 pinctrl-names = "default"; 284 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_hog>; 285 pinctrl-0 = <&pinctrl_pwm4>;
286 status = "okay";
287};
344 288
345 imx6qdl-gw53xx { 289&ssi1 {
346 pinctrl_hog: hoggrp { 290 fsl,mode = "i2s-slave";
347 fsl,pins = < 291 status = "okay";
348 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ 292};
349 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ 293
350 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 294&uart1 {
351 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ 295 pinctrl-names = "default";
352 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 296 pinctrl-0 = <&pinctrl_uart1>;
353 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ 297 status = "okay";
354 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ 298};
355 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 299
356 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ 300&uart2 {
357 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ 301 pinctrl-names = "default";
358 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ 302 pinctrl-0 = <&pinctrl_uart2>;
359 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ 303 status = "okay";
360 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ 304};
361 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
362 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
363 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
364 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
365 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
366 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
367 >;
368 };
369 305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 vbus-supply = <&reg_usb_h1_vbus>;
322 status = "okay";
323};
324
325&usdhc3 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc3>;
328 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
329 vmmc-supply = <&reg_3p3v>;
330 status = "okay";
331};
332
333&iomuxc {
334 imx6qdl-gw53xx {
370 pinctrl_audmux: audmuxgrp { 335 pinctrl_audmux: audmuxgrp {
371 fsl,pins = < 336 fsl,pins = <
372 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 337 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
373 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 338 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
374 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 339 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
375 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 340 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
376 >; 342 >;
377 }; 343 };
378 344
@@ -399,8 +365,17 @@
399 365
400 pinctrl_flexcan1: flexcan1grp { 366 pinctrl_flexcan1: flexcan1grp {
401 fsl,pins = < 367 fsl,pins = <
402 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 368 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
403 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 369 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
370 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
371 >;
372 };
373
374 pinctrl_gpio_leds: gpioledsgrp {
375 fsl,pins = <
376 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
377 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
378 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
404 >; 379 >;
405 }; 380 };
406 381
@@ -446,6 +421,19 @@
446 >; 421 >;
447 }; 422 };
448 423
424 pinctrl_pcie: pciegrp {
425 fsl,pins = <
426 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
427 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
428 >;
429 };
430
431 pinctrl_pps: ppsgrp {
432 fsl,pins = <
433 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
434 >;
435 };
436
449 pinctrl_pwm4: pwm4grp { 437 pinctrl_pwm4: pwm4grp {
450 fsl,pins = < 438 fsl,pins = <
451 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 439 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -476,6 +464,8 @@
476 pinctrl_usbotg: usbotggrp { 464 pinctrl_usbotg: usbotggrp {
477 fsl,pins = < 465 fsl,pins = <
478 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 466 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
467 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
468 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
479 >; 469 >;
480 }; 470 };
481 471
@@ -487,90 +477,8 @@
487 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 477 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
488 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 478 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
489 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 479 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
480 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
490 >; 481 >;
491 }; 482 };
492 }; 483 };
493}; 484};
494
495&ldb {
496 status = "okay";
497
498 lvds-channel@1 {
499 fsl,data-mapping = "spwg";
500 fsl,data-width = <18>;
501 status = "okay";
502
503 display-timings {
504 native-mode = <&timing0>;
505 timing0: hsd100pxn1 {
506 clock-frequency = <65000000>;
507 hactive = <1024>;
508 vactive = <768>;
509 hback-porch = <220>;
510 hfront-porch = <40>;
511 vback-porch = <21>;
512 vfront-porch = <7>;
513 hsync-len = <60>;
514 vsync-len = <10>;
515 };
516 };
517 };
518};
519
520&pcie {
521 reset-gpio = <&gpio1 29 0>;
522 status = "okay";
523
524 eth1: sky2@8 { /* MAC/PHY on bus 8 */
525 compatible = "marvell,sky2";
526 };
527};
528
529&pwm4 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_pwm4>;
532 status = "okay";
533};
534
535&ssi1 {
536 status = "okay";
537};
538
539&uart1 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart1>;
542 status = "okay";
543};
544
545&uart2 {
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_uart2>;
548 status = "okay";
549};
550
551&uart5 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_uart5>;
554 status = "okay";
555};
556
557&usbotg {
558 vbus-supply = <&reg_usb_otg_vbus>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_usbotg>;
561 disable-over-current;
562 status = "okay";
563};
564
565&usbh1 {
566 vbus-supply = <&reg_usb_h1_vbus>;
567 status = "okay";
568};
569
570&usdhc3 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_usdhc3>;
573 cd-gpios = <&gpio7 0 0>;
574 vmmc-supply = <&reg_3p3v>;
575 status = "okay";
576};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 16e7ad3d98ad..cf13239a1619 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -9,21 +9,19 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1; 17 ethernet1 = &eth1;
18 led0 = &led0; 18 led0 = &led0;
19 led1 = &led1; 19 led1 = &led1;
20 led2 = &led2; 20 led2 = &led2;
21 nand = &gpmi; 21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1; 22 ssi0 = &ssi1;
24 usb0 = &usbh1; 23 usb0 = &usbh1;
25 usb1 = &usbotg; 24 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 }; 25 };
28 26
29 chosen { 27 chosen {
@@ -39,23 +37,25 @@
39 37
40 leds { 38 leds {
41 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
42 42
43 led0: user1 { 43 led0: user1 {
44 label = "user1"; 44 label = "user1";
45 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 45 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 default-state = "on"; 46 default-state = "on";
47 linux,default-trigger = "heartbeat"; 47 linux,default-trigger = "heartbeat";
48 }; 48 };
49 49
50 led1: user2 { 50 led1: user2 {
51 label = "user2"; 51 label = "user2";
52 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 52 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
53 default-state = "off"; 53 default-state = "off";
54 }; 54 };
55 55
56 led2: user3 { 56 led2: user3 {
57 label = "user3"; 57 label = "user3";
58 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 58 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
59 default-state = "off"; 59 default-state = "off";
60 }; 60 };
61 }; 61 };
@@ -66,7 +66,9 @@
66 66
67 pps { 67 pps {
68 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 gpios = <&gpio1 26 0>; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
70 status = "okay"; 72 status = "okay";
71 }; 73 };
72 74
@@ -108,7 +110,7 @@
108 regulator-name = "usb_otg_vbus"; 110 regulator-name = "usb_otg_vbus";
109 regulator-min-microvolt = <5000000>; 111 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio3 22 0>; 113 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
112 enable-active-high; 114 enable-active-high;
113 }; 115 };
114 }; 116 };
@@ -144,7 +146,7 @@
144 pinctrl-names = "default"; 146 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_enet>; 147 pinctrl-0 = <&pinctrl_enet>;
146 phy-mode = "rgmii"; 148 phy-mode = "rgmii";
147 phy-reset-gpios = <&gpio1 30 0>; 149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
148 status = "okay"; 150 status = "okay";
149}; 151};
150 152
@@ -196,11 +198,6 @@
196 #gpio-cells = <2>; 198 #gpio-cells = <2>;
197 }; 199 };
198 200
199 hwmon: gsc@29 {
200 compatible = "gw,gsp";
201 reg = <0x29>;
202 };
203
204 rtc: ds1672@68 { 201 rtc: ds1672@68 {
205 compatible = "dallas,ds1672"; 202 compatible = "dallas,ds1672";
206 reg = <0x68>; 203 reg = <0x68>;
@@ -311,16 +308,6 @@
311 }; 308 };
312 }; 309 };
313 }; 310 };
314
315 pciswitch: pex8609@3f {
316 compatible = "plx,pex8609";
317 reg = <0x3f>;
318 };
319
320 pciclkgen: si52147@6b {
321 compatible = "sil,si52147";
322 reg = <0x6b>;
323 };
324}; 311};
325 312
326&i2c3 { 313&i2c3 {
@@ -329,11 +316,6 @@
329 pinctrl-0 = <&pinctrl_i2c3>; 316 pinctrl-0 = <&pinctrl_i2c3>;
330 status = "okay"; 317 status = "okay";
331 318
332 accelerometer: fxos8700@1e {
333 compatible = "fsl,fxos8700";
334 reg = <0x1e>;
335 };
336
337 codec: sgtl5000@0a { 319 codec: sgtl5000@0a {
338 compatible = "fsl,sgtl5000"; 320 compatible = "fsl,sgtl5000";
339 reg = <0x0a>; 321 reg = <0x0a>;
@@ -342,59 +324,115 @@
342 VDDIO-supply = <&reg_3p3v>; 324 VDDIO-supply = <&reg_3p3v>;
343 }; 325 };
344 326
345 hdmiin: adv7611@4c {
346 compatible = "adi,adv7611";
347 reg = <0x4c>;
348 };
349
350 touchscreen: egalax_ts@04 { 327 touchscreen: egalax_ts@04 {
351 compatible = "eeti,egalax_ts"; 328 compatible = "eeti,egalax_ts";
352 reg = <0x04>; 329 reg = <0x04>;
353 interrupt-parent = <&gpio7>; 330 interrupt-parent = <&gpio7>;
354 interrupts = <12 2>; /* gpio7_12 active low */ 331 interrupts = <12 2>;
355 wakeup-gpios = <&gpio7 12 0>; 332 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
356 }; 333 };
334};
357 335
358 videoout: adv7393@2a { 336&ldb {
359 compatible = "adi,adv7393"; 337 status = "okay";
360 reg = <0x2a>; 338
339 lvds-channel@1 {
340 fsl,data-mapping = "spwg";
341 fsl,data-width = <18>;
342 status = "okay";
343
344 display-timings {
345 native-mode = <&timing0>;
346 timing0: hsd100pxn1 {
347 clock-frequency = <65000000>;
348 hactive = <1024>;
349 vactive = <768>;
350 hback-porch = <220>;
351 hfront-porch = <40>;
352 vback-porch = <21>;
353 vfront-porch = <7>;
354 hsync-len = <60>;
355 vsync-len = <10>;
356 };
357 };
361 }; 358 };
359};
360
361&pcie {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pcie>;
364 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
365 status = "okay";
362 366
363 videoin: adv7180@20 { 367 eth1: sky2@8 { /* MAC/PHY on bus 8 */
364 compatible = "adi,adv7180"; 368 compatible = "marvell,sky2";
365 reg = <0x20>;
366 }; 369 };
367}; 370};
368 371
369&iomuxc { 372&pwm4 {
370 pinctrl-names = "default"; 373 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_hog>; 374 pinctrl-0 = <&pinctrl_pwm4>;
375 status = "okay";
376};
372 377
373 imx6qdl-gw54xx { 378&ssi1 {
374 pinctrl_hog: hoggrp { 379 fsl,mode = "i2s-slave";
375 fsl,pins = < 380 status = "okay";
376 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 381};
377 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ 382
378 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 383&ssi2 {
379 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ 384 fsl,mode = "i2s-slave";
380 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ 385 status = "okay";
381 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 386};
382 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ 387
383 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ 388&uart1 {
384 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ 389 pinctrl-names = "default";
385 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ 390 pinctrl-0 = <&pinctrl_uart1>;
386 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ 391 status = "okay";
387 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ 392};
388 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ 393
389 >; 394&uart2 {
390 }; 395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_uart2>;
397 status = "okay";
398};
399
400&uart5 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_uart5>;
403 status = "okay";
404};
405
406&usbotg {
407 vbus-supply = <&reg_usb_otg_vbus>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usbotg>;
410 disable-over-current;
411 status = "okay";
412};
413
414&usbh1 {
415 vbus-supply = <&reg_usb_h1_vbus>;
416 status = "okay";
417};
418
419&usdhc3 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usdhc3>;
422 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
423 vmmc-supply = <&reg_3p3v>;
424 status = "okay";
425};
391 426
427&iomuxc {
428 imx6qdl-gw54xx {
392 pinctrl_audmux: audmuxgrp { 429 pinctrl_audmux: audmuxgrp {
393 fsl,pins = < 430 fsl,pins = <
394 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 431 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
395 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 432 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
396 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 433 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
397 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 434 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
435 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
398 >; 436 >;
399 }; 437 };
400 438
@@ -421,8 +459,17 @@
421 459
422 pinctrl_flexcan1: flexcan1grp { 460 pinctrl_flexcan1: flexcan1grp {
423 fsl,pins = < 461 fsl,pins = <
424 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 462 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
425 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 463 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
464 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
465 >;
466 };
467
468 pinctrl_gpio_leds: gpioledsgrp {
469 fsl,pins = <
470 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
471 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
472 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
426 >; 473 >;
427 }; 474 };
428 475
@@ -468,6 +515,19 @@
468 >; 515 >;
469 }; 516 };
470 517
518 pinctrl_pcie: pciegrp {
519 fsl,pins = <
520 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
521 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
522 >;
523 };
524
525 pinctrl_pps: ppsgrp {
526 fsl,pins = <
527 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
528 >;
529 };
530
471 pinctrl_pwm4: pwm4grp { 531 pinctrl_pwm4: pwm4grp {
472 fsl,pins = < 532 fsl,pins = <
473 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 533 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -498,6 +558,7 @@
498 pinctrl_usbotg: usbotggrp { 558 pinctrl_usbotg: usbotggrp {
499 fsl,pins = < 559 fsl,pins = <
500 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 560 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
561 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
501 >; 562 >;
502 }; 563 };
503 564
@@ -513,90 +574,3 @@
513 }; 574 };
514 }; 575 };
515}; 576};
516
517&ldb {
518 status = "okay";
519
520 lvds-channel@1 {
521 fsl,data-mapping = "spwg";
522 fsl,data-width = <18>;
523 status = "okay";
524
525 display-timings {
526 native-mode = <&timing0>;
527 timing0: hsd100pxn1 {
528 clock-frequency = <65000000>;
529 hactive = <1024>;
530 vactive = <768>;
531 hback-porch = <220>;
532 hfront-porch = <40>;
533 vback-porch = <21>;
534 vfront-porch = <7>;
535 hsync-len = <60>;
536 vsync-len = <10>;
537 };
538 };
539 };
540};
541
542&pcie {
543 reset-gpio = <&gpio1 29 0>;
544 status = "okay";
545
546 eth1: sky2@8 { /* MAC/PHY on bus 8 */
547 compatible = "marvell,sky2";
548 };
549};
550
551&pwm4 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_pwm4>;
554 status = "okay";
555};
556
557&ssi1 {
558 status = "okay";
559};
560
561&ssi2 {
562 status = "okay";
563};
564
565&uart1 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_uart1>;
568 status = "okay";
569};
570
571&uart2 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_uart2>;
574 status = "okay";
575};
576
577&uart5 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_uart5>;
580 status = "okay";
581};
582
583&usbotg {
584 vbus-supply = <&reg_usb_otg_vbus>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_usbotg>;
587 disable-over-current;
588 status = "okay";
589};
590
591&usbh1 {
592 vbus-supply = <&reg_usb_h1_vbus>;
593 status = "okay";
594};
595
596&usdhc3 {
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_usdhc3>;
599 cd-gpios = <&gpio7 0 0>;
600 vmmc-supply = <&reg_3p3v>;
601 status = "okay";
602};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
new file mode 100644
index 000000000000..5c6587f6c420
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 };
24
25 chosen {
26 bootargs = "console=ttymxc1,115200";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_leds>;
33
34 led0: user1 {
35 label = "user1";
36 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
39 };
40
41 led1: user2 {
42 label = "user2";
43 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
44 default-state = "off";
45 };
46
47 led2: user3 {
48 label = "user3";
49 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
50 default-state = "off";
51 };
52 };
53
54 memory {
55 reg = <0x10000000 0x20000000>;
56 };
57
58 regulators {
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 reg_1p0v: regulator@0 {
64 compatible = "regulator-fixed";
65 reg = <0>;
66 regulator-name = "1P0V";
67 regulator-min-microvolt = <1000000>;
68 regulator-max-microvolt = <1000000>;
69 regulator-always-on;
70 };
71
72 reg_3p3v: regulator@2 {
73 compatible = "regulator-fixed";
74 reg = <2>;
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_5p0v: regulator@3 {
82 compatible = "regulator-fixed";
83 reg = <3>;
84 regulator-name = "5P0V";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 regulator-always-on;
88 };
89 };
90};
91
92&gpmi {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_gpmi_nand>;
95 status = "okay";
96};
97
98&hdmi {
99 ddc-i2c-bus = <&i2c3>;
100 status = "okay";
101};
102
103&i2c1 {
104 clock-frequency = <100000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 status = "okay";
108
109 eeprom1: eeprom@50 {
110 compatible = "atmel,24c02";
111 reg = <0x50>;
112 pagesize = <16>;
113 };
114
115 eeprom2: eeprom@51 {
116 compatible = "atmel,24c02";
117 reg = <0x51>;
118 pagesize = <16>;
119 };
120
121 eeprom3: eeprom@52 {
122 compatible = "atmel,24c02";
123 reg = <0x52>;
124 pagesize = <16>;
125 };
126
127 eeprom4: eeprom@53 {
128 compatible = "atmel,24c02";
129 reg = <0x53>;
130 pagesize = <16>;
131 };
132
133 gpio: pca9555@23 {
134 compatible = "nxp,pca9555";
135 reg = <0x23>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 rtc: ds1672@68 {
141 compatible = "dallas,ds1672";
142 reg = <0x68>;
143 };
144};
145
146&i2c2 {
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c2>;
150 status = "okay";
151};
152
153&i2c3 {
154 clock-frequency = <100000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c3>;
157 status = "okay";
158};
159
160&pcie {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_pcie>;
163 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
164 status = "okay";
165};
166
167&uart2 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 status = "okay";
171};
172
173&uart3 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart3>;
176 status = "okay";
177};
178
179&uart5 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart5>;
182 status = "okay"; };
183
184&usbh1 {
185 status = "okay";
186};
187
188&iomuxc {
189 imx6qdl-gw552x {
190 pinctrl_gpio_leds: gpioledsgrp {
191 fsl,pins = <
192 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
193 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
194 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
195 >;
196 };
197
198 pinctrl_gpmi_nand: gpminandgrp {
199 fsl,pins = <
200 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
201 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
205 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
206 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
207 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
208 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
209 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
210 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
211 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
212 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
213 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
214 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
215 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
216 >;
217 };
218
219 pinctrl_i2c1: i2c1grp {
220 fsl,pins = <
221 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
222 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
223 >;
224 };
225
226 pinctrl_i2c2: i2c2grp {
227 fsl,pins = <
228 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
229 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
230 >;
231 };
232
233 pinctrl_i2c3: i2c3grp {
234 fsl,pins = <
235 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
236 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
237 >;
238 };
239
240 pinctrl_pcie: pciegrp {
241 fsl,pins = <
242 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
243 >;
244 };
245
246 pinctrl_uart2: uart2grp {
247 fsl,pins = <
248 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
249 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
250 >;
251 };
252
253 pinctrl_uart3: uart3grp {
254 fsl,pins = <
255 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
256 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
257 >;
258 };
259
260 pinctrl_uart5: uart5grp {
261 fsl,pins = <
262 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
263 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
264 >;
265 };
266 };
267};
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
new file mode 100644
index 000000000000..62841e85a91e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -0,0 +1,200 @@
1/*
2 * Copyright (C) 2013,2014 Russell King
3 */
4#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi"
6
7/ {
8 chosen {
9 stdout-path = &uart1;
10 };
11
12 ir_recv: ir-receiver {
13 compatible = "gpio-ir-receiver";
14 gpios = <&gpio3 5 1>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
17 };
18
19 regulators {
20 compatible = "simple-bus";
21
22 reg_3p3v: 3p3v {
23 compatible = "regulator-fixed";
24 regulator-name = "3P3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-always-on;
28 };
29
30 reg_usbh1_vbus: usb-h1-vbus {
31 compatible = "regulator-fixed";
32 enable-active-high;
33 gpio = <&gpio1 0 0>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
36 regulator-name = "usb_h1_vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 };
40
41 reg_usbotg_vbus: usb-otg-vbus {
42 compatible = "regulator-fixed";
43 enable-active-high;
44 gpio = <&gpio3 22 0>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
47 regulator-name = "usb_otg_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 };
51 };
52
53 sound-spdif {
54 compatible = "fsl,imx-audio-spdif";
55 model = "On-board SPDIF";
56 /* IMX6 doesn't implement this yet */
57 spdif-controller = <&spdif>;
58 spdif-out;
59 };
60};
61
62&can1 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
65 status = "okay";
66};
67
68&hdmi {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
71 ddc-i2c-bus = <&i2c2>;
72 status = "okay";
73};
74
75&i2c1 {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
78
79 /*
80 * Not fitted on Carrier-1 board... yet
81 status = "okay";
82
83 rtc: pcf8523@68 {
84 compatible = "nxp,pcf8523";
85 reg = <0x68>;
86 };
87 */
88};
89
90&i2c2 {
91 clock-frequency = <100000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
94 status = "okay";
95};
96
97&iomuxc {
98 hummingboard {
99 pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
100 fsl,pins = <
101 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
102 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
103 >;
104 };
105
106 pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
107 fsl,pins = <
108 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
109 >;
110 };
111
112 pinctrl_hummingboard_hdmi: hummingboard-hdmi {
113 fsl,pins = <
114 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
115 >;
116 };
117
118 pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
119 fsl,pins = <
120 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
121 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
122 >;
123 };
124
125 pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
126 fsl,pins = <
127 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
128 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
129 >;
130 };
131
132 pinctrl_hummingboard_spdif: hummingboard-spdif {
133 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
134 };
135
136 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
137 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
138 };
139
140 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
141 /*
142 * Similar to pinctrl_usbotg_2, but we want it
143 * pulled down for a fixed host connection.
144 */
145 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
146 };
147
148 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
149 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
150 };
151
152 pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
153 fsl,pins = <
154 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
155 >;
156 };
157
158 pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
159 fsl,pins = <
160 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
161 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
162 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
163 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
164 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
165 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
166 >;
167 };
168 };
169};
170
171&spdif {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
174 status = "okay";
175};
176
177&usbh1 {
178 disable-over-current;
179 vbus-supply = <&reg_usbh1_vbus>;
180 status = "okay";
181};
182
183&usbotg {
184 disable-over-current;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
187 vbus-supply = <&reg_usbotg_vbus>;
188 status = "okay";
189};
190
191&usdhc2 {
192 pinctrl-names = "default";
193 pinctrl-0 = <
194 &pinctrl_hummingboard_usdhc2_aux
195 &pinctrl_hummingboard_usdhc2
196 >;
197 vmmc-supply = <&reg_3p3v>;
198 cd-gpios = <&gpio1 4 0>;
199 status = "okay";
200};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 42ff525ebe13..08218120e770 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -174,6 +174,11 @@
174 status = "okay"; 174 status = "okay";
175}; 175};
176 176
177&hdmi {
178 ddc-i2c-bus = <&i2c2>;
179 status = "okay";
180};
181
177&i2c1 { 182&i2c1 {
178 clock-frequency = <100000>; 183 clock-frequency = <100000>;
179 pinctrl-names = "default"; 184 pinctrl-names = "default";
@@ -187,6 +192,25 @@
187 VDDA-supply = <&reg_2p5v>; 192 VDDA-supply = <&reg_2p5v>;
188 VDDIO-supply = <&reg_3p3v>; 193 VDDIO-supply = <&reg_3p3v>;
189 }; 194 };
195
196 rtc: rtc@6f {
197 compatible = "isil,isl1208";
198 reg = <0x6f>;
199 };
200};
201
202&i2c2 {
203 clock-frequency = <100000>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c2>;
206 status = "okay";
207};
208
209&i2c3 {
210 clock-frequency = <100000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c3>;
213 status = "okay";
190}; 214};
191 215
192&iomuxc { 216&iomuxc {
@@ -266,6 +290,20 @@
266 >; 290 >;
267 }; 291 };
268 292
293 pinctrl_i2c2: i2c2grp {
294 fsl,pins = <
295 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
296 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
297 >;
298 };
299
300 pinctrl_i2c3: i2c3grp {
301 fsl,pins = <
302 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
303 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
304 >;
305 };
306
269 pinctrl_pwm1: pwm1grp { 307 pinctrl_pwm1: pwm1grp {
270 fsl,pins = < 308 fsl,pins = <
271 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 309 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 2694aa84e187..0e50bb0a6b94 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -83,7 +83,7 @@
83 }; 83 };
84 84
85 pmic@58 { 85 pmic@58 {
86 compatible = "dialog,da9063"; 86 compatible = "dlg,da9063";
87 reg = <0x58>; 87 reg = <0x58>;
88 interrupt-parent = <&gpio4>; 88 interrupt-parent = <&gpio4>;
89 interrupts = <17 0x8>; /* active-low GPIO4_17 */ 89 interrupts = <17 0x8>; /* active-low GPIO4_17 */
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index ec43dde78525..baf2f00d519a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -54,6 +54,19 @@
54 gpio = <&gpio4 10 0>; 54 gpio = <&gpio4 10 0>;
55 enable-active-high; 55 enable-active-high;
56 }; 56 };
57
58 reg_pcie: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_pcie_reg>;
63 regulator-name = "MPCIE_3V3";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&gpio3 19 0>;
67 regulator-always-on;
68 enable-active-high;
69 };
57 }; 70 };
58 71
59 gpio-keys { 72 gpio-keys {
@@ -314,15 +327,15 @@
314 imx6qdl-sabresd { 327 imx6qdl-sabresd {
315 pinctrl_hog: hoggrp { 328 pinctrl_hog: hoggrp {
316 fsl,pins = < 329 fsl,pins = <
317 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 330 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
318 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 331 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
319 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 332 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
320 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 333 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
321 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 334 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
322 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 335 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
323 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 336 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
324 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 337 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
325 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 338 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
326 >; 339 >;
327 }; 340 };
328 341
@@ -367,9 +380,9 @@
367 380
368 pinctrl_gpio_keys: gpio_keysgrp { 381 pinctrl_gpio_keys: gpio_keysgrp {
369 fsl,pins = < 382 fsl,pins = <
370 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 383 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
371 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 384 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
372 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 385 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
373 >; 386 >;
374 }; 387 };
375 388
@@ -396,7 +409,13 @@
396 409
397 pinctrl_pcie: pciegrp { 410 pinctrl_pcie: pciegrp {
398 fsl,pins = < 411 fsl,pins = <
399 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 412 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
413 >;
414 };
415
416 pinctrl_pcie_reg: pciereggrp {
417 fsl,pins = <
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
400 >; 419 >;
401 }; 420 };
402 421
@@ -468,7 +487,7 @@
468 gpio_leds { 487 gpio_leds {
469 pinctrl_gpio_leds: gpioledsgrp { 488 pinctrl_gpio_leds: gpioledsgrp {
470 fsl,pins = < 489 fsl,pins = <
471 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 490 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
472 >; 491 >;
473 }; 492 };
474 }; 493 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c701af958006..9596ed5867e6 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -137,7 +137,9 @@
137 137
138 pcie: pcie@0x01000000 { 138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x4000>; /* DBI */ 140 reg = <0x01ffc000 0x04000>,
141 <0x01f00000 0x80000>;
142 reg-names = "dbi", "config";
141 #address-cells = <3>; 143 #address-cells = <3>;
142 #size-cells = <2>; 144 #size-cells = <2>;
143 device_type = "pci"; 145 device_type = "pci";
@@ -273,11 +275,14 @@
273 }; 275 };
274 276
275 ssi1: ssi@02028000 { 277 ssi1: ssi@02028000 {
278 #sound-dai-cells = <0>;
276 compatible = "fsl,imx6q-ssi", 279 compatible = "fsl,imx6q-ssi",
277 "fsl,imx51-ssi"; 280 "fsl,imx51-ssi";
278 reg = <0x02028000 0x4000>; 281 reg = <0x02028000 0x4000>;
279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 282 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; 283 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
284 <&clks IMX6QDL_CLK_SSI1>;
285 clock-names = "ipg", "baud";
281 dmas = <&sdma 37 1 0>, 286 dmas = <&sdma 37 1 0>,
282 <&sdma 38 1 0>; 287 <&sdma 38 1 0>;
283 dma-names = "rx", "tx"; 288 dma-names = "rx", "tx";
@@ -286,11 +291,14 @@
286 }; 291 };
287 292
288 ssi2: ssi@0202c000 { 293 ssi2: ssi@0202c000 {
294 #sound-dai-cells = <0>;
289 compatible = "fsl,imx6q-ssi", 295 compatible = "fsl,imx6q-ssi",
290 "fsl,imx51-ssi"; 296 "fsl,imx51-ssi";
291 reg = <0x0202c000 0x4000>; 297 reg = <0x0202c000 0x4000>;
292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; 299 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
300 <&clks IMX6QDL_CLK_SSI2>;
301 clock-names = "ipg", "baud";
294 dmas = <&sdma 41 1 0>, 302 dmas = <&sdma 41 1 0>,
295 <&sdma 42 1 0>; 303 <&sdma 42 1 0>;
296 dma-names = "rx", "tx"; 304 dma-names = "rx", "tx";
@@ -299,11 +307,14 @@
299 }; 307 };
300 308
301 ssi3: ssi@02030000 { 309 ssi3: ssi@02030000 {
310 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6q-ssi", 311 compatible = "fsl,imx6q-ssi",
303 "fsl,imx51-ssi"; 312 "fsl,imx51-ssi";
304 reg = <0x02030000 0x4000>; 313 reg = <0x02030000 0x4000>;
305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 314 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; 315 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
316 <&clks IMX6QDL_CLK_SSI3>;
317 clock-names = "ipg", "baud";
307 dmas = <&sdma 45 1 0>, 318 dmas = <&sdma 45 1 0>,
308 <&sdma 46 1 0>; 319 <&sdma 46 1 0>;
309 dma-names = "rx", "tx"; 320 dma-names = "rx", "tx";
@@ -396,8 +407,9 @@
396 reg = <0x02098000 0x4000>; 407 reg = <0x02098000 0x4000>;
397 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 408 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 409 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
399 <&clks IMX6QDL_CLK_GPT_IPG_PER>; 410 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
400 clock-names = "ipg", "per"; 411 <&clks IMX6QDL_CLK_GPT_3M>;
412 clock-names = "ipg", "per", "osc_per";
401 }; 413 };
402 414
403 gpio1: gpio@0209c000 { 415 gpio1: gpio@0209c000 {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 3f9e041c0252..898d14fd765f 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -20,6 +20,13 @@
20 reg = <0x80000000 0x40000000>; 20 reg = <0x80000000 0x40000000>;
21 }; 21 };
22 22
23 backlight {
24 compatible = "pwm-backlight";
25 pwms = <&pwm1 0 5000000>;
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 };
29
23 leds { 30 leds {
24 compatible = "gpio-leds"; 31 compatible = "gpio-leds";
25 pinctrl-names = "default"; 32 pinctrl-names = "default";
@@ -74,6 +81,14 @@
74 regulator-max-microvolt = <4325000>; 81 regulator-max-microvolt = <4325000>;
75 regulator-boot-on; 82 regulator-boot-on;
76 }; 83 };
84
85 reg_lcd_3v3: regulator@4 {
86 compatible = "regulator-fixed";
87 reg = <4>;
88 regulator-name = "lcd-3v3";
89 gpio = <&gpio4 3 0>;
90 enable-active-high;
91 };
77 }; 92 };
78 93
79 sound { 94 sound {
@@ -329,12 +344,6 @@
329 >; 344 >;
330 }; 345 };
331 346
332 pinctrl_led: ledgrp {
333 fsl,pins = <
334 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
335 >;
336 };
337
338 pinctrl_kpp: kppgrp { 347 pinctrl_kpp: kppgrp {
339 fsl,pins = < 348 fsl,pins = <
340 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 349 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@@ -346,6 +355,51 @@
346 >; 355 >;
347 }; 356 };
348 357
358 pinctrl_lcd: lcdgrp {
359 fsl,pins = <
360 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
361 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
362 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
363 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
364 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
365 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
366 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
367 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
368 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
369 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
370 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
371 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
372 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
373 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
374 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
375 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
376 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
377 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
378 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
379 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
380 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
381 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
382 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
383 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
384 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
385 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
386 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
387 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
388 >;
389 };
390
391 pinctrl_led: ledgrp {
392 fsl,pins = <
393 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
394 >;
395 };
396
397 pinctrl_pwm1: pwmgrp {
398 fsl,pins = <
399 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
400 >;
401 };
402
349 pinctrl_uart1: uart1grp { 403 pinctrl_uart1: uart1grp {
350 fsl,pins = < 404 fsl,pins = <
351 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 405 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
@@ -488,6 +542,44 @@
488 status = "okay"; 542 status = "okay";
489}; 543};
490 544
545&lcdif {
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_lcd>;
548 lcd-supply = <&reg_lcd_3v3>;
549 display = <&display0>;
550 status = "okay";
551
552 display0: display0 {
553 bits-per-pixel = <32>;
554 bus-width = <24>;
555
556 display-timings {
557 native-mode = <&timing0>;
558 timing0: timing0 {
559 clock-frequency = <33500000>;
560 hactive = <800>;
561 vactive = <480>;
562 hback-porch = <89>;
563 hfront-porch = <164>;
564 vback-porch = <23>;
565 vfront-porch = <10>;
566 hsync-len = <10>;
567 vsync-len = <10>;
568 hsync-active = <0>;
569 vsync-active = <0>;
570 de-active = <1>;
571 pixelclk-active = <0>;
572 };
573 };
574 };
575};
576
577&pwm1 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_pwm1>;
580 status = "okay";
581};
582
491&ssi2 { 583&ssi2 {
492 status = "okay"; 584 status = "okay";
493}; 585};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c75800ca8b35..dfd83e6d8087 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -226,11 +226,14 @@
226 }; 226 };
227 227
228 ssi1: ssi@02028000 { 228 ssi1: ssi@02028000 {
229 #sound-dai-cells = <0>;
229 compatible = "fsl,imx6sl-ssi", 230 compatible = "fsl,imx6sl-ssi",
230 "fsl,imx51-ssi"; 231 "fsl,imx51-ssi";
231 reg = <0x02028000 0x4000>; 232 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SL_CLK_SSI1>; 234 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
235 <&clks IMX6SL_CLK_SSI1>;
236 clock-names = "ipg", "baud";
234 dmas = <&sdma 37 1 0>, 237 dmas = <&sdma 37 1 0>,
235 <&sdma 38 1 0>; 238 <&sdma 38 1 0>;
236 dma-names = "rx", "tx"; 239 dma-names = "rx", "tx";
@@ -239,11 +242,14 @@
239 }; 242 };
240 243
241 ssi2: ssi@0202c000 { 244 ssi2: ssi@0202c000 {
245 #sound-dai-cells = <0>;
242 compatible = "fsl,imx6sl-ssi", 246 compatible = "fsl,imx6sl-ssi",
243 "fsl,imx51-ssi"; 247 "fsl,imx51-ssi";
244 reg = <0x0202c000 0x4000>; 248 reg = <0x0202c000 0x4000>;
245 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 249 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6SL_CLK_SSI2>; 250 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
251 <&clks IMX6SL_CLK_SSI2>;
252 clock-names = "ipg", "baud";
247 dmas = <&sdma 41 1 0>, 253 dmas = <&sdma 41 1 0>,
248 <&sdma 42 1 0>; 254 <&sdma 42 1 0>;
249 dma-names = "rx", "tx"; 255 dma-names = "rx", "tx";
@@ -252,11 +258,14 @@
252 }; 258 };
253 259
254 ssi3: ssi@02030000 { 260 ssi3: ssi@02030000 {
261 #sound-dai-cells = <0>;
255 compatible = "fsl,imx6sl-ssi", 262 compatible = "fsl,imx6sl-ssi",
256 "fsl,imx51-ssi"; 263 "fsl,imx51-ssi";
257 reg = <0x02030000 0x4000>; 264 reg = <0x02030000 0x4000>;
258 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 265 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX6SL_CLK_SSI3>; 266 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
267 <&clks IMX6SL_CLK_SSI3>;
268 clock-names = "ipg", "baud";
260 dmas = <&sdma 45 1 0>, 269 dmas = <&sdma 45 1 0>,
261 <&sdma 46 1 0>; 270 <&sdma 46 1 0>;
262 dma-names = "rx", "tx"; 271 dma-names = "rx", "tx";
@@ -529,6 +538,14 @@
529 }; 538 };
530 }; 539 };
531 540
541 tempmon: tempmon {
542 compatible = "fsl,imx6q-tempmon";
543 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
544 fsl,tempmon = <&anatop>;
545 fsl,tempmon-data = <&ocotp>;
546 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
547 };
548
532 usbphy1: usbphy@020c9000 { 549 usbphy1: usbphy@020c9000 {
533 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 550 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
534 reg = <0x020c9000 0x1000>; 551 reg = <0x020c9000 0x1000>;
@@ -627,8 +644,14 @@
627 }; 644 };
628 645
629 lcdif: lcdif@020f8000 { 646 lcdif: lcdif@020f8000 {
647 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
630 reg = <0x020f8000 0x4000>; 648 reg = <0x020f8000 0x4000>;
631 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 649 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
651 <&clks IMX6SL_CLK_LCDIF_AXI>,
652 <&clks IMX6SL_CLK_DUMMY>;
653 clock-names = "pix", "axi", "disp_axi";
654 status = "disabled";
632 }; 655 };
633 656
634 dcp: dcp@020fc000 { 657 dcp: dcp@020fc000 {
@@ -784,7 +807,7 @@
784 }; 807 };
785 808
786 ocotp: ocotp@021bc000 { 809 ocotp: ocotp@021bc000 {
787 compatible = "fsl,imx6sl-ocotp"; 810 compatible = "fsl,imx6sl-ocotp", "syscon";
788 reg = <0x021bc000 0x4000>; 811 reg = <0x021bc000 0x4000>;
789 }; 812 };
790 813
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d970590..82d6b34527b7 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -24,6 +24,13 @@
24 reg = <0x80000000 0x40000000>; 24 reg = <0x80000000 0x40000000>;
25 }; 25 };
26 26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
27 gpio-keys { 34 gpio-keys {
28 compatible = "gpio-keys"; 35 compatible = "gpio-keys";
29 pinctrl-names = "default"; 36 pinctrl-names = "default";
@@ -90,6 +97,14 @@
90 regulator-min-microvolt = <5000000>; 97 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>;
92 }; 99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
93 }; 108 };
94 109
95 sound { 110 sound {
@@ -251,6 +266,44 @@
251 }; 266 };
252}; 267};
253 268
269&lcdif1 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_lcd>;
272 lcd-supply = <&reg_lcd_3v3>;
273 display = <&display0>;
274 status = "okay";
275
276 display0: display0 {
277 bits-per-pixel = <16>;
278 bus-width = <24>;
279
280 display-timings {
281 native-mode = <&timing0>;
282 timing0: timing0 {
283 clock-frequency = <33500000>;
284 hactive = <800>;
285 vactive = <480>;
286 hback-porch = <89>;
287 hfront-porch = <164>;
288 vback-porch = <23>;
289 vfront-porch = <10>;
290 hsync-len = <10>;
291 vsync-len = <10>;
292 hsync-active = <0>;
293 vsync-active = <0>;
294 de-active = <1>;
295 pixelclk-active = <0>;
296 };
297 };
298 };
299};
300
301&pwm3 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_pwm3>;
304 status = "okay";
305};
306
254&ssi2 { 307&ssi2 {
255 status = "okay"; 308 status = "okay";
256}; 309};
@@ -365,6 +418,46 @@
365 >; 418 >;
366 }; 419 };
367 420
421 pinctrl_lcd: lcdgrp {
422 fsl,pins = <
423 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
424 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
425 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
426 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
427 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
428 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
429 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
430 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
431 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
432 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
433 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
434 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
435 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
436 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
437 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
438 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
439 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
440 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
441 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
442 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
443 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
444 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
445 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
446 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
447 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
448 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
449 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
450 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
451 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
452 >;
453 };
454
455 pinctrl_pwm3: pwm3grp-1 {
456 fsl,pins = <
457 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
458 >;
459 };
460
368 pinctrl_vcc_sd3: vccsd3grp { 461 pinctrl_vcc_sd3: vccsd3grp {
369 fsl,pins = < 462 fsl,pins = <
370 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 463 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f4b9da65bc0f..888dd767a0b3 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -298,6 +298,7 @@
298 }; 298 };
299 299
300 ssi1: ssi@02028000 { 300 ssi1: ssi@02028000 {
301 #sound-dai-cells = <0>;
301 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 302 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
302 reg = <0x02028000 0x4000>; 303 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 304 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -311,6 +312,7 @@
311 }; 312 };
312 313
313 ssi2: ssi@0202c000 { 314 ssi2: ssi@0202c000 {
315 #sound-dai-cells = <0>;
314 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 316 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
315 reg = <0x0202c000 0x4000>; 317 reg = <0x0202c000 0x4000>;
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,6 +326,7 @@
324 }; 326 };
325 327
326 ssi3: ssi@02030000 { 328 ssi3: ssi@02030000 {
329 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 330 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02030000 0x4000>; 331 reg = <0x02030000 0x4000>;
329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -418,7 +421,7 @@
418 reg = <0x02098000 0x4000>; 421 reg = <0x02098000 0x4000>;
419 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 422 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 423 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
421 <&clks IMX6SX_CLK_GPT_SERIAL>; 424 <&clks IMX6SX_CLK_GPT_3M>;
422 clock-names = "ipg", "per"; 425 clock-names = "ipg", "per";
423 }; 426 };
424 427
@@ -1062,6 +1065,7 @@
1062 }; 1065 };
1063 1066
1064 lcdif1: lcdif@02220000 { 1067 lcdif1: lcdif@02220000 {
1068 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1065 reg = <0x02220000 0x4000>; 1069 reg = <0x02220000 0x4000>;
1066 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1070 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1071 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
@@ -1072,6 +1076,7 @@
1072 }; 1076 };
1073 1077
1074 lcdif2: lcdif@02224000 { 1078 lcdif2: lcdif@02224000 {
1079 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1075 reg = <0x02224000 0x4000>; 1080 reg = <0x02224000 0x4000>;
1076 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1081 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1082 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index 03d01909525b..c358b4b9a073 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -67,6 +67,8 @@
67 clock-names = "usb"; 67 clock-names = "usb";
68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; 68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
69 ranges; 69 ranges;
70 dma-coherent;
71 dma-ranges;
70 status = "disabled"; 72 status = "disabled";
71 73
72 dwc3@25010000 { 74 dwc3@25010000 {
@@ -76,5 +78,16 @@
76 usb-phy = <&usb1_phy>, <&usb1_phy>; 78 usb-phy = <&usb1_phy>, <&usb1_phy>;
77 }; 79 };
78 }; 80 };
81
82 dspgpio0: keystone_dsp_gpio@02620240 {
83 compatible = "ti,keystone-dsp-gpio";
84 gpio-controller;
85 #gpio-cells = <2>;
86 gpio,syscon-dev = <&devctrl 0x240>;
87 };
79 }; 88 };
80}; 89};
90
91&mdio {
92 reg = <0x24200f00 0x100>;
93};
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
index c73899c73118..d721f4b737f7 100644
--- a/arch/arm/boot/dts/k2hk.dtsi
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -42,5 +42,61 @@
42 42
43 soc { 43 soc {
44 /include/ "k2hk-clocks.dtsi" 44 /include/ "k2hk-clocks.dtsi"
45
46 dspgpio0: keystone_dsp_gpio@02620240 {
47 compatible = "ti,keystone-dsp-gpio";
48 gpio-controller;
49 #gpio-cells = <2>;
50 gpio,syscon-dev = <&devctrl 0x240>;
51 };
52
53 dspgpio1: keystone_dsp_gpio@2620244 {
54 compatible = "ti,keystone-dsp-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 gpio,syscon-dev = <&devctrl 0x244>;
58 };
59
60 dspgpio2: keystone_dsp_gpio@2620248 {
61 compatible = "ti,keystone-dsp-gpio";
62 gpio-controller;
63 #gpio-cells = <2>;
64 gpio,syscon-dev = <&devctrl 0x248>;
65 };
66
67 dspgpio3: keystone_dsp_gpio@262024c {
68 compatible = "ti,keystone-dsp-gpio";
69 gpio-controller;
70 #gpio-cells = <2>;
71 gpio,syscon-dev = <&devctrl 0x24c>;
72 };
73
74 dspgpio4: keystone_dsp_gpio@2620250 {
75 compatible = "ti,keystone-dsp-gpio";
76 gpio-controller;
77 #gpio-cells = <2>;
78 gpio,syscon-dev = <&devctrl 0x250>;
79 };
80
81 dspgpio5: keystone_dsp_gpio@2620254 {
82 compatible = "ti,keystone-dsp-gpio";
83 gpio-controller;
84 #gpio-cells = <2>;
85 gpio,syscon-dev = <&devctrl 0x254>;
86 };
87
88 dspgpio6: keystone_dsp_gpio@2620258 {
89 compatible = "ti,keystone-dsp-gpio";
90 gpio-controller;
91 #gpio-cells = <2>;
92 gpio,syscon-dev = <&devctrl 0x258>;
93 };
94
95 dspgpio7: keystone_dsp_gpio@262025c {
96 compatible = "ti,keystone-dsp-gpio";
97 gpio-controller;
98 #gpio-cells = <2>;
99 gpio,syscon-dev = <&devctrl 0x25c>;
100 };
45 }; 101 };
46}; 102};
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi
index 1f7f479589e1..e32c3baa77b8 100644
--- a/arch/arm/boot/dts/k2l.dtsi
+++ b/arch/arm/boot/dts/k2l.dtsi
@@ -51,5 +51,51 @@
51 clocks = <&clkuart3>; 51 clocks = <&clkuart3>;
52 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; 52 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
53 }; 53 };
54
55 dspgpio0: keystone_dsp_gpio@02620240 {
56 compatible = "ti,keystone-dsp-gpio";
57 gpio-controller;
58 #gpio-cells = <2>;
59 gpio,syscon-dev = <&devctrl 0x240>;
60 };
61
62 dspgpio1: keystone_dsp_gpio@2620244 {
63 compatible = "ti,keystone-dsp-gpio";
64 gpio-controller;
65 #gpio-cells = <2>;
66 gpio,syscon-dev = <&devctrl 0x244>;
67 };
68
69 dspgpio2: keystone_dsp_gpio@2620248 {
70 compatible = "ti,keystone-dsp-gpio";
71 gpio-controller;
72 #gpio-cells = <2>;
73 gpio,syscon-dev = <&devctrl 0x248>;
74 };
75
76 dspgpio3: keystone_dsp_gpio@262024c {
77 compatible = "ti,keystone-dsp-gpio";
78 gpio-controller;
79 #gpio-cells = <2>;
80 gpio,syscon-dev = <&devctrl 0x24c>;
81 };
54 }; 82 };
55}; 83};
84
85&spi0 {
86 ti,davinci-spi-num-cs = <5>;
87};
88
89&spi1 {
90 ti,davinci-spi-num-cs = <3>;
91};
92
93&spi2 {
94 ti,davinci-spi-num-cs = <5>;
95 /* Pin muxed. Enabled and configured by Bootloader */
96 status = "disabled";
97};
98
99&mdio {
100 reg = <0x26200f00 0x100>;
101};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 9e31fe7d31f8..5d3e83fa2242 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -172,7 +172,7 @@
172 compatible = "ti,keystone-usbphy"; 172 compatible = "ti,keystone-usbphy";
173 #address-cells = <1>; 173 #address-cells = <1>;
174 #size-cells = <1>; 174 #size-cells = <1>;
175 reg = <0x2620738 32>; 175 reg = <0x2620738 24>;
176 status = "disabled"; 176 status = "disabled";
177 }; 177 };
178 178
@@ -277,5 +277,13 @@
277 clock-names = "fck"; 277 clock-names = "fck";
278 bus_freq = <2500000>; 278 bus_freq = <2500000>;
279 }; 279 };
280
281 kirq0: keystone_irq@26202a0 {
282 compatible = "ti,keystone-irq";
283 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
284 interrupt-controller;
285 #interrupt-cells = <1>;
286 ti,syscon-dev = <&devctrl 0x2a0>;
287 };
280 }; 288 };
281}; 289};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
new file mode 100644
index 000000000000..e6539ea5a711
--- /dev/null
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -0,0 +1,110 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/include/ "skeleton.dtsi"
49
50/ {
51 interrupt-parent = <&gic>;
52
53 gic: interrupt-controller@c4301000 {
54 compatible = "arm,cortex-a9-gic";
55 reg = <0xc4301000 0x1000>,
56 <0xc4300100 0x0100>;
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 };
60
61 timer@c1109940 {
62 compatible = "amlogic,meson6-timer";
63 reg = <0xc1109940 0x14>;
64 interrupts = <0 10 1>;
65 };
66
67 soc {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges;
72
73 wdt: watchdog@c1109900 {
74 compatible = "amlogic,meson6-wdt";
75 reg = <0xc1109900 0x8>;
76 };
77
78 uart_AO: serial@c81004c0 {
79 compatible = "amlogic,meson-uart";
80 reg = <0xc81004c0 0x14>;
81 interrupts = <0 90 1>;
82 clocks = <&clk81>;
83 status = "disabled";
84 };
85
86 uart_A: serial@c81084c0 {
87 compatible = "amlogic,meson-uart";
88 reg = <0xc81084c0 0x14>;
89 interrupts = <0 90 1>;
90 clocks = <&clk81>;
91 status = "disabled";
92 };
93
94 uart_B: serial@c81084dc {
95 compatible = "amlogic,meson-uart";
96 reg = <0xc81084dc 0x14>;
97 interrupts = <0 90 1>;
98 clocks = <&clk81>;
99 status = "disabled";
100 };
101
102 uart_C: serial@c8108700 {
103 compatible = "amlogic,meson-uart";
104 reg = <0xc8108700 0x14>;
105 interrupts = <0 90 1>;
106 clocks = <&clk81>;
107 status = "disabled";
108 };
109 };
110}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
new file mode 100644
index 000000000000..dc2541faf1ec
--- /dev/null
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "meson6.dtsi"
50
51/ {
52 model = "Geniatech ATV1200";
53 compatible = "geniatech,atv1200";
54
55 aliases {
56 serial0 = &uart_AO;
57 };
58
59 memory {
60 reg = <0x40000000 0x80000000>;
61 };
62};
63
64&uart_AO {
65 status = "okay";
66};
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
new file mode 100644
index 000000000000..4ba49127779f
--- /dev/null
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/include/ "meson.dtsi"
49
50/ {
51 model = "Amlogic Meson6 SoC";
52 compatible = "amlogic,meson6";
53
54 interrupt-parent = <&gic>;
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu@200 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a9";
63 reg = <0x200>;
64 };
65
66 cpu@201 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a9";
69 reg = <0x201>;
70 };
71 };
72
73 clk81: clk@0 {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <200000000>;
77 };
78}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 443b4467de15..0da047013120 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -18,6 +18,11 @@
18 18
19/ { 19/ {
20 model = "bq Aquaris5"; 20 model = "bq Aquaris5";
21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
22
23 chosen {
24 bootargs = "earlyprintk";
25 };
21 26
22 memory { 27 memory {
23 reg = <0x80000000 0x40000000>; 28 reg = <0x80000000 0x40000000>;
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index d0297a051549..e3c7600ddb38 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -81,8 +81,8 @@
81 clock-names = "system-clk", "rtc-clk"; 81 clock-names = "system-clk", "rtc-clk";
82 }; 82 };
83 83
84 gic: interrupt-controller@10212000 { 84 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a15-gic"; 85 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 86 interrupt-controller;
87 #interrupt-cells = <3>; 87 #interrupt-cells = <3>;
88 reg = <0x10211000 0x1000>, 88 reg = <0x10211000 0x1000>,
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 9be3c1266378..ae89aad01595 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -159,6 +159,14 @@
159 ti,hwmods = "mailbox"; 159 ti,hwmods = "mailbox";
160 ti,mbox-num-users = <4>; 160 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>; 161 ti,mbox-num-fifos = <6>;
162 mbox_dsp: dsp {
163 ti,mbox-tx = <0 0 0>;
164 ti,mbox-rx = <1 0 0>;
165 };
166 mbox_iva: iva {
167 ti,mbox-tx = <2 1 3>;
168 ti,mbox-rx = <3 1 3>;
169 };
162 }; 170 };
163 171
164 timer1: timer@48028000 { 172 timer1: timer@48028000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 1a00f15d9096..b56d71611026 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -249,6 +249,10 @@
249 ti,hwmods = "mailbox"; 249 ti,hwmods = "mailbox";
250 ti,mbox-num-users = <4>; 250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <6>; 251 ti,mbox-num-fifos = <6>;
252 mbox_dsp: dsp {
253 ti,mbox-tx = <0 0 0>;
254 ti,mbox-rx = <1 0 0>;
255 };
252 }; 256 };
253 257
254 timer1: timer@49018000 { 258 timer1: timer@49018000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 1becefce821b..06a8aec4e6ea 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -174,8 +174,8 @@
174 174
175 uart3_pins: pinmux_uart3_pins { 175 uart3_pins: pinmux_uart3_pins {
176 pinctrl-single,pins = < 176 pinctrl-single,pins = <
177 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 177 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
178 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ 178 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
179 >; 179 >;
180 }; 180 };
181 181
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dtsi
index 021311f7964b..fd34f913ace3 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -26,6 +26,10 @@
26 reg = <0x80000000 0x20000000>; /* 512 MB */ 26 reg = <0x80000000 0x20000000>; /* 512 MB */
27 }; 27 };
28 28
29 aliases {
30 display0 = &lcd;
31 };
32
29 gpio-keys { 33 gpio-keys {
30 compatible = "gpio-keys"; 34 compatible = "gpio-keys";
31 35
@@ -74,9 +78,30 @@
74 }; 78 };
75 }; 79 };
76 }; 80 };
81
82 hsusb2_phy: hsusb2_phy {
83 compatible = "usb-nop-xceiv";
84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
85 };
77}; 86};
78 87
79&omap3_pmx_core { 88&omap3_pmx_core {
89 pinctrl-names = "default";
90 pinctrl-0 = <
91 &hsusb2_pins
92 >;
93
94 hsusb2_pins: pinmux_hsusb2_pins {
95 pinctrl-single,pins = <
96 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
97 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
98 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
99 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
100 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
101 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
102 >;
103 };
104
80 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
81 pinctrl-single,pins = < 106 pinctrl-single,pins = <
82 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
@@ -141,12 +166,31 @@
141 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
142 >; 167 >;
143 }; 168 };
169};
170
171&omap3_pmx_core2 {
172 pinctrl-names = "default";
173 pinctrl-0 = <
174 &hsusb2_2_pins
175 >;
176
177 hsusb2_2_pins: pinmux_hsusb2_2_pins {
178 pinctrl-single,pins = <
179 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
180 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
181 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
182 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
183 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
184 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
185 >;
186 };
144 187
145 spi_gpio_pins: spi_gpio_pinmux { 188 spi_gpio_pins: spi_gpio_pinmux {
146 pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */ 189 pinctrl-single,pins = <
147 0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */ 190 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
148 0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */ 191 OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */
149 0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */ 192 OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */
193 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */
150 >; 194 >;
151 }; 195 };
152}; 196};
@@ -196,6 +240,9 @@
196 #size-cells = <0>; 240 #size-cells = <0>;
197 reg = <0x45>; 241 reg = <0x45>;
198 242
243 gpio-controller;
244 #gpio-cells = <2>;
245
199 gta04_led0: red_aux@0 { 246 gta04_led0: red_aux@0 {
200 label = "gta04:red:aux"; 247 label = "gta04:red:aux";
201 reg = <0x0>; 248 reg = <0x0>;
@@ -216,11 +263,16 @@
216 label = "gta04:green:power"; 263 label = "gta04:green:power";
217 reg = <0x4>; 264 reg = <0x4>;
218 }; 265 };
266
267 wifi_reset: wifi_reset@6 {
268 reg = <0x6>;
269 compatible = "gpio";
270 };
219 }; 271 };
220 272
221 /* compass aka magnetometer */ 273 /* compass aka magnetometer */
222 hmc5843@1e { 274 hmc5843@1e {
223 compatible = "honeywell,hmc5843"; 275 compatible = "honeywell,hmc5883l";
224 reg = <0x1e>; 276 reg = <0x1e>;
225 }; 277 };
226 278
@@ -248,6 +300,14 @@
248 power = <50>; 300 power = <50>;
249}; 301};
250 302
303&usbhshost {
304 port2-mode = "ehci-phy";
305};
306
307&usbhsehci {
308 phys = <0 &hsusb2_phy>;
309};
310
251&mmc1 { 311&mmc1 {
252 pinctrl-names = "default"; 312 pinctrl-names = "default";
253 pinctrl-0 = <&mmc1_pins>; 313 pinctrl-0 = <&mmc1_pins>;
@@ -286,11 +346,37 @@
286 bb_uamp = <150>; 346 bb_uamp = <150>;
287}; 347};
288 348
349/* spare */
350&vaux1 {
351 regulator-min-microvolt = <2500000>;
352 regulator-max-microvolt = <3000000>;
353};
354
355/* sensors */
356&vaux2 {
357 regulator-min-microvolt = <2800000>;
358 regulator-max-microvolt = <2800000>;
359 regulator-always-on;
360};
361
362/* camera */
363&vaux3 {
364 regulator-min-microvolt = <2500000>;
365 regulator-max-microvolt = <2500000>;
366};
367
368/* WLAN/BT */
289&vaux4 { 369&vaux4 {
290 regulator-min-microvolt = <2800000>; 370 regulator-min-microvolt = <2800000>;
291 regulator-max-microvolt = <3150000>; 371 regulator-max-microvolt = <3150000>;
292}; 372};
293 373
374/* GPS LNA */
375&vsim {
376 regulator-min-microvolt = <2800000>;
377 regulator-max-microvolt = <3150000>;
378};
379
294/* Needed to power the DPI pins */ 380/* Needed to power the DPI pins */
295&vpll2 { 381&vpll2 {
296 regulator-always-on; 382 regulator-always-on;
@@ -309,3 +395,57 @@
309 }; 395 };
310 }; 396 };
311}; 397};
398
399&gpmc {
400 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
401
402 nand@0,0 {
403 reg = <0 0 0>; /* CS0, offset 0 */
404 nand-bus-width = <16>;
405 ti,nand-ecc-opt = "bch8";
406
407 gpmc,sync-clk-ps = <0>;
408 gpmc,cs-on-ns = <0>;
409 gpmc,cs-rd-off-ns = <44>;
410 gpmc,cs-wr-off-ns = <44>;
411 gpmc,adv-on-ns = <6>;
412 gpmc,adv-rd-off-ns = <34>;
413 gpmc,adv-wr-off-ns = <44>;
414 gpmc,we-off-ns = <40>;
415 gpmc,oe-off-ns = <54>;
416 gpmc,access-ns = <64>;
417 gpmc,rd-cycle-ns = <82>;
418 gpmc,wr-cycle-ns = <82>;
419 gpmc,wr-access-ns = <40>;
420 gpmc,wr-data-mux-bus-ns = <0>;
421 gpmc,device-width = <2>;
422
423 #address-cells = <1>;
424 #size-cells = <1>;
425
426 x-loader@0 {
427 label = "X-Loader";
428 reg = <0 0x80000>;
429 };
430
431 bootloaders@80000 {
432 label = "U-Boot";
433 reg = <0x80000 0x1e0000>;
434 };
435
436 bootloaders_env@260000 {
437 label = "U-Boot Env";
438 reg = <0x260000 0x20000>;
439 };
440
441 kernel@280000 {
442 label = "Kernel";
443 reg = <0x280000 0x400000>;
444 };
445
446 filesystem@680000 {
447 label = "File System";
448 reg = <0x680000 0xf980000>;
449 };
450 };
451};
diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts
new file mode 100644
index 000000000000..3099a892cf50
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a3.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A3";
13};
14
15&i2c2 {
16
17 /* alternate accelerometer that might be installed on some GTA04A3 boards */
18 lis302@1d {
19 compatible = "st,lis331dlh", "st,lis3lv02d";
20 reg = <0x1d>;
21 interrupt-parent = <&gpio3>;
22 interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
23 Vdd-supply = <&vaux2>;
24 Vdd_IO-supply = <&vaux2>;
25
26 st,click-single-x;
27 st,click-single-y;
28 st,click-single-z;
29 st,click-thresh-x = <8>;
30 st,click-thresh-y = <8>;
31 st,click-thresh-z = <10>;
32 st,click-click-time-limit = <9>;
33 st,click-latency = <50>;
34 st,irq1-click;
35 st,wakeup-x-lo;
36 st,wakeup-x-hi;
37 st,wakeup-y-lo;
38 st,wakeup-y-hi;
39 st,wakeup-z-lo;
40 st,wakeup-z-hi;
41 st,min-limit-x = <32>;
42 st,min-limit-y = <3>;
43 st,min-limit-z = <3>;
44 st,max-limit-x = <3>;
45 st,max-limit-y = <32>;
46 st,max-limit-z = <32>;
47 };
48};
diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts
new file mode 100644
index 000000000000..c918bb1f0529
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a4.dts
@@ -0,0 +1,13 @@
1/*
2 * Copyright (C) 2014 Marek Belisko <marek@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A4";
13};
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
new file mode 100644
index 000000000000..52b386f6865b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A5";
13
14 sound {
15 ti,jack-det-gpio = <&twl_gpio 2 0>; /* GTA04A5 only */
16 };
17};
diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi
new file mode 100644
index 000000000000..bd66545ef954
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-common.dtsi
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-tao3530.dtsi"
11
12/ {
13 gpio_poweroff {
14 pinctrl-names = "default";
15 pinctrl-0 = <&poweroff_pins>;
16
17 compatible = "gpio-poweroff";
18 gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */
19 };
20};
21
22&omap3_pmx_core {
23 sound2_pins: pinmux_sound2_pins {
24 pinctrl-single,pins = <
25 OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */
26 >;
27 };
28
29 led_blue_pins: pinmux_led_blue_pins {
30 pinctrl-single,pins = <
31 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */
32 >;
33 };
34
35 led_green_pins: pinmux_led_green_pins {
36 pinctrl-single,pins = <
37 OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */
38 >;
39 };
40
41 led_red_pins: pinmux_led_red_pins {
42 pinctrl-single,pins = <
43 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */
44 >;
45 };
46
47 poweroff_pins: pinmux_poweroff_pins {
48 pinctrl-single,pins = <
49 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */
50 >;
51 };
52
53 powerdown_input_pins: pinmux_powerdown_input_pins {
54 pinctrl-single,pins = <
55 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */
56 >;
57 };
58
59 fpga_boot0_pins: fpga_boot0_pins {
60 pinctrl-single,pins = <
61 OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */
62 OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */
63 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */
64 OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */
65 >;
66 };
67
68 fpga_boot1_pins: fpga_boot1_pins {
69 pinctrl-single,pins = <
70 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */
71 OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */
72 OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */
73 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */
74 >;
75 };
76};
77
78/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
79&i2c2 {
80 status = "disabled";
81};
82
83&i2c3 {
84 clock-frequency = <100000>;
85
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c3_pins>;
88};
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
new file mode 100644
index 000000000000..11aa28d73f3a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-ha-common.dtsi"
11
12/ {
13 model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
14 compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 pinctrl-names = "default";
19 pinctrl-0 = <
20 &hsusbb2_pins
21 &powerdown_input_pins
22 &fpga_boot0_pins
23 &fpga_boot1_pins
24 &led_blue_pins
25 &led_green_pins
26 &led_red_pins
27 &touchscreen_wake_pins
28 >;
29
30 touchscreen_irq_pins: pinmux_touchscreen_irq_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */
33 >;
34 };
35
36 touchscreen_wake_pins: pinmux_touchscreen_wake_pins {
37 pinctrl-single,pins = <
38 OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */
39 >;
40 };
41
42 dss_dpi_pins: pinmux_dss_dpi_pins {
43 pinctrl-single,pins = <
44 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
45 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
46 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
47 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
48 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
49 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
50 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
51 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
52 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
53 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
54 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
55 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
56 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
57 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
58 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
59 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
60 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
61 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
62 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
63 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
64 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
65 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
66 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
67 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
68 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
69 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
70 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
71 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
72 >;
73 };
74
75 lte430_pins: pinmux_lte430_pins {
76 pinctrl-single,pins = <
77 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
78 >;
79 };
80
81 backlight_pins: pinmux_backlight_pins {
82 pinctrl-single,pins = <
83 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
84 >;
85 };
86};
87
88/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
89&i2c2 {
90 status = "disabled";
91};
92
93&i2c3 {
94 clock-frequency = <100000>;
95
96 pinctrl-names = "default";
97 pinctrl-0 = <&i2c3_pins>;
98};
99
100/* Needed to power the DPI pins */
101&vpll2 {
102 regulator-always-on;
103};
104
105&dss {
106 status = "ok";
107
108 pinctrl-names = "default";
109 pinctrl-0 = <&dss_dpi_pins>;
110
111 port {
112 dpi_out: endpoint {
113 remote-endpoint = <&lcd_in>;
114 data-lines = <24>;
115 };
116 };
117};
118
119/ {
120 aliases {
121 display0 = &lcd0;
122 };
123
124 lcd0: display@0 {
125 compatible = "panel-dpi";
126 label = "lcd";
127
128 pinctrl-names = "default";
129 pinctrl-0 = <&lte430_pins>;
130 enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
131
132 port {
133 lcd_in: endpoint {
134 remote-endpoint = <&dpi_out>;
135 };
136 };
137
138 panel-timing {
139 clock-frequency = <31250000>;
140 hactive = <800>;
141 vactive = <480>;
142 hfront-porch = <40>;
143 hback-porch = <86>;
144 hsync-len = <1>;
145 vback-porch = <30>;
146 vfront-porch = <13>;
147 vsync-len = <3>;
148
149 hsync-active = <0>;
150 vsync-active = <0>;
151 de-active = <1>;
152 pixelclk-active = <1>;
153 };
154 };
155
156 backlight {
157 compatible = "gpio-backlight";
158
159 pinctrl-names = "default";
160 pinctrl-0 = <&backlight_pins>;
161 gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
162
163 default-on;
164 };
165};
diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts
new file mode 100644
index 000000000000..fde325688fb9
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha.dts
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-ha-common.dtsi"
11
12/ {
13 model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
14 compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 pinctrl-names = "default";
19 pinctrl-0 = <
20 &hsusbb2_pins
21 &powerdown_input_pins
22 &fpga_boot0_pins
23 &fpga_boot1_pins
24 &led_blue_pins
25 &led_green_pins
26 &led_red_pins
27 >;
28};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index af272c156e21..72dca0b7904d 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -159,6 +159,11 @@
159 reg = <0x48>; 159 reg = <0x48>;
160 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 160 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
161 interrupt-parent = <&intc>; 161 interrupt-parent = <&intc>;
162
163 twl_power: power {
164 compatible = "ti,twl4030-power-idle";
165 ti,use_poweroff;
166 };
162 }; 167 };
163}; 168};
164 169
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4361777a08d8..9b0494a8ab45 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -134,24 +134,32 @@
134 >; 134 >;
135 }; 135 };
136 136
137 ethernet_pins: pinmux_ethernet_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
140 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
141 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
142 >;
143 };
144
137 i2c1_pins: pinmux_i2c1_pins { 145 i2c1_pins: pinmux_i2c1_pins {
138 pinctrl-single,pins = < 146 pinctrl-single,pins = <
139 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ 147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
140 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ 148 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
141 >; 149 >;
142 }; 150 };
143 151
144 i2c2_pins: pinmux_i2c2_pins { 152 i2c2_pins: pinmux_i2c2_pins {
145 pinctrl-single,pins = < 153 pinctrl-single,pins = <
146 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ 154 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
147 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ 155 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
148 >; 156 >;
149 }; 157 };
150 158
151 i2c3_pins: pinmux_i2c3_pins { 159 i2c3_pins: pinmux_i2c3_pins {
152 pinctrl-single,pins = < 160 pinctrl-single,pins = <
153 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ 161 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
154 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ 162 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
155 >; 163 >;
156 }; 164 };
157 165
@@ -578,6 +586,8 @@
578 586
579&gpmc { 587&gpmc {
580 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ 588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
581 591
582 /* gpio-irq for dma: 65 */ 592 /* gpio-irq for dma: 65 */
583 593
@@ -646,6 +656,38 @@
646 reg = <0x004c0000 0x0fb40000>; 656 reg = <0x004c0000 0x0fb40000>;
647 }; 657 };
648 }; 658 };
659
660 ethernet@gpmc {
661 compatible = "smsc,lan91c94";
662 interrupt-parent = <&gpio2>;
663 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
664 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
665 bank-width = <2>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&ethernet_pins>;
668 gpmc,device-width = <2>;
669 gpmc,sync-clk-ps = <0>;
670 gpmc,cs-on-ns = <0>;
671 gpmc,cs-rd-off-ns = <48>;
672 gpmc,cs-wr-off-ns = <24>;
673 gpmc,adv-on-ns = <0>;
674 gpmc,adv-rd-off-ns = <0>;
675 gpmc,adv-wr-off-ns = <0>;
676 gpmc,we-on-ns = <12>;
677 gpmc,we-off-ns = <18>;
678 gpmc,oe-on-ns = <12>;
679 gpmc,oe-off-ns = <48>;
680 gpmc,page-burst-access-ns = <0>;
681 gpmc,access-ns = <42>;
682 gpmc,rd-cycle-ns = <180>;
683 gpmc,wr-cycle-ns = <180>;
684 gpmc,bus-turnaround-ns = <0>;
685 gpmc,cycle2cycle-delay-ns = <0>;
686 gpmc,wait-monitoring-ns = <0>;
687 gpmc,clk-activation-ns = <0>;
688 gpmc,wr-access-ns = <0>;
689 gpmc,wr-data-mux-bus-ns = <12>;
690 };
649}; 691};
650 692
651&mcspi1 { 693&mcspi1 {
diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
index 5831bcc52966..520453d95704 100644
--- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
@@ -36,8 +36,8 @@
36 36
37 uart3_pins: pinmux_uart3_pins { 37 uart3_pins: pinmux_uart3_pins {
38 pinctrl-single,pins = < 38 pinctrl-single,pins = <
39 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 39 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
40 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 40 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
41 >; 41 >;
42 }; 42 };
43}; 43};
@@ -88,6 +88,7 @@
88}; 88};
89 89
90&uart3 { 90&uart3 {
91 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
91 pinctrl-names = "default"; 92 pinctrl-names = "default";
92 pinctrl-0 = <&uart3_pins>; 93 pinctrl-0 = <&uart3_pins>;
93}; 94};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
new file mode 100644
index 000000000000..b30f387d3a83
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -0,0 +1,337 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10
11#include "omap34xx-hs.dtsi"
12
13/ {
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vcc>;
17 };
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x10000000>; /* 256 MB */
23 };
24
25 /* HS USB Port 2 Power */
26 hsusb2_power: hsusb2_power_reg {
27 compatible = "regulator-fixed";
28 regulator-name = "hsusb2_vbus";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
32 startup-delay-us = <70000>;
33 };
34
35 /* HS USB Host PHY on PORT 2 */
36 hsusb2_phy: hsusb2_phy {
37 compatible = "usb-nop-xceiv";
38 reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
39 vcc-supply = <&hsusb2_power>;
40 };
41
42 sound {
43 compatible = "ti,omap-twl4030";
44 ti,model = "omap3beagle";
45
46 /* McBSP2 is used for onboard sound, same as on beagle */
47 ti,mcbsp = <&mcbsp2>;
48 ti,codec = <&twl_audio>;
49 };
50
51 /* Regulator to enable/switch the vcc of the Wifi module */
52 mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
53 compatible = "regulator-fixed";
54 regulator-name = "regulator-mmc2-sdio-poweron";
55 regulator-min-microvolt = <3150000>;
56 regulator-max-microvolt = <3150000>;
57 gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
58 enable-active-low;
59 startup-delay-us = <10000>;
60 };
61};
62
63&omap3_pmx_core {
64 hsusbb2_pins: pinmux_hsusbb2_pins {
65 pinctrl-single,pins = <
66 OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
67 OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
68 OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
69 OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
70 OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
71 OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
72 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
73 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
74 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
75 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
76 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
77 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
78 >;
79 };
80
81 mmc1_pins: pinmux_mmc1_pins {
82 pinctrl-single,pins = <
83 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
84 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
85 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
86 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
87 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
88 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
89 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
90 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
91 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
92 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
93 >;
94 };
95
96 mmc2_pins: pinmux_mmc2_pins {
97 pinctrl-single,pins = <
98 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
99 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
100 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
101 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
102 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
103 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
104 >;
105 };
106
107 /* wlan GPIO output for WLAN_EN */
108 wlan_gpio: pinmux_wlan_gpio {
109 pinctrl-single,pins = <
110 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */
111 >;
112 };
113
114 uart3_pins: pinmux_uart3_pins {
115 pinctrl-single,pins = <
116 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
117 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
118 >;
119 };
120
121 i2c3_pins: pinmux_i2c3_pins {
122 pinctrl-single,pins = <
123 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
124 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
125 >;
126 };
127
128 mcspi1_pins: pinmux_mcspi1_pins {
129 pinctrl-single,pins = <
130 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
131 OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
132 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
133 OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
134 >;
135 };
136
137 mcspi3_pins: pinmux_mcspi3_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
140 OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
141 OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
142 OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
143 >;
144 };
145
146 mcbsp3_pins: pinmux_mcbsp3_pins {
147 pinctrl-single,pins = <
148 OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */
149 OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */
150 OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */
151 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */
152 >;
153 };
154};
155
156/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
157&mcbsp1 {
158 status = "disabled";
159};
160
161&mcbsp2 {
162 status = "okay";
163};
164
165&i2c1 {
166 clock-frequency = <2600000>;
167
168 twl: twl@48 {
169 reg = <0x48>;
170 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
171 interrupt-parent = <&intc>;
172
173 twl_audio: audio {
174 compatible = "ti,twl4030-audio";
175 codec {
176 };
177 };
178 };
179};
180
181&i2c3 {
182 clock-frequency = <100000>;
183
184 pinctrl-names = "default";
185 pinctrl-0 = <&i2c3_pins>;
186};
187
188&mcspi1 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&mcspi1_pins>;
191
192 spidev@0 {
193 compatible = "spidev";
194 spi-max-frequency = <48000000>;
195 reg = <0>;
196 spi-cpha;
197 };
198};
199
200&mcspi3 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&mcspi3_pins>;
203
204 spidev@0 {
205 compatible = "spidev";
206 spi-max-frequency = <48000000>;
207 reg = <0>;
208 spi-cpha;
209 };
210};
211
212#include "twl4030.dtsi"
213#include "twl4030_omap3.dtsi"
214
215&mmc1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&mmc1_pins>;
218 vmmc-supply = <&vmmc1>;
219 vmmc_aux-supply = <&vsim>;
220 cd-gpios = <&twl_gpio 0 0>;
221 bus-width = <8>;
222};
223
224// WiFi (Marvell 88W8686) on MMC2/SDIO
225&mmc2 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&mmc2_pins>;
228 vmmc-supply = <&mmc2_sdio_poweron>;
229 non-removable;
230 bus-width = <4>;
231 cap-power-off-card;
232};
233
234&mmc3 {
235 status = "disabled";
236};
237
238&usbhshost {
239 port2-mode = "ehci-phy";
240};
241
242&usbhsehci {
243 phys = <0 &hsusb2_phy>;
244};
245
246&twl_gpio {
247 ti,use-leds;
248 /* pullups: BIT(1) */
249 ti,pullups = <0x000002>;
250 /*
251 * pulldowns:
252 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
253 * BIT(15), BIT(16), BIT(17)
254 */
255 ti,pulldowns = <0x03a1c4>;
256};
257
258&uart3 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&uart3_pins>;
261};
262
263&mcbsp3 {
264 status = "okay";
265 pinctrl-names = "default";
266 pinctrl-0 = <&mcbsp3_pins>;
267};
268
269&gpmc {
270 ranges = <0 0 0x00000000 0x01000000>;
271
272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */
274 nand-bus-width = <16>;
275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
276 ti,nand-ecc-opt = "sw";
277
278 gpmc,cs-on-ns = <0>;
279 gpmc,cs-rd-off-ns = <36>;
280 gpmc,cs-wr-off-ns = <36>;
281 gpmc,adv-on-ns = <6>;
282 gpmc,adv-rd-off-ns = <24>;
283 gpmc,adv-wr-off-ns = <36>;
284 gpmc,oe-on-ns = <6>;
285 gpmc,oe-off-ns = <48>;
286 gpmc,we-on-ns = <6>;
287 gpmc,we-off-ns = <30>;
288 gpmc,rd-cycle-ns = <72>;
289 gpmc,wr-cycle-ns = <72>;
290 gpmc,access-ns = <54>;
291 gpmc,wr-access-ns = <30>;
292
293 #address-cells = <1>;
294 #size-cells = <1>;
295
296 x-loader@0 {
297 label = "X-Loader";
298 reg = <0 0x80000>;
299 };
300
301 bootloaders@80000 {
302 label = "U-Boot";
303 reg = <0x80000 0x1e0000>;
304 };
305
306 bootloaders_env@260000 {
307 label = "U-Boot Env";
308 reg = <0x260000 0x20000>;
309 };
310
311 kernel@280000 {
312 label = "Kernel";
313 reg = <0x280000 0x400000>;
314 };
315
316 filesystem@680000 {
317 label = "File System";
318 reg = <0x680000 0xf980000>;
319 };
320 };
321};
322
323&usb_otg_hs {
324 interface-type = <0>;
325 usb-phy = <&usb2_phy>;
326 phys = <&usb2_phy>;
327 phy-names = "usb2-phy";
328 mode = <3>;
329 power = <50>;
330};
331
332&vaux2 {
333 regulator-name = "vdd_ehci";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-always-on;
337};
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
new file mode 100644
index 000000000000..d659515ab9b8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-tao3530.dtsi"
11
12/ {
13 model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
14 compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 dss_dpi_pins: pinmux_dss_dpi_pins {
19 pinctrl-single,pins = <
20 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
21 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
22 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
23 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
24 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
25 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
26 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
27 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
28 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
29 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
30 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
31 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
32 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
33 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
34 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
35 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
36 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
37 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
38 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
39 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
40 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
41 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
42 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
43 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
44 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
45 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
46 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
47 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
48 >;
49 };
50
51 lte430_pins: pinmux_lte430_pins {
52 pinctrl-single,pins = <
53 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
54 >;
55 };
56
57 backlight_pins: pinmux_backlight_pins {
58 pinctrl-single,pins = <
59 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
60 >;
61 };
62};
63
64/* Needed to power the DPI pins */
65&vpll2 {
66 regulator-always-on;
67};
68
69&dss {
70 status = "ok";
71
72 pinctrl-names = "default";
73 pinctrl-0 = <&dss_dpi_pins>;
74
75 port {
76 dpi_out: endpoint {
77 remote-endpoint = <&lcd_in>;
78 data-lines = <24>;
79 };
80 };
81};
82
83/ {
84 aliases {
85 display0 = &lcd0;
86 };
87
88 lcd0: display@0 {
89 compatible = "samsung,lte430wq-f0c", "panel-dpi";
90 label = "lcd";
91
92 pinctrl-names = "default";
93 pinctrl-0 = <&lte430_pins>;
94 enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
95
96 port {
97 lcd_in: endpoint {
98 remote-endpoint = <&dpi_out>;
99 };
100 };
101
102 panel-timing {
103 clock-frequency = <9000000>;
104 hactive = <480>;
105 vactive = <272>;
106 hfront-porch = <3>;
107 hback-porch = <2>;
108 hsync-len = <42>;
109 vback-porch = <2>;
110 vfront-porch = <3>;
111 vsync-len = <11>;
112
113 hsync-active = <0>;
114 vsync-active = <0>;
115 de-active = <1>;
116 pixelclk-active = <1>;
117 };
118 };
119
120 backlight {
121 compatible = "gpio-backlight";
122
123 pinctrl-names = "default";
124 pinctrl-0 = <&backlight_pins>;
125 gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
126
127 default-on;
128 };
129};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 3136ed1a04ba..226f3631c230 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -335,6 +335,10 @@
335 interrupts = <26>; 335 interrupts = <26>;
336 ti,mbox-num-users = <2>; 336 ti,mbox-num-users = <2>;
337 ti,mbox-num-fifos = <2>; 337 ti,mbox-num-fifos = <2>;
338 mbox_dsp: dsp {
339 ti,mbox-tx = <0 0 0>;
340 ti,mbox-rx = <1 0 0>;
341 };
338 }; 342 };
339 343
340 mcspi1: spi@48098000 { 344 mcspi1: spi@48098000 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 8a944974d72e..878c979203d0 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -663,6 +663,14 @@
663 ti,hwmods = "mailbox"; 663 ti,hwmods = "mailbox";
664 ti,mbox-num-users = <3>; 664 ti,mbox-num-users = <3>;
665 ti,mbox-num-fifos = <8>; 665 ti,mbox-num-fifos = <8>;
666 mbox_ipu: mbox_ipu {
667 ti,mbox-tx = <0 0 0>;
668 ti,mbox-rx = <1 0 0>;
669 };
670 mbox_dsp: mbox_dsp {
671 ti,mbox-tx = <3 0 0>;
672 ti,mbox-rx = <2 0 0>;
673 };
666 }; 674 };
667 675
668 timer1: timer@4a318000 { 676 timer1: timer@4a318000 {
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index 429471aa7a1f..b54b271e153b 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -16,6 +16,12 @@
16 reg = <0x80000000 0x7F000000>; /* 2048 MB */ 16 reg = <0x80000000 0x7F000000>; /* 2048 MB */
17 }; 17 };
18 18
19 aliases {
20 display0 = &hdmi0;
21 display1 = &dvi0;
22 display2 = &lcd0;
23 };
24
19 vmmcsd_fixed: fixed-regulator-mmcsd { 25 vmmcsd_fixed: fixed-regulator-mmcsd {
20 compatible = "regulator-fixed"; 26 compatible = "regulator-fixed";
21 regulator-name = "vmmcsd_fixed"; 27 regulator-name = "vmmcsd_fixed";
@@ -45,6 +51,13 @@
45 enable-active-high; 51 enable-active-high;
46 }; 52 };
47 53
54 ads7846reg: ads7846-reg {
55 compatible = "regulator-fixed";
56 regulator-name = "ads7846-reg";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 };
60
48 /* HS USB Host PHY on PORT 2 */ 61 /* HS USB Host PHY on PORT 2 */
49 hsusb2_phy: hsusb2_phy { 62 hsusb2_phy: hsusb2_phy {
50 compatible = "usb-nop-xceiv"; 63 compatible = "usb-nop-xceiv";
@@ -66,6 +79,105 @@
66 default-state = "off"; 79 default-state = "off";
67 }; 80 };
68 }; 81 };
82
83 lcd0: display {
84 compatible = "startek,startek-kd050c", "panel-dpi";
85 label = "lcd";
86
87 pinctrl-names = "default";
88 pinctrl-0 = <&lcd_pins>;
89
90 enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
91
92 panel-timing {
93 clock-frequency = <33000000>;
94 hactive = <800>;
95 vactive = <480>;
96 hfront-porch = <40>;
97 hback-porch = <40>;
98 hsync-len = <43>;
99 vback-porch = <29>;
100 vfront-porch = <13>;
101 vsync-len = <3>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107
108 port {
109 lcd_in: endpoint {
110 remote-endpoint = <&dpi_lcd_out>;
111 };
112 };
113 };
114
115 hdmi0: connector@0 {
116 compatible = "hdmi-connector";
117 label = "hdmi";
118
119 type = "a";
120
121 pinctrl-names = "default";
122 pinctrl-0 = <&hdmi_conn_pins>;
123
124 hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
125
126 port {
127 hdmi_connector_in: endpoint {
128 remote-endpoint = <&hdmi_out>;
129 };
130 };
131 };
132
133 tfp410: encoder@0 {
134 compatible = "ti,tfp410";
135
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 port@0 {
141 reg = <0>;
142
143 tfp410_in: endpoint@0 {
144 remote-endpoint = <&dpi_dvi_out>;
145 };
146 };
147
148 port@1 {
149 reg = <1>;
150
151 tfp410_out: endpoint@0 {
152 remote-endpoint = <&dvi_connector_in>;
153 };
154 };
155 };
156 };
157
158 dvi0: connector@1 {
159 compatible = "dvi-connector";
160 label = "dvi";
161
162 digital;
163
164 ddc-i2c-bus = <&i2c2>;
165
166 port {
167 dvi_connector_in: endpoint {
168 remote-endpoint = <&tfp410_out>;
169 };
170 };
171 };
172};
173
174&omap5_pmx_wkup {
175
176 ads7846_pins: pinmux_ads7846_pins {
177 pinctrl-single,pins = <
178 0x02 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */
179 >;
180 };
69}; 181};
70 182
71&omap5_pmx_core { 183&omap5_pmx_core {
@@ -88,6 +200,13 @@
88 >; 200 >;
89 }; 201 };
90 202
203 i2c2_pins: pinmux_i2c2_pins {
204 pinctrl-single,pins = <
205 OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
206 OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
207 >;
208 };
209
91 mmc1_pins: pinmux_mmc1_pins { 210 mmc1_pins: pinmux_mmc1_pins {
92 pinctrl-single,pins = < 211 pinctrl-single,pins = <
93 OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ 212 OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */
@@ -127,8 +246,8 @@
127 246
128 wlan_gpios_pins: pinmux_wlan_gpios_pins { 247 wlan_gpios_pins: pinmux_wlan_gpios_pins {
129 pinctrl-single,pins = < 248 pinctrl-single,pins = <
130 OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ 249 OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */
131 OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ 250 OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */
132 >; 251 >;
133 }; 252 };
134 253
@@ -144,6 +263,104 @@
144 OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ 263 OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */
145 >; 264 >;
146 }; 265 };
266
267 dss_hdmi_pins: pinmux_dss_hdmi_pins {
268 pinctrl-single,pins = <
269 OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */
270 OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */
271 OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */
272 >;
273 };
274
275 lcd_pins: pinmux_lcd_pins {
276 pinctrl-single,pins = <
277 OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */
278 >;
279 };
280
281 hdmi_conn_pins: pinmux_hdmi_conn_pins {
282 pinctrl-single,pins = <
283 OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
284 >;
285 };
286
287 dss_dpi_pins: pinmux_dss_dpi_pins {
288 pinctrl-single,pins = <
289 OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */
290 OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */
291 OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */
292 OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */
293 OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */
294 OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */
295 OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */
296 OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */
297 OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */
298 OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */
299 OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */
300 OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */
301 OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */
302 OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */
303 OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */
304 OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */
305 OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */
306 OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */
307 OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */
308 OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */
309 OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */
310 OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */
311 OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */
312 OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */
313 OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */
314 OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */
315 OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */
316 OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */
317 >;
318 };
319
320 mcspi2_pins: pinmux_mcspi1_pins {
321 pinctrl-single,pins = <
322 OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
323 OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
324 OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */
325 OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */
326 >;
327 };
328};
329
330&mcspi2 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&mcspi2_pins>;
333
334 /* touch controller */
335 ads7846@0 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&ads7846_pins>;
338
339 compatible = "ti,ads7846";
340 vcc-supply = <&ads7846reg>;
341
342 reg = <0>; /* CS0 */
343 spi-max-frequency = <1500000>;
344
345 interrupt-parent = <&gpio1>;
346 interrupts = <15 0>; /* gpio1_wk15 */
347 pendown-gpio = <&gpio1 15 0>;
348
349
350 ti,x-min = /bits/ 16 <0x0>;
351 ti,x-max = /bits/ 16 <0x0fff>;
352 ti,y-min = /bits/ 16 <0x0>;
353 ti,y-max = /bits/ 16 <0x0fff>;
354
355 ti,x-plate-ohms = /bits/ 16 <180>;
356 ti,pressure-max = /bits/ 16 <255>;
357
358 ti,debounce-max = /bits/ 16 <30>;
359 ti,debounce-tol = /bits/ 16 <10>;
360 ti,debounce-rep = /bits/ 16 <1>;
361
362 linux,wakeup;
363 };
147}; 364};
148 365
149&mmc1 { 366&mmc1 {
@@ -398,6 +615,13 @@
398 }; 615 };
399}; 616};
400 617
618&i2c2 {
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c2_pins>;
621
622 clock-frequency = <100000>;
623};
624
401&usbhshost { 625&usbhshost {
402 port2-mode = "ehci-hsic"; 626 port2-mode = "ehci-hsic";
403 port3-mode = "ehci-hsic"; 627 port3-mode = "ehci-hsic";
@@ -407,6 +631,50 @@
407 phys = <0 &hsusb2_phy &hsusb3_phy>; 631 phys = <0 &hsusb2_phy &hsusb3_phy>;
408}; 632};
409 633
634&usb3 {
635 extcon = <&extcon_usb3>;
636 vbus-supply = <&smps10_out1_reg>;
637};
638
410&cpu0 { 639&cpu0 {
411 cpu0-supply = <&smps123_reg>; 640 cpu0-supply = <&smps123_reg>;
412}; 641};
642
643&dss {
644 status = "ok";
645
646 pinctrl-names = "default";
647 pinctrl-0 = <&dss_dpi_pins>;
648
649 port {
650 dpi_dvi_out: endpoint@0 {
651 remote-endpoint = <&tfp410_in>;
652 data-lines = <24>;
653 };
654
655 dpi_lcd_out: endpoint@1 {
656 remote-endpoint = <&lcd_in>;
657 data-lines = <24>;
658 };
659 };
660};
661
662&dsi2 {
663 status = "ok";
664 vdd-supply = <&ldo4_reg>;
665};
666
667&hdmi {
668 status = "ok";
669 vdda-supply = <&ldo4_reg>;
670
671 pinctrl-names = "default";
672 pinctrl-0 = <&dss_hdmi_pins>;
673
674 port {
675 hdmi_out: endpoint {
676 remote-endpoint = <&hdmi_connector_in>;
677 lanes = <1 0 3 2 5 4 7 6>;
678 };
679 };
680};
diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts
index aa98fea3f2b3..337bbbc01a35 100644
--- a/arch/arm/boot/dts/omap5-sbc-t54.dts
+++ b/arch/arm/boot/dts/omap5-sbc-t54.dts
@@ -1,11 +1,11 @@
1/* 1/*
2 * Suppport for CompuLab SBC-T54 with CM-T54 2 * Suppport for CompuLab CM-T54 on SB-T54 baseboard
3 */ 3 */
4 4
5#include "omap5-cm-t54.dts" 5#include "omap5-cm-t54.dts"
6 6
7/ { 7/ {
8 model = "CompuLab SBC-T54 with CM-T54"; 8 model = "CompuLab CM-T54 on SB-T54";
9 compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; 9 compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5";
10}; 10};
11 11
@@ -19,8 +19,8 @@
19 19
20 mmc1_aux_pins: pinmux_mmc1_aux_pins { 20 mmc1_aux_pins: pinmux_mmc1_aux_pins {
21 pinctrl-single,pins = < 21 pinctrl-single,pins = <
22 OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ 22 OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */
23 OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ 23 OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */
24 >; 24 >;
25 }; 25 };
26}; 26};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 4a6091d717b5..256b7f69e45b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -189,18 +189,22 @@
189 }; 189 };
190 190
191 omap5_pmx_core: pinmux@4a002840 { 191 omap5_pmx_core: pinmux@4a002840 {
192 compatible = "ti,omap4-padconf", "pinctrl-single"; 192 compatible = "ti,omap5-padconf", "pinctrl-single";
193 reg = <0x4a002840 0x01b6>; 193 reg = <0x4a002840 0x01b6>;
194 #address-cells = <1>; 194 #address-cells = <1>;
195 #size-cells = <0>; 195 #size-cells = <0>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
196 pinctrl-single,register-width = <16>; 198 pinctrl-single,register-width = <16>;
197 pinctrl-single,function-mask = <0x7fff>; 199 pinctrl-single,function-mask = <0x7fff>;
198 }; 200 };
199 omap5_pmx_wkup: pinmux@4ae0c840 { 201 omap5_pmx_wkup: pinmux@4ae0c840 {
200 compatible = "ti,omap4-padconf", "pinctrl-single"; 202 compatible = "ti,omap5-padconf", "pinctrl-single";
201 reg = <0x4ae0c840 0x0038>; 203 reg = <0x4ae0c840 0x0038>;
202 #address-cells = <1>; 204 #address-cells = <1>;
203 #size-cells = <0>; 205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
204 pinctrl-single,register-width = <16>; 208 pinctrl-single,register-width = <16>;
205 pinctrl-single,function-mask = <0x7fff>; 209 pinctrl-single,function-mask = <0x7fff>;
206 }; 210 };
@@ -454,7 +458,7 @@
454 uart1: serial@4806a000 { 458 uart1: serial@4806a000 {
455 compatible = "ti,omap4-uart"; 459 compatible = "ti,omap4-uart";
456 reg = <0x4806a000 0x100>; 460 reg = <0x4806a000 0x100>;
457 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 461 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "uart1"; 462 ti,hwmods = "uart1";
459 clock-frequency = <48000000>; 463 clock-frequency = <48000000>;
460 }; 464 };
@@ -462,7 +466,7 @@
462 uart2: serial@4806c000 { 466 uart2: serial@4806c000 {
463 compatible = "ti,omap4-uart"; 467 compatible = "ti,omap4-uart";
464 reg = <0x4806c000 0x100>; 468 reg = <0x4806c000 0x100>;
465 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 469 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
466 ti,hwmods = "uart2"; 470 ti,hwmods = "uart2";
467 clock-frequency = <48000000>; 471 clock-frequency = <48000000>;
468 }; 472 };
@@ -470,7 +474,7 @@
470 uart3: serial@48020000 { 474 uart3: serial@48020000 {
471 compatible = "ti,omap4-uart"; 475 compatible = "ti,omap4-uart";
472 reg = <0x48020000 0x100>; 476 reg = <0x48020000 0x100>;
473 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 477 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
474 ti,hwmods = "uart3"; 478 ti,hwmods = "uart3";
475 clock-frequency = <48000000>; 479 clock-frequency = <48000000>;
476 }; 480 };
@@ -478,7 +482,7 @@
478 uart4: serial@4806e000 { 482 uart4: serial@4806e000 {
479 compatible = "ti,omap4-uart"; 483 compatible = "ti,omap4-uart";
480 reg = <0x4806e000 0x100>; 484 reg = <0x4806e000 0x100>;
481 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 485 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
482 ti,hwmods = "uart4"; 486 ti,hwmods = "uart4";
483 clock-frequency = <48000000>; 487 clock-frequency = <48000000>;
484 }; 488 };
@@ -486,7 +490,7 @@
486 uart5: serial@48066000 { 490 uart5: serial@48066000 {
487 compatible = "ti,omap4-uart"; 491 compatible = "ti,omap4-uart";
488 reg = <0x48066000 0x100>; 492 reg = <0x48066000 0x100>;
489 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 493 interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
490 ti,hwmods = "uart5"; 494 ti,hwmods = "uart5";
491 clock-frequency = <48000000>; 495 clock-frequency = <48000000>;
492 }; 496 };
@@ -494,7 +498,7 @@
494 uart6: serial@48068000 { 498 uart6: serial@48068000 {
495 compatible = "ti,omap4-uart"; 499 compatible = "ti,omap4-uart";
496 reg = <0x48068000 0x100>; 500 reg = <0x48068000 0x100>;
497 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 501 interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "uart6"; 502 ti,hwmods = "uart6";
499 clock-frequency = <48000000>; 503 clock-frequency = <48000000>;
500 }; 504 };
@@ -649,6 +653,14 @@
649 ti,hwmods = "mailbox"; 653 ti,hwmods = "mailbox";
650 ti,mbox-num-users = <3>; 654 ti,mbox-num-users = <3>;
651 ti,mbox-num-fifos = <8>; 655 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu {
657 ti,mbox-tx = <0 0 0>;
658 ti,mbox-rx = <1 0 0>;
659 };
660 mbox_dsp: mbox_dsp {
661 ti,mbox-tx = <3 0 0>;
662 ti,mbox-rx = <2 0 0>;
663 };
652 }; 664 };
653 665
654 timer1: timer@4ae18000 { 666 timer1: timer@4ae18000 {
@@ -952,6 +964,15 @@
952 clock-names = "fck"; 964 clock-names = "fck";
953 }; 965 };
954 966
967 rfbi: encoder@58002000 {
968 compatible = "ti,omap5-rfbi";
969 reg = <0x58002000 0x100>;
970 status = "disabled";
971 ti,hwmods = "dss_rfbi";
972 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
973 clock-names = "fck", "ick";
974 };
975
955 dsi1: encoder@58004000 { 976 dsi1: encoder@58004000 {
956 compatible = "ti,omap5-dsi"; 977 compatible = "ti,omap5-dsi";
957 reg = <0x58004000 0x200>, 978 reg = <0x58004000 0x200>,
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index a5e90f078aa9..c08f84629aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -113,14 +113,14 @@
113 }; 113 };
114 114
115 usb0: ohci@4c000000 { 115 usb0: ohci@4c000000 {
116 compatible = "mrvl,pxa-ohci"; 116 compatible = "marvell,pxa-ohci";
117 reg = <0x4c000000 0x10000>; 117 reg = <0x4c000000 0x10000>;
118 interrupts = <3>; 118 interrupts = <3>;
119 status = "disabled"; 119 status = "disabled";
120 }; 120 };
121 121
122 mmc0: mmc@41100000 { 122 mmc0: mmc@41100000 {
123 compatible = "mrvl,pxa-mmc"; 123 compatible = "marvell,pxa-mmc";
124 reg = <0x41100000 0x1000>; 124 reg = <0x41100000 0x1000>;
125 interrupts = <23>; 125 interrupts = <23>;
126 status = "disabled"; 126 status = "disabled";
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d526bc..b396c8311b27 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,33 @@
5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; 5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
6 6
7 soc { 7 soc {
8 pinctrl@800000 {
9 i2c1_pins: i2c1 {
10 mux {
11 pins = "gpio20", "gpio21";
12 function = "gsbi1";
13 };
14 };
15 };
16
17 gsbi@12440000 {
18 status = "okay";
19 qcom,mode = <GSBI_PROT_I2C>;
20
21 i2c@12460000 {
22 status = "okay";
23 clock-frequency = <200000>;
24 pinctrl-0 = <&i2c1_pins>;
25 pinctrl-names = "default";
26
27 eeprom: eeprom@52 {
28 compatible = "atmel,24c128";
29 reg = <0x52>;
30 pagesize = <32>;
31 };
32 };
33 };
34
8 gsbi@16600000 { 35 gsbi@16600000 {
9 status = "ok"; 36 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>; 37 qcom,mode = <GSBI_PROT_I2C_UART>;
@@ -12,5 +39,21 @@
12 status = "ok"; 39 status = "ok";
13 }; 40 };
14 }; 41 };
42
43 amba {
44 /* eMMC */
45 sdcc1: sdcc@12400000 {
46 status = "okay";
47 };
48
49 /* External micro SD card */
50 sdcc3: sdcc@12180000 {
51 status = "okay";
52 };
53 /* WLAN */
54 sdcc4: sdcc@121c0000 {
55 status = "okay";
56 };
57 };
15 }; 58 };
16}; 59};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793622c3..b3154c071652 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,7 +2,9 @@
2 2
3#include "skeleton.dtsi" 3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
5#include <dt-bindings/soc/qcom,gsbi.h> 6#include <dt-bindings/soc/qcom,gsbi.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
6 8
7/ { 9/ {
8 model = "Qualcomm APQ8064"; 10 model = "Qualcomm APQ8064";
@@ -70,6 +72,34 @@
70 ranges; 72 ranges;
71 compatible = "simple-bus"; 73 compatible = "simple-bus";
72 74
75 tlmm_pinmux: pinctrl@800000 {
76 compatible = "qcom,apq8064-pinctrl";
77 reg = <0x800000 0x4000>;
78
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <2>;
83 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
84
85 pinctrl-names = "default";
86 pinctrl-0 = <&ps_hold>;
87
88 sdc4_gpios: sdc4-gpios {
89 pios {
90 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
91 function = "sdc4";
92 };
93 };
94
95 ps_hold: ps_hold {
96 mux {
97 pins = "gpio78";
98 function = "ps_hold";
99 };
100 };
101 };
102
73 intc: interrupt-controller@2000000 { 103 intc: interrupt-controller@2000000 {
74 compatible = "qcom,msm-qgic2"; 104 compatible = "qcom,msm-qgic2";
75 interrupt-controller; 105 interrupt-controller;
@@ -133,6 +163,48 @@
133 regulator; 163 regulator;
134 }; 164 };
135 165
166 gsbi1: gsbi@12440000 {
167 status = "disabled";
168 compatible = "qcom,gsbi-v1.0.0";
169 reg = <0x12440000 0x100>;
170 clocks = <&gcc GSBI1_H_CLK>;
171 clock-names = "iface";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 i2c1: i2c@12460000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x12460000 0x1000>;
179 interrupts = <0 194 IRQ_TYPE_NONE>;
180 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
181 clock-names = "core", "iface";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185 };
186
187 gsbi2: gsbi@12480000 {
188 status = "disabled";
189 compatible = "qcom,gsbi-v1.0.0";
190 reg = <0x12480000 0x100>;
191 clocks = <&gcc GSBI2_H_CLK>;
192 clock-names = "iface";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges;
196
197 i2c2: i2c@124a0000 {
198 compatible = "qcom,i2c-qup-v1.1.1";
199 reg = <0x124a0000 0x1000>;
200 interrupts = <0 196 IRQ_TYPE_NONE>;
201 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
202 clock-names = "core", "iface";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 };
206 };
207
136 gsbi7: gsbi@16600000 { 208 gsbi7: gsbi@16600000 {
137 status = "disabled"; 209 status = "disabled";
138 compatible = "qcom,gsbi-v1.0.0"; 210 compatible = "qcom,gsbi-v1.0.0";
@@ -166,5 +238,116 @@
166 #clock-cells = <1>; 238 #clock-cells = <1>;
167 #reset-cells = <1>; 239 #reset-cells = <1>;
168 }; 240 };
241
242 mmcc: clock-controller@4000000 {
243 compatible = "qcom,mmcc-apq8064";
244 reg = <0x4000000 0x1000>;
245 #clock-cells = <1>;
246 #reset-cells = <1>;
247 };
248
249 /* Temporary fixed regulator */
250 vsdcc_fixed: vsdcc-regulator {
251 compatible = "regulator-fixed";
252 regulator-name = "SDCC Power";
253 regulator-min-microvolt = <2700000>;
254 regulator-max-microvolt = <2700000>;
255 regulator-always-on;
256 };
257
258 sdcc1bam:dma@12402000{
259 compatible = "qcom,bam-v1.3.0";
260 reg = <0x12402000 0x8000>;
261 interrupts = <0 98 0>;
262 clocks = <&gcc SDC1_H_CLK>;
263 clock-names = "bam_clk";
264 #dma-cells = <1>;
265 qcom,ee = <0>;
266 };
267
268 sdcc3bam:dma@12182000{
269 compatible = "qcom,bam-v1.3.0";
270 reg = <0x12182000 0x8000>;
271 interrupts = <0 96 0>;
272 clocks = <&gcc SDC3_H_CLK>;
273 clock-names = "bam_clk";
274 #dma-cells = <1>;
275 qcom,ee = <0>;
276 };
277
278 sdcc4bam:dma@121c2000{
279 compatible = "qcom,bam-v1.3.0";
280 reg = <0x121c2000 0x8000>;
281 interrupts = <0 95 0>;
282 clocks = <&gcc SDC4_H_CLK>;
283 clock-names = "bam_clk";
284 #dma-cells = <1>;
285 qcom,ee = <0>;
286 };
287
288 amba {
289 compatible = "arm,amba-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293 sdcc1: sdcc@12400000 {
294 status = "disabled";
295 compatible = "arm,pl18x", "arm,primecell";
296 arm,primecell-periphid = <0x00051180>;
297 reg = <0x12400000 0x2000>;
298 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-names = "cmd_irq";
300 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
301 clock-names = "mclk", "apb_pclk";
302 bus-width = <8>;
303 max-frequency = <96000000>;
304 non-removable;
305 cap-sd-highspeed;
306 cap-mmc-highspeed;
307 vmmc-supply = <&vsdcc_fixed>;
308 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
309 dma-names = "tx", "rx";
310 };
311
312 sdcc3: sdcc@12180000 {
313 compatible = "arm,pl18x", "arm,primecell";
314 arm,primecell-periphid = <0x00051180>;
315 status = "disabled";
316 reg = <0x12180000 0x2000>;
317 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "cmd_irq";
319 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
320 clock-names = "mclk", "apb_pclk";
321 bus-width = <4>;
322 cap-sd-highspeed;
323 cap-mmc-highspeed;
324 max-frequency = <192000000>;
325 no-1-8-v;
326 vmmc-supply = <&vsdcc_fixed>;
327 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
328 dma-names = "tx", "rx";
329 };
330
331 sdcc4: sdcc@121c0000 {
332 compatible = "arm,pl18x", "arm,primecell";
333 arm,primecell-periphid = <0x00051180>;
334 status = "disabled";
335 reg = <0x121c0000 0x2000>;
336 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
337 interrupt-names = "cmd_irq";
338 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
339 clock-names = "mclk", "apb_pclk";
340 bus-width = <4>;
341 cap-sd-highspeed;
342 cap-mmc-highspeed;
343 max-frequency = <48000000>;
344 vmmc-supply = <&vsdcc_fixed>;
345 vqmmc-supply = <&vsdcc_fixed>;
346 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
347 dma-names = "tx", "rx";
348 pinctrl-names = "default";
349 pinctrl-0 = <&sdc4_gpios>;
350 };
351 };
169 }; 352 };
170}; 353};
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index b4dfb01fe6fb..47370494d0f8 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -22,6 +22,13 @@
22 22
23 23
24 pinctrl@fd510000 { 24 pinctrl@fd510000 {
25 i2c11_pins: i2c11 {
26 mux {
27 pins = "gpio83", "gpio84";
28 function = "blsp_i2c11";
29 };
30 };
31
25 spi8_default: spi8_default { 32 spi8_default: spi8_default {
26 mosi { 33 mosi {
27 pins = "gpio45"; 34 pins = "gpio45";
@@ -41,5 +48,19 @@
41 }; 48 };
42 }; 49 };
43 }; 50 };
51
52 i2c@f9967000 {
53 status = "okay";
54 clock-frequency = <200000>;
55 pinctrl-0 = <&i2c11_pins>;
56 pinctrl-names = "default";
57
58 eeprom: eeprom@52 {
59 compatible = "atmel,24c128";
60 reg = <0x52>;
61 pagesize = <32>;
62 read-only;
63 };
64 };
44 }; 65 };
45}; 66};
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
new file mode 100644
index 000000000000..c9ff10821ad9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -0,0 +1,23 @@
1#include "qcom-apq8084.dtsi"
2
3/ {
4 model = "Qualcomm APQ8084/IFC6540";
5 compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
6
7 soc {
8 serial@f995e000 {
9 status = "okay";
10 };
11
12 sdhci@f9824900 {
13 bus-width = <8>;
14 non-removable;
15 status = "okay";
16 };
17
18 sdhci@f98a4900 {
19 cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
20 bus-width = <4>;
21 };
22 };
23};
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 9dae3878b71d..8ecec58a9ff6 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -3,4 +3,10 @@
3/ { 3/ {
4 model = "Qualcomm APQ 8084-MTP"; 4 model = "Qualcomm APQ 8084-MTP";
5 compatible = "qcom,apq8084-mtp", "qcom,apq8084"; 5 compatible = "qcom,apq8084-mtp", "qcom,apq8084";
6
7 soc {
8 serial@f995e000 {
9 status = "okay";
10 };
11 };
6}; 12};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index e3e009a5912b..1f130bc16858 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -2,6 +2,9 @@
2 2
3#include "skeleton.dtsi" 3#include "skeleton.dtsi"
4 4
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
5/ { 8/ {
6 model = "Qualcomm APQ 8084"; 9 model = "Qualcomm APQ 8084";
7 compatible = "qcom,apq8084"; 10 compatible = "qcom,apq8084";
@@ -175,5 +178,53 @@
175 compatible = "qcom,pshold"; 178 compatible = "qcom,pshold";
176 reg = <0xfc4ab000 0x4>; 179 reg = <0xfc4ab000 0x4>;
177 }; 180 };
181
182 gcc: clock-controller@fc400000 {
183 compatible = "qcom,gcc-apq8084";
184 #clock-cells = <1>;
185 #reset-cells = <1>;
186 reg = <0xfc400000 0x4000>;
187 };
188
189 tlmm: pinctrl@fd510000 {
190 compatible = "qcom,apq8084-pinctrl";
191 reg = <0xfd510000 0x4000>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 interrupts = <0 208 0>;
197 };
198
199 serial@f995e000 {
200 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
201 reg = <0xf995e000 0x1000>;
202 interrupts = <0 114 0x0>;
203 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
204 clock-names = "core", "iface";
205 status = "disabled";
206 };
207
208 sdhci@f9824900 {
209 compatible = "qcom,sdhci-msm-v4";
210 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
211 reg-names = "hc_mem", "core_mem";
212 interrupts = <0 123 0>, <0 138 0>;
213 interrupt-names = "hc_irq", "pwr_irq";
214 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
215 clock-names = "core", "iface";
216 status = "disabled";
217 };
218
219 sdhci@f98a4900 {
220 compatible = "qcom,sdhci-msm-v4";
221 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
222 reg-names = "hc_mem", "core_mem";
223 interrupts = <0 125 0>, <0 221 0>;
224 interrupt-names = "hc_irq", "pwr_irq";
225 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
226 clock-names = "core", "iface";
227 status = "disabled";
228 };
178 }; 229 };
179}; 230};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
new file mode 100644
index 000000000000..95e64955fb8e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -0,0 +1,85 @@
1#include "qcom-ipq8064-v1.0.dtsi"
2
3/ {
4 model = "Qualcomm IPQ8064/AP148";
5 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
6
7 reserved-memory {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges;
11 rsvd@41200000 {
12 reg = <0x41200000 0x300000>;
13 no-map;
14 };
15 };
16
17 soc {
18 pinmux@800000 {
19 i2c4_pins: i2c4_pinmux {
20 pins = "gpio12", "gpio13";
21 function = "gsbi4";
22 bias-disable;
23 };
24
25 spi_pins: spi_pins {
26 mux {
27 pins = "gpio18", "gpio19", "gpio21";
28 function = "gsbi5";
29 drive-strength = <10>;
30 bias-none;
31 };
32 };
33 };
34
35 gsbi@16300000 {
36 qcom,mode = <GSBI_PROT_I2C_UART>;
37 status = "ok";
38 serial@16340000 {
39 status = "ok";
40 };
41
42 i2c4: i2c@16380000 {
43 status = "ok";
44
45 clock-frequency = <200000>;
46
47 pinctrl-0 = <&i2c4_pins>;
48 pinctrl-names = "default";
49 };
50 };
51
52 gsbi5: gsbi@1a200000 {
53 qcom,mode = <GSBI_PROT_SPI>;
54 status = "ok";
55
56 spi4: spi@1a280000 {
57 status = "ok";
58 spi-max-frequency = <50000000>;
59
60 pinctrl-0 = <&spi_pins>;
61 pinctrl-names = "default";
62
63 cs-gpios = <&qcom_pinmux 20 0>;
64
65 flash: m25p80@0 {
66 compatible = "s25fl256s1";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 spi-max-frequency = <50000000>;
70 reg = <0>;
71
72 partition@0 {
73 label = "rootfs";
74 reg = <0x0 0x1000000>;
75 };
76
77 partition@1 {
78 label = "scratch";
79 reg = <0x1000000 0x1000000>;
80 };
81 };
82 };
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
new file mode 100644
index 000000000000..7093b075e408
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -0,0 +1 @@
#include "qcom-ipq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
new file mode 100644
index 000000000000..244f857f0e6f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -0,0 +1,250 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5#include <dt-bindings/soc/qcom,gsbi.h>
6
7/ {
8 model = "Qualcomm IPQ8064";
9 compatible = "qcom,ipq8064";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v1";
19 device_type = "cpu";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 qcom,acc = <&acc0>;
23 qcom,saw = <&saw0>;
24 };
25
26 cpu@1 {
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v1";
29 device_type = "cpu";
30 reg = <1>;
31 next-level-cache = <&L2>;
32 qcom,acc = <&acc1>;
33 qcom,saw = <&saw1>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
41
42 cpu-pmu {
43 compatible = "qcom,krait-pmu";
44 interrupts = <1 10 0x304>;
45 };
46
47 reserved-memory {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 nss@40000000 {
53 reg = <0x40000000 0x1000000>;
54 no-map;
55 };
56
57 smem@41000000 {
58 reg = <0x41000000 0x200000>;
59 no-map;
60 };
61 };
62
63 soc: soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67 compatible = "simple-bus";
68
69 qcom_pinmux: pinmux@800000 {
70 compatible = "qcom,ipq8064-pinctrl";
71 reg = <0x800000 0x4000>;
72
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>;
78 };
79
80 intc: interrupt-controller@2000000 {
81 compatible = "qcom,msm-qgic2";
82 interrupt-controller;
83 #interrupt-cells = <3>;
84 reg = <0x02000000 0x1000>,
85 <0x02002000 0x1000>;
86 };
87
88 timer@200a000 {
89 compatible = "qcom,kpss-timer", "qcom,msm-timer";
90 interrupts = <1 1 0x301>,
91 <1 2 0x301>,
92 <1 3 0x301>;
93 reg = <0x0200a000 0x100>;
94 clock-frequency = <25000000>,
95 <32768>;
96 cpu-offset = <0x80000>;
97 };
98
99 acc0: clock-controller@2088000 {
100 compatible = "qcom,kpss-acc-v1";
101 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
102 };
103
104 acc1: clock-controller@2098000 {
105 compatible = "qcom,kpss-acc-v1";
106 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
107 };
108
109 saw0: regulator@2089000 {
110 compatible = "qcom,saw2";
111 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
112 regulator;
113 };
114
115 saw1: regulator@2099000 {
116 compatible = "qcom,saw2";
117 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
118 regulator;
119 };
120
121 gsbi2: gsbi@12480000 {
122 compatible = "qcom,gsbi-v1.0.0";
123 reg = <0x12480000 0x100>;
124 clocks = <&gcc GSBI2_H_CLK>;
125 clock-names = "iface";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129 status = "disabled";
130
131 serial@12490000 {
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
133 reg = <0x12490000 0x1000>,
134 <0x12480000 0x1000>;
135 interrupts = <0 195 0x0>;
136 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
137 clock-names = "core", "iface";
138 status = "disabled";
139 };
140
141 i2c@124a0000 {
142 compatible = "qcom,i2c-qup-v1.1.1";
143 reg = <0x124a0000 0x1000>;
144 interrupts = <0 196 0>;
145
146 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
147 clock-names = "core", "iface";
148 status = "disabled";
149
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 };
155
156 gsbi4: gsbi@16300000 {
157 compatible = "qcom,gsbi-v1.0.0";
158 reg = <0x16300000 0x100>;
159 clocks = <&gcc GSBI4_H_CLK>;
160 clock-names = "iface";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164 status = "disabled";
165
166 serial@16340000 {
167 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
168 reg = <0x16340000 0x1000>,
169 <0x16300000 0x1000>;
170 interrupts = <0 152 0x0>;
171 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
172 clock-names = "core", "iface";
173 status = "disabled";
174 };
175
176 i2c@16380000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x16380000 0x1000>;
179 interrupts = <0 153 0>;
180
181 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
182 clock-names = "core", "iface";
183 status = "disabled";
184
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188 };
189
190 gsbi5: gsbi@1a200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 reg = <0x1a200000 0x100>;
193 clocks = <&gcc GSBI5_H_CLK>;
194 clock-names = "iface";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 ranges;
198 status = "disabled";
199
200 serial@1a240000 {
201 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
202 reg = <0x1a240000 0x1000>,
203 <0x1a200000 0x1000>;
204 interrupts = <0 154 0x0>;
205 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
206 clock-names = "core", "iface";
207 status = "disabled";
208 };
209
210 i2c@1a280000 {
211 compatible = "qcom,i2c-qup-v1.1.1";
212 reg = <0x1a280000 0x1000>;
213 interrupts = <0 155 0>;
214
215 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
216 clock-names = "core", "iface";
217 status = "disabled";
218
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 spi@1a280000 {
224 compatible = "qcom,spi-qup-v1.1.1";
225 reg = <0x1a280000 0x1000>;
226 interrupts = <0 155 0>;
227
228 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
229 clock-names = "core", "iface";
230 status = "disabled";
231
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235 };
236
237 qcom,ssbi@500000 {
238 compatible = "qcom,ssbi";
239 reg = <0x00500000 0x1000>;
240 qcom,controller-type = "pmic-arbiter";
241 };
242
243 gcc: clock-controller@900000 {
244 compatible = "qcom,gcc-ipq8064";
245 reg = <0x00900000 0x4000>;
246 #clock-cells = <1>;
247 #reset-cells = <1>;
248 };
249 };
250};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 45180adfadf1..e0883c376248 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,3 +1,5 @@
1#include <dt-bindings/input/input.h>
2
1#include "qcom-msm8660.dtsi" 3#include "qcom-msm8660.dtsi"
2 4
3/ { 5/ {
@@ -12,5 +14,45 @@
12 status = "ok"; 14 status = "ok";
13 }; 15 };
14 }; 16 };
17
18 amba {
19 /* eMMC */
20 sdcc1: sdcc@12400000 {
21 status = "okay";
22 };
23
24 /* External micro SD card */
25 sdcc3: sdcc@12180000 {
26 status = "okay";
27 };
28 };
29 };
30};
31
32&pmicintc {
33 keypad@148 {
34 linux,keymap = <
35 MATRIX_KEY(0, 0, KEY_FN_F1)
36 MATRIX_KEY(0, 1, KEY_UP)
37 MATRIX_KEY(0, 2, KEY_LEFT)
38 MATRIX_KEY(0, 3, KEY_VOLUMEUP)
39 MATRIX_KEY(1, 0, KEY_FN_F2)
40 MATRIX_KEY(1, 1, KEY_RIGHT)
41 MATRIX_KEY(1, 2, KEY_DOWN)
42 MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
43 MATRIX_KEY(2, 3, KEY_ENTER)
44 MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
45 MATRIX_KEY(4, 1, KEY_UP)
46 MATRIX_KEY(4, 2, KEY_LEFT)
47 MATRIX_KEY(4, 3, KEY_HOME)
48 MATRIX_KEY(4, 4, KEY_FN_F3)
49 MATRIX_KEY(5, 0, KEY_CAMERA)
50 MATRIX_KEY(5, 1, KEY_RIGHT)
51 MATRIX_KEY(5, 2, KEY_DOWN)
52 MATRIX_KEY(5, 3, KEY_BACK)
53 MATRIX_KEY(5, 4, KEY_MENU)
54 >;
55 keypad,num-rows = <6>;
56 keypad,num-columns = <5>;
15 }; 57 };
16}; 58};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 53837aaa2f72..0affd6193f56 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -2,6 +2,7 @@
2 2
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8660.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6#include <dt-bindings/soc/qcom,gsbi.h> 7#include <dt-bindings/soc/qcom,gsbi.h>
7 8
@@ -103,6 +104,98 @@
103 compatible = "qcom,ssbi"; 104 compatible = "qcom,ssbi";
104 reg = <0x500000 0x1000>; 105 reg = <0x500000 0x1000>;
105 qcom,controller-type = "pmic-arbiter"; 106 qcom,controller-type = "pmic-arbiter";
107
108 pmicintc: pmic@0 {
109 compatible = "qcom,pm8058";
110 interrupt-parent = <&msmgpio>;
111 interrupts = <88 8>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 pwrkey@1c {
118 compatible = "qcom,pm8058-pwrkey";
119 reg = <0x1c>;
120 interrupt-parent = <&pmicintc>;
121 interrupts = <50 1>, <51 1>;
122 debounce = <15625>;
123 pull-up;
124 };
125
126 keypad@148 {
127 compatible = "qcom,pm8058-keypad";
128 reg = <0x148>;
129 interrupt-parent = <&pmicintc>;
130 interrupts = <74 1>, <75 1>;
131 debounce = <15>;
132 scan-delay = <32>;
133 row-hold = <91500>;
134 };
135
136 rtc@11d {
137 compatible = "qcom,pm8058-rtc";
138 interrupt-parent = <&pmicintc>;
139 interrupts = <39 1>;
140 reg = <0x11d>;
141 allow-set-time;
142 };
143
144 vibrator@4a {
145 compatible = "qcom,pm8058-vib";
146 reg = <0x4a>;
147 };
148 };
149 };
150
151 /* Temporary fixed regulator */
152 vsdcc_fixed: vsdcc-regulator {
153 compatible = "regulator-fixed";
154 regulator-name = "SDCC Power";
155 regulator-min-microvolt = <2700000>;
156 regulator-max-microvolt = <2700000>;
157 regulator-always-on;
158 };
159
160 amba {
161 compatible = "arm,amba-bus";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 sdcc1: sdcc@12400000 {
166 status = "disabled";
167 compatible = "arm,pl18x", "arm,primecell";
168 arm,primecell-periphid = <0x00051180>;
169 reg = <0x12400000 0x8000>;
170 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "cmd_irq";
172 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
173 clock-names = "mclk", "apb_pclk";
174 bus-width = <8>;
175 max-frequency = <48000000>;
176 non-removable;
177 cap-sd-highspeed;
178 cap-mmc-highspeed;
179 vmmc-supply = <&vsdcc_fixed>;
180 };
181
182 sdcc3: sdcc@12180000 {
183 compatible = "arm,pl18x", "arm,primecell";
184 arm,primecell-periphid = <0x00051180>;
185 status = "disabled";
186 reg = <0x12180000 0x8000>;
187 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "cmd_irq";
189 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
190 clock-names = "mclk", "apb_pclk";
191 bus-width = <4>;
192 cap-sd-highspeed;
193 cap-mmc-highspeed;
194 max-frequency = <48000000>;
195 no-1-8-v;
196 vmmc-supply = <&vsdcc_fixed>;
197 };
106 }; 198 };
107 }; 199 };
200
108}; 201};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 8f75cc4c8340..7f70fae90959 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,3 +1,5 @@
1#include <dt-bindings/input/input.h>
2
1#include "qcom-msm8960.dtsi" 3#include "qcom-msm8960.dtsi"
2 4
3/ { 5/ {
@@ -12,5 +14,30 @@
12 status = "ok"; 14 status = "ok";
13 }; 15 };
14 }; 16 };
17
18 amba {
19 /* eMMC */
20 sdcc1: sdcc@12400000 {
21 status = "okay";
22 };
23
24 /* External micro SD card */
25 sdcc3: sdcc@12180000 {
26 status = "okay";
27 };
28 };
29 };
30};
31
32&pmicintc {
33 keypad@148 {
34 linux,keymap = <
35 MATRIX_KEY(0, 0, KEY_VOLUMEUP)
36 MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
37 MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
38 MATRIX_KEY(0, 3, KEY_CAMERA)
39 >;
40 keypad,num-rows = <1>;
41 keypad,num-columns = <5>;
15 }; 42 };
16}; 43};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 5303e53e34dc..e1b0d5cd9e3c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -2,6 +2,7 @@
2 2
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/soc/qcom,gsbi.h> 7#include <dt-bindings/soc/qcom,gsbi.h>
7 8
@@ -143,6 +144,43 @@
143 compatible = "qcom,ssbi"; 144 compatible = "qcom,ssbi";
144 reg = <0x500000 0x1000>; 145 reg = <0x500000 0x1000>;
145 qcom,controller-type = "pmic-arbiter"; 146 qcom,controller-type = "pmic-arbiter";
147
148 pmicintc: pmic@0 {
149 compatible = "qcom,pm8921";
150 interrupt-parent = <&msmgpio>;
151 interrupts = <104 8>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 pwrkey@1c {
158 compatible = "qcom,pm8921-pwrkey";
159 reg = <0x1c>;
160 interrupt-parent = <&pmicintc>;
161 interrupts = <50 1>, <51 1>;
162 debounce = <15625>;
163 pull-up;
164 };
165
166 keypad@148 {
167 compatible = "qcom,pm8921-keypad";
168 reg = <0x148>;
169 interrupt-parent = <&pmicintc>;
170 interrupts = <74 1>, <75 1>;
171 debounce = <15>;
172 scan-delay = <32>;
173 row-hold = <91500>;
174 };
175
176 rtc@11d {
177 compatible = "qcom,pm8921-rtc";
178 interrupt-parent = <&pmicintc>;
179 interrupts = <39 1>;
180 reg = <0x11d>;
181 allow-set-time;
182 };
183 };
146 }; 184 };
147 185
148 rng@1a500000 { 186 rng@1a500000 {
@@ -151,5 +189,54 @@
151 clocks = <&gcc PRNG_CLK>; 189 clocks = <&gcc PRNG_CLK>;
152 clock-names = "core"; 190 clock-names = "core";
153 }; 191 };
192
193 /* Temporary fixed regulator */
194 vsdcc_fixed: vsdcc-regulator {
195 compatible = "regulator-fixed";
196 regulator-name = "SDCC Power";
197 regulator-min-microvolt = <2700000>;
198 regulator-max-microvolt = <2700000>;
199 regulator-always-on;
200 };
201
202 amba {
203 compatible = "arm,amba-bus";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges;
207 sdcc1: sdcc@12400000 {
208 status = "disabled";
209 compatible = "arm,pl18x", "arm,primecell";
210 arm,primecell-periphid = <0x00051180>;
211 reg = <0x12400000 0x8000>;
212 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "cmd_irq";
214 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
215 clock-names = "mclk", "apb_pclk";
216 bus-width = <8>;
217 max-frequency = <96000000>;
218 non-removable;
219 cap-sd-highspeed;
220 cap-mmc-highspeed;
221 vmmc-supply = <&vsdcc_fixed>;
222 };
223
224 sdcc3: sdcc@12180000 {
225 compatible = "arm,pl18x", "arm,primecell";
226 arm,primecell-periphid = <0x00051180>;
227 status = "disabled";
228 reg = <0x12180000 0x8000>;
229 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "cmd_irq";
231 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
232 clock-names = "mclk", "apb_pclk";
233 bus-width = <4>;
234 cap-sd-highspeed;
235 cap-mmc-highspeed;
236 max-frequency = <192000000>;
237 no-1-8-v;
238 vmmc-supply = <&vsdcc_fixed>;
239 };
240 };
154 }; 241 };
155}; 242};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 69dca2aca25a..e265ec16a787 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,8 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include "skeleton.dtsi" 3#include <dt-bindings/interrupt-controller/irq.h>
4
5#include <dt-bindings/clock/qcom,gcc-msm8974.h> 4#include <dt-bindings/clock/qcom,gcc-msm8974.h>
5#include "skeleton.dtsi"
6 6
7/ { 7/ {
8 model = "Qualcomm MSM8974"; 8 model = "Qualcomm MSM8974";
@@ -236,5 +236,16 @@
236 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
237 interrupts = <0 208 0>; 237 interrupts = <0 208 0>;
238 }; 238 };
239
240 blsp_i2c11: i2c@f9967000 {
241 status = "disable";
242 compatible = "qcom,i2c-qup-v2.1.1";
243 reg = <0xf9967000 0x1000>;
244 interrupts = <0 105 IRQ_TYPE_NONE>;
245 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
246 clock-names = "core", "iface";
247 #address-cells = <1>;
248 #size-cells = <0>;
249 };
239 }; 250 };
240}; 251};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index d8ec5058c351..ef152e384822 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -51,7 +51,7 @@
51 }; 51 };
52 52
53 irqc0: interrupt-controller@e61c0000 { 53 irqc0: interrupt-controller@e61c0000 {
54 compatible = "renesas,irqc"; 54 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
55 #interrupt-cells = <2>; 55 #interrupt-cells = <2>;
56 interrupt-controller; 56 interrupt-controller;
57 reg = <0 0xe61c0000 0 0x200>; 57 reg = <0 0xe61c0000 0 0x200>;
@@ -90,7 +90,7 @@
90 }; 90 };
91 91
92 irqc1: interrupt-controller@e61c0200 { 92 irqc1: interrupt-controller@e61c0200 {
93 compatible = "renesas,irqc"; 93 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
94 #interrupt-cells = <2>; 94 #interrupt-cells = <2>;
95 interrupt-controller; 95 interrupt-controller;
96 reg = <0 0xe61c0200 0 0x200>; 96 reg = <0 0xe61c0200 0 0x200>;
@@ -165,7 +165,7 @@
165 }; 165 };
166 166
167 thermal@e61f0000 { 167 thermal@e61f0000 {
168 compatible = "renesas,rcar-thermal"; 168 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
169 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 169 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
170 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 170 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 72891e5f0f1b..7cfba9aa1b41 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -199,7 +199,6 @@
199 scif0: serial@ffe40000 { 199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif"; 200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>; 201 reg = <0xffe40000 0x100>;
202 interrupt-parent = <&gic>;
203 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg_clocks R8A7779_CLK_P>; 203 clocks = <&cpg_clocks R8A7779_CLK_P>;
205 clock-names = "sci_ick"; 204 clock-names = "sci_ick";
@@ -209,7 +208,6 @@
209 scif1: serial@ffe41000 { 208 scif1: serial@ffe41000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif"; 209 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe41000 0x100>; 210 reg = <0xffe41000 0x100>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cpg_clocks R8A7779_CLK_P>; 212 clocks = <&cpg_clocks R8A7779_CLK_P>;
215 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
@@ -219,7 +217,6 @@
219 scif2: serial@ffe42000 { 217 scif2: serial@ffe42000 {
220 compatible = "renesas,scif-r8a7779", "renesas,scif"; 218 compatible = "renesas,scif-r8a7779", "renesas,scif";
221 reg = <0xffe42000 0x100>; 219 reg = <0xffe42000 0x100>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cpg_clocks R8A7779_CLK_P>; 221 clocks = <&cpg_clocks R8A7779_CLK_P>;
225 clock-names = "sci_ick"; 222 clock-names = "sci_ick";
@@ -229,7 +226,6 @@
229 scif3: serial@ffe43000 { 226 scif3: serial@ffe43000 {
230 compatible = "renesas,scif-r8a7779", "renesas,scif"; 227 compatible = "renesas,scif-r8a7779", "renesas,scif";
231 reg = <0xffe43000 0x100>; 228 reg = <0xffe43000 0x100>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpg_clocks R8A7779_CLK_P>; 230 clocks = <&cpg_clocks R8A7779_CLK_P>;
235 clock-names = "sci_ick"; 231 clock-names = "sci_ick";
@@ -239,7 +235,6 @@
239 scif4: serial@ffe44000 { 235 scif4: serial@ffe44000 {
240 compatible = "renesas,scif-r8a7779", "renesas,scif"; 236 compatible = "renesas,scif-r8a7779", "renesas,scif";
241 reg = <0xffe44000 0x100>; 237 reg = <0xffe44000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg_clocks R8A7779_CLK_P>; 239 clocks = <&cpg_clocks R8A7779_CLK_P>;
245 clock-names = "sci_ick"; 240 clock-names = "sci_ick";
@@ -249,7 +244,6 @@
249 scif5: serial@ffe45000 { 244 scif5: serial@ffe45000 {
250 compatible = "renesas,scif-r8a7779", "renesas,scif"; 245 compatible = "renesas,scif-r8a7779", "renesas,scif";
251 reg = <0xffe45000 0x100>; 246 reg = <0xffe45000 0x100>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cpg_clocks R8A7779_CLK_P>; 248 clocks = <&cpg_clocks R8A7779_CLK_P>;
255 clock-names = "sci_ick"; 249 clock-names = "sci_ick";
@@ -262,7 +256,7 @@
262 }; 256 };
263 257
264 thermal@ffc48000 { 258 thermal@ffc48000 {
265 compatible = "renesas,rcar-thermal"; 259 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
266 reg = <0xffc48000 0x38>; 260 reg = <0xffc48000 0x38>;
267 }; 261 };
268 262
@@ -446,10 +440,10 @@
446 /* Gate clocks */ 440 /* Gate clocks */
447 mstp0_clks: clocks@ffc80030 { 441 mstp0_clks: clocks@ffc80030 {
448 compatible = "renesas,r8a7779-mstp-clocks", 442 compatible = "renesas,r8a7779-mstp-clocks",
449 "renesas,cpg-mstp-clocks"; 443 "renesas,cpg-mstp-clocks";
450 reg = <0xffc80030 4>; 444 reg = <0xffc80030 4>;
451 clocks = <&cpg_clocks R8A7779_CLK_S>, 445 clocks = <&cpg_clocks R8A7779_CLK_S>,
452 <&cpg_clocks R8A7779_CLK_P>, 446 <&cpg_clocks R8A7779_CLK_P>,
453 <&cpg_clocks R8A7779_CLK_P>, 447 <&cpg_clocks R8A7779_CLK_P>,
454 <&cpg_clocks R8A7779_CLK_P>, 448 <&cpg_clocks R8A7779_CLK_P>,
455 <&cpg_clocks R8A7779_CLK_S>, 449 <&cpg_clocks R8A7779_CLK_S>,
@@ -483,7 +477,7 @@
483 }; 477 };
484 mstp1_clks: clocks@ffc80034 { 478 mstp1_clks: clocks@ffc80034 {
485 compatible = "renesas,r8a7779-mstp-clocks", 479 compatible = "renesas,r8a7779-mstp-clocks",
486 "renesas,cpg-mstp-clocks"; 480 "renesas,cpg-mstp-clocks";
487 reg = <0xffc80034 4>, <0xffc80044 4>; 481 reg = <0xffc80034 4>, <0xffc80044 4>;
488 clocks = <&cpg_clocks R8A7779_CLK_P>, 482 clocks = <&cpg_clocks R8A7779_CLK_P>,
489 <&cpg_clocks R8A7779_CLK_P>, 483 <&cpg_clocks R8A7779_CLK_P>,
@@ -512,7 +506,7 @@
512 }; 506 };
513 mstp3_clks: clocks@ffc8003c { 507 mstp3_clks: clocks@ffc8003c {
514 compatible = "renesas,r8a7779-mstp-clocks", 508 compatible = "renesas,r8a7779-mstp-clocks",
515 "renesas,cpg-mstp-clocks"; 509 "renesas,cpg-mstp-clocks";
516 reg = <0xffc8003c 4>; 510 reg = <0xffc8003c 4>;
517 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 511 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
518 <&s4_clk>, <&s4_clk>; 512 <&s4_clk>, <&s4_clk>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 7853c2c15ce6..69098b906b39 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -32,7 +32,7 @@
32 reg = <0 0x40000000 0 0x40000000>; 32 reg = <0 0x40000000 0 0x40000000>;
33 }; 33 };
34 34
35 memory@180000000 { 35 memory@140000000 {
36 device_type = "memory"; 36 device_type = "memory";
37 reg = <1 0x40000000 0 0xc0000000>; 37 reg = <1 0x40000000 0 0xc0000000>;
38 }; 38 };
@@ -234,6 +234,11 @@
234 renesas,groups = "usb2"; 234 renesas,groups = "usb2";
235 renesas,function = "usb2"; 235 renesas,function = "usb2";
236 }; 236 };
237
238 vin1_pins: vin {
239 renesas,groups = "vin1_data8", "vin1_clk";
240 renesas,function = "vin1";
241 };
237}; 242};
238 243
239&ether { 244&ether {
@@ -370,6 +375,19 @@
370 status = "ok"; 375 status = "ok";
371 pinctrl-0 = <&iic2_pins>; 376 pinctrl-0 = <&iic2_pins>;
372 pinctrl-names = "default"; 377 pinctrl-names = "default";
378
379 composite-in@20 {
380 compatible = "adi,adv7180";
381 reg = <0x20>;
382 remote = <&vin1>;
383
384 port {
385 adv7180: endpoint {
386 bus-width = <8>;
387 remote-endpoint = <&vin1ep0>;
388 };
389 };
390 };
373}; 391};
374 392
375&iic3 { 393&iic3 {
@@ -378,7 +396,7 @@
378 status = "okay"; 396 status = "okay";
379 397
380 vdd_dvfs: regulator@68 { 398 vdd_dvfs: regulator@68 {
381 compatible = "diasemi,da9210"; 399 compatible = "dlg,da9210";
382 reg = <0x68>; 400 reg = <0x68>;
383 401
384 regulator-min-microvolt = <1000000>; 402 regulator-min-microvolt = <1000000>;
@@ -405,3 +423,21 @@
405 pinctrl-0 = <&usb2_pins>; 423 pinctrl-0 = <&usb2_pins>;
406 pinctrl-names = "default"; 424 pinctrl-names = "default";
407}; 425};
426
427/* composite video input */
428&vin1 {
429 pinctrl-0 = <&vin1_pins>;
430 pinctrl-names = "default";
431
432 status = "ok";
433
434 port {
435 #address-cells = <1>;
436 #size-cells = <0>;
437
438 vin1ep0: endpoint {
439 remote-endpoint = <&adv7180>;
440 bus-width = <8>;
441 };
442 };
443};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index aa146d2d1022..d0e17733dc1a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -33,6 +33,10 @@
33 spi2 = &msiof1; 33 spi2 = &msiof1;
34 spi3 = &msiof2; 34 spi3 = &msiof2;
35 spi4 = &msiof3; 35 spi4 = &msiof3;
36 vin0 = &vin0;
37 vin1 = &vin1;
38 vin2 = &vin2;
39 vin3 = &vin3;
36 }; 40 };
37 41
38 cpus { 42 cpus {
@@ -249,6 +253,65 @@
249 <0 3 IRQ_TYPE_LEVEL_HIGH>; 253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
250 }; 254 };
251 255
256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
281 clock-names = "fck";
282 #dma-cells = <1>;
283 dma-channels = <15>;
284 };
285
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
311 clock-names = "fck";
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
252 i2c0: i2c@e6508000 { 315 i2c0: i2c@e6508000 {
253 #address-cells = <1>; 316 #address-cells = <1>;
254 #size-cells = <0>; 317 #size-cells = <0>;
@@ -505,6 +568,38 @@
505 status = "disabled"; 568 status = "disabled";
506 }; 569 };
507 570
571 vin0: video@e6ef0000 {
572 compatible = "renesas,vin-r8a7790";
573 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
574 reg = <0 0xe6ef0000 0 0x1000>;
575 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
576 status = "disabled";
577 };
578
579 vin1: video@e6ef1000 {
580 compatible = "renesas,vin-r8a7790";
581 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
582 reg = <0 0xe6ef1000 0 0x1000>;
583 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
584 status = "disabled";
585 };
586
587 vin2: video@e6ef2000 {
588 compatible = "renesas,vin-r8a7790";
589 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
590 reg = <0 0xe6ef2000 0 0x1000>;
591 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
592 status = "disabled";
593 };
594
595 vin3: video@e6ef3000 {
596 compatible = "renesas,vin-r8a7790";
597 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
598 reg = <0 0xe6ef3000 0 0x1000>;
599 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
600 status = "disabled";
601 };
602
508 clocks { 603 clocks {
509 #address-cells = <2>; 604 #address-cells = <2>;
510 #size-cells = <2>; 605 #size-cells = <2>;
@@ -773,33 +868,36 @@
773 mstp1_clks: mstp1_clks@e6150134 { 868 mstp1_clks: mstp1_clks@e6150134 {
774 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 869 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
775 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 870 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
776 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 871 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
777 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 872 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
778 <&zs_clk>; 873 <&zs_clk>;
779 #clock-cells = <1>; 874 #clock-cells = <1>;
780 renesas,clock-indices = < 875 renesas,clock-indices = <
781 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 876 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
782 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 877 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
783 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 878 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
784 >; 879 >;
785 clock-output-names = 880 clock-output-names =
786 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 881 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
787 "vsp1-du0", "vsp1-rt", "vsp1-sy"; 882 "vsp1-du0", "vsp1-rt", "vsp1-sy";
788 }; 883 };
789 mstp2_clks: mstp2_clks@e6150138 { 884 mstp2_clks: mstp2_clks@e6150138 {
790 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 885 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
791 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 886 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
792 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 887 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
793 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; 888 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
889 <&zs_clk>;
794 #clock-cells = <1>; 890 #clock-cells = <1>;
795 renesas,clock-indices = < 891 renesas,clock-indices = <
796 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 892 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
797 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 893 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
798 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 894 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
895 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
799 >; 896 >;
800 clock-output-names = 897 clock-output-names =
801 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 898 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
802 "scifb1", "msiof1", "msiof3", "scifb2"; 899 "scifb1", "msiof1", "msiof3", "scifb2",
900 "sys-dmac1", "sys-dmac0";
803 }; 901 };
804 mstp3_clks: mstp3_clks@e615013c { 902 mstp3_clks: mstp3_clks@e615013c {
805 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 903 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -916,6 +1014,8 @@
916 reg = <0 0xe6b10000 0 0x2c>; 1014 reg = <0 0xe6b10000 0 0x2c>;
917 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1015 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; 1016 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1017 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1018 dma-names = "tx", "rx";
919 num-cs = <1>; 1019 num-cs = <1>;
920 #address-cells = <1>; 1020 #address-cells = <1>;
921 #size-cells = <0>; 1021 #size-cells = <0>;
@@ -924,9 +1024,11 @@
924 1024
925 msiof0: spi@e6e20000 { 1025 msiof0: spi@e6e20000 {
926 compatible = "renesas,msiof-r8a7790"; 1026 compatible = "renesas,msiof-r8a7790";
927 reg = <0 0xe6e20000 0 0x0064>; 1027 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
928 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; 1029 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1030 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1031 dma-names = "tx", "rx";
930 #address-cells = <1>; 1032 #address-cells = <1>;
931 #size-cells = <0>; 1033 #size-cells = <0>;
932 status = "disabled"; 1034 status = "disabled";
@@ -934,9 +1036,11 @@
934 1036
935 msiof1: spi@e6e10000 { 1037 msiof1: spi@e6e10000 {
936 compatible = "renesas,msiof-r8a7790"; 1038 compatible = "renesas,msiof-r8a7790";
937 reg = <0 0xe6e10000 0 0x0064>; 1039 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
938 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1040 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; 1041 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1042 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1043 dma-names = "tx", "rx";
940 #address-cells = <1>; 1044 #address-cells = <1>;
941 #size-cells = <0>; 1045 #size-cells = <0>;
942 status = "disabled"; 1046 status = "disabled";
@@ -944,9 +1048,11 @@
944 1048
945 msiof2: spi@e6e00000 { 1049 msiof2: spi@e6e00000 {
946 compatible = "renesas,msiof-r8a7790"; 1050 compatible = "renesas,msiof-r8a7790";
947 reg = <0 0xe6e00000 0 0x0064>; 1051 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
948 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; 1053 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1054 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1055 dma-names = "tx", "rx";
950 #address-cells = <1>; 1056 #address-cells = <1>;
951 #size-cells = <0>; 1057 #size-cells = <0>;
952 status = "disabled"; 1058 status = "disabled";
@@ -954,9 +1060,11 @@
954 1060
955 msiof3: spi@e6c90000 { 1061 msiof3: spi@e6c90000 {
956 compatible = "renesas,msiof-r8a7790"; 1062 compatible = "renesas,msiof-r8a7790";
957 reg = <0 0xe6c90000 0 0x0064>; 1063 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
958 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; 1064 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; 1065 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1066 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1067 dma-names = "tx", "rx";
960 #address-cells = <1>; 1068 #address-cells = <1>;
961 #size-cells = <0>; 1069 #size-cells = <0>;
962 status = "disabled"; 1070 status = "disabled";
@@ -1050,7 +1158,6 @@
1050 rcar_sound: rcar_sound@0xec500000 { 1158 rcar_sound: rcar_sound@0xec500000 {
1051 #sound-dai-cells = <1>; 1159 #sound-dai-cells = <1>;
1052 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1160 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1053 interrupt-parent = <&gic>;
1054 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1161 reg = <0 0xec500000 0 0x1000>, /* SCU */
1055 <0 0xec5a0000 0 0x100>, /* ADG */ 1162 <0 0xec5a0000 0 0x100>, /* ADG */
1056 <0 0xec540000 0 0x1000>, /* SSIU */ 1163 <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 3a2ef0a2a137..f1b56de10205 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -135,6 +135,11 @@
135 renesas,groups = "usb1"; 135 renesas,groups = "usb1";
136 renesas,function = "usb1"; 136 renesas,function = "usb1";
137 }; 137 };
138
139 vin0_pins: vin0 {
140 renesas,groups = "vin0_data8", "vin0_clk";
141 renesas,function = "vin0";
142 };
138}; 143};
139 144
140&scif0 { 145&scif0 {
@@ -191,6 +196,19 @@
191 196
192 status = "okay"; 197 status = "okay";
193 clock-frequency = <400000>; 198 clock-frequency = <400000>;
199
200 composite-in@20 {
201 compatible = "adi,adv7180";
202 reg = <0x20>;
203 remote = <&vin0>;
204
205 port {
206 adv7180: endpoint {
207 bus-width = <8>;
208 remote-endpoint = <&vin0ep>;
209 };
210 };
211 };
194}; 212};
195 213
196&qspi { 214&qspi {
@@ -260,3 +278,20 @@
260&pciec { 278&pciec {
261 status = "okay"; 279 status = "okay";
262}; 280};
281
282/* composite video input */
283&vin0 {
284 status = "ok";
285 pinctrl-0 = <&vin0_pins>;
286 pinctrl-names = "default";
287
288 port {
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 vin0ep: endpoint {
293 remote-endpoint = <&adv7180>;
294 bus-width = <8>;
295 };
296 };
297};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 740308e09457..07550e775e80 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -284,6 +284,11 @@
284 renesas,groups = "usb1"; 284 renesas,groups = "usb1";
285 renesas,function = "usb1"; 285 renesas,function = "usb1";
286 }; 286 };
287
288 vin1_pins: vin1 {
289 renesas,groups = "vin1_data8", "vin1_clk";
290 renesas,function = "vin1";
291 };
287}; 292};
288 293
289&ether { 294&ether {
@@ -411,6 +416,19 @@
411 status = "okay"; 416 status = "okay";
412 clock-frequency = <400000>; 417 clock-frequency = <400000>;
413 418
419 composite-in@20 {
420 compatible = "adi,adv7180";
421 reg = <0x20>;
422 remote = <&vin1>;
423
424 port {
425 adv7180: endpoint {
426 bus-width = <8>;
427 remote-endpoint = <&vin1ep>;
428 };
429 };
430 };
431
414 eeprom@50 { 432 eeprom@50 {
415 compatible = "renesas,24c02"; 433 compatible = "renesas,24c02";
416 reg = <0x50>; 434 reg = <0x50>;
@@ -423,7 +441,7 @@
423 clock-frequency = <100000>; 441 clock-frequency = <100000>;
424 442
425 vdd_dvfs: regulator@68 { 443 vdd_dvfs: regulator@68 {
426 compatible = "diasemi,da9210"; 444 compatible = "dlg,da9210";
427 reg = <0x68>; 445 reg = <0x68>;
428 446
429 regulator-min-microvolt = <1000000>; 447 regulator-min-microvolt = <1000000>;
@@ -456,3 +474,20 @@
456&cpu0 { 474&cpu0 {
457 cpu0-supply = <&vdd_dvfs>; 475 cpu0-supply = <&vdd_dvfs>;
458}; 476};
477
478/* composite video input */
479&vin1 {
480 status = "ok";
481 pinctrl-0 = <&vin1_pins>;
482 pinctrl-names = "default";
483
484 port {
485 #address-cells = <1>;
486 #size-cells = <0>;
487
488 vin1ep: endpoint {
489 remote-endpoint = <&adv7180>;
490 bus-width = <8>;
491 };
492 };
493};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e270f38d827f..e06c11fa8698 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -34,6 +34,9 @@
34 spi1 = &msiof0; 34 spi1 = &msiof0;
35 spi2 = &msiof1; 35 spi2 = &msiof1;
36 spi3 = &msiof2; 36 spi3 = &msiof2;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
37 }; 40 };
38 41
39 cpus { 42 cpus {
@@ -238,6 +241,66 @@
238 <0 17 IRQ_TYPE_LEVEL_HIGH>; 241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
239 }; 242 };
240 243
244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
269 clock-names = "fck";
270 #dma-cells = <1>;
271 dma-channels = <15>;
272 };
273
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
299 clock-names = "fck";
300 #dma-cells = <1>;
301 dma-channels = <15>;
302 };
303
241 /* The memory map in the User's Manual maps the cores to bus numbers */ 304 /* The memory map in the User's Manual maps the cores to bus numbers */
242 i2c0: i2c@e6508000 { 305 i2c0: i2c@e6508000 {
243 #address-cells = <1>; 306 #address-cells = <1>;
@@ -550,6 +613,30 @@
550 status = "disabled"; 613 status = "disabled";
551 }; 614 };
552 615
616 vin0: video@e6ef0000 {
617 compatible = "renesas,vin-r8a7791";
618 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
619 reg = <0 0xe6ef0000 0 0x1000>;
620 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
621 status = "disabled";
622 };
623
624 vin1: video@e6ef1000 {
625 compatible = "renesas,vin-r8a7791";
626 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
627 reg = <0 0xe6ef1000 0 0x1000>;
628 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
629 status = "disabled";
630 };
631
632 vin2: video@e6ef2000 {
633 compatible = "renesas,vin-r8a7791";
634 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
635 reg = <0 0xe6ef2000 0 0x1000>;
636 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
637 status = "disabled";
638 };
639
553 clocks { 640 clocks {
554 #address-cells = <2>; 641 #address-cells = <2>;
555 #size-cells = <2>; 642 #size-cells = <2>;
@@ -802,16 +889,16 @@
802 mstp1_clks: mstp1_clks@e6150134 { 889 mstp1_clks: mstp1_clks@e6150134 {
803 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 890 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
804 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 891 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
805 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 892 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
806 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 893 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
807 #clock-cells = <1>; 894 #clock-cells = <1>;
808 renesas,clock-indices = < 895 renesas,clock-indices = <
809 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 896 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
810 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 897 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
811 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S 898 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
812 >; 899 >;
813 clock-output-names = 900 clock-output-names =
814 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 901 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
815 "vsp1-du0", "vsp1-sy"; 902 "vsp1-du0", "vsp1-sy";
816 }; 903 };
817 mstp2_clks: mstp2_clks@e6150138 { 904 mstp2_clks: mstp2_clks@e6150138 {
@@ -957,6 +1044,8 @@
957 reg = <0 0xe6b10000 0 0x2c>; 1044 reg = <0 0xe6b10000 0 0x2c>;
958 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; 1046 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1047 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1048 dma-names = "tx", "rx";
960 num-cs = <1>; 1049 num-cs = <1>;
961 #address-cells = <1>; 1050 #address-cells = <1>;
962 #size-cells = <0>; 1051 #size-cells = <0>;
@@ -965,9 +1054,11 @@
965 1054
966 msiof0: spi@e6e20000 { 1055 msiof0: spi@e6e20000 {
967 compatible = "renesas,msiof-r8a7791"; 1056 compatible = "renesas,msiof-r8a7791";
968 reg = <0 0xe6e20000 0 0x0064>; 1057 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
969 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 1059 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1060 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1061 dma-names = "tx", "rx";
971 #address-cells = <1>; 1062 #address-cells = <1>;
972 #size-cells = <0>; 1063 #size-cells = <0>;
973 status = "disabled"; 1064 status = "disabled";
@@ -975,9 +1066,11 @@
975 1066
976 msiof1: spi@e6e10000 { 1067 msiof1: spi@e6e10000 {
977 compatible = "renesas,msiof-r8a7791"; 1068 compatible = "renesas,msiof-r8a7791";
978 reg = <0 0xe6e10000 0 0x0064>; 1069 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
979 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1070 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; 1071 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1072 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1073 dma-names = "tx", "rx";
981 #address-cells = <1>; 1074 #address-cells = <1>;
982 #size-cells = <0>; 1075 #size-cells = <0>;
983 status = "disabled"; 1076 status = "disabled";
@@ -985,9 +1078,11 @@
985 1078
986 msiof2: spi@e6e00000 { 1079 msiof2: spi@e6e00000 {
987 compatible = "renesas,msiof-r8a7791"; 1080 compatible = "renesas,msiof-r8a7791";
988 reg = <0 0xe6e00000 0 0x0064>; 1081 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
989 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1082 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; 1083 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1084 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1085 dma-names = "tx", "rx";
991 #address-cells = <1>; 1086 #address-cells = <1>;
992 #size-cells = <0>; 1087 #size-cells = <0>;
993 status = "disabled"; 1088 status = "disabled";
@@ -1061,7 +1156,6 @@
1061 rcar_sound: rcar_sound@0xec500000 { 1156 rcar_sound: rcar_sound@0xec500000 {
1062 #sound-dai-cells = <1>; 1157 #sound-dai-cells = <1>;
1063 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1158 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1064 interrupt-parent = <&gic>;
1065 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1159 reg = <0 0xec500000 0 0x1000>, /* SCU */
1066 <0 0xec5a0000 0 0x100>, /* ADG */ 1160 <0 0xec5a0000 0 0x100>, /* ADG */
1067 <0 0xec540000 0 0x1000>, /* SSIU */ 1161 <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
new file mode 100644
index 000000000000..79d06ef017a0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -0,0 +1,47 @@
1/*
2 * Device Tree Source for the Alt board
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7794.dtsi"
13
14/ {
15 model = "Alt";
16 compatible = "renesas,alt", "renesas,r8a7794";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
23 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0 0x40000000 0 0x40000000>;
29 };
30
31 lbsc {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 };
35};
36
37&extal_clk {
38 clock-frequency = <20000000>;
39};
40
41&cmt0 {
42 status = "ok";
43};
44
45&scif2 {
46 status = "ok";
47};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
new file mode 100644
index 000000000000..d4e8bce1e0b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -0,0 +1,531 @@
1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a7";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 };
32
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a7";
36 reg = <1>;
37 clock-frequency = <1000000000>;
38 };
39 };
40
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a7-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
51 };
52
53 cmt0: timer@ffca0000 {
54 compatible = "renesas,cmt-48-gen2";
55 reg = <0 0xffca0000 0 0x1004>;
56 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
57 <0 143 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
59 clock-names = "fck";
60
61 renesas,channels-mask = <0x60>;
62
63 status = "disabled";
64 };
65
66 cmt1: timer@e6130000 {
67 compatible = "renesas,cmt-48-gen2";
68 reg = <0 0xe6130000 0 0x1004>;
69 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
70 <0 121 IRQ_TYPE_LEVEL_HIGH>,
71 <0 122 IRQ_TYPE_LEVEL_HIGH>,
72 <0 123 IRQ_TYPE_LEVEL_HIGH>,
73 <0 124 IRQ_TYPE_LEVEL_HIGH>,
74 <0 125 IRQ_TYPE_LEVEL_HIGH>,
75 <0 126 IRQ_TYPE_LEVEL_HIGH>,
76 <0 127 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
78 clock-names = "fck";
79
80 renesas,channels-mask = <0xff>;
81
82 status = "disabled";
83 };
84
85 irqc0: interrupt-controller@e61c0000 {
86 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
87 #interrupt-cells = <2>;
88 interrupt-controller;
89 reg = <0 0xe61c0000 0 0x200>;
90 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
91 <0 1 IRQ_TYPE_LEVEL_HIGH>,
92 <0 2 IRQ_TYPE_LEVEL_HIGH>,
93 <0 3 IRQ_TYPE_LEVEL_HIGH>,
94 <0 12 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>,
96 <0 14 IRQ_TYPE_LEVEL_HIGH>,
97 <0 15 IRQ_TYPE_LEVEL_HIGH>,
98 <0 16 IRQ_TYPE_LEVEL_HIGH>,
99 <0 17 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 scifa0: serial@e6c40000 {
103 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
104 reg = <0 0xe6c40000 0 64>;
105 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
107 clock-names = "sci_ick";
108 status = "disabled";
109 };
110
111 scifa1: serial@e6c50000 {
112 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
113 reg = <0 0xe6c50000 0 64>;
114 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
116 clock-names = "sci_ick";
117 status = "disabled";
118 };
119
120 scifa2: serial@e6c60000 {
121 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
122 reg = <0 0xe6c60000 0 64>;
123 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
125 clock-names = "sci_ick";
126 status = "disabled";
127 };
128
129 scifa3: serial@e6c70000 {
130 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
131 reg = <0 0xe6c70000 0 64>;
132 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
134 clock-names = "sci_ick";
135 status = "disabled";
136 };
137
138 scifa4: serial@e6c78000 {
139 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
140 reg = <0 0xe6c78000 0 64>;
141 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
143 clock-names = "sci_ick";
144 status = "disabled";
145 };
146
147 scifa5: serial@e6c80000 {
148 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
149 reg = <0 0xe6c80000 0 64>;
150 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
152 clock-names = "sci_ick";
153 status = "disabled";
154 };
155
156 scifb0: serial@e6c20000 {
157 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
158 reg = <0 0xe6c20000 0 64>;
159 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
161 clock-names = "sci_ick";
162 status = "disabled";
163 };
164
165 scifb1: serial@e6c30000 {
166 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
167 reg = <0 0xe6c30000 0 64>;
168 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
170 clock-names = "sci_ick";
171 status = "disabled";
172 };
173
174 scifb2: serial@e6ce0000 {
175 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
176 reg = <0 0xe6ce0000 0 64>;
177 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
179 clock-names = "sci_ick";
180 status = "disabled";
181 };
182
183 scif0: serial@e6e60000 {
184 compatible = "renesas,scif-r8a7794", "renesas,scif";
185 reg = <0 0xe6e60000 0 64>;
186 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
188 clock-names = "sci_ick";
189 status = "disabled";
190 };
191
192 scif1: serial@e6e68000 {
193 compatible = "renesas,scif-r8a7794", "renesas,scif";
194 reg = <0 0xe6e68000 0 64>;
195 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
197 clock-names = "sci_ick";
198 status = "disabled";
199 };
200
201 scif2: serial@e6e58000 {
202 compatible = "renesas,scif-r8a7794", "renesas,scif";
203 reg = <0 0xe6e58000 0 64>;
204 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
206 clock-names = "sci_ick";
207 status = "disabled";
208 };
209
210 scif3: serial@e6ea8000 {
211 compatible = "renesas,scif-r8a7794", "renesas,scif";
212 reg = <0 0xe6ea8000 0 64>;
213 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
215 clock-names = "sci_ick";
216 status = "disabled";
217 };
218
219 scif4: serial@e6ee0000 {
220 compatible = "renesas,scif-r8a7794", "renesas,scif";
221 reg = <0 0xe6ee0000 0 64>;
222 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
224 clock-names = "sci_ick";
225 status = "disabled";
226 };
227
228 scif5: serial@e6ee8000 {
229 compatible = "renesas,scif-r8a7794", "renesas,scif";
230 reg = <0 0xe6ee8000 0 64>;
231 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
233 clock-names = "sci_ick";
234 status = "disabled";
235 };
236
237 hscif0: serial@e62c0000 {
238 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
239 reg = <0 0xe62c0000 0 96>;
240 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
242 clock-names = "sci_ick";
243 status = "disabled";
244 };
245
246 hscif1: serial@e62c8000 {
247 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
248 reg = <0 0xe62c8000 0 96>;
249 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
251 clock-names = "sci_ick";
252 status = "disabled";
253 };
254
255 hscif2: serial@e62d0000 {
256 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
257 reg = <0 0xe62d0000 0 96>;
258 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
260 clock-names = "sci_ick";
261 status = "disabled";
262 };
263
264 clocks {
265 #address-cells = <2>;
266 #size-cells = <2>;
267 ranges;
268
269 /* External root clock */
270 extal_clk: extal_clk {
271 compatible = "fixed-clock";
272 #clock-cells = <0>;
273 /* This value must be overriden by the board. */
274 clock-frequency = <0>;
275 clock-output-names = "extal";
276 };
277
278 /* Special CPG clocks */
279 cpg_clocks: cpg_clocks@e6150000 {
280 compatible = "renesas,r8a7794-cpg-clocks",
281 "renesas,rcar-gen2-cpg-clocks";
282 reg = <0 0xe6150000 0 0x1000>;
283 clocks = <&extal_clk>;
284 #clock-cells = <1>;
285 clock-output-names = "main", "pll0", "pll1", "pll3",
286 "lb", "qspi", "sdh", "sd0", "z";
287 };
288
289 /* Fixed factor clocks */
290 pll1_div2_clk: pll1_div2_clk {
291 compatible = "fixed-factor-clock";
292 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
293 #clock-cells = <0>;
294 clock-div = <2>;
295 clock-mult = <1>;
296 clock-output-names = "pll1_div2";
297 };
298 zg_clk: zg_clk {
299 compatible = "fixed-factor-clock";
300 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
301 #clock-cells = <0>;
302 clock-div = <6>;
303 clock-mult = <1>;
304 clock-output-names = "zg";
305 };
306 zx_clk: zx_clk {
307 compatible = "fixed-factor-clock";
308 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
309 #clock-cells = <0>;
310 clock-div = <3>;
311 clock-mult = <1>;
312 clock-output-names = "zx";
313 };
314 zs_clk: zs_clk {
315 compatible = "fixed-factor-clock";
316 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
317 #clock-cells = <0>;
318 clock-div = <6>;
319 clock-mult = <1>;
320 clock-output-names = "zs";
321 };
322 hp_clk: hp_clk {
323 compatible = "fixed-factor-clock";
324 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
325 #clock-cells = <0>;
326 clock-div = <12>;
327 clock-mult = <1>;
328 clock-output-names = "hp";
329 };
330 i_clk: i_clk {
331 compatible = "fixed-factor-clock";
332 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
333 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "i";
337 };
338 b_clk: b_clk {
339 compatible = "fixed-factor-clock";
340 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
341 #clock-cells = <0>;
342 clock-div = <12>;
343 clock-mult = <1>;
344 clock-output-names = "b";
345 };
346 p_clk: p_clk {
347 compatible = "fixed-factor-clock";
348 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
349 #clock-cells = <0>;
350 clock-div = <24>;
351 clock-mult = <1>;
352 clock-output-names = "p";
353 };
354 cl_clk: cl_clk {
355 compatible = "fixed-factor-clock";
356 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
357 #clock-cells = <0>;
358 clock-div = <48>;
359 clock-mult = <1>;
360 clock-output-names = "cl";
361 };
362 m2_clk: m2_clk {
363 compatible = "fixed-factor-clock";
364 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
365 #clock-cells = <0>;
366 clock-div = <8>;
367 clock-mult = <1>;
368 clock-output-names = "m2";
369 };
370 imp_clk: imp_clk {
371 compatible = "fixed-factor-clock";
372 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
373 #clock-cells = <0>;
374 clock-div = <4>;
375 clock-mult = <1>;
376 clock-output-names = "imp";
377 };
378 rclk_clk: rclk_clk {
379 compatible = "fixed-factor-clock";
380 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
381 #clock-cells = <0>;
382 clock-div = <(48 * 1024)>;
383 clock-mult = <1>;
384 clock-output-names = "rclk";
385 };
386 oscclk_clk: oscclk_clk {
387 compatible = "fixed-factor-clock";
388 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
389 #clock-cells = <0>;
390 clock-div = <(12 * 1024)>;
391 clock-mult = <1>;
392 clock-output-names = "oscclk";
393 };
394 zb3_clk: zb3_clk {
395 compatible = "fixed-factor-clock";
396 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
397 #clock-cells = <0>;
398 clock-div = <4>;
399 clock-mult = <1>;
400 clock-output-names = "zb3";
401 };
402 zb3d2_clk: zb3d2_clk {
403 compatible = "fixed-factor-clock";
404 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
405 #clock-cells = <0>;
406 clock-div = <8>;
407 clock-mult = <1>;
408 clock-output-names = "zb3d2";
409 };
410 ddr_clk: ddr_clk {
411 compatible = "fixed-factor-clock";
412 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
413 #clock-cells = <0>;
414 clock-div = <8>;
415 clock-mult = <1>;
416 clock-output-names = "ddr";
417 };
418 mp_clk: mp_clk {
419 compatible = "fixed-factor-clock";
420 clocks = <&pll1_div2_clk>;
421 #clock-cells = <0>;
422 clock-div = <15>;
423 clock-mult = <1>;
424 clock-output-names = "mp";
425 };
426 cp_clk: cp_clk {
427 compatible = "fixed-factor-clock";
428 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
429 #clock-cells = <0>;
430 clock-div = <48>;
431 clock-mult = <1>;
432 clock-output-names = "cp";
433 };
434
435 acp_clk: acp_clk {
436 compatible = "fixed-factor-clock";
437 clocks = <&extal_clk>;
438 #clock-cells = <0>;
439 clock-div = <2>;
440 clock-mult = <1>;
441 clock-output-names = "acp";
442 };
443
444 /* Gate clocks */
445 mstp0_clks: mstp0_clks@e6150130 {
446 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
447 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
448 clocks = <&mp_clk>;
449 #clock-cells = <1>;
450 renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
451 clock-output-names = "msiof0";
452 };
453 mstp1_clks: mstp1_clks@e6150134 {
454 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
455 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
456 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
457 <&cp_clk>,
458 <&zs_clk>, <&zs_clk>, <&zs_clk>;
459 #clock-cells = <1>;
460 renesas,clock-indices = <
461 R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
462 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
463 >;
464 clock-output-names =
465 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
466 };
467 mstp2_clks: mstp2_clks@e6150138 {
468 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
469 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
470 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
471 <&mp_clk>, <&mp_clk>, <&mp_clk>;
472 #clock-cells = <1>;
473 renesas,clock-indices = <
474 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
475 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
476 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
477 >;
478 clock-output-names =
479 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
480 "scifb1", "msiof1", "scifb2";
481 };
482 mstp3_clks: mstp3_clks@e615013c {
483 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
484 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
485 clocks = <&rclk_clk>;
486 #clock-cells = <1>;
487 renesas,clock-indices = <
488 R8A7794_CLK_CMT1
489 >;
490 clock-output-names =
491 "cmt1";
492 };
493 mstp7_clks: mstp7_clks@e615014c {
494 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
495 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
496 clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
497 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
498 #clock-cells = <1>;
499 renesas,clock-indices = <
500 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
501 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
502 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
503 R8A7794_CLK_SCIF0
504 >;
505 clock-output-names =
506 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
507 "scif3", "scif2", "scif1", "scif0";
508 };
509 mstp8_clks: mstp8_clks@e6150990 {
510 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
511 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
512 clocks = <&p_clk>;
513 #clock-cells = <1>;
514 renesas,clock-indices = <
515 R8A7794_CLK_ETHER
516 >;
517 clock-output-names =
518 "ether";
519 };
520 mstp11_clks: mstp11_clks@e615099c {
521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
522 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
523 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
524 #clock-cells = <1>;
525 renesas,clock-indices = <
526 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
527 >;
528 clock-output-names = "scifa3", "scifa4", "scifa5";
529 };
530 };
531};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index c9d912da6141..d5344510c676 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -152,12 +152,8 @@
152 pinctrl-names = "default"; 152 pinctrl-names = "default";
153 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 153 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
154 vmmc-supply = <&vcc_sd0>; 154 vmmc-supply = <&vcc_sd0>;
155 155 bus-width = <4>;
156 slot@0 { 156 disable-wp;
157 reg = <0>;
158 bus-width = <4>;
159 disable-wp;
160 };
161}; 157};
162 158
163&mmc1 { /* wifi */ 159&mmc1 { /* wifi */
@@ -168,11 +164,8 @@
168 pinctrl-names = "default"; 164 pinctrl-names = "default";
169 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; 165 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
170 166
171 slot@0 { 167 bus-width = <4>;
172 reg = <0>; 168 disable-wp;
173 bus-width = <4>;
174 disable-wp;
175 };
176}; 169};
177 170
178&uart0 { 171&uart0 {
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 879a818fba51..ad9c2db59670 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -179,6 +179,27 @@
179 bias-disable; 179 bias-disable;
180 }; 180 };
181 181
182 emmc {
183 emmc_clk: emmc-clk {
184 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
185 };
186
187 emmc_cmd: emmc-cmd {
188 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
189 };
190
191 emmc_rst: emmc-rst {
192 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
193 };
194
195 /*
196 * The data pins are shared between nandc and emmc and
197 * not accessible through pinctrl. Also they should've
198 * been already set correctly by firmware, as
199 * flash/emmc is the boot-device.
200 */
201 };
202
182 i2c0 { 203 i2c0 {
183 i2c0_xfer: i2c0-xfer { 204 i2c0_xfer: i2c0-xfer {
184 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>, 205 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
@@ -238,6 +259,42 @@
238 }; 259 };
239 }; 260 };
240 261
262 spi0 {
263 spi0_clk: spi0-clk {
264 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
265 };
266 spi0_cs0: spi0-cs0 {
267 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
268 };
269 spi0_tx: spi0-tx {
270 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
271 };
272 spi0_rx: spi0-rx {
273 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
274 };
275 spi0_cs1: spi0-cs1 {
276 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
277 };
278 };
279
280 spi1 {
281 spi1_clk: spi1-clk {
282 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
283 };
284 spi1_cs0: spi1-cs0 {
285 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
286 };
287 spi1_rx: spi1-rx {
288 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
289 };
290 spi1_tx: spi1-tx {
291 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
292 };
293 spi1_cs1: spi1-cs1 {
294 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
295 };
296 };
297
241 uart0 { 298 uart0 {
242 uart0_xfer: uart0-xfer { 299 uart0_xfer: uart0-xfer {
243 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 300 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
@@ -406,6 +463,16 @@
406 pinctrl-0 = <&pwm3_out>; 463 pinctrl-0 = <&pwm3_out>;
407}; 464};
408 465
466&spi0 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
469};
470
471&spi1 {
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
474};
475
409&uart0 { 476&uart0 {
410 pinctrl-names = "default"; 477 pinctrl-names = "default";
411 pinctrl-0 = <&uart0_xfer>; 478 pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 5e4e3c238b2d..39f66e349445 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -65,6 +65,19 @@
65 pinctrl-0 = <&ir_recv_pin>; 65 pinctrl-0 = <&ir_recv_pin>;
66 }; 66 };
67 67
68 vcc_otg: usb-otg-regulator {
69 compatible = "regulator-fixed";
70 enable-active-high;
71 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&otg_vbus_drv>;
74 regulator-name = "otg-vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 regulator-always-on;
78 regulator-boot-on;
79 };
80
68 vcc_sd0: sdmmc-regulator { 81 vcc_sd0: sdmmc-regulator {
69 compatible = "regulator-fixed"; 82 compatible = "regulator-fixed";
70 regulator-name = "sdmmc-supply"; 83 regulator-name = "sdmmc-supply";
@@ -74,12 +87,36 @@
74 startup-delay-us = <100000>; 87 startup-delay-us = <100000>;
75 vin-supply = <&vcc_io>; 88 vin-supply = <&vcc_io>;
76 }; 89 };
90
91 vcc_host: usb-host-regulator {
92 compatible = "regulator-fixed";
93 enable-active-high;
94 gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&host_vbus_drv>;
97 regulator-name = "host-pwr";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
77}; 103};
78 104
79&i2c1 { 105&i2c1 {
80 status = "okay"; 106 status = "okay";
81 clock-frequency = <400000>; 107 clock-frequency = <400000>;
82 108
109 rtc@51 {
110 compatible = "haoyu,hym8563";
111 reg = <0x51>;
112 interrupt-parent = <&gpio0>;
113 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&rtc_int>;
116 #clock-cells = <0>;
117 clock-output-names = "xin32k";
118 };
119
83 act8846: act8846@5a { 120 act8846: act8846@5a {
84 compatible = "active-semi,act8846"; 121 compatible = "active-semi,act8846";
85 reg = <0x5a>; 122 reg = <0x5a>;
@@ -149,7 +186,6 @@
149 regulator-name = "VCC_RMII"; 186 regulator-name = "VCC_RMII";
150 regulator-min-microvolt = <3300000>; 187 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>; 188 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 }; 189 };
154 190
155 vccio_wl: REG10 { 191 vccio_wl: REG10 {
@@ -183,11 +219,8 @@
183 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 219 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
184 vmmc-supply = <&vcc_sd0>; 220 vmmc-supply = <&vcc_sd0>;
185 221
186 slot@0 { 222 bus-width = <4>;
187 reg = <0>; 223 disable-wp;
188 bus-width = <4>;
189 disable-wp;
190 };
191}; 224};
192 225
193&pinctrl { 226&pinctrl {
@@ -201,11 +234,26 @@
201 }; 234 };
202 }; 235 };
203 236
237 hym8563 {
238 rtc_int: rtc-int {
239 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
240 };
241 };
242
204 ir-receiver { 243 ir-receiver {
205 ir_recv_pin: ir-recv-pin { 244 ir_recv_pin: ir-recv-pin {
206 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>; 245 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
207 }; 246 };
208 }; 247 };
248
249 usb {
250 host_vbus_drv: host-vbus-drv {
251 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
252 };
253 otg_vbus_drv: otg-vbus-drv {
254 rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
255 };
256 };
209}; 257};
210 258
211&uart0 { 259&uart0 {
@@ -224,6 +272,14 @@
224 status = "okay"; 272 status = "okay";
225}; 273};
226 274
275&usb_host {
276 status = "okay";
277};
278
279&usb_otg {
280 status = "okay";
281};
282
227&wdt { 283&wdt {
228 status = "okay"; 284 status = "okay";
229}; 285};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ee801a9c6b74..82732f5249b2 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -147,6 +147,27 @@
147 bias-disable; 147 bias-disable;
148 }; 148 };
149 149
150 emmc {
151 emmc_clk: emmc-clk {
152 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
153 };
154
155 emmc_cmd: emmc-cmd {
156 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
157 };
158
159 emmc_rst: emmc-rst {
160 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
161 };
162
163 /*
164 * The data pins are shared between nandc and emmc and
165 * not accessible through pinctrl. Also they should've
166 * been already set correctly by firmware, as
167 * flash/emmc is the boot-device.
168 */
169 };
170
150 i2c0 { 171 i2c0 {
151 i2c0_xfer: i2c0-xfer { 172 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, 173 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
@@ -206,6 +227,42 @@
206 }; 227 };
207 }; 228 };
208 229
230 spi0 {
231 spi0_clk: spi0-clk {
232 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
233 };
234 spi0_cs0: spi0-cs0 {
235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
236 };
237 spi0_tx: spi0-tx {
238 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
239 };
240 spi0_rx: spi0-rx {
241 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
242 };
243 spi0_cs1: spi0-cs1 {
244 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
245 };
246 };
247
248 spi1 {
249 spi1_clk: spi1-clk {
250 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
251 };
252 spi1_cs0: spi1-cs0 {
253 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
254 };
255 spi1_rx: spi1-rx {
256 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
257 };
258 spi1_tx: spi1-tx {
259 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
260 };
261 spi1_cs1: spi1-cs1 {
262 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
263 };
264 };
265
209 uart0 { 266 uart0 {
210 uart0_xfer: uart0-xfer { 267 uart0_xfer: uart0-xfer {
211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 268 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
@@ -381,6 +438,18 @@
381 pinctrl-0 = <&pwm3_out>; 438 pinctrl-0 = <&pwm3_out>;
382}; 439};
383 440
441&spi0 {
442 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
443 pinctrl-names = "default";
444 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
445};
446
447&spi1 {
448 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
451};
452
384&uart0 { 453&uart0 {
385 pinctrl-names = "default"; 454 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>; 455 pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 7d59ff4de408..a76dd44adb53 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -26,7 +26,7 @@
26 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 26 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
27 27
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&hym8563_int>; 29 pinctrl-0 = <&pmic_int>;
30 30
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 clock-output-names = "xin32k"; 32 clock-output-names = "xin32k";
@@ -124,11 +124,3 @@
124 }; 124 };
125 }; 125 };
126}; 126};
127
128&pinctrl {
129 hym8563 {
130 hym8563_int: hym8563-int {
131 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 9a88b6c66396..ff522f8e3df4 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -16,3 +16,135 @@
16/ { 16/ {
17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; 17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
18}; 18};
19
20&i2c0 {
21 clock-frequency = <400000>;
22 status = "okay";
23
24 rk808: pmic@1b {
25 compatible = "rockchip,rk808";
26 reg = <0x1b>;
27 interrupt-parent = <&gpio0>;
28 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pmic_int>;
31 rockchip,system-power-controller;
32 wakeup-source;
33 #clock-cells = <1>;
34 clock-output-names = "xin32k", "rk808-clkout2";
35
36 vcc8-supply = <&vcc_18>;
37 vcc9-supply = <&vcc_io>;
38 vcc10-supply = <&vcc_io>;
39 vcc12-supply = <&vcc_io>;
40 vddio-supply = <&vccio_pmu>;
41
42 regulators {
43 vdd_cpu: DCDC_REG1 {
44 regulator-always-on;
45 regulator-boot-on;
46 regulator-min-microvolt = <750000>;
47 regulator-max-microvolt = <1300000>;
48 regulator-name = "vdd_arm";
49 };
50
51 vdd_gpu: DCDC_REG2 {
52 regulator-always-on;
53 regulator-boot-on;
54 regulator-min-microvolt = <850000>;
55 regulator-max-microvolt = <1250000>;
56 regulator-name = "vdd_gpu";
57 };
58
59 vcc_ddr: DCDC_REG3 {
60 regulator-always-on;
61 regulator-boot-on;
62 regulator-name = "vcc_ddr";
63 };
64
65 vcc_io: DCDC_REG4 {
66 regulator-always-on;
67 regulator-boot-on;
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 regulator-name = "vcc_io";
71 };
72
73 vccio_pmu: LDO_REG1 {
74 regulator-always-on;
75 regulator-boot-on;
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-name = "vccio_pmu";
79 };
80
81 vcc_tp: LDO_REG2 {
82 regulator-always-on;
83 regulator-boot-on;
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-name = "vcc_tp";
87 };
88
89 vdd_10: LDO_REG3 {
90 regulator-always-on;
91 regulator-boot-on;
92 regulator-min-microvolt = <1000000>;
93 regulator-max-microvolt = <1000000>;
94 regulator-name = "vdd_10";
95 };
96
97 vcc18_lcd: LDO_REG4 {
98 regulator-always-on;
99 regulator-boot-on;
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 regulator-name = "vcc18_lcd";
103 };
104
105 vccio_sd: LDO_REG5 {
106 regulator-always-on;
107 regulator-boot-on;
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <3300000>;
110 regulator-name = "vccio_sd";
111 };
112
113 vdd10_lcd: LDO_REG6 {
114 regulator-always-on;
115 regulator-boot-on;
116 regulator-min-microvolt = <1000000>;
117 regulator-max-microvolt = <1000000>;
118 regulator-name = "vdd10_lcd";
119 };
120
121 vcc_18: LDO_REG7 {
122 regulator-always-on;
123 regulator-boot-on;
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 regulator-name = "vcc_18";
127 };
128
129 vcca_codec: LDO_REG8 {
130 regulator-always-on;
131 regulator-boot-on;
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 regulator-name = "vcca_codec";
135 };
136
137 vcc_wl: SWITCH_REG1 {
138 regulator-always-on;
139 regulator-boot-on;
140 regulator-name = "vcc_wl";
141 };
142
143 vcc_lcd: SWITCH_REG2 {
144 regulator-always-on;
145 regulator-boot-on;
146 regulator-name = "vcc_lcd";
147 };
148 };
149 };
150};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4f572093c8b4..cb83cea52fa1 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -10,6 +10,7 @@
10 * GNU General Public License for more details. 10 * GNU General Public License for more details.
11 */ 11 */
12 12
13#include <dt-bindings/pwm/pwm.h>
13#include "rk3288.dtsi" 14#include "rk3288.dtsi"
14 15
15/ { 16/ {
@@ -17,6 +18,48 @@
17 reg = <0x0 0x80000000>; 18 reg = <0x0 0x80000000>;
18 }; 19 };
19 20
21 backlight {
22 compatible = "pwm-backlight";
23 brightness-levels = <
24 0 1 2 3 4 5 6 7
25 8 9 10 11 12 13 14 15
26 16 17 18 19 20 21 22 23
27 24 25 26 27 28 29 30 31
28 32 33 34 35 36 37 38 39
29 40 41 42 43 44 45 46 47
30 48 49 50 51 52 53 54 55
31 56 57 58 59 60 61 62 63
32 64 65 66 67 68 69 70 71
33 72 73 74 75 76 77 78 79
34 80 81 82 83 84 85 86 87
35 88 89 90 91 92 93 94 95
36 96 97 98 99 100 101 102 103
37 104 105 106 107 108 109 110 111
38 112 113 114 115 116 117 118 119
39 120 121 122 123 124 125 126 127
40 128 129 130 131 132 133 134 135
41 136 137 138 139 140 141 142 143
42 144 145 146 147 148 149 150 151
43 152 153 154 155 156 157 158 159
44 160 161 162 163 164 165 166 167
45 168 169 170 171 172 173 174 175
46 176 177 178 179 180 181 182 183
47 184 185 186 187 188 189 190 191
48 192 193 194 195 196 197 198 199
49 200 201 202 203 204 205 206 207
50 208 209 210 211 212 213 214 215
51 216 217 218 219 220 221 222 223
52 224 225 226 227 228 229 230 231
53 232 233 234 235 236 237 238 239
54 240 241 242 243 244 245 246 247
55 248 249 250 251 252 253 254 255>;
56 default-brightness-level = <128>;
57 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&bl_en>;
60 pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
61 };
62
20 gpio-keys { 63 gpio-keys {
21 compatible = "gpio-keys"; 64 compatible = "gpio-keys";
22 #address-cells = <1>; 65 #address-cells = <1>;
@@ -49,6 +92,30 @@
49 }; 92 };
50}; 93};
51 94
95&emmc {
96 broken-cd;
97 bus-width = <8>;
98 cap-mmc-highspeed;
99 disable-wp;
100 non-removable;
101 num-slots = <1>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
104 status = "okay";
105};
106
107&sdmmc {
108 bus-width = <4>;
109 cap-mmc-highspeed;
110 cap-sd-highspeed;
111 card-detect-delay = <200>;
112 disable-wp; /* wp not hooked up */
113 num-slots = <1>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
116 status = "okay";
117};
118
52&i2c0 { 119&i2c0 {
53 status = "okay"; 120 status = "okay";
54}; 121};
@@ -57,6 +124,10 @@
57 status = "okay"; 124 status = "okay";
58}; 125};
59 126
127&pwm0 {
128 status = "okay";
129};
130
60&uart0 { 131&uart0 {
61 status = "okay"; 132 status = "okay";
62}; 133};
@@ -78,12 +149,24 @@
78}; 149};
79 150
80&pinctrl { 151&pinctrl {
152 backlight {
153 bl_en: bl-en {
154 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
155 };
156 };
157
81 buttons { 158 buttons {
82 pwrbtn: pwrbtn { 159 pwrbtn: pwrbtn {
83 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; 160 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
84 }; 161 };
85 }; 162 };
86 163
164 pmic {
165 pmic_int: pmic-int {
166 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
167 };
168 };
169
87 usb { 170 usb {
88 host_vbus_drv: host-vbus-drv { 171 host_vbus_drv: host-vbus-drv {
89 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; 172 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -94,3 +177,7 @@
94&usb_host0_ehci { 177&usb_host0_ehci {
95 status = "okay"; 178 status = "okay";
96}; 179};
180
181&usb_host1 {
182 status = "okay";
183};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a53224..874e66dbb93b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -29,11 +29,18 @@
29 i2c3 = &i2c3; 29 i2c3 = &i2c3;
30 i2c4 = &i2c4; 30 i2c4 = &i2c4;
31 i2c5 = &i2c5; 31 i2c5 = &i2c5;
32 mshc0 = &emmc;
33 mshc1 = &sdmmc;
34 mshc2 = &sdio0;
35 mshc3 = &sdio1;
32 serial0 = &uart0; 36 serial0 = &uart0;
33 serial1 = &uart1; 37 serial1 = &uart1;
34 serial2 = &uart2; 38 serial2 = &uart2;
35 serial3 = &uart3; 39 serial3 = &uart3;
36 serial4 = &uart4; 40 serial4 = &uart4;
41 spi0 = &spi0;
42 spi1 = &spi1;
43 spi2 = &spi2;
37 }; 44 };
38 45
39 cpus { 46 cpus {
@@ -62,6 +69,44 @@
62 }; 69 };
63 }; 70 };
64 71
72 amba {
73 compatible = "arm,amba-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 dmac_peri: dma-controller@ff250000 {
79 compatible = "arm,pl330", "arm,primecell";
80 reg = <0xff250000 0x4000>;
81 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
83 #dma-cells = <1>;
84 clocks = <&cru ACLK_DMAC2>;
85 clock-names = "apb_pclk";
86 };
87
88 dmac_bus_ns: dma-controller@ff600000 {
89 compatible = "arm,pl330", "arm,primecell";
90 reg = <0xff600000 0x4000>;
91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
93 #dma-cells = <1>;
94 clocks = <&cru ACLK_DMAC1>;
95 clock-names = "apb_pclk";
96 status = "disabled";
97 };
98
99 dmac_bus_s: dma-controller@ffb20000 {
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0xffb20000 0x4000>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
104 #dma-cells = <1>;
105 clocks = <&cru ACLK_DMAC1>;
106 clock-names = "apb_pclk";
107 };
108 };
109
65 xin24m: oscillator { 110 xin24m: oscillator {
66 compatible = "fixed-clock"; 111 compatible = "fixed-clock";
67 clock-frequency = <24000000>; 112 clock-frequency = <24000000>;
@@ -78,6 +123,95 @@
78 clock-frequency = <24000000>; 123 clock-frequency = <24000000>;
79 }; 124 };
80 125
126 sdmmc: dwmmc@ff0c0000 {
127 compatible = "rockchip,rk3288-dw-mshc";
128 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
129 clock-names = "biu", "ciu";
130 fifo-depth = <0x100>;
131 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
132 reg = <0xff0c0000 0x4000>;
133 status = "disabled";
134 };
135
136 sdio0: dwmmc@ff0d0000 {
137 compatible = "rockchip,rk3288-dw-mshc";
138 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
139 clock-names = "biu", "ciu";
140 fifo-depth = <0x100>;
141 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
142 reg = <0xff0d0000 0x4000>;
143 status = "disabled";
144 };
145
146 sdio1: dwmmc@ff0e0000 {
147 compatible = "rockchip,rk3288-dw-mshc";
148 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
149 clock-names = "biu", "ciu";
150 fifo-depth = <0x100>;
151 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
152 reg = <0xff0e0000 0x4000>;
153 status = "disabled";
154 };
155
156 emmc: dwmmc@ff0f0000 {
157 compatible = "rockchip,rk3288-dw-mshc";
158 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
159 clock-names = "biu", "ciu";
160 fifo-depth = <0x100>;
161 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0xff0f0000 0x4000>;
163 status = "disabled";
164 };
165
166 saradc: saradc@ff100000 {
167 compatible = "rockchip,saradc";
168 reg = <0xff100000 0x100>;
169 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
170 #io-channel-cells = <1>;
171 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
172 clock-names = "saradc", "apb_pclk";
173 status = "disabled";
174 };
175
176 spi0: spi@ff110000 {
177 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
178 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
179 clock-names = "spiclk", "apb_pclk";
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
183 reg = <0xff110000 0x1000>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 status = "disabled";
187 };
188
189 spi1: spi@ff120000 {
190 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
191 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
192 clock-names = "spiclk", "apb_pclk";
193 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
196 reg = <0xff120000 0x1000>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 spi2: spi@ff130000 {
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
205 clock-names = "spiclk", "apb_pclk";
206 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
209 reg = <0xff130000 0x1000>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213 };
214
81 i2c1: i2c@ff140000 { 215 i2c1: i2c@ff140000 {
82 compatible = "rockchip,rk3288-i2c"; 216 compatible = "rockchip,rk3288-i2c";
83 reg = <0xff140000 0x1000>; 217 reg = <0xff140000 0x1000>;
@@ -206,6 +340,26 @@
206 340
207 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 341 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
208 342
343 usb_host1: usb@ff540000 {
344 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
345 "snps,dwc2";
346 reg = <0xff540000 0x40000>;
347 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_USBHOST1>;
349 clock-names = "otg";
350 status = "disabled";
351 };
352
353 usb_otg: usb@ff580000 {
354 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
355 "snps,dwc2";
356 reg = <0xff580000 0x40000>;
357 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&cru HCLK_OTG0>;
359 clock-names = "otg";
360 status = "disabled";
361 };
362
209 usb_hsic: usb@ff5c0000 { 363 usb_hsic: usb@ff5c0000 {
210 compatible = "generic-ehci"; 364 compatible = "generic-ehci";
211 reg = <0xff5c0000 0x100>; 365 reg = <0xff5c0000 0x100>;
@@ -241,6 +395,50 @@
241 status = "disabled"; 395 status = "disabled";
242 }; 396 };
243 397
398 pwm0: pwm@ff680000 {
399 compatible = "rockchip,rk3288-pwm";
400 reg = <0xff680000 0x10>;
401 #pwm-cells = <3>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm0_pin>;
404 clocks = <&cru PCLK_PWM>;
405 clock-names = "pwm";
406 status = "disabled";
407 };
408
409 pwm1: pwm@ff680010 {
410 compatible = "rockchip,rk3288-pwm";
411 reg = <0xff680010 0x10>;
412 #pwm-cells = <3>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm1_pin>;
415 clocks = <&cru PCLK_PWM>;
416 clock-names = "pwm";
417 status = "disabled";
418 };
419
420 pwm2: pwm@ff680020 {
421 compatible = "rockchip,rk3288-pwm";
422 reg = <0xff680020 0x10>;
423 #pwm-cells = <3>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm2_pin>;
426 clocks = <&cru PCLK_PWM>;
427 clock-names = "pwm";
428 status = "disabled";
429 };
430
431 pwm3: pwm@ff680030 {
432 compatible = "rockchip,rk3288-pwm";
433 reg = <0xff680030 0x10>;
434 #pwm-cells = <2>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 clocks = <&cru PCLK_PWM>;
438 clock-names = "pwm";
439 status = "disabled";
440 };
441
244 pmu: power-management@ff730000 { 442 pmu: power-management@ff730000 {
245 compatible = "rockchip,rk3288-pmu", "syscon"; 443 compatible = "rockchip,rk3288-pmu", "syscon";
246 reg = <0xff730000 0x100>; 444 reg = <0xff730000 0x100>;
@@ -271,6 +469,21 @@
271 status = "disabled"; 469 status = "disabled";
272 }; 470 };
273 471
472 i2s: i2s@ff890000 {
473 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
474 reg = <0xff890000 0x10000>;
475 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
479 dma-names = "tx", "rx";
480 clock-names = "i2s_hclk", "i2s_clk";
481 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&i2s0_bus>;
484 status = "disabled";
485 };
486
274 gic: interrupt-controller@ffc01000 { 487 gic: interrupt-controller@ffc01000 {
275 compatible = "arm,gic-400"; 488 compatible = "arm,gic-400";
276 interrupt-controller; 489 interrupt-controller;
@@ -463,6 +676,17 @@
463 }; 676 };
464 }; 677 };
465 678
679 i2s0 {
680 i2s0_bus: i2s0-bus {
681 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
682 <6 1 RK_FUNC_1 &pcfg_pull_none>,
683 <6 2 RK_FUNC_1 &pcfg_pull_none>,
684 <6 3 RK_FUNC_1 &pcfg_pull_none>,
685 <6 4 RK_FUNC_1 &pcfg_pull_none>,
686 <6 8 RK_FUNC_1 &pcfg_pull_none>;
687 };
688 };
689
466 sdmmc { 690 sdmmc {
467 sdmmc_clk: sdmmc-clk { 691 sdmmc_clk: sdmmc-clk {
468 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 692 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
@@ -488,6 +712,88 @@
488 }; 712 };
489 }; 713 };
490 714
715 sdio0 {
716 sdio0_bus1: sdio0-bus1 {
717 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
718 };
719
720 sdio0_bus4: sdio0-bus4 {
721 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
722 <4 21 RK_FUNC_1 &pcfg_pull_up>,
723 <4 22 RK_FUNC_1 &pcfg_pull_up>,
724 <4 23 RK_FUNC_1 &pcfg_pull_up>;
725 };
726
727 sdio0_cmd: sdio0-cmd {
728 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
729 };
730
731 sdio0_clk: sdio0-clk {
732 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
733 };
734
735 sdio0_cd: sdio0-cd {
736 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
737 };
738
739 sdio0_wp: sdio0-wp {
740 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
741 };
742
743 sdio0_pwr: sdio0-pwr {
744 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
745 };
746
747 sdio0_bkpwr: sdio0-bkpwr {
748 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
749 };
750
751 sdio0_int: sdio0-int {
752 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
753 };
754 };
755
756 sdio1 {
757 sdio1_bus1: sdio1-bus1 {
758 rockchip,pins = <3 24 4 &pcfg_pull_up>;
759 };
760
761 sdio1_bus4: sdio1-bus4 {
762 rockchip,pins = <3 24 4 &pcfg_pull_up>,
763 <3 25 4 &pcfg_pull_up>,
764 <3 26 4 &pcfg_pull_up>,
765 <3 27 4 &pcfg_pull_up>;
766 };
767
768 sdio1_cd: sdio1-cd {
769 rockchip,pins = <3 28 4 &pcfg_pull_up>;
770 };
771
772 sdio1_wp: sdio1-wp {
773 rockchip,pins = <3 29 4 &pcfg_pull_up>;
774 };
775
776 sdio1_bkpwr: sdio1-bkpwr {
777 rockchip,pins = <3 30 4 &pcfg_pull_up>;
778 };
779
780 sdio1_int: sdio1-int {
781 rockchip,pins = <3 31 4 &pcfg_pull_up>;
782 };
783
784 sdio1_cmd: sdio1-cmd {
785 rockchip,pins = <4 6 4 &pcfg_pull_up>;
786 };
787
788 sdio1_clk: sdio1-clk {
789 rockchip,pins = <4 7 4 &pcfg_pull_none>;
790 };
791
792 sdio1_pwr: sdio1-pwr {
793 rockchip,pins = <4 9 4 &pcfg_pull_up>;
794 };
795 };
796
491 emmc { 797 emmc {
492 emmc_clk: emmc-clk { 798 emmc_clk: emmc-clk {
493 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 799 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
@@ -524,6 +830,56 @@
524 }; 830 };
525 }; 831 };
526 832
833 spi0 {
834 spi0_clk: spi0-clk {
835 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
836 };
837 spi0_cs0: spi0-cs0 {
838 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
839 };
840 spi0_tx: spi0-tx {
841 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
842 };
843 spi0_rx: spi0-rx {
844 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
845 };
846 spi0_cs1: spi0-cs1 {
847 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
848 };
849 };
850 spi1 {
851 spi1_clk: spi1-clk {
852 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
853 };
854 spi1_cs0: spi1-cs0 {
855 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
856 };
857 spi1_rx: spi1-rx {
858 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
859 };
860 spi1_tx: spi1-tx {
861 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
862 };
863 };
864
865 spi2 {
866 spi2_cs1: spi2-cs1 {
867 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
868 };
869 spi2_clk: spi2-clk {
870 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
871 };
872 spi2_cs0: spi2-cs0 {
873 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
874 };
875 spi2_rx: spi2-rx {
876 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
877 };
878 spi2_tx: spi2-tx {
879 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
880 };
881 };
882
527 uart0 { 883 uart0 {
528 uart0_xfer: uart0-xfer { 884 uart0_xfer: uart0-xfer {
529 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 885 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
@@ -591,5 +947,29 @@
591 rockchip,pins = <5 15 3 &pcfg_pull_none>; 947 rockchip,pins = <5 15 3 &pcfg_pull_none>;
592 }; 948 };
593 }; 949 };
950
951 pwm0 {
952 pwm0_pin: pwm0-pin {
953 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
954 };
955 };
956
957 pwm1 {
958 pwm1_pin: pwm1-pin {
959 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
960 };
961 };
962
963 pwm2 {
964 pwm2_pin: pwm2-pin {
965 rockchip,pins = <7 22 3 &pcfg_pull_none>;
966 };
967 };
968
969 pwm3 {
970 pwm3_pin: pwm3-pin {
971 rockchip,pins = <7 23 3 &pcfg_pull_none>;
972 };
973 };
594 }; 974 };
595}; 975};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8caf85d83901..7332d12eb565 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,49 @@
26 i2c2 = &i2c2; 26 i2c2 = &i2c2;
27 i2c3 = &i2c3; 27 i2c3 = &i2c3;
28 i2c4 = &i2c4; 28 i2c4 = &i2c4;
29 mshc0 = &emmc;
30 mshc1 = &mmc0;
31 mshc2 = &mmc1;
32 spi0 = &spi0;
33 spi1 = &spi1;
34 };
35
36 amba {
37 compatible = "arm,amba-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41
42 dmac1_s: dma-controller@20018000 {
43 compatible = "arm,pl330", "arm,primecell";
44 reg = <0x20018000 0x4000>;
45 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
47 #dma-cells = <1>;
48 clocks = <&cru ACLK_DMA1>;
49 clock-names = "apb_pclk";
50 };
51
52 dmac1_ns: dma-controller@2001c000 {
53 compatible = "arm,pl330", "arm,primecell";
54 reg = <0x2001c000 0x4000>;
55 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
57 #dma-cells = <1>;
58 clocks = <&cru ACLK_DMA1>;
59 clock-names = "apb_pclk";
60 status = "disabled";
61 };
62
63 dmac2: dma-controller@20078000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
68 #dma-cells = <1>;
69 clocks = <&cru ACLK_DMA2>;
70 clock-names = "apb_pclk";
71 };
29 }; 72 };
30 73
31 xin24m: oscillator { 74 xin24m: oscillator {
@@ -91,12 +134,28 @@
91 status = "disabled"; 134 status = "disabled";
92 }; 135 };
93 136
137 usb_otg: usb@10180000 {
138 compatible = "rockchip,rk3066-usb", "snps,dwc2";
139 reg = <0x10180000 0x40000>;
140 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cru HCLK_OTG0>;
142 clock-names = "otg";
143 status = "disabled";
144 };
145
146 usb_host: usb@101c0000 {
147 compatible = "snps,dwc2";
148 reg = <0x101c0000 0x40000>;
149 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&cru HCLK_OTG1>;
151 clock-names = "otg";
152 status = "disabled";
153 };
154
94 mmc0: dwmmc@10214000 { 155 mmc0: dwmmc@10214000 {
95 compatible = "rockchip,rk2928-dw-mshc"; 156 compatible = "rockchip,rk2928-dw-mshc";
96 reg = <0x10214000 0x1000>; 157 reg = <0x10214000 0x1000>;
97 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 159
101 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 160 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
102 clock-names = "biu", "ciu"; 161 clock-names = "biu", "ciu";
@@ -108,8 +167,6 @@
108 compatible = "rockchip,rk2928-dw-mshc"; 167 compatible = "rockchip,rk2928-dw-mshc";
109 reg = <0x10218000 0x1000>; 168 reg = <0x10218000 0x1000>;
110 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 169 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 170
114 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 171 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
115 clock-names = "biu", "ciu"; 172 clock-names = "biu", "ciu";
@@ -117,6 +174,17 @@
117 status = "disabled"; 174 status = "disabled";
118 }; 175 };
119 176
177 emmc: dwmmc@1021c000 {
178 compatible = "rockchip,rk2928-dw-mshc";
179 reg = <0x1021c000 0x1000>;
180 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
181
182 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
183 clock-names = "biu", "ciu";
184
185 status = "disabled";
186 };
187
120 pmu: pmu@20004000 { 188 pmu: pmu@20004000 {
121 compatible = "rockchip,rk3066-pmu", "syscon"; 189 compatible = "rockchip,rk3066-pmu", "syscon";
122 reg = <0x20004000 0x100>; 190 reg = <0x20004000 0x100>;
@@ -135,7 +203,6 @@
135 #size-cells = <0>; 203 #size-cells = <0>;
136 204
137 rockchip,grf = <&grf>; 205 rockchip,grf = <&grf>;
138 rockchip,bus-index = <0>;
139 206
140 clock-names = "i2c"; 207 clock-names = "i2c";
141 clocks = <&cru PCLK_I2C0>; 208 clocks = <&cru PCLK_I2C0>;
@@ -264,4 +331,36 @@
264 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 331 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
265 status = "disabled"; 332 status = "disabled";
266 }; 333 };
334
335 saradc: saradc@2006c000 {
336 compatible = "rockchip,saradc";
337 reg = <0x2006c000 0x100>;
338 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
339 #io-channel-cells = <1>;
340 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
341 clock-names = "saradc", "apb_pclk";
342 status = "disabled";
343 };
344
345 spi0: spi@20070000 {
346 compatible = "rockchip,rk3066-spi";
347 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
348 clock-names = "spiclk", "apb_pclk";
349 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
350 reg = <0x20070000 0x1000>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 status = "disabled";
354 };
355
356 spi1: spi@20074000 {
357 compatible = "rockchip,rk3066-spi";
358 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
359 clock-names = "spiclk", "apb_pclk";
360 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
361 reg = <0x20074000 0x1000>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 status = "disabled";
365 };
267}; 366};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 45013b867c8d..5f4144d1e3a1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -177,6 +177,9 @@
177 compatible = "atmel,at91sam9260-usart"; 177 compatible = "atmel,at91sam9260-usart";
178 reg = <0xf001c000 0x100>; 178 reg = <0xf001c000 0x100>;
179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
180 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
181 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
182 dma-names = "tx", "rx";
180 pinctrl-names = "default"; 183 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usart0>; 184 pinctrl-0 = <&pinctrl_usart0>;
182 clocks = <&usart0_clk>; 185 clocks = <&usart0_clk>;
@@ -188,6 +191,9 @@
188 compatible = "atmel,at91sam9260-usart"; 191 compatible = "atmel,at91sam9260-usart";
189 reg = <0xf0020000 0x100>; 192 reg = <0xf0020000 0x100>;
190 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 193 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
194 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
195 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
196 dma-names = "tx", "rx";
191 pinctrl-names = "default"; 197 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usart1>; 198 pinctrl-0 = <&pinctrl_usart1>;
193 clocks = <&usart1_clk>; 199 clocks = <&usart1_clk>;
@@ -333,6 +339,9 @@
333 compatible = "atmel,at91sam9260-usart"; 339 compatible = "atmel,at91sam9260-usart";
334 reg = <0xf8020000 0x100>; 340 reg = <0xf8020000 0x100>;
335 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 341 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
342 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
343 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
344 dma-names = "tx", "rx";
336 pinctrl-names = "default"; 345 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usart2>; 346 pinctrl-0 = <&pinctrl_usart2>;
338 clocks = <&usart2_clk>; 347 clocks = <&usart2_clk>;
@@ -344,6 +353,9 @@
344 compatible = "atmel,at91sam9260-usart"; 353 compatible = "atmel,at91sam9260-usart";
345 reg = <0xf8024000 0x100>; 354 reg = <0xf8024000 0x100>;
346 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 355 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
357 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
358 dma-names = "tx", "rx";
347 pinctrl-names = "default"; 359 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_usart3>; 360 pinctrl-0 = <&pinctrl_usart3>;
349 clocks = <&usart3_clk>; 361 clocks = <&usart3_clk>;
@@ -402,14 +414,19 @@
402 }; 414 };
403 415
404 ramc0: ramc@ffffea00 { 416 ramc0: ramc@ffffea00 {
405 compatible = "atmel,at91sam9g45-ddramc"; 417 compatible = "atmel,sama5d3-ddramc";
406 reg = <0xffffea00 0x200>; 418 reg = <0xffffea00 0x200>;
419 clocks = <&ddrck>, <&mpddr_clk>;
420 clock-names = "ddrck", "mpddr";
407 }; 421 };
408 422
409 dbgu: serial@ffffee00 { 423 dbgu: serial@ffffee00 {
410 compatible = "atmel,at91sam9260-usart"; 424 compatible = "atmel,at91sam9260-usart";
411 reg = <0xffffee00 0x200>; 425 reg = <0xffffee00 0x200>;
412 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 426 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
427 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
428 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
429 dma-names = "tx", "rx";
413 pinctrl-names = "default"; 430 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_dbgu>; 431 pinctrl-0 = <&pinctrl_dbgu>;
415 clocks = <&dbgu_clk>; 432 clocks = <&dbgu_clk>;
@@ -428,7 +445,7 @@
428 pinctrl@fffff200 { 445 pinctrl@fffff200 {
429 #address-cells = <1>; 446 #address-cells = <1>;
430 #size-cells = <1>; 447 #size-cells = <1>;
431 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 448 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
432 ranges = <0xfffff200 0xfffff200 0xa00>; 449 ranges = <0xfffff200 0xfffff200 0xa00>;
433 atmel,mux-mask = < 450 atmel,mux-mask = <
434 /* A B C */ 451 /* A B C */
@@ -1003,6 +1020,11 @@
1003 reg = <2>; 1020 reg = <2>;
1004 }; 1021 };
1005 1022
1023 hsmc_clk: hsmc_clk {
1024 #clock-cells = <0>;
1025 reg = <5>;
1026 };
1027
1006 pioA_clk: pioA_clk { 1028 pioA_clk: pioA_clk {
1007 #clock-cells = <0>; 1029 #clock-cells = <0>;
1008 reg = <6>; 1030 reg = <6>;
@@ -1170,6 +1192,11 @@
1170 #clock-cells = <0>; 1192 #clock-cells = <0>;
1171 reg = <48>; 1193 reg = <48>;
1172 }; 1194 };
1195
1196 mpddr_clk: mpddr_clk {
1197 #clock-cells = <0>;
1198 reg = <49>;
1199 };
1173 }; 1200 };
1174 }; 1201 };
1175 1202
@@ -1178,6 +1205,11 @@
1178 reg = <0xfffffe00 0x10>; 1205 reg = <0xfffffe00 0x10>;
1179 }; 1206 };
1180 1207
1208 shutdown-controller@fffffe10 {
1209 compatible = "atmel,at91sam9x5-shdwc";
1210 reg = <0xfffffe10 0x10>;
1211 };
1212
1181 pit: timer@fffffe30 { 1213 pit: timer@fffffe30 {
1182 compatible = "atmel,at91sam9260-pit"; 1214 compatible = "atmel,at91sam9260-pit";
1183 reg = <0xfffffe30 0xf>; 1215 reg = <0xfffffe30 0xf>;
@@ -1393,6 +1425,7 @@
1393 0xffffc000 0x00000070 /* NFC HSMC regs */ 1425 0xffffc000 0x00000070 /* NFC HSMC regs */
1394 0x00200000 0x00100000 /* NFC SRAM banks */ 1426 0x00200000 0x00100000 /* NFC SRAM banks */
1395 >; 1427 >;
1428 clocks = <&hsmc_clk>;
1396 }; 1429 };
1397 }; 1430 };
1398 }; 1431 };
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index a0775851cce5..eaf41451ad0c 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -40,7 +40,7 @@
40 atmel,clk-output-range = <0 66000000>; 40 atmel,clk-output-range = <0 66000000>;
41 }; 41 };
42 42
43 can1_clk: can0_clk { 43 can1_clk: can1_clk {
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 reg = <41>; 45 reg = <41>;
46 atmel,clk-output-range = <0 66000000>; 46 atmel,clk-output-range = <0 66000000>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f7d8583eef82..962dc28dc37b 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -36,6 +36,36 @@
36 36
37 macb0: ethernet@f0028000 { 37 macb0: ethernet@f0028000 {
38 phy-mode = "rgmii"; 38 phy-mode = "rgmii";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ethernet-phy@1 {
43 reg = <0x1>;
44 interrupt-parent = <&pioB>;
45 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
46 txen-skew-ps = <800>;
47 txc-skew-ps = <3000>;
48 rxdv-skew-ps = <400>;
49 rxc-skew-ps = <3000>;
50 rxd0-skew-ps = <400>;
51 rxd1-skew-ps = <400>;
52 rxd2-skew-ps = <400>;
53 rxd3-skew-ps = <400>;
54 };
55
56 ethernet-phy@7 {
57 reg = <0x7>;
58 interrupt-parent = <&pioB>;
59 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
60 txen-skew-ps = <800>;
61 txc-skew-ps = <3000>;
62 rxdv-skew-ps = <400>;
63 rxc-skew-ps = <3000>;
64 rxd0-skew-ps = <400>;
65 rxd1-skew-ps = <400>;
66 rxd2-skew-ps = <400>;
67 rxd3-skew-ps = <400>;
68 };
39 }; 69 };
40 70
41 pmc: pmc@fffffc00 { 71 pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index b8c6f20e780c..49c10d33df30 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -25,6 +25,8 @@
25 }; 25 };
26 26
27 spi0: spi@f0004000 { 27 spi0: spi@f0004000 {
28 dmas = <0>, <0>; /* Do not use DMA for spi0 */
29
28 m25p80@0 { 30 m25p80@0 {
29 compatible = "atmel,at25df321a"; 31 compatible = "atmel,at25df321a";
30 spi-max-frequency = <50000000>; 32 spi-max-frequency = <50000000>;
@@ -51,6 +53,7 @@
51 }; 53 };
52 54
53 usart1: serial@f0020000 { 55 usart1: serial@f0020000 {
56 dmas = <0>, <0>; /* Do not use DMA for usart1 */
54 pinctrl-names = "default"; 57 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; 58 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
56 status = "okay"; 59 status = "okay";
@@ -132,6 +135,7 @@
132 }; 135 };
133 136
134 dbgu: serial@ffffee00 { 137 dbgu: serial@ffffee00 {
138 dmas = <0>, <0>; /* Do not use DMA for dbgu */
135 status = "okay"; 139 status = "okay";
136 }; 140 };
137 141
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 99659db97e89..30ef97e99dc5 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -66,7 +66,7 @@
66 }; 66 };
67 67
68 vmmc_sdhi0: regulator@2 { 68 vmmc_sdhi0: regulator@2 {
69 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
70 regulator-name = "SDHI0 Vcc"; 70 regulator-name = "SDHI0 Vcc";
71 regulator-min-microvolt = <3300000>; 71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>;
@@ -75,7 +75,7 @@
75 }; 75 };
76 76
77 vmmc_sdhi2: regulator@3 { 77 vmmc_sdhi2: regulator@3 {
78 compatible = "regulator-fixed"; 78 compatible = "regulator-fixed";
79 regulator-name = "SDHI2 Vcc"; 79 regulator-name = "SDHI2 Vcc";
80 regulator-min-microvolt = <3300000>; 80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index d7f52cf31350..030a5920312f 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -14,6 +14,7 @@
14 14
15/ { 15/ {
16 compatible = "renesas,sh73a0"; 16 compatible = "renesas,sh73a0";
17 interrupt-parent = <&gic>;
17 18
18 cpus { 19 cpus {
19 #address-cells = <1>; 20 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 <0xe6900020 1>, 67 <0xe6900020 1>,
67 <0xe6900040 1>, 68 <0xe6900040 1>,
68 <0xe6900060 1>; 69 <0xe6900060 1>;
69 interrupt-parent = <&gic>;
70 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH 70 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
71 0 2 IRQ_TYPE_LEVEL_HIGH 71 0 2 IRQ_TYPE_LEVEL_HIGH
72 0 3 IRQ_TYPE_LEVEL_HIGH 72 0 3 IRQ_TYPE_LEVEL_HIGH
@@ -86,7 +86,6 @@
86 <0xe6900024 1>, 86 <0xe6900024 1>,
87 <0xe6900044 1>, 87 <0xe6900044 1>,
88 <0xe6900064 1>; 88 <0xe6900064 1>;
89 interrupt-parent = <&gic>;
90 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH 89 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
91 0 10 IRQ_TYPE_LEVEL_HIGH 90 0 10 IRQ_TYPE_LEVEL_HIGH
92 0 11 IRQ_TYPE_LEVEL_HIGH 91 0 11 IRQ_TYPE_LEVEL_HIGH
@@ -107,7 +106,6 @@
107 <0xe6900028 1>, 106 <0xe6900028 1>,
108 <0xe6900048 1>, 107 <0xe6900048 1>,
109 <0xe6900068 1>; 108 <0xe6900068 1>;
110 interrupt-parent = <&gic>;
111 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH 109 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
112 0 18 IRQ_TYPE_LEVEL_HIGH 110 0 18 IRQ_TYPE_LEVEL_HIGH
113 0 19 IRQ_TYPE_LEVEL_HIGH 111 0 19 IRQ_TYPE_LEVEL_HIGH
@@ -127,7 +125,6 @@
127 <0xe690002c 1>, 125 <0xe690002c 1>,
128 <0xe690004c 1>, 126 <0xe690004c 1>,
129 <0xe690006c 1>; 127 <0xe690006c 1>;
130 interrupt-parent = <&gic>;
131 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH 128 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
132 0 26 IRQ_TYPE_LEVEL_HIGH 129 0 26 IRQ_TYPE_LEVEL_HIGH
133 0 27 IRQ_TYPE_LEVEL_HIGH 130 0 27 IRQ_TYPE_LEVEL_HIGH
@@ -143,7 +140,6 @@
143 #size-cells = <0>; 140 #size-cells = <0>;
144 compatible = "renesas,rmobile-iic"; 141 compatible = "renesas,rmobile-iic";
145 reg = <0xe6820000 0x425>; 142 reg = <0xe6820000 0x425>;
146 interrupt-parent = <&gic>;
147 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
148 0 168 IRQ_TYPE_LEVEL_HIGH 144 0 168 IRQ_TYPE_LEVEL_HIGH
149 0 169 IRQ_TYPE_LEVEL_HIGH 145 0 169 IRQ_TYPE_LEVEL_HIGH
@@ -156,7 +152,6 @@
156 #size-cells = <0>; 152 #size-cells = <0>;
157 compatible = "renesas,rmobile-iic"; 153 compatible = "renesas,rmobile-iic";
158 reg = <0xe6822000 0x425>; 154 reg = <0xe6822000 0x425>;
159 interrupt-parent = <&gic>;
160 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
161 0 52 IRQ_TYPE_LEVEL_HIGH 156 0 52 IRQ_TYPE_LEVEL_HIGH
162 0 53 IRQ_TYPE_LEVEL_HIGH 157 0 53 IRQ_TYPE_LEVEL_HIGH
@@ -169,7 +164,6 @@
169 #size-cells = <0>; 164 #size-cells = <0>;
170 compatible = "renesas,rmobile-iic"; 165 compatible = "renesas,rmobile-iic";
171 reg = <0xe6824000 0x425>; 166 reg = <0xe6824000 0x425>;
172 interrupt-parent = <&gic>;
173 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
174 0 172 IRQ_TYPE_LEVEL_HIGH 168 0 172 IRQ_TYPE_LEVEL_HIGH
175 0 173 IRQ_TYPE_LEVEL_HIGH 169 0 173 IRQ_TYPE_LEVEL_HIGH
@@ -182,7 +176,6 @@
182 #size-cells = <0>; 176 #size-cells = <0>;
183 compatible = "renesas,rmobile-iic"; 177 compatible = "renesas,rmobile-iic";
184 reg = <0xe6826000 0x425>; 178 reg = <0xe6826000 0x425>;
185 interrupt-parent = <&gic>;
186 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
187 0 184 IRQ_TYPE_LEVEL_HIGH 180 0 184 IRQ_TYPE_LEVEL_HIGH
188 0 185 IRQ_TYPE_LEVEL_HIGH 181 0 185 IRQ_TYPE_LEVEL_HIGH
@@ -195,7 +188,6 @@
195 #size-cells = <0>; 188 #size-cells = <0>;
196 compatible = "renesas,rmobile-iic"; 189 compatible = "renesas,rmobile-iic";
197 reg = <0xe6828000 0x425>; 190 reg = <0xe6828000 0x425>;
198 interrupt-parent = <&gic>;
199 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
200 0 188 IRQ_TYPE_LEVEL_HIGH 192 0 188 IRQ_TYPE_LEVEL_HIGH
201 0 189 IRQ_TYPE_LEVEL_HIGH 193 0 189 IRQ_TYPE_LEVEL_HIGH
@@ -206,7 +198,6 @@
206 mmcif: mmc@e6bd0000 { 198 mmcif: mmc@e6bd0000 {
207 compatible = "renesas,sh-mmcif"; 199 compatible = "renesas,sh-mmcif";
208 reg = <0xe6bd0000 0x100>; 200 reg = <0xe6bd0000 0x100>;
209 interrupt-parent = <&gic>;
210 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 201 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
211 0 141 IRQ_TYPE_LEVEL_HIGH>; 202 0 141 IRQ_TYPE_LEVEL_HIGH>;
212 reg-io-width = <4>; 203 reg-io-width = <4>;
@@ -216,7 +207,6 @@
216 sdhi0: sd@ee100000 { 207 sdhi0: sd@ee100000 {
217 compatible = "renesas,sdhi-sh73a0"; 208 compatible = "renesas,sdhi-sh73a0";
218 reg = <0xee100000 0x100>; 209 reg = <0xee100000 0x100>;
219 interrupt-parent = <&gic>;
220 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 210 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
221 0 84 IRQ_TYPE_LEVEL_HIGH 211 0 84 IRQ_TYPE_LEVEL_HIGH
222 0 85 IRQ_TYPE_LEVEL_HIGH>; 212 0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -228,7 +218,6 @@
228 sdhi1: sd@ee120000 { 218 sdhi1: sd@ee120000 {
229 compatible = "renesas,sdhi-sh73a0"; 219 compatible = "renesas,sdhi-sh73a0";
230 reg = <0xee120000 0x100>; 220 reg = <0xee120000 0x100>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 221 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
233 0 89 IRQ_TYPE_LEVEL_HIGH>; 222 0 89 IRQ_TYPE_LEVEL_HIGH>;
234 toshiba,mmc-wrprotect-disable; 223 toshiba,mmc-wrprotect-disable;
@@ -239,7 +228,6 @@
239 sdhi2: sd@ee140000 { 228 sdhi2: sd@ee140000 {
240 compatible = "renesas,sdhi-sh73a0"; 229 compatible = "renesas,sdhi-sh73a0";
241 reg = <0xee140000 0x100>; 230 reg = <0xee140000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 231 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
244 0 105 IRQ_TYPE_LEVEL_HIGH>; 232 0 105 IRQ_TYPE_LEVEL_HIGH>;
245 toshiba,mmc-wrprotect-disable; 233 toshiba,mmc-wrprotect-disable;
@@ -250,7 +238,6 @@
250 scifa0: serial@e6c40000 { 238 scifa0: serial@e6c40000 {
251 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 239 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
252 reg = <0xe6c40000 0x100>; 240 reg = <0xe6c40000 0x100>;
253 interrupt-parent = <&gic>;
254 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
255 status = "disabled"; 242 status = "disabled";
256 }; 243 };
@@ -258,7 +245,6 @@
258 scifa1: serial@e6c50000 { 245 scifa1: serial@e6c50000 {
259 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 246 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
260 reg = <0xe6c50000 0x100>; 247 reg = <0xe6c50000 0x100>;
261 interrupt-parent = <&gic>;
262 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 248 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled"; 249 status = "disabled";
264 }; 250 };
@@ -266,7 +252,6 @@
266 scifa2: serial@e6c60000 { 252 scifa2: serial@e6c60000 {
267 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 253 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
268 reg = <0xe6c60000 0x100>; 254 reg = <0xe6c60000 0x100>;
269 interrupt-parent = <&gic>;
270 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
271 status = "disabled"; 256 status = "disabled";
272 }; 257 };
@@ -274,7 +259,6 @@
274 scifa3: serial@e6c70000 { 259 scifa3: serial@e6c70000 {
275 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 260 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
276 reg = <0xe6c70000 0x100>; 261 reg = <0xe6c70000 0x100>;
277 interrupt-parent = <&gic>;
278 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
279 status = "disabled"; 263 status = "disabled";
280 }; 264 };
@@ -282,7 +266,6 @@
282 scifa4: serial@e6c80000 { 266 scifa4: serial@e6c80000 {
283 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 267 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
284 reg = <0xe6c80000 0x100>; 268 reg = <0xe6c80000 0x100>;
285 interrupt-parent = <&gic>;
286 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 269 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
287 status = "disabled"; 270 status = "disabled";
288 }; 271 };
@@ -290,7 +273,6 @@
290 scifa5: serial@e6cb0000 { 273 scifa5: serial@e6cb0000 {
291 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 274 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
292 reg = <0xe6cb0000 0x100>; 275 reg = <0xe6cb0000 0x100>;
293 interrupt-parent = <&gic>;
294 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 276 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
295 status = "disabled"; 277 status = "disabled";
296 }; 278 };
@@ -298,7 +280,6 @@
298 scifa6: serial@e6cc0000 { 280 scifa6: serial@e6cc0000 {
299 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 281 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
300 reg = <0xe6cc0000 0x100>; 282 reg = <0xe6cc0000 0x100>;
301 interrupt-parent = <&gic>;
302 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 283 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
303 status = "disabled"; 284 status = "disabled";
304 }; 285 };
@@ -306,7 +287,6 @@
306 scifa7: serial@e6cd0000 { 287 scifa7: serial@e6cd0000 {
307 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 288 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
308 reg = <0xe6cd0000 0x100>; 289 reg = <0xe6cd0000 0x100>;
309 interrupt-parent = <&gic>;
310 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 290 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
311 status = "disabled"; 291 status = "disabled";
312 }; 292 };
@@ -314,7 +294,6 @@
314 scifb8: serial@e6c30000 { 294 scifb8: serial@e6c30000 {
315 compatible = "renesas,scifb-sh73a0", "renesas,scifb"; 295 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
316 reg = <0xe6c30000 0x100>; 296 reg = <0xe6c30000 0x100>;
317 interrupt-parent = <&gic>;
318 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
319 status = "disabled"; 298 status = "disabled";
320 }; 299 };
@@ -340,7 +319,6 @@
340 #sound-dai-cells = <1>; 319 #sound-dai-cells = <1>;
341 compatible = "renesas,sh_fsi2"; 320 compatible = "renesas,sh_fsi2";
342 reg = <0xec230000 0x400>; 321 reg = <0xec230000 0x400>;
343 interrupt-parent = <&gic>;
344 interrupts = <0 146 0x4>; 322 interrupts = <0 146 0x4>;
345 status = "disabled"; 323 status = "disabled";
346 }; 324 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4d77ad690ed5..45fce2cf6fed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -607,6 +607,17 @@
607 }; 607 };
608 }; 608 };
609 609
610 sdr: sdr@ffc25000 {
611 compatible = "syscon";
612 reg = <0xffc25000 0x1000>;
613 };
614
615 sdramedac {
616 compatible = "altr,sdram-edac";
617 altr,sdr-syscon = <&sdr>;
618 interrupts = <0 39 4>;
619 };
620
610 L2: l2-cache@fffef000 { 621 L2: l2-cache@fffef000 {
611 compatible = "arm,pl310-cache"; 622 compatible = "arm,pl310-cache";
612 reg = <0xfffef000 0x1000>; 623 reg = <0xfffef000 0x1000>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2ccaf5b..03e8268ae219 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -15,6 +15,8 @@
15 */ 15 */
16 16
17/dts-v1/; 17/dts-v1/;
18/* First 4KB has trampoline code for secondary cores. */
19/memreserve/ 0x00000000 0x0001000;
18#include "socfpga.dtsi" 20#include "socfpga.dtsi"
19 21
20/ { 22/ {
@@ -29,13 +31,10 @@
29 31
30 dwmmc0@ff704000 { 32 dwmmc0@ff704000 {
31 num-slots = <1>; 33 num-slots = <1>;
32 supports-highspeed;
33 broken-cd; 34 broken-cd;
34 35 bus-width = <4>;
35 slot@0 { 36 cap-mmc-highspeed;
36 reg = <0>; 37 cap-sd-highspeed;
37 bus-width = <4>;
38 };
39 }; 38 };
40 39
41 sysmgr@ffd08000 { 40 sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index d532d171e391..27d551c384d0 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,13 +37,6 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 aliases {
42 /* this allow the ethaddr uboot environmnet variable contents
43 * to be added to the gmac1 device tree blob.
44 */
45 ethernet0 = &gmac1;
46 };
47}; 40};
48 41
49&gmac1 { 42&gmac1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf511828729f..28c05e7a31c9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -16,6 +16,8 @@
16 */ 16 */
17 17
18/dts-v1/; 18/dts-v1/;
19/* First 4KB has trampoline code for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
19#include "socfpga.dtsi" 21#include "socfpga.dtsi"
20 22
21/ { 23/ {
@@ -28,15 +30,12 @@
28 }; 30 };
29 }; 31 };
30 32
31 dwmmc0@ff704000 { 33 mmc0: dwmmc0@ff704000 {
32 num-slots = <1>; 34 num-slots = <1>;
33 supports-highspeed;
34 broken-cd; 35 broken-cd;
35 36 bus-width = <4>;
36 slot@0 { 37 cap-mmc-highspeed;
37 reg = <0>; 38 cap-sd-highspeed;
38 bus-width = <4>;
39 };
40 }; 39 };
41 40
42 ethernet@ff702000 { 41 ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 45de1514af0a..d7296a5f750c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -68,6 +68,10 @@
68 }; 68 };
69}; 69};
70 70
71&mmc0 {
72 cd-gpios = <&gpio1 18 0>;
73};
74
71&usb1 { 75&usb1 {
72 status = "okay"; 76 status = "okay";
73}; 77};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b411110..f9345e02ca49 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
43 43
44 dwmmc0@ff704000 { 44 dwmmc0@ff704000 {
45 num-slots = <1>; 45 num-slots = <1>;
46 supports-highspeed;
47 broken-cd; 46 broken-cd;
48 47 bus-width = <4>;
49 slot@0 { 48 cap-mmc-highspeed;
50 reg = <0>; 49 cap-sd-highspeed;
51 bus-width = <4>;
52 };
53 }; 50 };
54 51
55 ethernet@ff700000 { 52 ethernet@ff700000 {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 459cb6377764..380f914b226d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,12 +339,22 @@
339 #size-cells = <1>; 339 #size-cells = <1>;
340 ranges; 340 ranges;
341 341
342 dma: dma-controller@01c02000 {
343 compatible = "allwinner,sun4i-a10-dma";
344 reg = <0x01c02000 0x1000>;
345 interrupts = <27>;
346 clocks = <&ahb_gates 6>;
347 #dma-cells = <2>;
348 };
349
342 spi0: spi@01c05000 { 350 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi"; 351 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>; 352 reg = <0x01c05000 0x1000>;
345 interrupts = <10>; 353 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>; 354 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod"; 355 clock-names = "ahb", "mod";
356 dmas = <&dma 1 27>, <&dma 1 26>;
357 dma-names = "rx", "tx";
348 status = "disabled"; 358 status = "disabled";
349 #address-cells = <1>; 359 #address-cells = <1>;
350 #size-cells = <0>; 360 #size-cells = <0>;
@@ -356,6 +366,8 @@
356 interrupts = <11>; 366 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>; 367 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod"; 368 clock-names = "ahb", "mod";
369 dmas = <&dma 1 9>, <&dma 1 8>;
370 dma-names = "rx", "tx";
359 status = "disabled"; 371 status = "disabled";
360 #address-cells = <1>; 372 #address-cells = <1>;
361 #size-cells = <0>; 373 #size-cells = <0>;
@@ -451,6 +463,8 @@
451 interrupts = <12>; 463 interrupts = <12>;
452 clocks = <&ahb_gates 22>, <&spi2_clk>; 464 clocks = <&ahb_gates 22>, <&spi2_clk>;
453 clock-names = "ahb", "mod"; 465 clock-names = "ahb", "mod";
466 dmas = <&dma 1 29>, <&dma 1 28>;
467 dma-names = "rx", "tx";
454 status = "disabled"; 468 status = "disabled";
455 #address-cells = <1>; 469 #address-cells = <1>;
456 #size-cells = <0>; 470 #size-cells = <0>;
@@ -490,6 +504,8 @@
490 interrupts = <50>; 504 interrupts = <50>;
491 clocks = <&ahb_gates 23>, <&spi3_clk>; 505 clocks = <&ahb_gates 23>, <&spi3_clk>;
492 clock-names = "ahb", "mod"; 506 clock-names = "ahb", "mod";
507 dmas = <&dma 1 31>, <&dma 1 30>;
508 dma-names = "rx", "tx";
493 status = "disabled"; 509 status = "disabled";
494 #address-cells = <1>; 510 #address-cells = <1>;
495 #size-cells = <0>; 511 #size-cells = <0>;
@@ -749,7 +765,6 @@
749 reg = <0x01c2ac00 0x400>; 765 reg = <0x01c2ac00 0x400>;
750 interrupts = <7>; 766 interrupts = <7>;
751 clocks = <&apb1_gates 0>; 767 clocks = <&apb1_gates 0>;
752 clock-frequency = <100000>;
753 status = "disabled"; 768 status = "disabled";
754 #address-cells = <1>; 769 #address-cells = <1>;
755 #size-cells = <0>; 770 #size-cells = <0>;
@@ -760,7 +775,6 @@
760 reg = <0x01c2b000 0x400>; 775 reg = <0x01c2b000 0x400>;
761 interrupts = <8>; 776 interrupts = <8>;
762 clocks = <&apb1_gates 1>; 777 clocks = <&apb1_gates 1>;
763 clock-frequency = <100000>;
764 status = "disabled"; 778 status = "disabled";
765 #address-cells = <1>; 779 #address-cells = <1>;
766 #size-cells = <0>; 780 #size-cells = <0>;
@@ -771,7 +785,6 @@
771 reg = <0x01c2b400 0x400>; 785 reg = <0x01c2b400 0x400>;
772 interrupts = <9>; 786 interrupts = <9>;
773 clocks = <&apb1_gates 2>; 787 clocks = <&apb1_gates 2>;
774 clock-frequency = <100000>;
775 status = "disabled"; 788 status = "disabled";
776 #address-cells = <1>; 789 #address-cells = <1>;
777 #size-cells = <0>; 790 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0ad3a7c07..d73a2287b37a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -300,12 +300,22 @@
300 #size-cells = <1>; 300 #size-cells = <1>;
301 ranges; 301 ranges;
302 302
303 dma: dma-controller@01c02000 {
304 compatible = "allwinner,sun4i-a10-dma";
305 reg = <0x01c02000 0x1000>;
306 interrupts = <27>;
307 clocks = <&ahb_gates 6>;
308 #dma-cells = <2>;
309 };
310
303 spi0: spi@01c05000 { 311 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi"; 312 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>; 313 reg = <0x01c05000 0x1000>;
306 interrupts = <10>; 314 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>; 315 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod"; 316 clock-names = "ahb", "mod";
317 dmas = <&dma 1 27>, <&dma 1 26>;
318 dma-names = "rx", "tx";
309 status = "disabled"; 319 status = "disabled";
310 #address-cells = <1>; 320 #address-cells = <1>;
311 #size-cells = <0>; 321 #size-cells = <0>;
@@ -317,6 +327,8 @@
317 interrupts = <11>; 327 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>; 328 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod"; 329 clock-names = "ahb", "mod";
330 dmas = <&dma 1 9>, <&dma 1 8>;
331 dma-names = "rx", "tx";
320 status = "disabled"; 332 status = "disabled";
321 #address-cells = <1>; 333 #address-cells = <1>;
322 #size-cells = <0>; 334 #size-cells = <0>;
@@ -403,6 +415,8 @@
403 interrupts = <12>; 415 interrupts = <12>;
404 clocks = <&ahb_gates 22>, <&spi2_clk>; 416 clocks = <&ahb_gates 22>, <&spi2_clk>;
405 clock-names = "ahb", "mod"; 417 clock-names = "ahb", "mod";
418 dmas = <&dma 1 29>, <&dma 1 28>;
419 dma-names = "rx", "tx";
406 status = "disabled"; 420 status = "disabled";
407 #address-cells = <1>; 421 #address-cells = <1>;
408 #size-cells = <0>; 422 #size-cells = <0>;
@@ -564,7 +578,6 @@
564 reg = <0x01c2ac00 0x400>; 578 reg = <0x01c2ac00 0x400>;
565 interrupts = <7>; 579 interrupts = <7>;
566 clocks = <&apb1_gates 0>; 580 clocks = <&apb1_gates 0>;
567 clock-frequency = <100000>;
568 status = "disabled"; 581 status = "disabled";
569 }; 582 };
570 583
@@ -575,7 +588,6 @@
575 reg = <0x01c2b000 0x400>; 588 reg = <0x01c2b000 0x400>;
576 interrupts = <8>; 589 interrupts = <8>;
577 clocks = <&apb1_gates 1>; 590 clocks = <&apb1_gates 1>;
578 clock-frequency = <100000>;
579 status = "disabled"; 591 status = "disabled";
580 }; 592 };
581 593
@@ -586,7 +598,6 @@
586 reg = <0x01c2b400 0x400>; 598 reg = <0x01c2b400 0x400>;
587 interrupts = <9>; 599 interrupts = <9>;
588 clocks = <&apb1_gates 2>; 600 clocks = <&apb1_gates 2>;
589 clock-frequency = <100000>;
590 status = "disabled"; 601 status = "disabled";
591 }; 602 };
592 603
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
new file mode 100644
index 000000000000..8b3cd0907b32
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -0,0 +1,130 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai <wens@csie.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "sun5i-a13.dtsi"
50/include/ "sunxi-common-regulators.dtsi"
51
52/ {
53 model = "HSG H702";
54 compatible = "hsg,h702", "allwinner,sun5i-a13";
55
56 soc@01c00000 {
57 mmc0: mmc@01c0f000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
60 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>;
62 cd-gpios = <&pio 6 0 0>; /* PG0 */
63 cd-inverted;
64 status = "okay";
65 };
66
67 usbphy: phy@01c13400 {
68 /*
69 * There doesn't seem to be a GPIO for controlling
70 * usb1 vbus, despite the fex file saying otherwise.
71 */
72 usb1_vbus-supply = <&reg_vcc5v0>;
73 status = "okay";
74 };
75
76 ehci0: usb@01c14000 {
77 status = "okay";
78 };
79
80 ohci0: usb@01c14400 {
81 status = "okay";
82 };
83
84 pinctrl@01c20800 {
85 mmc0_cd_pin_h702: mmc0_cd_pin@0 {
86 allwinner,pins = "PG0";
87 allwinner,function = "gpio_in";
88 allwinner,drive = <0>;
89 allwinner,pull = <1>;
90 };
91 };
92
93 uart1: serial@01c28400 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&uart1_pins_b>;
96 status = "okay";
97 };
98
99 i2c0: i2c@01c2ac00 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&i2c0_pins_a>;
102 status = "okay";
103
104 axp209: pmic@34 {
105 compatible = "x-powers,axp209";
106 reg = <0x34>;
107 interrupts = <0>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 };
111 };
112
113 i2c1: i2c@01c2b000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c1_pins_a>;
116 status = "okay";
117
118 pcf8563: rtc@51 {
119 compatible = "nxp,pcf8563";
120 reg = <0x51>;
121 };
122 };
123
124 i2c2: i2c@01c2b400 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&i2c2_pins_a>;
127 status = "okay";
128 };
129 };
130};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index bf86e65dd167..c4b5d7825b9f 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,12 +298,22 @@
298 #size-cells = <1>; 298 #size-cells = <1>;
299 ranges; 299 ranges;
300 300
301 dma: dma-controller@01c02000 {
302 compatible = "allwinner,sun4i-a10-dma";
303 reg = <0x01c02000 0x1000>;
304 interrupts = <27>;
305 clocks = <&ahb_gates 6>;
306 #dma-cells = <2>;
307 };
308
301 spi0: spi@01c05000 { 309 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi"; 310 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>; 311 reg = <0x01c05000 0x1000>;
304 interrupts = <10>; 312 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>; 313 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod"; 314 clock-names = "ahb", "mod";
315 dmas = <&dma 1 27>, <&dma 1 26>;
316 dma-names = "rx", "tx";
307 status = "disabled"; 317 status = "disabled";
308 #address-cells = <1>; 318 #address-cells = <1>;
309 #size-cells = <0>; 319 #size-cells = <0>;
@@ -315,6 +325,8 @@
315 interrupts = <11>; 325 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>; 326 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod"; 327 clock-names = "ahb", "mod";
328 dmas = <&dma 1 9>, <&dma 1 8>;
329 dma-names = "rx", "tx";
318 status = "disabled"; 330 status = "disabled";
319 #address-cells = <1>; 331 #address-cells = <1>;
320 #size-cells = <0>; 332 #size-cells = <0>;
@@ -376,6 +388,8 @@
376 interrupts = <12>; 388 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>; 389 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod"; 390 clock-names = "ahb", "mod";
391 dmas = <&dma 1 29>, <&dma 1 28>;
392 dma-names = "rx", "tx";
379 status = "disabled"; 393 status = "disabled";
380 #address-cells = <1>; 394 #address-cells = <1>;
381 #size-cells = <0>; 395 #size-cells = <0>;
@@ -490,7 +504,6 @@
490 reg = <0x01c2ac00 0x400>; 504 reg = <0x01c2ac00 0x400>;
491 interrupts = <7>; 505 interrupts = <7>;
492 clocks = <&apb1_gates 0>; 506 clocks = <&apb1_gates 0>;
493 clock-frequency = <100000>;
494 status = "disabled"; 507 status = "disabled";
495 #address-cells = <1>; 508 #address-cells = <1>;
496 #size-cells = <0>; 509 #size-cells = <0>;
@@ -501,7 +514,6 @@
501 reg = <0x01c2b000 0x400>; 514 reg = <0x01c2b000 0x400>;
502 interrupts = <8>; 515 interrupts = <8>;
503 clocks = <&apb1_gates 1>; 516 clocks = <&apb1_gates 1>;
504 clock-frequency = <100000>;
505 status = "disabled"; 517 status = "disabled";
506 #address-cells = <1>; 518 #address-cells = <1>;
507 #size-cells = <0>; 519 #size-cells = <0>;
@@ -512,7 +524,6 @@
512 reg = <0x01c2b400 0x400>; 524 reg = <0x01c2b400 0x400>;
513 interrupts = <9>; 525 interrupts = <9>;
514 clocks = <&apb1_gates 2>; 526 clocks = <&apb1_gates 2>;
515 clock-frequency = <100000>;
516 status = "disabled"; 527 status = "disabled";
517 #address-cells = <1>; 528 #address-cells = <1>;
518 #size-cells = <0>; 529 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index e06fbfc55bb7..543f895d18d3 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -657,7 +693,6 @@
657 reg = <0x01c2ac00 0x400>; 693 reg = <0x01c2ac00 0x400>;
658 interrupts = <0 6 4>; 694 interrupts = <0 6 4>;
659 clocks = <&apb2_gates 0>; 695 clocks = <&apb2_gates 0>;
660 clock-frequency = <100000>;
661 resets = <&apb2_rst 0>; 696 resets = <&apb2_rst 0>;
662 status = "disabled"; 697 status = "disabled";
663 #address-cells = <1>; 698 #address-cells = <1>;
@@ -669,7 +704,6 @@
669 reg = <0x01c2b000 0x400>; 704 reg = <0x01c2b000 0x400>;
670 interrupts = <0 7 4>; 705 interrupts = <0 7 4>;
671 clocks = <&apb2_gates 1>; 706 clocks = <&apb2_gates 1>;
672 clock-frequency = <100000>;
673 resets = <&apb2_rst 1>; 707 resets = <&apb2_rst 1>;
674 status = "disabled"; 708 status = "disabled";
675 #address-cells = <1>; 709 #address-cells = <1>;
@@ -681,7 +715,6 @@
681 reg = <0x01c2b400 0x400>; 715 reg = <0x01c2b400 0x400>;
682 interrupts = <0 8 4>; 716 interrupts = <0 8 4>;
683 clocks = <&apb2_gates 2>; 717 clocks = <&apb2_gates 2>;
684 clock-frequency = <100000>;
685 resets = <&apb2_rst 2>; 718 resets = <&apb2_rst 2>;
686 status = "disabled"; 719 status = "disabled";
687 #address-cells = <1>; 720 #address-cells = <1>;
@@ -693,7 +726,6 @@
693 reg = <0x01c2b800 0x400>; 726 reg = <0x01c2b800 0x400>;
694 interrupts = <0 9 4>; 727 interrupts = <0 9 4>;
695 clocks = <&apb2_gates 3>; 728 clocks = <&apb2_gates 3>;
696 clock-frequency = <100000>;
697 resets = <&apb2_rst 3>; 729 resets = <&apb2_rst 3>;
698 status = "disabled"; 730 status = "disabled";
699 #address-cells = <1>; 731 #address-cells = <1>;
@@ -787,6 +819,12 @@
787 interrupts = <1 9 0xf04>; 819 interrupts = <1 9 0xf04>;
788 }; 820 };
789 821
822 rtc: rtc@01f00000 {
823 compatible = "allwinner,sun6i-a31-rtc";
824 reg = <0x01f00000 0x54>;
825 interrupts = <0 40 4>, <0 41 4>;
826 };
827
790 nmi_intc: interrupt-controller@01f00c0c { 828 nmi_intc: interrupt-controller@01f00c0c {
791 compatible = "allwinner,sun6i-a31-sc-nmi"; 829 compatible = "allwinner,sun6i-a31-sc-nmi";
792 interrupt-controller; 830 interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
new file mode 100644
index 000000000000..0e4bfa3b2b85
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -0,0 +1,236 @@
1/*
2 * Copyright 2013 Wills Wang
3 *
4 * Wills Wang <wills.wang.open@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
17
18/ {
19 model = "Merrii A20 Hummingbird";
20 compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
21
22 soc@01c00000 {
23 mmc0: mmc@01c0f000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
26 vmmc-supply = <&reg_vcc3v0>;
27 bus-width = <4>;
28 cd-gpios = <&pio 7 1 0>; /* PH1 */
29 cd-inverted;
30 status = "okay";
31 };
32
33 mmc3: mmc@01c12000 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&mmc3_pins_a>;
36 vmmc-supply = <&reg_mmc3_vdd>;
37 bus-width = <4>;
38 non-removable;
39 status = "okay";
40 };
41
42 usbphy: phy@01c13400 {
43 usb1_vbus-supply = <&reg_usb1_vbus>;
44 usb2_vbus-supply = <&reg_usb2_vbus>;
45 status = "okay";
46 };
47
48 ehci0: usb@01c14000 {
49 status = "okay";
50 };
51
52 ohci0: usb@01c14400 {
53 status = "okay";
54 };
55
56 ahci: sata@01c18000 {
57 target-supply = <&reg_ahci_5v>;
58 status = "okay";
59 };
60
61 ehci1: usb@01c1c000 {
62 status = "okay";
63 };
64
65 ohci1: usb@01c1c400 {
66 status = "okay";
67 };
68
69 pio: pinctrl@01c20800 {
70 ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
71 allwinner,pins = "PH15";
72 allwinner,function = "gpio_out";
73 allwinner,drive = <0>;
74 allwinner,pull = <0>;
75 };
76
77 usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
78 allwinner,pins = "PH2";
79 allwinner,function = "gpio_out";
80 allwinner,drive = <0>;
81 allwinner,pull = <0>;
82 };
83
84 mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
85 allwinner,pins = "PH9";
86 allwinner,function = "gpio_out";
87 allwinner,drive = <0>;
88 allwinner,pull = <0>;
89 };
90
91 gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
92 allwinner,pins = "PH16";
93 allwinner,function = "gpio_out";
94 allwinner,drive = <0>;
95 allwinner,pull = <0>;
96 };
97 };
98
99 pwm: pwm@01c20e00 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pwm0_pins_a>;
102 status = "okay";
103 };
104
105 ir0: ir@01c21800 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&ir0_pins_a>;
108 status = "okay";
109 };
110
111 uart0: serial@01c28000 {
112 pinctrl-names = "default";
113 pinctrl-0 = <&uart0_pins_a>;
114 status = "okay";
115 };
116
117 uart2: serial@01c28800 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&uart2_pins_a>;
120 status = "okay";
121 };
122
123 uart3: serial@01c28c00 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart3_pins_a>;
126 status = "okay";
127 };
128
129 uart4: serial@01c29000 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&uart4_pins_a>;
132 status = "okay";
133 };
134
135 uart5: serial@01c29400 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&uart5_pins_a>;
138 status = "okay";
139 };
140
141 i2c0: i2c@01c2ac00 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&i2c0_pins_a>;
144 status = "okay";
145
146 axp209: pmic@34 {
147 compatible = "x-powers,axp209";
148 reg = <0x34>;
149 interrupt-parent = <&nmi_intc>;
150 interrupts = <0 8>;
151 interrupt-controller;
152 #interrupt-cells = <1>;
153 };
154 };
155
156 i2c1: i2c@01c2b000 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&i2c1_pins_a>;
159 status = "okay";
160 };
161
162 i2c2: i2c@01c2b400 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c2_pins_a>;
165 status = "okay";
166 };
167
168 i2c3: i2c@01c2b800 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c3_pins_a>;
171 status = "okay";
172 };
173
174 spi2: spi@01c17000 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&spi2_pins_b>;
177 status = "okay";
178 };
179
180 gmac: ethernet@01c50000 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&gmac_pins_rgmii_a>;
183 phy = <&phy1>;
184 phy-mode = "rgmii";
185 phy-supply = <&reg_gmac_vdd>;
186 /* phy reset config */
187 snps,reset-gpio = <&pio 0 17 0>; /* PA17 */
188 snps,reset-active-low;
189 /* wait 1s after reset, otherwise fail to read phy id */
190 snps,reset-delays-us = <0 10000 1000000>;
191 status = "okay";
192
193 phy1: ethernet-phy@1 {
194 reg = <1>;
195 };
196 };
197 };
198
199 reg_ahci_5v: ahci-5v {
200 pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
201 gpio = <&pio 7 15 0>; /* PH15 */
202 status = "okay";
203 };
204
205 reg_usb1_vbus: usb1-vbus {
206 pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
207 gpio = <&pio 7 2 0>; /* PH2 */
208 status = "okay";
209 };
210
211 reg_usb2_vbus: usb2-vbus {
212 status = "okay";
213 };
214
215 reg_mmc3_vdd: mmc3_vdd {
216 compatible = "regulator-fixed";
217 pinctrl-names = "default";
218 pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
219 regulator-name = "mmc3_vdd";
220 regulator-min-microvolt = <3000000>;
221 regulator-max-microvolt = <3000000>;
222 enable-active-high;
223 gpio = <&pio 7 9 0>; /* PH9 */
224 };
225
226 reg_gmac_vdd: gmac_vdd {
227 compatible = "regulator-fixed";
228 pinctrl-names = "default";
229 pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
230 regulator-name = "gmac_vdd";
231 regulator-min-microvolt = <3000000>;
232 regulator-max-microvolt = <3000000>;
233 enable-active-high;
234 gpio = <&pio 7 16 0>; /* PH16 */
235 };
236};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
new file mode 100644
index 000000000000..1eb8175959a6
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -0,0 +1,137 @@
1/*
2 * This is based on sun4i-a10-olinuxino-lime.dts
3 *
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
16/include/ "sun7i-a20.dtsi"
17/include/ "sunxi-common-regulators.dtsi"
18
19/ {
20 model = "Olimex A20-OLinuXino-LIME";
21 compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20";
22
23 soc@01c00000 {
24 mmc0: mmc@01c0f000 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
27 vmmc-supply = <&reg_vcc3v3>;
28 bus-width = <4>;
29 cd-gpios = <&pio 7 1 0>; /* PH1 */
30 cd-inverted;
31 status = "okay";
32 };
33
34 usbphy: phy@01c13400 {
35 usb1_vbus-supply = <&reg_usb1_vbus>;
36 usb2_vbus-supply = <&reg_usb2_vbus>;
37 status = "okay";
38 };
39
40 ehci0: usb@01c14000 {
41 status = "okay";
42 };
43
44 ohci0: usb@01c14400 {
45 status = "okay";
46 };
47
48 ahci: sata@01c18000 {
49 target-supply = <&reg_ahci_5v>;
50 status = "okay";
51 };
52
53 ehci1: usb@01c1c000 {
54 status = "okay";
55 };
56
57 ohci1: usb@01c1c400 {
58 status = "okay";
59 };
60
61 pinctrl@01c20800 {
62 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
63 allwinner,pins = "PC3";
64 allwinner,function = "gpio_out";
65 allwinner,drive = <0>;
66 allwinner,pull = <0>;
67 };
68
69 led_pins_olinuxinolime: led_pins@0 {
70 allwinner,pins = "PH2";
71 allwinner,function = "gpio_out";
72 allwinner,drive = <1>;
73 allwinner,pull = <0>;
74 };
75 };
76
77 uart0: serial@01c28000 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart0_pins_a>;
80 status = "okay";
81 };
82
83 i2c0: i2c@01c2ac00 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2c0_pins_a>;
86 status = "okay";
87
88 axp209: pmic@34 {
89 compatible = "x-powers,axp209";
90 reg = <0x34>;
91 interrupt-parent = <&nmi_intc>;
92 interrupts = <0 8>;
93
94 interrupt-controller;
95 #interrupt-cells = <1>;
96 };
97 };
98
99 gmac: ethernet@01c50000 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&gmac_pins_mii_a>;
102 phy = <&phy1>;
103 phy-mode = "mii";
104 status = "okay";
105
106 phy1: ethernet-phy@1 {
107 reg = <1>;
108 };
109 };
110 };
111
112 leds {
113 compatible = "gpio-leds";
114 pinctrl-names = "default";
115 pinctrl-0 = <&led_pins_olinuxinolime>;
116
117 green {
118 label = "a20-olinuxino-lime:green:usr";
119 gpios = <&pio 7 2 0>;
120 default-state = "on";
121 };
122 };
123
124 reg_ahci_5v: ahci-5v {
125 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
126 gpio = <&pio 2 3 0>;
127 status = "okay";
128 };
129
130 reg_usb1_vbus: usb1-vbus {
131 status = "okay";
132 };
133
134 reg_usb2_vbus: usb2-vbus {
135 status = "okay";
136 };
137};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4011628c7381..a96b99465069 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -423,12 +459,22 @@
423 interrupts = <0 0 4>; 459 interrupts = <0 0 4>;
424 }; 460 };
425 461
462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun4i-a10-dma";
464 reg = <0x01c02000 0x1000>;
465 interrupts = <0 27 4>;
466 clocks = <&ahb_gates 6>;
467 #dma-cells = <2>;
468 };
469
426 spi0: spi@01c05000 { 470 spi0: spi@01c05000 {
427 compatible = "allwinner,sun4i-a10-spi"; 471 compatible = "allwinner,sun4i-a10-spi";
428 reg = <0x01c05000 0x1000>; 472 reg = <0x01c05000 0x1000>;
429 interrupts = <0 10 4>; 473 interrupts = <0 10 4>;
430 clocks = <&ahb_gates 20>, <&spi0_clk>; 474 clocks = <&ahb_gates 20>, <&spi0_clk>;
431 clock-names = "ahb", "mod"; 475 clock-names = "ahb", "mod";
476 dmas = <&dma 1 27>, <&dma 1 26>;
477 dma-names = "rx", "tx";
432 status = "disabled"; 478 status = "disabled";
433 #address-cells = <1>; 479 #address-cells = <1>;
434 #size-cells = <0>; 480 #size-cells = <0>;
@@ -440,6 +486,8 @@
440 interrupts = <0 11 4>; 486 interrupts = <0 11 4>;
441 clocks = <&ahb_gates 21>, <&spi1_clk>; 487 clocks = <&ahb_gates 21>, <&spi1_clk>;
442 clock-names = "ahb", "mod"; 488 clock-names = "ahb", "mod";
489 dmas = <&dma 1 9>, <&dma 1 8>;
490 dma-names = "rx", "tx";
443 status = "disabled"; 491 status = "disabled";
444 #address-cells = <1>; 492 #address-cells = <1>;
445 #size-cells = <0>; 493 #size-cells = <0>;
@@ -535,6 +583,8 @@
535 interrupts = <0 12 4>; 583 interrupts = <0 12 4>;
536 clocks = <&ahb_gates 22>, <&spi2_clk>; 584 clocks = <&ahb_gates 22>, <&spi2_clk>;
537 clock-names = "ahb", "mod"; 585 clock-names = "ahb", "mod";
586 dmas = <&dma 1 29>, <&dma 1 28>;
587 dma-names = "rx", "tx";
538 status = "disabled"; 588 status = "disabled";
539 #address-cells = <1>; 589 #address-cells = <1>;
540 #size-cells = <0>; 590 #size-cells = <0>;
@@ -574,6 +624,8 @@
574 interrupts = <0 50 4>; 624 interrupts = <0 50 4>;
575 clocks = <&ahb_gates 23>, <&spi3_clk>; 625 clocks = <&ahb_gates 23>, <&spi3_clk>;
576 clock-names = "ahb", "mod"; 626 clock-names = "ahb", "mod";
627 dmas = <&dma 1 31>, <&dma 1 30>;
628 dma-names = "rx", "tx";
577 status = "disabled"; 629 status = "disabled";
578 #address-cells = <1>; 630 #address-cells = <1>;
579 #size-cells = <0>; 631 #size-cells = <0>;
@@ -618,6 +670,27 @@
618 allwinner,pull = <0>; 670 allwinner,pull = <0>;
619 }; 671 };
620 672
673 uart3_pins_a: uart3@0 {
674 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
675 allwinner,function = "uart3";
676 allwinner,drive = <0>;
677 allwinner,pull = <0>;
678 };
679
680 uart4_pins_a: uart4@0 {
681 allwinner,pins = "PG10", "PG11";
682 allwinner,function = "uart4";
683 allwinner,drive = <0>;
684 allwinner,pull = <0>;
685 };
686
687 uart5_pins_a: uart5@0 {
688 allwinner,pins = "PI10", "PI11";
689 allwinner,function = "uart5";
690 allwinner,drive = <0>;
691 allwinner,pull = <0>;
692 };
693
621 uart6_pins_a: uart6@0 { 694 uart6_pins_a: uart6@0 {
622 allwinner,pins = "PI12", "PI13"; 695 allwinner,pins = "PI12", "PI13";
623 allwinner,function = "uart6"; 696 allwinner,function = "uart6";
@@ -653,6 +726,13 @@
653 allwinner,pull = <0>; 726 allwinner,pull = <0>;
654 }; 727 };
655 728
729 i2c3_pins_a: i2c3@0 {
730 allwinner,pins = "PI0", "PI1";
731 allwinner,function = "i2c3";
732 allwinner,drive = <0>;
733 allwinner,pull = <0>;
734 };
735
656 emac_pins_a: emac0@0 { 736 emac_pins_a: emac0@0 {
657 allwinner,pins = "PA0", "PA1", "PA2", 737 allwinner,pins = "PA0", "PA1", "PA2",
658 "PA3", "PA4", "PA5", "PA6", 738 "PA3", "PA4", "PA5", "PA6",
@@ -718,6 +798,13 @@
718 allwinner,pull = <0>; 798 allwinner,pull = <0>;
719 }; 799 };
720 800
801 spi2_pins_b: spi2@1 {
802 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
803 allwinner,function = "spi2";
804 allwinner,drive = <0>;
805 allwinner,pull = <0>;
806 };
807
721 mmc0_pins_a: mmc0@0 { 808 mmc0_pins_a: mmc0@0 {
722 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 809 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
723 allwinner,function = "mmc0"; 810 allwinner,function = "mmc0";
@@ -899,7 +986,6 @@
899 reg = <0x01c2ac00 0x400>; 986 reg = <0x01c2ac00 0x400>;
900 interrupts = <0 7 4>; 987 interrupts = <0 7 4>;
901 clocks = <&apb1_gates 0>; 988 clocks = <&apb1_gates 0>;
902 clock-frequency = <100000>;
903 status = "disabled"; 989 status = "disabled";
904 #address-cells = <1>; 990 #address-cells = <1>;
905 #size-cells = <0>; 991 #size-cells = <0>;
@@ -910,7 +996,6 @@
910 reg = <0x01c2b000 0x400>; 996 reg = <0x01c2b000 0x400>;
911 interrupts = <0 8 4>; 997 interrupts = <0 8 4>;
912 clocks = <&apb1_gates 1>; 998 clocks = <&apb1_gates 1>;
913 clock-frequency = <100000>;
914 status = "disabled"; 999 status = "disabled";
915 #address-cells = <1>; 1000 #address-cells = <1>;
916 #size-cells = <0>; 1001 #size-cells = <0>;
@@ -921,7 +1006,6 @@
921 reg = <0x01c2b400 0x400>; 1006 reg = <0x01c2b400 0x400>;
922 interrupts = <0 9 4>; 1007 interrupts = <0 9 4>;
923 clocks = <&apb1_gates 2>; 1008 clocks = <&apb1_gates 2>;
924 clock-frequency = <100000>;
925 status = "disabled"; 1009 status = "disabled";
926 #address-cells = <1>; 1010 #address-cells = <1>;
927 #size-cells = <0>; 1011 #size-cells = <0>;
@@ -932,7 +1016,6 @@
932 reg = <0x01c2b800 0x400>; 1016 reg = <0x01c2b800 0x400>;
933 interrupts = <0 88 4>; 1017 interrupts = <0 88 4>;
934 clocks = <&apb1_gates 3>; 1018 clocks = <&apb1_gates 3>;
935 clock-frequency = <100000>;
936 status = "disabled"; 1019 status = "disabled";
937 #address-cells = <1>; 1020 #address-cells = <1>;
938 #size-cells = <0>; 1021 #size-cells = <0>;
@@ -943,7 +1026,6 @@
943 reg = <0x01c2c000 0x400>; 1026 reg = <0x01c2c000 0x400>;
944 interrupts = <0 89 4>; 1027 interrupts = <0 89 4>;
945 clocks = <&apb1_gates 15>; 1028 clocks = <&apb1_gates 15>;
946 clock-frequency = <100000>;
947 status = "disabled"; 1029 status = "disabled";
948 #address-cells = <1>; 1030 #address-cells = <1>;
949 #size-cells = <0>; 1031 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 34002e3eba9d..e9b8cca8dcc1 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun8i-a23.dtsi" 15/include/ "sun8i-a23.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Ippo Q8H Dual Core Tablet (v5)"; 19 model = "Ippo Q8H Dual Core Tablet (v5)";
@@ -23,7 +24,47 @@
23 }; 24 };
24 25
25 soc@01c00000 { 26 soc@01c00000 {
27 mmc0: mmc@01c0f000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
30 vmmc-supply = <&reg_vcc3v0>;
31 bus-width = <4>;
32 cd-gpios = <&pio 1 4 0>; /* PB4 */
33 cd-inverted;
34 status = "okay";
35 };
36
37 pinctrl@01c20800 {
38 mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
39 allwinner,pins = "PB4";
40 allwinner,function = "gpio_in";
41 allwinner,drive = <0>;
42 allwinner,pull = <1>;
43 };
44 };
45
46 i2c0: i2c@01c2ac00 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&i2c0_pins_a>;
49 status = "okay";
50 };
51
52 i2c1: i2c@01c2b000 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&i2c1_pins_a>;
55 status = "okay";
56 };
57
58 i2c2: i2c@01c2b400 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c2_pins_a>;
61 /* pull-ups and devices require PMIC regulator */
62 status = "failed";
63 };
64
26 r_uart: serial@01f02800 { 65 r_uart: serial@01f02800 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&r_uart_pins_a>;
27 status = "okay"; 68 status = "okay";
28 }; 69 };
29 }; 70 };
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 54ac0787216a..6146ef15efbe 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Chen-Yu Tsai <wens@csie.org> 4 * Chen-Yu Tsai <wens@csie.org>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -179,6 +215,30 @@
179 "apb2_uart1", "apb2_uart2", 215 "apb2_uart1", "apb2_uart2",
180 "apb2_uart3", "apb2_uart4"; 216 "apb2_uart3", "apb2_uart4";
181 }; 217 };
218
219 mmc0_clk: clk@01c20088 {
220 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20088 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc0";
225 };
226
227 mmc1_clk: clk@01c2008c {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c2008c 0x4>;
231 clocks = <&osc24M>, <&pll6>;
232 clock-output-names = "mmc1";
233 };
234
235 mmc2_clk: clk@01c20090 {
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c20090 0x4>;
239 clocks = <&osc24M>, <&pll6>;
240 clock-output-names = "mmc2";
241 };
182 }; 242 };
183 243
184 soc@01c00000 { 244 soc@01c00000 {
@@ -187,6 +247,104 @@
187 #size-cells = <1>; 247 #size-cells = <1>;
188 ranges; 248 ranges;
189 249
250 dma: dma-controller@01c02000 {
251 compatible = "allwinner,sun8i-a23-dma";
252 reg = <0x01c02000 0x1000>;
253 interrupts = <0 50 4>;
254 clocks = <&ahb1_gates 6>;
255 resets = <&ahb1_rst 6>;
256 #dma-cells = <1>;
257 };
258
259 mmc0: mmc@01c0f000 {
260 compatible = "allwinner,sun5i-a13-mmc";
261 reg = <0x01c0f000 0x1000>;
262 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
263 clock-names = "ahb", "mmc";
264 resets = <&ahb1_rst 8>;
265 reset-names = "ahb";
266 interrupts = <0 60 4>;
267 status = "disabled";
268 };
269
270 mmc1: mmc@01c10000 {
271 compatible = "allwinner,sun5i-a13-mmc";
272 reg = <0x01c10000 0x1000>;
273 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
274 clock-names = "ahb", "mmc";
275 resets = <&ahb1_rst 9>;
276 reset-names = "ahb";
277 interrupts = <0 61 4>;
278 status = "disabled";
279 };
280
281 mmc2: mmc@01c11000 {
282 compatible = "allwinner,sun5i-a13-mmc";
283 reg = <0x01c11000 0x1000>;
284 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
285 clock-names = "ahb", "mmc";
286 resets = <&ahb1_rst 10>;
287 reset-names = "ahb";
288 interrupts = <0 62 4>;
289 status = "disabled";
290 };
291
292 pio: pinctrl@01c20800 {
293 compatible = "allwinner,sun8i-a23-pinctrl";
294 reg = <0x01c20800 0x400>;
295 interrupts = <0 11 4>,
296 <0 15 4>,
297 <0 17 4>;
298 clocks = <&apb1_gates 5>;
299 gpio-controller;
300 interrupt-controller;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 #gpio-cells = <3>;
304
305 uart0_pins_a: uart0@0 {
306 allwinner,pins = "PF2", "PF4";
307 allwinner,function = "uart0";
308 allwinner,drive = <0>;
309 allwinner,pull = <0>;
310 };
311
312 mmc0_pins_a: mmc0@0 {
313 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
314 allwinner,function = "mmc0";
315 allwinner,drive = <2>;
316 allwinner,pull = <0>;
317 };
318
319 mmc1_pins_a: mmc1@0 {
320 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
321 allwinner,function = "mmc1";
322 allwinner,drive = <2>;
323 allwinner,pull = <0>;
324 };
325
326 i2c0_pins_a: i2c0@0 {
327 allwinner,pins = "PH2", "PH3";
328 allwinner,function = "i2c0";
329 allwinner,drive = <0>;
330 allwinner,pull = <0>;
331 };
332
333 i2c1_pins_a: i2c1@0 {
334 allwinner,pins = "PH4", "PH5";
335 allwinner,function = "i2c1";
336 allwinner,drive = <0>;
337 allwinner,pull = <0>;
338 };
339
340 i2c2_pins_a: i2c2@0 {
341 allwinner,pins = "PE12", "PE13";
342 allwinner,function = "i2c2";
343 allwinner,drive = <0>;
344 allwinner,pull = <0>;
345 };
346 };
347
190 ahb1_rst: reset@01c202c0 { 348 ahb1_rst: reset@01c202c0 {
191 #reset-cells = <1>; 349 #reset-cells = <1>;
192 compatible = "allwinner,sun6i-a31-clock-reset"; 350 compatible = "allwinner,sun6i-a31-clock-reset";
@@ -227,6 +385,8 @@
227 reg-io-width = <4>; 385 reg-io-width = <4>;
228 clocks = <&apb2_gates 16>; 386 clocks = <&apb2_gates 16>;
229 resets = <&apb2_rst 16>; 387 resets = <&apb2_rst 16>;
388 dmas = <&dma 6>, <&dma 6>;
389 dma-names = "rx", "tx";
230 status = "disabled"; 390 status = "disabled";
231 }; 391 };
232 392
@@ -238,6 +398,8 @@
238 reg-io-width = <4>; 398 reg-io-width = <4>;
239 clocks = <&apb2_gates 17>; 399 clocks = <&apb2_gates 17>;
240 resets = <&apb2_rst 17>; 400 resets = <&apb2_rst 17>;
401 dmas = <&dma 7>, <&dma 7>;
402 dma-names = "rx", "tx";
241 status = "disabled"; 403 status = "disabled";
242 }; 404 };
243 405
@@ -249,6 +411,8 @@
249 reg-io-width = <4>; 411 reg-io-width = <4>;
250 clocks = <&apb2_gates 18>; 412 clocks = <&apb2_gates 18>;
251 resets = <&apb2_rst 18>; 413 resets = <&apb2_rst 18>;
414 dmas = <&dma 8>, <&dma 8>;
415 dma-names = "rx", "tx";
252 status = "disabled"; 416 status = "disabled";
253 }; 417 };
254 418
@@ -260,6 +424,8 @@
260 reg-io-width = <4>; 424 reg-io-width = <4>;
261 clocks = <&apb2_gates 19>; 425 clocks = <&apb2_gates 19>;
262 resets = <&apb2_rst 19>; 426 resets = <&apb2_rst 19>;
427 dmas = <&dma 9>, <&dma 9>;
428 dma-names = "rx", "tx";
263 status = "disabled"; 429 status = "disabled";
264 }; 430 };
265 431
@@ -271,9 +437,44 @@
271 reg-io-width = <4>; 437 reg-io-width = <4>;
272 clocks = <&apb2_gates 20>; 438 clocks = <&apb2_gates 20>;
273 resets = <&apb2_rst 20>; 439 resets = <&apb2_rst 20>;
440 dmas = <&dma 10>, <&dma 10>;
441 dma-names = "rx", "tx";
274 status = "disabled"; 442 status = "disabled";
275 }; 443 };
276 444
445 i2c0: i2c@01c2ac00 {
446 compatible = "allwinner,sun6i-a31-i2c";
447 reg = <0x01c2ac00 0x400>;
448 interrupts = <0 6 4>;
449 clocks = <&apb2_gates 0>;
450 resets = <&apb2_rst 0>;
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 };
455
456 i2c1: i2c@01c2b000 {
457 compatible = "allwinner,sun6i-a31-i2c";
458 reg = <0x01c2b000 0x400>;
459 interrupts = <0 7 4>;
460 clocks = <&apb2_gates 1>;
461 resets = <&apb2_rst 1>;
462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
466
467 i2c2: i2c@01c2b400 {
468 compatible = "allwinner,sun6i-a31-i2c";
469 reg = <0x01c2b400 0x400>;
470 interrupts = <0 8 4>;
471 clocks = <&apb2_gates 2>;
472 resets = <&apb2_rst 2>;
473 status = "disabled";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 };
477
277 gic: interrupt-controller@01c81000 { 478 gic: interrupt-controller@01c81000 {
278 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 479 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
279 reg = <0x01c81000 0x1000>, 480 reg = <0x01c81000 0x1000>,
@@ -285,6 +486,12 @@
285 interrupts = <1 9 0xf04>; 486 interrupts = <1 9 0xf04>;
286 }; 487 };
287 488
489 rtc: rtc@01f00000 {
490 compatible = "allwinner,sun6i-a31-rtc";
491 reg = <0x01f00000 0x54>;
492 interrupts = <0 40 4>, <0 41 4>;
493 };
494
288 prcm@01f01400 { 495 prcm@01f01400 {
289 compatible = "allwinner,sun8i-a23-prcm"; 496 compatible = "allwinner,sun8i-a23-prcm";
290 reg = <0x01f01400 0x200>; 497 reg = <0x01f01400 0x200>;
@@ -339,5 +546,25 @@
339 resets = <&apb0_rst 4>; 546 resets = <&apb0_rst 4>;
340 status = "disabled"; 547 status = "disabled";
341 }; 548 };
549
550 r_pio: pinctrl@01f02c00 {
551 compatible = "allwinner,sun8i-a23-r-pinctrl";
552 reg = <0x01f02c00 0x400>;
553 interrupts = <0 45 4>;
554 clocks = <&apb0_gates 0>;
555 resets = <&apb0_rst 0>;
556 gpio-controller;
557 interrupt-controller;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 #gpio-cells = <3>;
561
562 r_uart_pins_a: r_uart@0 {
563 allwinner,pins = "PL2", "PL3";
564 allwinner,function = "s_uart";
565 allwinner,drive = <0>;
566 allwinner,pull = <0>;
567 };
568 };
342 }; 569 };
343}; 570};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 3d021efd1a38..c9c5b10e03eb 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -86,4 +86,11 @@
86 regulator-min-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>;
88 }; 88 };
89
90 reg_vcc5v0: vcc5v0 {
91 compatible = "regulator-fixed";
92 regulator-name = "vcc5v0";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 };
89}; 96};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 80b8eddb4105..2ca9c1807f72 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -157,6 +157,11 @@
157 #reset-cells = <1>; 157 #reset-cells = <1>;
158 }; 158 };
159 159
160 flow-controller@60007000 {
161 compatible = "nvidia,tegra114-flowctrl";
162 reg = <0x60007000 0x1000>;
163 };
164
160 apbdma: dma@6000a000 { 165 apbdma: dma@6000a000 {
161 compatible = "nvidia,tegra114-apbdma"; 166 compatible = "nvidia,tegra114-apbdma";
162 reg = <0x6000a000 0x1400>; 167 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 624b0fba2d0a..029c9a021541 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -16,6 +16,26 @@
16 reg = <0x0 0x80000000 0x0 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 pcie-controller@0,01003000 {
20 status = "okay";
21
22 avddio-pex-supply = <&vdd_1v05_run>;
23 dvddio-pex-supply = <&vdd_1v05_run>;
24 avdd-pex-pll-supply = <&vdd_1v05_run>;
25 hvdd-pex-supply = <&vdd_3v3_lp0>;
26 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
27 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
28 avdd-pll-erefe-supply = <&avdd_1v05_run>;
29
30 pci@1,0 {
31 status = "okay";
32 };
33
34 pci@2,0 {
35 status = "okay";
36 };
37 };
38
19 host1x@0,50000000 { 39 host1x@0,50000000 {
20 hdmi@0,54280000 { 40 hdmi@0,54280000 {
21 status = "okay"; 41 status = "okay";
@@ -31,10 +51,10 @@
31 }; 51 };
32 52
33 pinmux: pinmux@0,70000868 { 53 pinmux: pinmux@0,70000868 {
34 pinctrl-names = "default"; 54 pinctrl-names = "boot";
35 pinctrl-0 = <&state_default>; 55 pinctrl-0 = <&state_boot>;
36 56
37 state_default: pinmux { 57 state_boot: pinmux {
38 clk_32k_out_pa0 { 58 clk_32k_out_pa0 {
39 nvidia,pins = "clk_32k_out_pa0"; 59 nvidia,pins = "clk_32k_out_pa0";
40 nvidia,function = "soc"; 60 nvidia,function = "soc";
@@ -1231,6 +1251,41 @@
1231 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1252 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233 }; 1253 };
1254 pex_l0_rst_n_pdd1 {
1255 nvidia,pins = "pex_l0_rst_n_pdd1";
1256 nvidia,function = "pe0";
1257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260 };
1261 pex_l0_clkreq_n_pdd2 {
1262 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1263 nvidia,function = "pe0";
1264 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1266 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1267 };
1268 pex_wake_n_pdd3 {
1269 nvidia,pins = "pex_wake_n_pdd3";
1270 nvidia,function = "pe";
1271 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1274 };
1275 pex_l1_rst_n_pdd5 {
1276 nvidia,pins = "pex_l1_rst_n_pdd5";
1277 nvidia,function = "pe1";
1278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1280 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1281 };
1282 pex_l1_clkreq_n_pdd6 {
1283 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1284 nvidia,function = "pe1";
1285 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1288 };
1234 clk3_out_pee0 { 1289 clk3_out_pee0 {
1235 nvidia,pins = "clk3_out_pee0"; 1290 nvidia,pins = "clk3_out_pee0";
1236 nvidia,function = "extperiph3"; 1291 nvidia,function = "extperiph3";
@@ -1515,7 +1570,7 @@
1515 regulator-always-on; 1570 regulator-always-on;
1516 }; 1571 };
1517 1572
1518 ldo0 { 1573 avdd_1v05_run: ldo0 {
1519 regulator-name = "+1.05V_RUN_AVDD"; 1574 regulator-name = "+1.05V_RUN_AVDD";
1520 regulator-min-microvolt = <1050000>; 1575 regulator-min-microvolt = <1050000>;
1521 regulator-max-microvolt = <1050000>; 1576 regulator-max-microvolt = <1050000>;
@@ -1619,6 +1674,18 @@
1619 nvidia,sys-clock-req-active-high; 1674 nvidia,sys-clock-req-active-high;
1620 }; 1675 };
1621 1676
1677 /* Serial ATA */
1678 sata@0,70020000 {
1679 status = "okay";
1680
1681 hvdd-supply = <&vdd_3v3_lp0>;
1682 vddio-supply = <&vdd_1v05_run>;
1683 avdd-supply = <&vdd_1v05_run>;
1684
1685 target-5v-supply = <&vdd_5v0_sata>;
1686 target-12v-supply = <&vdd_12v0_sata>;
1687 };
1688
1622 padctl@0,7009f000 { 1689 padctl@0,7009f000 {
1623 pinctrl-0 = <&padctl_default>; 1690 pinctrl-0 = <&padctl_default>;
1624 pinctrl-names = "default"; 1691 pinctrl-names = "default";
@@ -1828,6 +1895,29 @@
1828 enable-active-high; 1895 enable-active-high;
1829 vin-supply = <&vdd_5v0_sys>; 1896 vin-supply = <&vdd_5v0_sys>;
1830 }; 1897 };
1898
1899 /* Molex power connector */
1900 vdd_5v0_sata: regulator@13 {
1901 compatible = "regulator-fixed";
1902 reg = <13>;
1903 regulator-name = "+5V_SATA";
1904 regulator-min-microvolt = <5000000>;
1905 regulator-max-microvolt = <5000000>;
1906 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1907 enable-active-high;
1908 vin-supply = <&vdd_5v0_sys>;
1909 };
1910
1911 vdd_12v0_sata: regulator@14 {
1912 compatible = "regulator-fixed";
1913 reg = <14>;
1914 regulator-name = "+12V_SATA";
1915 regulator-min-microvolt = <12000000>;
1916 regulator-max-microvolt = <12000000>;
1917 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1918 enable-active-high;
1919 vin-supply = <&vdd_mux>;
1920 };
1831 }; 1921 };
1832 1922
1833 sound { 1923 sound {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
new file mode 100644
index 000000000000..7d0784ce4c74
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -0,0 +1,1136 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra124.dtsi"
5
6/ {
7 model = "Acer Chromebook 13 CB5-311";
8 compatible = "google,nyan-big", "nvidia,tegra124";
9
10 aliases {
11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@0,7000e000";
13 };
14
15 memory {
16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 };
18
19 host1x@0,50000000 {
20 hdmi@0,54280000 {
21 status = "okay";
22
23 vdd-supply = <&vdd_3v3_hdmi>;
24 pll-supply = <&vdd_hdmi_pll>;
25 hdmi-supply = <&vdd_5v0_hdmi>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio =
29 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
30 };
31
32 sor@0,54540000 {
33 status = "okay";
34
35 nvidia,dpaux = <&dpaux>;
36 nvidia,panel = <&panel>;
37 };
38
39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay";
42 };
43 };
44
45 pinmux@0,70000868 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinmux_default>;
48
49 pinmux_default: common {
50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1";
53 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57 dap2_din_pa4 {
58 nvidia,pins = "dap2_din_pa4";
59 nvidia,function = "i2s1";
60 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
61 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 };
64 dap2_dout_pa5 {
65 nvidia,pins = "dap2_dout_pa5",
66 "dap2_fs_pa2",
67 "dap2_sclk_pa3";
68 nvidia,function = "i2s1";
69 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 };
73 dvfs_pwm_px0 {
74 nvidia,pins = "dvfs_pwm_px0",
75 "dvfs_clk_px2";
76 nvidia,function = "cldvfs";
77 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81 ulpi_clk_py0 {
82 nvidia,pins = "ulpi_clk_py0",
83 "ulpi_nxt_py2",
84 "ulpi_stp_py3";
85 nvidia,function = "spi1";
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 };
90 ulpi_dir_py1 {
91 nvidia,pins = "ulpi_dir_py1";
92 nvidia,function = "spi1";
93 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 };
97 cam_i2c_scl_pbb1 {
98 nvidia,pins = "cam_i2c_scl_pbb1",
99 "cam_i2c_sda_pbb2";
100 nvidia,function = "i2c3";
101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,lock = <TEGRA_PIN_DISABLE>;
105 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
106 };
107 gen2_i2c_scl_pt5 {
108 nvidia,pins = "gen2_i2c_scl_pt5",
109 "gen2_i2c_sda_pt6";
110 nvidia,function = "i2c2";
111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,lock = <TEGRA_PIN_DISABLE>;
115 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
116 };
117 pg4 {
118 nvidia,pins = "pg4",
119 "pg5",
120 "pg6",
121 "pi3";
122 nvidia,function = "spi4";
123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 };
127 pg7 {
128 nvidia,pins = "pg7";
129 nvidia,function = "spi4";
130 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 };
134 ph1 {
135 nvidia,pins = "ph1";
136 nvidia,function = "pwm1";
137 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 };
141 pk0 {
142 nvidia,pins = "pk0",
143 "kb_row15_ps7",
144 "clk_32k_out_pa0";
145 nvidia,function = "soc";
146 nvidia,pull = <TEGRA_PIN_PULL_UP>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 };
150 sdmmc1_clk_pz0 {
151 nvidia,pins = "sdmmc1_clk_pz0";
152 nvidia,function = "sdmmc1";
153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157 sdmmc1_cmd_pz1 {
158 nvidia,pins = "sdmmc1_cmd_pz1",
159 "sdmmc1_dat0_py7",
160 "sdmmc1_dat1_py6",
161 "sdmmc1_dat2_py5",
162 "sdmmc1_dat3_py4";
163 nvidia,function = "sdmmc1";
164 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 nvidia,pull = <TEGRA_PIN_PULL_UP>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168 sdmmc3_clk_pa6 {
169 nvidia,pins = "sdmmc3_clk_pa6";
170 nvidia,function = "sdmmc3";
171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 };
175 sdmmc3_cmd_pa7 {
176 nvidia,pins = "sdmmc3_cmd_pa7",
177 "sdmmc3_dat0_pb7",
178 "sdmmc3_dat1_pb6",
179 "sdmmc3_dat2_pb5",
180 "sdmmc3_dat3_pb4",
181 "kb_col4_pq4",
182 "sdmmc3_clk_lb_out_pee4",
183 "sdmmc3_clk_lb_in_pee5",
184 "sdmmc3_cd_n_pv2";
185 nvidia,function = "sdmmc3";
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,pull = <TEGRA_PIN_PULL_UP>;
188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 };
190 sdmmc4_clk_pcc4 {
191 nvidia,pins = "sdmmc4_clk_pcc4";
192 nvidia,function = "sdmmc4";
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristate = <TEGRA_PIN_DISABLE>;
196 };
197 sdmmc4_cmd_pt7 {
198 nvidia,pins = "sdmmc4_cmd_pt7",
199 "sdmmc4_dat0_paa0",
200 "sdmmc4_dat1_paa1",
201 "sdmmc4_dat2_paa2",
202 "sdmmc4_dat3_paa3",
203 "sdmmc4_dat4_paa4",
204 "sdmmc4_dat5_paa5",
205 "sdmmc4_dat6_paa6",
206 "sdmmc4_dat7_paa7";
207 nvidia,function = "sdmmc4";
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 pwr_i2c_scl_pz6 {
213 nvidia,pins = "pwr_i2c_scl_pz6",
214 "pwr_i2c_sda_pz7";
215 nvidia,function = "i2cpwr";
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,lock = <TEGRA_PIN_DISABLE>;
220 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
221 };
222 jtag_rtck {
223 nvidia,pins = "jtag_rtck";
224 nvidia,function = "rtck";
225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229 clk_32k_in {
230 nvidia,pins = "clk_32k_in";
231 nvidia,function = "clk";
232 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 core_pwr_req {
237 nvidia,pins = "core_pwr_req";
238 nvidia,function = "pwron";
239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 cpu_pwr_req {
244 nvidia,pins = "cpu_pwr_req";
245 nvidia,function = "cpu";
246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 pwr_int_n {
251 nvidia,pins = "pwr_int_n";
252 nvidia,function = "pmi";
253 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 reset_out_n {
258 nvidia,pins = "reset_out_n";
259 nvidia,function = "reset_out_n";
260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 clk3_out_pee0 {
265 nvidia,pins = "clk3_out_pee0";
266 nvidia,function = "extperiph3";
267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 gen1_i2c_sda_pc5 {
272 nvidia,pins = "gen1_i2c_sda_pc5",
273 "gen1_i2c_scl_pc4";
274 nvidia,function = "i2c1";
275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 nvidia,lock = <TEGRA_PIN_DISABLE>;
279 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
280 };
281 hdmi_cec_pee3 {
282 nvidia,pins = "hdmi_cec_pee3";
283 nvidia,function = "cec";
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,lock = <TEGRA_PIN_DISABLE>;
288 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
289 };
290 hdmi_int_pn7 {
291 nvidia,pins = "hdmi_int_pn7";
292 nvidia,function = "rsvd1";
293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
297 ddc_scl_pv4 {
298 nvidia,pins = "ddc_scl_pv4",
299 "ddc_sda_pv5";
300 nvidia,function = "i2c4";
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,lock = <TEGRA_PIN_DISABLE>;
305 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
306 };
307 kb_row10_ps2 {
308 nvidia,pins = "kb_row10_ps2";
309 nvidia,function = "uarta";
310 nvidia,pull = <TEGRA_PIN_PULL_UP>;
311 nvidia,tristate = <TEGRA_PIN_DISABLE>;
312 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
313 };
314 kb_row9_ps1 {
315 nvidia,pins = "kb_row9_ps1";
316 nvidia,function = "uarta";
317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
320 };
321 usb_vbus_en0_pn4 {
322 nvidia,pins = "usb_vbus_en0_pn4",
323 "usb_vbus_en1_pn5";
324 nvidia,function = "usb";
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,lock = <TEGRA_PIN_DISABLE>;
329 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330 };
331 drive_sdio1 {
332 nvidia,pins = "drive_sdio1";
333 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
334 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
335 nvidia,pull-down-strength = <36>;
336 nvidia,pull-up-strength = <20>;
337 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
338 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
339 };
340 drive_sdio3 {
341 nvidia,pins = "drive_sdio3";
342 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
343 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
344 nvidia,pull-down-strength = <22>;
345 nvidia,pull-up-strength = <36>;
346 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
347 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
348 };
349 drive_gma {
350 nvidia,pins = "drive_gma";
351 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
352 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
353 nvidia,pull-down-strength = <2>;
354 nvidia,pull-up-strength = <1>;
355 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
356 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
357 nvidia,drive-type = <1>;
358 };
359 codec_irq_l {
360 nvidia,pins = "ph4";
361 nvidia,function = "gmi";
362 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
363 nvidia,tristate = <TEGRA_PIN_DISABLE>;
364 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365 };
366 lcd_bl_en {
367 nvidia,pins = "ph2";
368 nvidia,function = "gmi";
369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
372 };
373 touch_irq_l {
374 nvidia,pins = "gpio_w3_aud_pw3";
375 nvidia,function = "spi6";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_DISABLE>;
378 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379 };
380 tpm_davint_l {
381 nvidia,pins = "ph6";
382 nvidia,function = "gmi";
383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
386 };
387 ts_irq_l {
388 nvidia,pins = "pk2";
389 nvidia,function = "gmi";
390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393 };
394 ts_reset_l {
395 nvidia,pins = "pk4";
396 nvidia,function = "gmi";
397 nvidia,pull = <TEGRA_PIN_PULL_UP>;
398 nvidia,tristate = <TEGRA_PIN_DISABLE>;
399 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400 };
401 ts_shdn_l {
402 nvidia,pins = "pk1";
403 nvidia,function = "gmi";
404 nvidia,pull = <TEGRA_PIN_PULL_UP>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
407 };
408 ph7 {
409 nvidia,pins = "ph7";
410 nvidia,function = "gmi";
411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
414 };
415 kb_col0_ap {
416 nvidia,pins = "kb_col0_pq0";
417 nvidia,function = "rsvd4";
418 nvidia,pull = <TEGRA_PIN_PULL_UP>;
419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
420 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
421 };
422 lid_open {
423 nvidia,pins = "kb_row4_pr4";
424 nvidia,function = "rsvd3";
425 nvidia,pull = <TEGRA_PIN_PULL_UP>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
428 };
429 en_vdd_sd {
430 nvidia,pins = "kb_row0_pr0";
431 nvidia,function = "rsvd4";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
435 };
436 ac_ok {
437 nvidia,pins = "pj0";
438 nvidia,function = "gmi";
439 nvidia,pull = <TEGRA_PIN_PULL_UP>;
440 nvidia,tristate = <TEGRA_PIN_DISABLE>;
441 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
442 };
443 sensor_irq_l {
444 nvidia,pins = "pi6";
445 nvidia,function = "gmi";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449 };
450 wifi_en {
451 nvidia,pins = "gpio_x7_aud_px7";
452 nvidia,function = "rsvd4";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
456 };
457 en_vdd_bl {
458 nvidia,pins = "dap3_dout_pp2";
459 nvidia,function = "i2s2";
460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
463 };
464 en_vdd_hdmi {
465 nvidia,pins = "spdif_in_pk6";
466 nvidia,function = "spdif";
467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
468 nvidia,tristate = <TEGRA_PIN_DISABLE>;
469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
470 };
471 soc_warm_reset_l {
472 nvidia,pins = "pi5";
473 nvidia,function = "gmi";
474 nvidia,pull = <TEGRA_PIN_PULL_UP>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477 };
478 hp_det_l {
479 nvidia,pins = "pi7";
480 nvidia,function = "rsvd1";
481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484 };
485 mic_det_l {
486 nvidia,pins = "kb_row7_pr7";
487 nvidia,function = "rsvd2";
488 nvidia,pull = <TEGRA_PIN_PULL_UP>;
489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
490 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491 };
492 };
493 };
494
495 serial@0,70006000 {
496 /* Debug connector on the bottom of the board near SD card. */
497 status = "okay";
498 };
499
500 pwm@0,7000a000 {
501 status = "okay";
502 };
503
504 i2c@0,7000c000 {
505 status = "okay";
506 clock-frequency = <100000>;
507
508 acodec: audio-codec@10 {
509 compatible = "maxim,max98090";
510 reg = <0x10>;
511 interrupt-parent = <&gpio>;
512 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
513 };
514
515 temperature-sensor@4c {
516 compatible = "ti,tmp451";
517 reg = <0x4c>;
518 interrupt-parent = <&gpio>;
519 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
520
521 #thermal-sensor-cells = <1>;
522 };
523 };
524
525 i2c@0,7000c400 {
526 status = "okay";
527 clock-frequency = <100000>;
528 };
529
530 i2c@0,7000c500 {
531 status = "okay";
532 clock-frequency = <400000>;
533
534 tpm@20 {
535 compatible = "infineon,slb9645tt";
536 reg = <0x20>;
537 };
538 };
539
540 hdmi_ddc: i2c@0,7000c700 {
541 status = "okay";
542 clock-frequency = <100000>;
543 };
544
545 i2c@0,7000d000 {
546 status = "okay";
547 clock-frequency = <400000>;
548
549 pmic: pmic@40 {
550 compatible = "ams,as3722";
551 reg = <0x40>;
552 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
553
554 ams,system-power-controller;
555
556 #interrupt-cells = <2>;
557 interrupt-controller;
558
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 pinctrl-names = "default";
563 pinctrl-0 = <&as3722_default>;
564
565 as3722_default: pinmux {
566 gpio0 {
567 pins = "gpio0";
568 function = "gpio";
569 bias-pull-down;
570 };
571
572 gpio1 {
573 pins = "gpio1";
574 function = "gpio";
575 bias-pull-up;
576 };
577
578 gpio2_4_7 {
579 pins = "gpio2", "gpio4", "gpio7";
580 function = "gpio";
581 bias-pull-up;
582 };
583
584 gpio3_6 {
585 pins = "gpio3", "gpio6";
586 bias-high-impedance;
587 };
588
589 gpio5 {
590 pins = "gpio5";
591 function = "clk32k-out";
592 bias-pull-down;
593 };
594 };
595
596 regulators {
597 vsup-sd2-supply = <&vdd_5v0_sys>;
598 vsup-sd3-supply = <&vdd_5v0_sys>;
599 vsup-sd4-supply = <&vdd_5v0_sys>;
600 vsup-sd5-supply = <&vdd_5v0_sys>;
601 vin-ldo0-supply = <&vdd_1v35_lp0>;
602 vin-ldo1-6-supply = <&vdd_3v3_run>;
603 vin-ldo2-5-7-supply = <&vddio_1v8>;
604 vin-ldo3-4-supply = <&vdd_3v3_sys>;
605 vin-ldo9-10-supply = <&vdd_5v0_sys>;
606 vin-ldo11-supply = <&vdd_3v3_run>;
607
608 sd0 {
609 regulator-name = "+VDD_CPU_AP";
610 regulator-min-microvolt = <700000>;
611 regulator-max-microvolt = <1350000>;
612 regulator-min-microamp = <3500000>;
613 regulator-max-microamp = <3500000>;
614 regulator-always-on;
615 regulator-boot-on;
616 ams,ext-control = <2>;
617 };
618
619 sd1 {
620 regulator-name = "+VDD_CORE";
621 regulator-min-microvolt = <700000>;
622 regulator-max-microvolt = <1350000>;
623 regulator-min-microamp = <2500000>;
624 regulator-max-microamp = <4000000>;
625 regulator-always-on;
626 regulator-boot-on;
627 ams,ext-control = <1>;
628 };
629
630 vdd_1v35_lp0: sd2 {
631 regulator-name = "+1.35V_LP0(sd2)";
632 regulator-min-microvolt = <1350000>;
633 regulator-max-microvolt = <1350000>;
634 regulator-always-on;
635 regulator-boot-on;
636 };
637
638 sd3 {
639 regulator-name = "+1.35V_LP0(sd3)";
640 regulator-min-microvolt = <1350000>;
641 regulator-max-microvolt = <1350000>;
642 regulator-always-on;
643 regulator-boot-on;
644 };
645
646 vdd_1v05_run: sd4 {
647 regulator-name = "+1.05V_RUN";
648 regulator-min-microvolt = <1050000>;
649 regulator-max-microvolt = <1050000>;
650 };
651
652 vddio_1v8: sd5 {
653 regulator-name = "+1.8V_VDDIO";
654 regulator-min-microvolt = <1800000>;
655 regulator-max-microvolt = <1800000>;
656 regulator-boot-on;
657 regulator-always-on;
658 };
659
660 sd6 {
661 regulator-name = "+VDD_GPU_AP";
662 regulator-min-microvolt = <650000>;
663 regulator-max-microvolt = <1200000>;
664 regulator-min-microamp = <3500000>;
665 regulator-max-microamp = <3500000>;
666 regulator-boot-on;
667 regulator-always-on;
668 };
669
670 ldo0 {
671 regulator-name = "+1.05V_RUN_AVDD";
672 regulator-min-microvolt = <1050000>;
673 regulator-max-microvolt = <1050000>;
674 regulator-boot-on;
675 regulator-always-on;
676 ams,ext-control = <1>;
677 };
678
679 ldo1 {
680 regulator-name = "+1.8V_RUN_CAM";
681 regulator-min-microvolt = <1800000>;
682 regulator-max-microvolt = <1800000>;
683 };
684
685 ldo2 {
686 regulator-name = "+1.2V_GEN_AVDD";
687 regulator-min-microvolt = <1200000>;
688 regulator-max-microvolt = <1200000>;
689 regulator-boot-on;
690 regulator-always-on;
691 };
692
693 ldo3 {
694 regulator-name = "+1.00V_LP0_VDD_RTC";
695 regulator-min-microvolt = <1000000>;
696 regulator-max-microvolt = <1000000>;
697 regulator-boot-on;
698 regulator-always-on;
699 ams,enable-tracking;
700 };
701
702 vdd_run_cam: ldo4 {
703 regulator-name = "+3.3V_RUN_CAM";
704 regulator-min-microvolt = <2800000>;
705 regulator-max-microvolt = <2800000>;
706 };
707
708 ldo5 {
709 regulator-name = "+1.2V_RUN_CAM_FRONT";
710 regulator-min-microvolt = <1200000>;
711 regulator-max-microvolt = <1200000>;
712 };
713
714 vddio_sdmmc3: ldo6 {
715 regulator-name = "+VDDIO_SDMMC3";
716 regulator-min-microvolt = <1800000>;
717 regulator-max-microvolt = <3300000>;
718 };
719
720 ldo7 {
721 regulator-name = "+1.05V_RUN_CAM_REAR";
722 regulator-min-microvolt = <1050000>;
723 regulator-max-microvolt = <1050000>;
724 };
725
726 ldo9 {
727 regulator-name = "+2.8V_RUN_TOUCH";
728 regulator-min-microvolt = <2800000>;
729 regulator-max-microvolt = <2800000>;
730 };
731
732 ldo10 {
733 regulator-name = "+2.8V_RUN_CAM_AF";
734 regulator-min-microvolt = <2800000>;
735 regulator-max-microvolt = <2800000>;
736 };
737
738 ldo11 {
739 regulator-name = "+1.8V_RUN_VPP_FUSE";
740 regulator-min-microvolt = <1800000>;
741 regulator-max-microvolt = <1800000>;
742 };
743 };
744 };
745 };
746
747 spi@0,7000d400 {
748 status = "okay";
749
750 cros_ec: cros-ec@0 {
751 compatible = "google,cros-ec-spi";
752 spi-max-frequency = <3000000>;
753 interrupt-parent = <&gpio>;
754 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
755 reg = <0>;
756
757 google,cros-ec-spi-msg-delay = <2000>;
758
759 i2c-tunnel {
760 compatible = "google,cros-ec-i2c-tunnel";
761 #address-cells = <1>;
762 #size-cells = <0>;
763
764 google,remote-bus = <0>;
765
766 charger: bq24735@9 {
767 compatible = "ti,bq24735";
768 reg = <0x9>;
769 interrupt-parent = <&gpio>;
770 interrupts = <TEGRA_GPIO(J, 0)
771 GPIO_ACTIVE_HIGH>;
772 ti,ac-detect-gpios = <&gpio
773 TEGRA_GPIO(J, 0)
774 GPIO_ACTIVE_HIGH>;
775 };
776
777 battery: sbs-battery@b {
778 compatible = "sbs,sbs-battery";
779 reg = <0xb>;
780 sbs,i2c-retry-count = <2>;
781 sbs,poll-retry-count = <10>;
782 power-supplies = <&charger>;
783 };
784 };
785 };
786 };
787
788 spi@0,7000da00 {
789 status = "okay";
790 spi-max-frequency = <25000000>;
791
792 flash@0 {
793 compatible = "winbond,w25q32dw";
794 reg = <0>;
795 };
796 };
797
798 pmc@0,7000e400 {
799 nvidia,invert-interrupt;
800 nvidia,suspend-mode = <0>;
801 nvidia,cpu-pwr-good-time = <500>;
802 nvidia,cpu-pwr-off-time = <300>;
803 nvidia,core-pwr-good-time = <641 3845>;
804 nvidia,core-pwr-off-time = <61036>;
805 nvidia,core-power-req-active-high;
806 nvidia,sys-clock-req-active-high;
807 };
808
809 hda@0,70030000 {
810 status = "okay";
811 };
812
813 sdhci@0,700b0000 { /* WiFi/BT on this bus */
814 status = "okay";
815 power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
816 bus-width = <4>;
817 no-1-8-v;
818 non-removable;
819 };
820
821 sdhci@0,700b0400 { /* SD Card on this bus */
822 status = "okay";
823 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
824 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
825 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
826 bus-width = <4>;
827 no-1-8-v;
828 vqmmc-supply = <&vddio_sdmmc3>;
829 };
830
831 sdhci@0,700b0600 { /* eMMC on this bus */
832 status = "okay";
833 bus-width = <8>;
834 no-1-8-v;
835 non-removable;
836 };
837
838 ahub@0,70300000 {
839 i2s@0,70301100 {
840 status = "okay";
841 };
842 };
843
844 usb@0,7d000000 { /* Rear external USB port. */
845 status = "okay";
846 };
847
848 usb-phy@0,7d000000 {
849 status = "okay";
850 vbus-supply = <&vdd_usb1_vbus>;
851 };
852
853 usb@0,7d004000 { /* Internal webcam. */
854 status = "okay";
855 };
856
857 usb-phy@0,7d004000 {
858 status = "okay";
859 vbus-supply = <&vdd_run_cam>;
860 };
861
862 usb@0,7d008000 { /* Left external USB port. */
863 status = "okay";
864 };
865
866 usb-phy@0,7d008000 {
867 status = "okay";
868 vbus-supply = <&vdd_usb3_vbus>;
869 };
870
871 backlight: backlight {
872 compatible = "pwm-backlight";
873
874 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
875 power-supply = <&vdd_led>;
876 pwms = <&pwm 1 1000000>;
877
878 default-brightness-level = <224>;
879 brightness-levels =
880 < 0 1 2 3 4 5 6 7
881 8 9 10 11 12 13 14 15
882 16 17 18 19 20 21 22 23
883 24 25 26 27 28 29 30 31
884 32 33 34 35 36 37 38 39
885 40 41 42 43 44 45 46 47
886 48 49 50 51 52 53 54 55
887 56 57 58 59 60 61 62 63
888 64 65 66 67 68 69 70 71
889 72 73 74 75 76 77 78 79
890 80 81 82 83 84 85 86 87
891 88 89 90 91 92 93 94 95
892 96 97 98 99 100 101 102 103
893 104 105 106 107 108 109 110 111
894 112 113 114 115 116 117 118 119
895 120 121 122 123 124 125 126 127
896 128 129 130 131 132 133 134 135
897 136 137 138 139 140 141 142 143
898 144 145 146 147 148 149 150 151
899 152 153 154 155 156 157 158 159
900 160 161 162 163 164 165 166 167
901 168 169 170 171 172 173 174 175
902 176 177 178 179 180 181 182 183
903 184 185 186 187 188 189 190 191
904 192 193 194 195 196 197 198 199
905 200 201 202 203 204 205 206 207
906 208 209 210 211 212 213 214 215
907 216 217 218 219 220 221 222 223
908 224 225 226 227 228 229 230 231
909 232 233 234 235 236 237 238 239
910 240 241 242 243 244 245 246 247
911 248 249 250 251 252 253 254 255
912 256>;
913 };
914
915 clocks {
916 compatible = "simple-bus";
917 #address-cells = <1>;
918 #size-cells = <0>;
919
920 clk32k_in: clock@0 {
921 compatible = "fixed-clock";
922 reg = <0>;
923 #clock-cells = <0>;
924 clock-frequency = <32768>;
925 };
926 };
927
928 gpio-keys {
929 compatible = "gpio-keys";
930
931 lid {
932 label = "Lid";
933 gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
934 linux,input-type = <5>;
935 linux,code = <KEY_RESERVED>;
936 debounce-interval = <1>;
937 gpio-key,wakeup;
938 };
939
940 power {
941 label = "Power";
942 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
943 linux,code = <KEY_POWER>;
944 debounce-interval = <30>;
945 gpio-key,wakeup;
946 };
947 };
948
949 panel: panel {
950 compatible = "auo,b133xtn01";
951
952 backlight = <&backlight>;
953 ddc-i2c-bus = <&dpaux>;
954 };
955
956 regulators {
957 compatible = "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <0>;
960
961 vdd_mux: regulator@0 {
962 compatible = "regulator-fixed";
963 reg = <0>;
964 regulator-name = "+VDD_MUX";
965 regulator-min-microvolt = <12000000>;
966 regulator-max-microvolt = <12000000>;
967 regulator-always-on;
968 regulator-boot-on;
969 };
970
971 vdd_5v0_sys: regulator@1 {
972 compatible = "regulator-fixed";
973 reg = <1>;
974 regulator-name = "+5V_SYS";
975 regulator-min-microvolt = <5000000>;
976 regulator-max-microvolt = <5000000>;
977 regulator-always-on;
978 regulator-boot-on;
979 vin-supply = <&vdd_mux>;
980 };
981
982 vdd_3v3_sys: regulator@2 {
983 compatible = "regulator-fixed";
984 reg = <2>;
985 regulator-name = "+3.3V_SYS";
986 regulator-min-microvolt = <3300000>;
987 regulator-max-microvolt = <3300000>;
988 regulator-always-on;
989 regulator-boot-on;
990 vin-supply = <&vdd_mux>;
991 };
992
993 vdd_3v3_run: regulator@3 {
994 compatible = "regulator-fixed";
995 reg = <3>;
996 regulator-name = "+3.3V_RUN";
997 regulator-min-microvolt = <3300000>;
998 regulator-max-microvolt = <3300000>;
999 regulator-always-on;
1000 regulator-boot-on;
1001 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1002 enable-active-high;
1003 vin-supply = <&vdd_3v3_sys>;
1004 };
1005
1006 vdd_3v3_hdmi: regulator@4 {
1007 compatible = "regulator-fixed";
1008 reg = <4>;
1009 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1010 regulator-min-microvolt = <3300000>;
1011 regulator-max-microvolt = <3300000>;
1012 vin-supply = <&vdd_3v3_run>;
1013 };
1014
1015 vdd_led: regulator@5 {
1016 compatible = "regulator-fixed";
1017 reg = <5>;
1018 regulator-name = "+VDD_LED";
1019 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1020 enable-active-high;
1021 vin-supply = <&vdd_mux>;
1022 };
1023
1024 vdd_5v0_ts: regulator@6 {
1025 compatible = "regulator-fixed";
1026 reg = <6>;
1027 regulator-name = "+5V_VDD_TS_SW";
1028 regulator-min-microvolt = <5000000>;
1029 regulator-max-microvolt = <5000000>;
1030 regulator-boot-on;
1031 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1032 enable-active-high;
1033 vin-supply = <&vdd_5v0_sys>;
1034 };
1035
1036 vdd_usb1_vbus: regulator@7 {
1037 compatible = "regulator-fixed";
1038 reg = <7>;
1039 regulator-name = "+5V_USB_HS";
1040 regulator-min-microvolt = <5000000>;
1041 regulator-max-microvolt = <5000000>;
1042 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1043 enable-active-high;
1044 gpio-open-drain;
1045 vin-supply = <&vdd_5v0_sys>;
1046 };
1047
1048 vdd_usb3_vbus: regulator@8 {
1049 compatible = "regulator-fixed";
1050 reg = <8>;
1051 regulator-name = "+5V_USB_SS";
1052 regulator-min-microvolt = <5000000>;
1053 regulator-max-microvolt = <5000000>;
1054 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1055 enable-active-high;
1056 gpio-open-drain;
1057 vin-supply = <&vdd_5v0_sys>;
1058 };
1059
1060 vdd_3v3_panel: regulator@9 {
1061 compatible = "regulator-fixed";
1062 reg = <9>;
1063 regulator-name = "+3.3V_PANEL";
1064 regulator-min-microvolt = <3300000>;
1065 regulator-max-microvolt = <3300000>;
1066 gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
1067 enable-active-high;
1068 vin-supply = <&vdd_3v3_run>;
1069 };
1070
1071 vdd_3v3_lp0: regulator@10 {
1072 compatible = "regulator-fixed";
1073 reg = <10>;
1074 regulator-name = "+3.3V_LP0";
1075 regulator-min-microvolt = <3300000>;
1076 regulator-max-microvolt = <3300000>;
1077 /*
1078 * TODO: find a way to wire this up with the USB EHCI
1079 * controllers so that it can be enabled on demand.
1080 */
1081 regulator-always-on;
1082 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1083 enable-active-high;
1084 vin-supply = <&vdd_3v3_sys>;
1085 };
1086
1087 vdd_hdmi_pll: regulator@11 {
1088 compatible = "regulator-fixed";
1089 reg = <11>;
1090 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1091 regulator-min-microvolt = <1050000>;
1092 regulator-max-microvolt = <1050000>;
1093 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1094 vin-supply = <&vdd_1v05_run>;
1095 };
1096
1097 vdd_5v0_hdmi: regulator@12 {
1098 compatible = "regulator-fixed";
1099 reg = <12>;
1100 regulator-name = "+5V_HDMI_CON";
1101 regulator-min-microvolt = <5000000>;
1102 regulator-max-microvolt = <5000000>;
1103 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1104 enable-active-high;
1105 vin-supply = <&vdd_5v0_sys>;
1106 };
1107 };
1108
1109 sound {
1110 compatible = "nvidia,tegra-audio-max98090-nyan-big",
1111 "nvidia,tegra-audio-max98090";
1112 nvidia,model = "Acer Chromebook 13";
1113
1114 nvidia,audio-routing =
1115 "Headphones", "HPR",
1116 "Headphones", "HPL",
1117 "Speakers", "SPKR",
1118 "Speakers", "SPKL",
1119 "Mic Jack", "MICBIAS",
1120 "DMICL", "Int Mic",
1121 "DMICR", "Int Mic",
1122 "IN34", "Mic Jack";
1123
1124 nvidia,i2s-controller = <&tegra_i2s1>;
1125 nvidia,audio-codec = <&acodec>;
1126
1127 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1128 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1129 <&tegra_car TEGRA124_CLK_EXTERN1>;
1130 clock-names = "pll_a", "pll_a_out0", "mclk";
1131
1132 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1133 };
1134};
1135
1136#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 70ad91d1a20b..13008858e967 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -36,17 +36,17 @@
36 nvidia,panel = <&panel>; 36 nvidia,panel = <&panel>;
37 }; 37 };
38 38
39 dpaux: dpaux@0,545c0000 { 39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>; 40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 }; 43 };
44 44
45 pinmux: pinmux@0,70000868 { 45 pinmux: pinmux@0,70000868 {
46 pinctrl-names = "default"; 46 pinctrl-names = "boot";
47 pinctrl-0 = <&pinmux_default>; 47 pinctrl-0 = <&pinmux_boot>;
48 48
49 pinmux_default: common { 49 pinmux_boot: common {
50 dap_mclk1_pw4 { 50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4"; 51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1"; 52 nvidia,function = "extperiph1";
@@ -587,7 +587,7 @@
587 status = "okay"; 587 status = "okay";
588 }; 588 };
589 589
590 pwm: pwm@0,7000a000 { 590 pwm@0,7000a000 {
591 status = "okay"; 591 status = "okay";
592 }; 592 };
593 593
@@ -606,6 +606,14 @@
606 i2c@0,7000c400 { 606 i2c@0,7000c400 {
607 status = "okay"; 607 status = "okay";
608 clock-frequency = <100000>; 608 clock-frequency = <100000>;
609
610 trackpad@4b {
611 compatible = "atmel,maxtouch";
612 reg = <0x4b>;
613 interrupt-parent = <&gpio>;
614 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
615 linux,gpio-keymap = <0 0 0 BTN_LEFT>;
616 };
609 }; 617 };
610 618
611 i2c@0,7000c500 { 619 i2c@0,7000c500 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916efd6fa9..478c555ebd96 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -12,6 +12,72 @@
12 #address-cells = <2>; 12 #address-cells = <2>;
13 #size-cells = <2>; 13 #size-cells = <2>;
14 14
15 pcie-controller@0,01003000 {
16 compatible = "nvidia,tegra124-pcie";
17 device_type = "pci";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
25
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41 <&tegra_car TEGRA124_CLK_AFI>,
42 <&tegra_car TEGRA124_CLK_PLL_E>,
43 <&tegra_car TEGRA124_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
52 phy-names = "pcie";
53
54 pci@1,0 {
55 device_type = "pci";
56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57 reg = <0x000800 0 0 0 0>;
58 status = "disabled";
59
60 #address-cells = <3>;
61 #size-cells = <2>;
62 ranges;
63
64 nvidia,num-lanes = <2>;
65 };
66
67 pci@2,0 {
68 device_type = "pci";
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 status = "disabled";
72
73 #address-cells = <3>;
74 #size-cells = <2>;
75 ranges;
76
77 nvidia,num-lanes = <1>;
78 };
79 };
80
15 host1x@0,50000000 { 81 host1x@0,50000000 {
16 compatible = "nvidia,tegra124-host1x", "simple-bus"; 82 compatible = "nvidia,tegra124-host1x", "simple-bus";
17 reg = <0x0 0x50000000 0x0 0x00034000>; 83 reg = <0x0 0x50000000 0x0 0x00034000>;
@@ -78,7 +144,7 @@
78 status = "disabled"; 144 status = "disabled";
79 }; 145 };
80 146
81 dpaux@0,545c0000 { 147 dpaux: dpaux@0,545c0000 {
82 compatible = "nvidia,tegra124-dpaux"; 148 compatible = "nvidia,tegra124-dpaux";
83 reg = <0x0 0x545c0000 0x0 0x00040000>; 149 reg = <0x0 0x545c0000 0x0 0x00040000>;
84 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 150 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,6 +203,11 @@
137 #reset-cells = <1>; 203 #reset-cells = <1>;
138 }; 204 };
139 205
206 flow-controller@0,60007000 {
207 compatible = "nvidia,tegra124-flowctrl";
208 reg = <0x0 0x60007000 0x0 0x1000>;
209 };
210
140 gpio: gpio@0,6000d000 { 211 gpio: gpio@0,6000d000 {
141 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 212 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
142 reg = <0x0 0x6000d000 0x0 0x1000>; 213 reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -267,7 +338,7 @@
267 status = "disabled"; 338 status = "disabled";
268 }; 339 };
269 340
270 pwm@0,7000a000 { 341 pwm: pwm@0,7000a000 {
271 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 342 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
272 reg = <0x0 0x7000a000 0x0 0x100>; 343 reg = <0x0 0x7000a000 0x0 0x100>;
273 #pwm-cells = <2>; 344 #pwm-cells = <2>;
@@ -480,6 +551,31 @@
480 reset-names = "fuse"; 551 reset-names = "fuse";
481 }; 552 };
482 553
554 sata@0,70020000 {
555 compatible = "nvidia,tegra124-ahci";
556
557 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
558 <0x0 0x70020000 0x0 0x7000>; /* SATA */
559
560 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
561
562 clocks = <&tegra_car TEGRA124_CLK_SATA>,
563 <&tegra_car TEGRA124_CLK_SATA_OOB>,
564 <&tegra_car TEGRA124_CLK_CML1>,
565 <&tegra_car TEGRA124_CLK_PLL_E>;
566 clock-names = "sata", "sata-oob", "cml1", "pll_e";
567
568 resets = <&tegra_car 124>,
569 <&tegra_car 123>,
570 <&tegra_car 129>;
571 reset-names = "sata", "sata-oob", "sata-cold";
572
573 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
574 phy-names = "sata-phy";
575
576 status = "disabled";
577 };
578
483 hda@0,70030000 { 579 hda@0,70030000 {
484 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 580 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
485 reg = <0x0 0x70030000 0x0 0x10000>; 581 reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 1908f6937e53..3b374c49d04d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -190,6 +190,11 @@
190 #reset-cells = <1>; 190 #reset-cells = <1>;
191 }; 191 };
192 192
193 flow-controller@60007000 {
194 compatible = "nvidia,tegra20-flowctrl";
195 reg = <0x60007000 0x1000>;
196 };
197
193 apbdma: dma@6000a000 { 198 apbdma: dma@6000a000 {
194 compatible = "nvidia,tegra20-apbdma"; 199 compatible = "nvidia,tegra20-apbdma";
195 reg = <0x6000a000 0x1200>; 200 reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 6b35c29278d7..aa6ccea13d30 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -272,6 +272,11 @@
272 #reset-cells = <1>; 272 #reset-cells = <1>;
273 }; 273 };
274 274
275 flow-controller@60007000 {
276 compatible = "nvidia,tegra30-flowctrl";
277 reg = <0x60007000 0x1000>;
278 };
279
275 apbdma: dma@6000a000 { 280 apbdma: dma@6000a000 {
276 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 281 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
277 reg = <0x6000a000 0x1400>; 282 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 756c986995a3..2efb2058ba49 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -41,7 +41,7 @@
41 bank-width = <4>; 41 bank-width = <4>;
42 }; 42 };
43 43
44 vram@2,00000000 { 44 v2m_video_ram: vram@2,00000000 {
45 compatible = "arm,vexpress-vram"; 45 compatible = "arm,vexpress-vram";
46 reg = <2 0x00000000 0x00800000>; 46 reg = <2 0x00000000 0x00800000>;
47 }; 47 };
@@ -246,9 +246,41 @@
246 clcd@1f0000 { 246 clcd@1f0000 {
247 compatible = "arm,pl111", "arm,primecell"; 247 compatible = "arm,pl111", "arm,primecell";
248 reg = <0x1f0000 0x1000>; 248 reg = <0x1f0000 0x1000>;
249 interrupt-names = "combined";
249 interrupts = <14>; 250 interrupts = <14>;
250 clocks = <&v2m_oscclk1>, <&smbclk>; 251 clocks = <&v2m_oscclk1>, <&smbclk>;
251 clock-names = "clcdclk", "apb_pclk"; 252 clock-names = "clcdclk", "apb_pclk";
253 memory-region = <&v2m_video_ram>;
254 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
255
256 port {
257 v2m_clcd_pads: endpoint {
258 remote-endpoint = <&v2m_clcd_panel>;
259 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
260 };
261 };
262
263 panel {
264 compatible = "panel-dpi";
265
266 port {
267 v2m_clcd_panel: endpoint {
268 remote-endpoint = <&v2m_clcd_pads>;
269 };
270 };
271
272 panel-timing {
273 clock-frequency = <25175000>;
274 hactive = <640>;
275 hback-porch = <40>;
276 hfront-porch = <24>;
277 hsync-len = <96>;
278 vactive = <480>;
279 vback-porch = <32>;
280 vfront-porch = <11>;
281 vsync-len = <2>;
282 };
283 };
252 }; 284 };
253 }; 285 };
254 286
@@ -350,7 +382,7 @@
350 /* CLCD clock */ 382 /* CLCD clock */
351 compatible = "arm,vexpress-osc"; 383 compatible = "arm,vexpress-osc";
352 arm,vexpress-sysreg,func = <1 1>; 384 arm,vexpress-sysreg,func = <1 1>;
353 freq-range = <23750000 63500000>; 385 freq-range = <23750000 65000000>;
354 #clock-cells = <0>; 386 #clock-cells = <0>;
355 clock-output-names = "v2m:oscclk1"; 387 clock-output-names = "v2m:oscclk1";
356 }; 388 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index ba856d604fb7..cb3090f919a7 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -40,7 +40,7 @@
40 bank-width = <4>; 40 bank-width = <4>;
41 }; 41 };
42 42
43 vram@3,00000000 { 43 v2m_video_ram: vram@3,00000000 {
44 compatible = "arm,vexpress-vram"; 44 compatible = "arm,vexpress-vram";
45 reg = <3 0x00000000 0x00800000>; 45 reg = <3 0x00000000 0x00800000>;
46 }; 46 };
@@ -245,9 +245,41 @@
245 clcd@1f000 { 245 clcd@1f000 {
246 compatible = "arm,pl111", "arm,primecell"; 246 compatible = "arm,pl111", "arm,primecell";
247 reg = <0x1f000 0x1000>; 247 reg = <0x1f000 0x1000>;
248 interrupt-names = "combined";
248 interrupts = <14>; 249 interrupts = <14>;
249 clocks = <&v2m_oscclk1>, <&smbclk>; 250 clocks = <&v2m_oscclk1>, <&smbclk>;
250 clock-names = "clcdclk", "apb_pclk"; 251 clock-names = "clcdclk", "apb_pclk";
252 memory-region = <&v2m_video_ram>;
253 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
254
255 port {
256 v2m_clcd_pads: endpoint {
257 remote-endpoint = <&v2m_clcd_panel>;
258 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
259 };
260 };
261
262 panel {
263 compatible = "panel-dpi";
264
265 port {
266 v2m_clcd_panel: endpoint {
267 remote-endpoint = <&v2m_clcd_pads>;
268 };
269 };
270
271 panel-timing {
272 clock-frequency = <25175000>;
273 hactive = <640>;
274 hback-porch = <40>;
275 hfront-porch = <24>;
276 hsync-len = <96>;
277 vactive = <480>;
278 vback-porch = <32>;
279 vfront-porch = <11>;
280 vsync-len = <2>;
281 };
282 };
251 }; 283 };
252 }; 284 };
253 285
@@ -349,7 +381,7 @@
349 /* CLCD clock */ 381 /* CLCD clock */
350 compatible = "arm,vexpress-osc"; 382 compatible = "arm,vexpress-osc";
351 arm,vexpress-sysreg,func = <1 1>; 383 arm,vexpress-sysreg,func = <1 1>;
352 freq-range = <23750000 63500000>; 384 freq-range = <23750000 65000000>;
353 #clock-cells = <0>; 385 #clock-cells = <0>;
354 clock-output-names = "v2m:oscclk1"; 386 clock-output-names = "v2m:oscclk1";
355 }; 387 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 62d9b225dcce..23662b5a5e9d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -70,9 +70,40 @@
70 clcd@10020000 { 70 clcd@10020000 {
71 compatible = "arm,pl111", "arm,primecell"; 71 compatible = "arm,pl111", "arm,primecell";
72 reg = <0x10020000 0x1000>; 72 reg = <0x10020000 0x1000>;
73 interrupt-names = "combined";
73 interrupts = <0 44 4>; 74 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>; 75 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk"; 76 clock-names = "clcdclk", "apb_pclk";
77 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
78
79 port {
80 clcd_pads: endpoint {
81 remote-endpoint = <&clcd_panel>;
82 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
83 };
84 };
85
86 panel {
87 compatible = "panel-dpi";
88
89 port {
90 clcd_panel: endpoint {
91 remote-endpoint = <&clcd_pads>;
92 };
93 };
94
95 panel-timing {
96 clock-frequency = <63500127>;
97 hactive = <1024>;
98 hback-porch = <152>;
99 hfront-porch = <48>;
100 hsync-len = <104>;
101 vactive = <768>;
102 vback-porch = <23>;
103 vfront-porch = <3>;
104 vsync-len = <4>;
105 };
106 };
76 }; 107 };
77 108
78 memory-controller@100e0000 { 109 memory-controller@100e0000 {
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fb306679341
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf610-colibri.dtsi"
12
13/ {
14 model = "Toradex Colibri VF61 on Colibri Evaluation Board";
15 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20};
21
22&esdhc1 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_esdhc1>;
25 bus-width = <4>;
26 status = "okay";
27};
28
29&fec1 {
30 phy-mode = "rmii";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec1>;
33 status = "okay";
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 status = "okay";
42};
43
44&uart2 {
45 status = "okay";
46};
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dtsi
index aecc7dbc65e8..0cd83434b073 100644
--- a/arch/arm/boot/dts/vf610-colibri.dts
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -7,16 +7,11 @@
7 * (at your option) any later version. 7 * (at your option) any later version.
8 */ 8 */
9 9
10/dts-v1/;
11#include "vf610.dtsi" 10#include "vf610.dtsi"
12 11
13/ { 12/ {
14 model = "Toradex Colibri VF61 COM"; 13 model = "Toradex Colibri VF61 COM";
15 compatible = "toradex,vf610-colibri", "fsl,vf610"; 14 compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20 15
21 memory { 16 memory {
22 reg = <0x80000000 0x10000000>; 17 reg = <0x80000000 0x10000000>;
@@ -36,14 +31,12 @@
36 pinctrl-names = "default"; 31 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc1>; 32 pinctrl-0 = <&pinctrl_esdhc1>;
38 bus-width = <4>; 33 bus-width = <4>;
39 status = "okay";
40}; 34};
41 35
42&fec1 { 36&fec1 {
43 phy-mode = "rmii"; 37 phy-mode = "rmii";
44 pinctrl-names = "default"; 38 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_fec1>; 39 pinctrl-0 = <&pinctrl_fec1>;
46 status = "okay";
47}; 40};
48 41
49&L2 { 42&L2 {
@@ -54,25 +47,32 @@
54&uart0 { 47&uart0 {
55 pinctrl-names = "default"; 48 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_uart0>; 49 pinctrl-0 = <&pinctrl_uart0>;
57 status = "okay";
58}; 50};
59 51
60&uart1 { 52&uart1 {
61 pinctrl-names = "default"; 53 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_uart1>; 54 pinctrl-0 = <&pinctrl_uart1>;
63 status = "okay";
64}; 55};
65 56
66&uart2 { 57&uart2 {
67 pinctrl-names = "default"; 58 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_uart2>; 59 pinctrl-0 = <&pinctrl_uart2>;
60};
61
62&usbdev0 {
63 disable-over-current;
64 status = "okay";
65};
66
67&usbh1 {
68 disable-over-current;
69 status = "okay"; 69 status = "okay";
70}; 70};
71 71
72&iomuxc { 72&iomuxc {
73 vf610-colibri { 73 vf610-colibri {
74 pinctrl_esdhc1: esdhc1grp { 74 pinctrl_esdhc1: esdhc1grp {
75 fsl,fsl,pins = < 75 fsl,pins = <
76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index e4bffbae515f..189b6975fe7d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -220,8 +220,6 @@
220 VF610_PAD_PTB1__FTM0_CH1 0x1582 220 VF610_PAD_PTB1__FTM0_CH1 0x1582
221 VF610_PAD_PTB2__FTM0_CH2 0x1582 221 VF610_PAD_PTB2__FTM0_CH2 0x1582
222 VF610_PAD_PTB3__FTM0_CH3 0x1582 222 VF610_PAD_PTB3__FTM0_CH3 0x1582
223 VF610_PAD_PTB6__FTM0_CH6 0x1582
224 VF610_PAD_PTB7__FTM0_CH7 0x1582
225 >; 223 >;
226 }; 224 };
227 225
@@ -243,6 +241,13 @@
243 VF610_PAD_PTB5__UART1_RX 0x21a1 241 VF610_PAD_PTB5__UART1_RX 0x21a1
244 >; 242 >;
245 }; 243 };
244
245 pinctrl_uart2: uart2grp {
246 fsl,pins = <
247 VF610_PAD_PTB6__UART2_TX 0x21a2
248 VF610_PAD_PTB7__UART2_RX 0x21a1
249 >;
250 };
246 }; 251 };
247}; 252};
248 253
@@ -264,3 +269,19 @@
264 pinctrl-0 = <&pinctrl_uart1>; 269 pinctrl-0 = <&pinctrl_uart1>;
265 status = "okay"; 270 status = "okay";
266}; 271};
272
273&uart2 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_uart2>;
276 status = "okay";
277};
278
279&usbdev0 {
280 disable-over-current;
281 status = "okay";
282};
283
284&usbh1 {
285 disable-over-current;
286 status = "okay";
287};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 583dd363c9dc..4d2ec32de96f 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -27,6 +27,8 @@
27 gpio2 = &gpio3; 27 gpio2 = &gpio3;
28 gpio3 = &gpio4; 28 gpio3 = &gpio4;
29 gpio4 = &gpio5; 29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
30 }; 32 };
31 33
32 cpus { 34 cpus {
@@ -297,9 +299,25 @@
297 gpio-ranges = <&iomuxc 0 128 7>; 299 gpio-ranges = <&iomuxc 0 128 7>;
298 }; 300 };
299 301
300 anatop@40050000 { 302 anatop: anatop@40050000 {
301 compatible = "fsl,vf610-anatop"; 303 compatible = "fsl,vf610-anatop", "syscon";
302 reg = <0x40050000 0x1000>; 304 reg = <0x40050000 0x400>;
305 };
306
307 usbphy0: usbphy@40050800 {
308 compatible = "fsl,vf610-usbphy";
309 reg = <0x40050800 0x400>;
310 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks VF610_CLK_USBPHY0>;
312 fsl,anatop = <&anatop>;
313 };
314
315 usbphy1: usbphy@40050c00 {
316 compatible = "fsl,vf610-usbphy";
317 reg = <0x40050c00 0x400>;
318 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks VF610_CLK_USBPHY1>;
320 fsl,anatop = <&anatop>;
303 }; 321 };
304 322
305 i2c0: i2c@40066000 { 323 i2c0: i2c@40066000 {
@@ -321,6 +339,24 @@
321 reg = <0x4006b000 0x1000>; 339 reg = <0x4006b000 0x1000>;
322 #clock-cells = <1>; 340 #clock-cells = <1>;
323 }; 341 };
342
343 usbdev0: usb@40034000 {
344 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
345 reg = <0x40034000 0x800>;
346 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks VF610_CLK_USBC0>;
348 fsl,usbphy = <&usbphy0>;
349 fsl,usbmisc = <&usbmisc0 0>;
350 dr_mode = "peripheral";
351 status = "disabled";
352 };
353
354 usbmisc0: usb@40034800 {
355 #index-cells = <1>;
356 compatible = "fsl,vf610-usbmisc";
357 reg = <0x40034800 0x200>;
358 clocks = <&clks VF610_CLK_USBC0>;
359 };
324 }; 360 };
325 361
326 aips1: aips-bus@40080000 { 362 aips1: aips-bus@40080000 {
@@ -383,6 +419,24 @@
383 status = "disabled"; 419 status = "disabled";
384 }; 420 };
385 421
422 usbh1: usb@400b4000 {
423 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
424 reg = <0x400b4000 0x800>;
425 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks VF610_CLK_USBC1>;
427 fsl,usbphy = <&usbphy1>;
428 fsl,usbmisc = <&usbmisc1 0>;
429 dr_mode = "host";
430 status = "disabled";
431 };
432
433 usbmisc1: usb@400b4800 {
434 #index-cells = <1>;
435 compatible = "fsl,vf610-usbmisc";
436 reg = <0x400b4800 0x200>;
437 clocks = <&clks VF610_CLK_USBC1>;
438 };
439
386 ftm: ftm@400b8000 { 440 ftm: ftm@400b8000 {
387 compatible = "fsl,ftm-timer"; 441 compatible = "fsl,ftm-timer";
388 reg = <0x400b8000 0x1000 0x400b9000 0x1000>; 442 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 587cadcf7001..24036c440440 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -200,6 +200,8 @@
200 interrupts = <0 22 4>; 200 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
202 clock-names = "pclk", "hclk", "tx_clk"; 202 clock-names = "pclk", "hclk", "tx_clk";
203 #address-cells = <1>;
204 #size-cells = <0>;
203 }; 205 };
204 206
205 gem1: ethernet@e000c000 { 207 gem1: ethernet@e000c000 {
@@ -209,6 +211,8 @@
209 interrupts = <0 45 4>; 211 interrupts = <0 45 4>;
210 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
211 clock-names = "pclk", "hclk", "tx_clk"; 213 clock-names = "pclk", "hclk", "tx_clk";
214 #address-cells = <1>;
215 #size-cells = <0>;
212 }; 216 };
213 217
214 sdhci0: sdhci@e0100000 { 218 sdhci0: sdhci@e0100000 {
@@ -219,7 +223,7 @@
219 interrupt-parent = <&intc>; 223 interrupt-parent = <&intc>;
220 interrupts = <0 24 4>; 224 interrupts = <0 24 4>;
221 reg = <0xe0100000 0x1000>; 225 reg = <0xe0100000 0x1000>;
222 } ; 226 };
223 227
224 sdhci1: sdhci@e0101000 { 228 sdhci1: sdhci@e0101000 {
225 compatible = "arasan,sdhci-8.9a"; 229 compatible = "arasan,sdhci-8.9a";
@@ -229,7 +233,7 @@
229 interrupt-parent = <&intc>; 233 interrupt-parent = <&intc>;
230 interrupts = <0 47 4>; 234 interrupts = <0 47 4>;
231 reg = <0xe0101000 0x1000>; 235 reg = <0xe0101000 0x1000>;
232 } ; 236 };
233 237
234 slcr: slcr@f8000000 { 238 slcr: slcr@f8000000 {
235 #address-cells = <1>; 239 #address-cells = <1>;
@@ -261,6 +265,8 @@
261 compatible = "arm,pl330", "arm,primecell"; 265 compatible = "arm,pl330", "arm,primecell";
262 reg = <0xf8003000 0x1000>; 266 reg = <0xf8003000 0x1000>;
263 interrupt-parent = <&intc>; 267 interrupt-parent = <&intc>;
268 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
269 "dma4", "dma5", "dma6", "dma7";
264 interrupts = <0 13 4>, 270 interrupts = <0 13 4>,
265 <0 14 4>, <0 15 4>, 271 <0 14 4>, <0 15 4>,
266 <0 16 4>, <0 17 4>, 272 <0 16 4>, <0 17 4>,
@@ -276,7 +282,7 @@
276 devcfg: devcfg@f8007000 { 282 devcfg: devcfg@f8007000 {
277 compatible = "xlnx,zynq-devcfg-1.0"; 283 compatible = "xlnx,zynq-devcfg-1.0";
278 reg = <0xf8007000 0x100>; 284 reg = <0xf8007000 0x100>;
279 } ; 285 };
280 286
281 global_timer: timer@f8f00200 { 287 global_timer: timer@f8f00200 {
282 compatible = "arm,cortex-a9-global-timer"; 288 compatible = "arm,cortex-a9-global-timer";
@@ -308,6 +314,6 @@
308 compatible = "arm,cortex-a9-twd-timer"; 314 compatible = "arm,cortex-a9-twd-timer";
309 reg = <0xf8f00600 0x20>; 315 reg = <0xf8f00600 0x20>;
310 clocks = <&clkc 4>; 316 clocks = <&clkc 4>;
311 } ; 317 };
312 }; 318 };
313}; 319};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 41afd9da6876..e1f51ca127fe 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -25,7 +25,7 @@
25 25
26 memory { 26 memory {
27 device_type = "memory"; 27 device_type = "memory";
28 reg = <0 0x40000000>; 28 reg = <0x0 0x40000000>;
29 }; 29 };
30 30
31 chosen { 31 chosen {
@@ -38,8 +38,6 @@
38 status = "okay"; 38 status = "okay";
39 phy-mode = "rgmii-id"; 39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>; 40 phy-handle = <&ethernet_phy>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 41
44 ethernet_phy: ethernet-phy@0 { 42 ethernet_phy: ethernet-phy@0 {
45 /* Marvell 88E1318 */ 43 /* Marvell 88E1318 */
@@ -53,6 +51,29 @@
53 51
54&i2c0 { 52&i2c0 {
55 status = "okay"; 53 status = "okay";
54
55 isl9305: isl9305@68 {
56 compatible = "isl,isl9305";
57 reg = <0x68>;
58
59 regulators {
60 dcd1 {
61 regulator-name = "VDD_DSP";
62 regulator-always-on;
63 };
64 dcd2 {
65 regulator-name = "1P35V";
66 regulator-always-on;
67 };
68 ldo1 {
69 regulator-name = "VDD_ADJ";
70 };
71 ldo2 {
72 regulator-name = "VDD_GPIO";
73 regulator-always-on;
74 };
75 };
76 };
56}; 77};
57 78
58&sdhci1 { 79&sdhci1 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 835c3089c61c..94e2cda6f9b6 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -27,6 +27,15 @@
27 bootargs = "console=ttyPS0,115200 earlyprintk"; 27 bootargs = "console=ttyPS0,115200 earlyprintk";
28 }; 28 };
29 29
30 leds {
31 compatible = "gpio-leds";
32
33 ds23 {
34 label = "ds23";
35 gpios = <&gpio0 10 0>;
36 linux,default-trigger = "heartbeat";
37 };
38 };
30}; 39};
31 40
32&can0 { 41&can0 {
@@ -35,7 +44,12 @@
35 44
36&gem0 { 45&gem0 {
37 status = "okay"; 46 status = "okay";
38 phy-mode = "rgmii"; 47 phy-mode = "rgmii-id";
48 phy-handle = <&ethernet_phy>;
49
50 ethernet_phy: ethernet-phy@7 {
51 reg = <7>;
52 };
39}; 53};
40 54
41&i2c0 { 55&i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 4cc9913078cd..a8bbdfbc7093 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * Copyright (C) 2013 Xilinx
5 * 4 *
6 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -21,7 +20,7 @@
21 20
22 memory { 21 memory {
23 device_type = "memory"; 22 device_type = "memory";
24 reg = <0 0x40000000>; 23 reg = <0x0 0x40000000>;
25 }; 24 };
26 25
27 chosen { 26 chosen {
@@ -32,7 +31,12 @@
32 31
33&gem0 { 32&gem0 {
34 status = "okay"; 33 status = "okay";
35 phy-mode = "rgmii"; 34 phy-mode = "rgmii-id";
35 phy-handle = <&ethernet_phy>;
36
37 ethernet_phy: ethernet-phy@7 {
38 reg = <7>;
39 };
36}; 40};
37 41
38&i2c0 { 42&i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 82d7ef1a9a9c..697779a353ed 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * Copyright (C) 2013 Xilinx
5 * 4 *
6 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -17,11 +16,11 @@
17 16
18/ { 17/ {
19 model = "Zynq Zed Development Board"; 18 model = "Zynq Zed Development Board";
20 compatible = "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
21 20
22 memory { 21 memory {
23 device_type = "memory"; 22 device_type = "memory";
24 reg = <0 0x20000000>; 23 reg = <0x0 0x20000000>;
25 }; 24 };
26 25
27 chosen { 26 chosen {
@@ -32,7 +31,12 @@
32 31
33&gem0 { 32&gem0 {
34 status = "okay"; 33 status = "okay";
35 phy-mode = "rgmii"; 34 phy-mode = "rgmii-id";
35 phy-handle = <&ethernet_phy>;
36
37 ethernet_phy: ethernet-phy@0 {
38 reg = <0>;
39 };
36}; 40};
37 41
38&sdhci0 { 42&sdhci0 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 15:28:15 -0500