diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2013-04-23 20:34:25 -0400 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-05-17 06:11:39 -0400 |
| commit | c9d0f317c6dc45f84888bc11947bc10e6c547dc3 (patch) | |
| tree | ef4d865a48a66b378917b101c85eb011f5ca624b /arch/arm/boot/dts/at91sam9g45.dtsi | |
| parent | 0e4686e6e662205b87e64af7c0ba9ef81e2c8791 (diff) | |
ARM: at91: dt: switch to pinctrl to pre-processor
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9g45.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/at91sam9g45.dtsi | 153 |
1 files changed, 77 insertions, 76 deletions
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 5d7c1f79dc4a..8ba4c71221d9 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include <dt-bindings/pinctrl/at91.h> | ||
| 13 | #include <dt-bindings/gpio/gpio.h> | 14 | #include <dt-bindings/gpio/gpio.h> |
| 14 | 15 | ||
| 15 | / { | 16 | / { |
| @@ -131,214 +132,214 @@ | |||
| 131 | dbgu { | 132 | dbgu { |
| 132 | pinctrl_dbgu: dbgu-0 { | 133 | pinctrl_dbgu: dbgu-0 { |
| 133 | atmel,pins = | 134 | atmel,pins = |
| 134 | <1 12 0x1 0x0 /* PB12 periph A */ | 135 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 135 | 1 13 0x1 0x0>; /* PB13 periph A */ | 136 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ |
| 136 | }; | 137 | }; |
| 137 | }; | 138 | }; |
| 138 | 139 | ||
| 139 | usart0 { | 140 | usart0 { |
| 140 | pinctrl_usart0: usart0-0 { | 141 | pinctrl_usart0: usart0-0 { |
| 141 | atmel,pins = | 142 | atmel,pins = |
| 142 | <1 19 0x1 0x1 /* PB19 periph A with pullup */ | 143 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ |
| 143 | 1 18 0x1 0x0>; /* PB18 periph A */ | 144 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
| 144 | }; | 145 | }; |
| 145 | 146 | ||
| 146 | pinctrl_usart0_rts: usart0_rts-0 { | 147 | pinctrl_usart0_rts: usart0_rts-0 { |
| 147 | atmel,pins = | 148 | atmel,pins = |
| 148 | <1 17 0x2 0x0>; /* PB17 periph B */ | 149 | <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ |
| 149 | }; | 150 | }; |
| 150 | 151 | ||
| 151 | pinctrl_usart0_cts: usart0_cts-0 { | 152 | pinctrl_usart0_cts: usart0_cts-0 { |
| 152 | atmel,pins = | 153 | atmel,pins = |
| 153 | <1 15 0x2 0x0>; /* PB15 periph B */ | 154 | <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ |
| 154 | }; | 155 | }; |
| 155 | }; | 156 | }; |
| 156 | 157 | ||
| 157 | uart1 { | 158 | uart1 { |
| 158 | pinctrl_usart1: usart1-0 { | 159 | pinctrl_usart1: usart1-0 { |
| 159 | atmel,pins = | 160 | atmel,pins = |
| 160 | <1 4 0x1 0x1 /* PB4 periph A with pullup */ | 161 | <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ |
| 161 | 1 5 0x1 0x0>; /* PB5 periph A */ | 162 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
| 162 | }; | 163 | }; |
| 163 | 164 | ||
| 164 | pinctrl_usart1_rts: usart1_rts-0 { | 165 | pinctrl_usart1_rts: usart1_rts-0 { |
| 165 | atmel,pins = | 166 | atmel,pins = |
| 166 | <3 16 0x1 0x0>; /* PD16 periph A */ | 167 | <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ |
| 167 | }; | 168 | }; |
| 168 | 169 | ||
| 169 | pinctrl_usart1_cts: usart1_cts-0 { | 170 | pinctrl_usart1_cts: usart1_cts-0 { |
| 170 | atmel,pins = | 171 | atmel,pins = |
| 171 | <3 17 0x1 0x0>; /* PD17 periph A */ | 172 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ |
| 172 | }; | 173 | }; |
| 173 | }; | 174 | }; |
| 174 | 175 | ||
| 175 | usart2 { | 176 | usart2 { |
| 176 | pinctrl_usart2: usart2-0 { | 177 | pinctrl_usart2: usart2-0 { |
| 177 | atmel,pins = | 178 | atmel,pins = |
| 178 | <1 6 0x1 0x1 /* PB6 periph A with pullup */ | 179 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ |
| 179 | 1 7 0x1 0x0>; /* PB7 periph A */ | 180 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ |
| 180 | }; | 181 | }; |
| 181 | 182 | ||
| 182 | pinctrl_usart2_rts: usart2_rts-0 { | 183 | pinctrl_usart2_rts: usart2_rts-0 { |
| 183 | atmel,pins = | 184 | atmel,pins = |
| 184 | <2 9 0x2 0x0>; /* PC9 periph B */ | 185 | <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ |
| 185 | }; | 186 | }; |
| 186 | 187 | ||
| 187 | pinctrl_usart2_cts: usart2_cts-0 { | 188 | pinctrl_usart2_cts: usart2_cts-0 { |
| 188 | atmel,pins = | 189 | atmel,pins = |
| 189 | <2 11 0x2 0x0>; /* PC11 periph B */ | 190 | <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ |
| 190 | }; | 191 | }; |
| 191 | }; | 192 | }; |
| 192 | 193 | ||
| 193 | usart3 { | 194 | usart3 { |
| 194 | pinctrl_usart3: usart3-0 { | 195 | pinctrl_usart3: usart3-0 { |
| 195 | atmel,pins = | 196 | atmel,pins = |
| 196 | <1 8 0x1 0x1 /* PB9 periph A with pullup */ | 197 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ |
| 197 | 1 9 0x1 0x0>; /* PB8 periph A */ | 198 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ |
| 198 | }; | 199 | }; |
| 199 | 200 | ||
| 200 | pinctrl_usart3_rts: usart3_rts-0 { | 201 | pinctrl_usart3_rts: usart3_rts-0 { |
| 201 | atmel,pins = | 202 | atmel,pins = |
| 202 | <0 23 0x2 0x0>; /* PA23 periph B */ | 203 | <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ |
| 203 | }; | 204 | }; |
| 204 | 205 | ||
| 205 | pinctrl_usart3_cts: usart3_cts-0 { | 206 | pinctrl_usart3_cts: usart3_cts-0 { |
| 206 | atmel,pins = | 207 | atmel,pins = |
| 207 | <0 24 0x2 0x0>; /* PA24 periph B */ | 208 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ |
| 208 | }; | 209 | }; |
| 209 | }; | 210 | }; |
| 210 | 211 | ||
| 211 | nand { | 212 | nand { |
| 212 | pinctrl_nand: nand-0 { | 213 | pinctrl_nand: nand-0 { |
| 213 | atmel,pins = | 214 | atmel,pins = |
| 214 | <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ | 215 | <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ |
| 215 | 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ | 216 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
| 216 | }; | 217 | }; |
| 217 | }; | 218 | }; |
| 218 | 219 | ||
| 219 | macb { | 220 | macb { |
| 220 | pinctrl_macb_rmii: macb_rmii-0 { | 221 | pinctrl_macb_rmii: macb_rmii-0 { |
| 221 | atmel,pins = | 222 | atmel,pins = |
| 222 | <0 10 0x1 0x0 /* PA10 periph A */ | 223 | <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ |
| 223 | 0 11 0x1 0x0 /* PA11 periph A */ | 224 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ |
| 224 | 0 12 0x1 0x0 /* PA12 periph A */ | 225 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 225 | 0 13 0x1 0x0 /* PA13 periph A */ | 226 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 226 | 0 14 0x1 0x0 /* PA14 periph A */ | 227 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 227 | 0 15 0x1 0x0 /* PA15 periph A */ | 228 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 228 | 0 16 0x1 0x0 /* PA16 periph A */ | 229 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ |
| 229 | 0 17 0x1 0x0 /* PA17 periph A */ | 230 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 230 | 0 18 0x1 0x0 /* PA18 periph A */ | 231 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ |
| 231 | 0 19 0x1 0x0>; /* PA19 periph A */ | 232 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ |
| 232 | }; | 233 | }; |
| 233 | 234 | ||
| 234 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { | 235 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 235 | atmel,pins = | 236 | atmel,pins = |
| 236 | <0 6 0x2 0x0 /* PA6 periph B */ | 237 | <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ |
| 237 | 0 7 0x2 0x0 /* PA7 periph B */ | 238 | AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ |
| 238 | 0 8 0x2 0x0 /* PA8 periph B */ | 239 | AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ |
| 239 | 0 9 0x2 0x0 /* PA9 periph B */ | 240 | AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ |
| 240 | 0 27 0x2 0x0 /* PA27 periph B */ | 241 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 241 | 0 28 0x2 0x0 /* PA28 periph B */ | 242 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 242 | 0 29 0x2 0x0 /* PA29 periph B */ | 243 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ |
| 243 | 0 30 0x2 0x0>; /* PA30 periph B */ | 244 | AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
| 244 | }; | 245 | }; |
| 245 | }; | 246 | }; |
| 246 | 247 | ||
| 247 | mmc0 { | 248 | mmc0 { |
| 248 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | 249 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 249 | atmel,pins = | 250 | atmel,pins = |
| 250 | <0 0 0x1 0x0 /* PA0 periph A */ | 251 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ |
| 251 | 0 1 0x1 0x1 /* PA1 periph A with pullup */ | 252 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 252 | 0 2 0x1 0x1>; /* PA2 periph A with pullup */ | 253 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ |
| 253 | }; | 254 | }; |
| 254 | 255 | ||
| 255 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 256 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 256 | atmel,pins = | 257 | atmel,pins = |
| 257 | <0 3 0x1 0x1 /* PA3 periph A with pullup */ | 258 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ |
| 258 | 0 4 0x1 0x1 /* PA4 periph A with pullup */ | 259 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ |
| 259 | 0 5 0x1 0x1>; /* PA5 periph A with pullup */ | 260 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ |
| 260 | }; | 261 | }; |
| 261 | 262 | ||
| 262 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | 263 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 263 | atmel,pins = | 264 | atmel,pins = |
| 264 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ | 265 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 265 | 0 7 0x1 0x1 /* PA7 periph A with pullup */ | 266 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 266 | 0 8 0x1 0x1 /* PA8 periph A with pullup */ | 267 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 267 | 0 9 0x1 0x1>; /* PA9 periph A with pullup */ | 268 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ |
| 268 | }; | 269 | }; |
| 269 | }; | 270 | }; |
| 270 | 271 | ||
| 271 | mmc1 { | 272 | mmc1 { |
| 272 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | 273 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 273 | atmel,pins = | 274 | atmel,pins = |
| 274 | <0 31 0x1 0x0 /* PA31 periph A */ | 275 | <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ |
| 275 | 0 22 0x1 0x1 /* PA22 periph A with pullup */ | 276 | AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ |
| 276 | 0 23 0x1 0x1>; /* PA23 periph A with pullup */ | 277 | AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ |
| 277 | }; | 278 | }; |
| 278 | 279 | ||
| 279 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | 280 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 280 | atmel,pins = | 281 | atmel,pins = |
| 281 | <0 24 0x1 0x1 /* PA24 periph A with pullup */ | 282 | <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ |
| 282 | 0 25 0x1 0x1 /* PA25 periph A with pullup */ | 283 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ |
| 283 | 0 26 0x1 0x1>; /* PA26 periph A with pullup */ | 284 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ |
| 284 | }; | 285 | }; |
| 285 | 286 | ||
| 286 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { | 287 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { |
| 287 | atmel,pins = | 288 | atmel,pins = |
| 288 | <0 27 0x1 0x1 /* PA27 periph A with pullup */ | 289 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ |
| 289 | 0 28 0x1 0x1 /* PA28 periph A with pullup */ | 290 | AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ |
| 290 | 0 29 0x1 0x1 /* PA29 periph A with pullup */ | 291 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ |
| 291 | 0 20 0x1 0x1>; /* PA30 periph A with pullup */ | 292 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ |
| 292 | }; | 293 | }; |
| 293 | }; | 294 | }; |
| 294 | 295 | ||
| 295 | ssc0 { | 296 | ssc0 { |
| 296 | pinctrl_ssc0_tx: ssc0_tx-0 { | 297 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 297 | atmel,pins = | 298 | atmel,pins = |
| 298 | <3 0 0x1 0x0 /* PD0 periph A */ | 299 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ |
| 299 | 3 1 0x1 0x0 /* PD1 periph A */ | 300 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ |
| 300 | 3 2 0x1 0x0>; /* PD2 periph A */ | 301 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ |
| 301 | }; | 302 | }; |
| 302 | 303 | ||
| 303 | pinctrl_ssc0_rx: ssc0_rx-0 { | 304 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 304 | atmel,pins = | 305 | atmel,pins = |
| 305 | <3 3 0x1 0x0 /* PD3 periph A */ | 306 | <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ |
| 306 | 3 4 0x1 0x0 /* PD4 periph A */ | 307 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ |
| 307 | 3 5 0x1 0x0>; /* PD5 periph A */ | 308 | AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ |
| 308 | }; | 309 | }; |
| 309 | }; | 310 | }; |
| 310 | 311 | ||
| 311 | ssc1 { | 312 | ssc1 { |
| 312 | pinctrl_ssc1_tx: ssc1_tx-0 { | 313 | pinctrl_ssc1_tx: ssc1_tx-0 { |
| 313 | atmel,pins = | 314 | atmel,pins = |
| 314 | <3 10 0x1 0x0 /* PD10 periph A */ | 315 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ |
| 315 | 3 11 0x1 0x0 /* PD11 periph A */ | 316 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ |
| 316 | 3 12 0x1 0x0>; /* PD12 periph A */ | 317 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ |
| 317 | }; | 318 | }; |
| 318 | 319 | ||
| 319 | pinctrl_ssc1_rx: ssc1_rx-0 { | 320 | pinctrl_ssc1_rx: ssc1_rx-0 { |
| 320 | atmel,pins = | 321 | atmel,pins = |
| 321 | <3 13 0x1 0x0 /* PD13 periph A */ | 322 | <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ |
| 322 | 3 14 0x1 0x0 /* PD14 periph A */ | 323 | AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ |
| 323 | 3 15 0x1 0x0>; /* PD15 periph A */ | 324 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ |
| 324 | }; | 325 | }; |
| 325 | }; | 326 | }; |
| 326 | 327 | ||
| 327 | spi0 { | 328 | spi0 { |
| 328 | pinctrl_spi0: spi0-0 { | 329 | pinctrl_spi0: spi0-0 { |
| 329 | atmel,pins = | 330 | atmel,pins = |
| 330 | <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */ | 331 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ |
| 331 | 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */ | 332 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ |
| 332 | 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */ | 333 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ |
| 333 | }; | 334 | }; |
| 334 | }; | 335 | }; |
| 335 | 336 | ||
| 336 | spi1 { | 337 | spi1 { |
| 337 | pinctrl_spi1: spi1-0 { | 338 | pinctrl_spi1: spi1-0 { |
| 338 | atmel,pins = | 339 | atmel,pins = |
| 339 | <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */ | 340 | <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ |
| 340 | 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */ | 341 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ |
| 341 | 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */ | 342 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ |
| 342 | }; | 343 | }; |
| 343 | }; | 344 | }; |
| 344 | 345 | ||