Merge tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:
 "Nothing too exciting here, just minor fixes/cleanup.  Only noteworthy
  ones are:

   - Moving cache disabling to early boot
   - ARC UART enabled only if earlyprintk setup in cmdline"

* tag 'arc-v3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: Disable caches in early boot if so configured
  ARC: [arcfpga] Early ARC UART to be only activated by cmdline
  ARC: [arcfpga] Get rid of legacy BVCI latency unit support
  ARC: remove duplicate header exports
  ARC: arc_local_timer_setup() need not pass own cpu id
  ARC: Fixed spelling errors within comments
  ARC: make start_thread() out-of-line
  ARC: fix mmuv2 warning
  ARC: [SMP] ISS SMP extension bitrot

6 files changed, 71 insertions, 33 deletions

diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 29b82adbf0b4..83a046a7cd06 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -156,7 +156,7 @@ ARCFP_DATA int1_saved_reg
 int1_saved_reg:
         .zero 4
 
-/* Each Interrupt level needs it's own scratch */
+/* Each Interrupt level needs its own scratch */
 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
 
 ARCFP_DATA int2_saved_reg
@@ -473,7 +473,7 @@ trap_with_param:
         lr  r0, [efa]
         mov r1, sp
 
-        ; Now that we have read EFA, its safe to do "fake" rtie
+        ; Now that we have read EFA, it is safe to do "fake" rtie
         ;   and get out of CPU exception mode
         FAKE_RET_FROM_EXCPN r11
 
@@ -678,9 +678,9 @@ not_exception:
         brne r9, event_IRQ2, 149f
 
         ;------------------------------------------------------------------
-        ; if L2 IRQ interrupted a L1 ISR,  we'd disbaled preemption earlier
-        ; so that sched doesnt move to new task, causing L1 to be delayed
-        ; undeterministically. Now that we've achieved that, lets reset
+        ; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
+        ; so that sched doesn't move to new task, causing L1 to be delayed
+        ; undeterministically. Now that we've achieved that, let's reset
         ; things to what they were, before returning from L2 context
         ;----------------------------------------------------------------
 
@@ -736,7 +736,7 @@ ENTRY(ret_from_fork)
         ; put last task in scheduler queue
         bl   @schedule_tail
 
-        ; If kernel thread, jump to it's entry-point
+        ; If kernel thread, jump to its entry-point
         ld   r9, [sp, PT_status32]
         brne r9, 0, 1f
 
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 4ad04915dc6b..07a58f2d3077 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -12,10 +12,42 @@
  *      to skip certain things during boot on simulator
  */
 
+#include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/entry.h>
-#include <linux/linkage.h>
 #include <asm/arcregs.h>
+#include <asm/cache.h>
+
+.macro CPU_EARLY_SETUP
+
+        ; Setting up Vectror Table (in case exception happens in early boot
+        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+
+        ; Disable I-cache/D-cache if kernel so configured
+        lr      r5, [ARC_REG_IC_BCR]
+        breq    r5, 0, 1f               ; I$ doesn't exist
+        lr      r5, [ARC_REG_IC_CTRL]
+#ifdef CONFIG_ARC_HAS_ICACHE
+        bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
+#else
+        bset    r5, r5, 0               ; I$ exists, but is not used
+#endif
+        sr      r5, [ARC_REG_IC_CTRL]
+
+1:
+        lr      r5, [ARC_REG_DC_BCR]
+        breq    r5, 0, 1f               ; D$ doesn't exist
+        lr      r5, [ARC_REG_DC_CTRL]
+        bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
+#ifdef CONFIG_ARC_HAS_DCACHE
+        bclr    r5, r5, 0               ; Enable (+Inv)
+#else
+        bset    r5, r5, 0               ; Disable (+Inv)
+#endif
+        sr      r5, [ARC_REG_DC_CTRL]
+
+1:
+.endm
 
         .cpu A7
 
@@ -27,7 +59,7 @@ stext:
         ; Don't clobber r0-r2 yet. It might have bootloader provided info
         ;-------------------------------------------------------------------
 
-        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+        CPU_EARLY_SETUP
 
 #ifdef CONFIG_SMP
         ; Ensure Boot (Master) proceeds. Others wait in platform dependent way
@@ -90,7 +122,7 @@ stext:
 
 first_lines_of_secondary:
 
-        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+        CPU_EARLY_SETUP
 
         ; setup per-cpu idle task as "current" on this CPU
         ld      r0, [@secondary_idle_tsk]
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index a4b141ee9a6a..7d653c0d0773 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -150,24 +150,6 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
         set_irq_regs(old_regs);
 }
 
-int get_hw_config_num_irq(void)
-{
-        uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
-
-        switch (val & 0x03) {
-        case 0:
-                return 16;
-        case 1:
-                return 32;
-        case 2:
-                return 8;
-        default:
-                return 0;
-        }
-
-        return 0;
-}
-
 /*
  * arch_local_irq_enable - Enable interrupts.
  *
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 07a3a968fe49..fdd89715d2d3 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -151,6 +151,29 @@ int copy_thread(unsigned long clone_flags,
 }
 
 /*
+ * Do necessary setup to start up a new user task
+ */
+void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
+{
+        set_fs(USER_DS); /* user space */
+
+        regs->sp = usp;
+        regs->ret = pc;
+
+        /*
+         * [U]ser Mode bit set
+         * [L] ZOL loop inhibited to begin with - cleared by a LP insn
+         * Interrupts enabled
+         */
+        regs->status32 = STATUS_U_MASK | STATUS_L_MASK |
+                         STATUS_E1_MASK | STATUS_E2_MASK;
+
+        /* bogus seed values for debugging */
+        regs->lp_start = 0x10;
+        regs->lp_end = 0x80;
+}
+
+/*
  * Some archs flush debug and FPU info here
  */
 void flush_thread(void)
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 40859e5619f9..cf90b6f4d3e0 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -138,7 +138,7 @@ void start_kernel_secondary(void)
         if (machine_desc->init_smp)
                 machine_desc->init_smp(smp_processor_id());
 
-        arc_local_timer_setup(cpu);
+        arc_local_timer_setup();
 
         local_irq_enable();
         preempt_disable();
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 71c42521c77f..36c2aa99436f 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -219,12 +219,13 @@ static struct irqaction arc_timer_irq = {
 /*
  * Setup the local event timer for @cpu
  */
-void arc_local_timer_setup(unsigned int cpu)
+void arc_local_timer_setup()
 {
-        struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
+        struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+        int cpu = smp_processor_id();
 
-        clk->cpumask = cpumask_of(cpu);
-        clockevents_config_and_register(clk, arc_get_core_freq(),
+        evt->cpumask = cpumask_of(cpu);
+        clockevents_config_and_register(evt, arc_get_core_freq(),
                                         0, ARC_TIMER_MAX);
 
         /*
@@ -261,7 +262,7 @@ void __init time_init(void)
                 clocksource_register_hz(&arc_counter, arc_get_core_freq());
 
         /* sets up the periodic event timer */
-        arc_local_timer_setup(smp_processor_id());
+        arc_local_timer_setup();
 
         if (machine_desc->init_time)
                 machine_desc->init_time();