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-rw-r--r--arch/arc/boot/dts/angel4.dts2
-rw-r--r--arch/arc/include/asm/cache.h27
-rw-r--r--arch/arc/include/asm/irq.h4
-rw-r--r--arch/arc/include/asm/processor.h29
-rw-r--r--arch/arc/include/uapi/asm/Kbuild7
-rw-r--r--arch/arc/kernel/entry.S12
-rw-r--r--arch/arc/kernel/head.S38
-rw-r--r--arch/arc/kernel/irq.c18
-rw-r--r--arch/arc/kernel/process.c23
-rw-r--r--arch/arc/kernel/smp.c2
-rw-r--r--arch/arc/kernel/time.c11
-rw-r--r--arch/arc/mm/cache_arc700.c110
-rw-r--r--arch/arc/plat-arcfpga/Kconfig32
-rw-r--r--arch/arc/plat-arcfpga/Makefile2
-rw-r--r--arch/arc/plat-arcfpga/platform.c72
-rw-r--r--arch/arc/plat-arcfpga/smp.c18
16 files changed, 158 insertions, 249 deletions
diff --git a/arch/arc/boot/dts/angel4.dts b/arch/arc/boot/dts/angel4.dts
index bcf662d21a57..5bb2fdaca02f 100644
--- a/arch/arc/boot/dts/angel4.dts
+++ b/arch/arc/boot/dts/angel4.dts
@@ -17,7 +17,7 @@
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 chosen { 19 chosen {
20 bootargs = "console=ttyARC0,115200n8"; 20 bootargs = "console=ttyARC0,115200n8 earlyprintk=ttyARC0";
21 }; 21 };
22 22
23 aliases { 23 aliases {
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 2fd3162ec4df..c1d3d2da1191 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -55,4 +55,31 @@ extern void read_decode_cache_bcr(void);
55 55
56#endif /* !__ASSEMBLY__ */ 56#endif /* !__ASSEMBLY__ */
57 57
58/* Instruction cache related Auxiliary registers */
59#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
60#define ARC_REG_IC_IVIC 0x10
61#define ARC_REG_IC_CTRL 0x11
62#define ARC_REG_IC_IVIL 0x19
63#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
64#define ARC_REG_IC_PTAG 0x1E
65#endif
66
67/* Bit val in IC_CTRL */
68#define IC_CTRL_CACHE_DISABLE 0x1
69
70/* Data cache related Auxiliary registers */
71#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
72#define ARC_REG_DC_IVDC 0x47
73#define ARC_REG_DC_CTRL 0x48
74#define ARC_REG_DC_IVDL 0x4A
75#define ARC_REG_DC_FLSH 0x4B
76#define ARC_REG_DC_FLDL 0x4C
77#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
78#define ARC_REG_DC_PTAG 0x5C
79#endif
80
81/* Bit val in DC_CTRL */
82#define DC_CTRL_INV_MODE_FLUSH 0x40
83#define DC_CTRL_FLUSH_STATUS 0x100
84
58#endif /* _ASM_CACHE_H */ 85#endif /* _ASM_CACHE_H */
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 291a70db68b8..fb4efb648971 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -19,8 +19,6 @@
19#include <asm-generic/irq.h> 19#include <asm-generic/irq.h>
20 20
21extern void arc_init_IRQ(void); 21extern void arc_init_IRQ(void);
22extern int get_hw_config_num_irq(void); 22void arc_local_timer_setup(void);
23
24void arc_local_timer_setup(unsigned int cpu);
25 23
26#endif 24#endif
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 15334ab66b56..d99f9b37cd15 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -18,7 +18,6 @@
18 18
19#ifndef __ASSEMBLY__ 19#ifndef __ASSEMBLY__
20 20
21#include <asm/arcregs.h> /* for STATUS_E1_MASK et all */
22#include <asm/ptrace.h> 21#include <asm/ptrace.h>
23 22
24/* Arch specific stuff which needs to be saved per task. 23/* Arch specific stuff which needs to be saved per task.
@@ -41,15 +40,13 @@ struct thread_struct {
41/* Forward declaration, a strange C thing */ 40/* Forward declaration, a strange C thing */
42struct task_struct; 41struct task_struct;
43 42
44/* 43/* Return saved PC of a blocked thread */
45 * Return saved PC of a blocked thread.
46 */
47unsigned long thread_saved_pc(struct task_struct *t); 44unsigned long thread_saved_pc(struct task_struct *t);
48 45
49#define task_pt_regs(p) \ 46#define task_pt_regs(p) \
50 ((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1) 47 ((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
51 48
52/* Free all resources held by a thread. */ 49/* Free all resources held by a thread */
53#define release_thread(thread) do { } while (0) 50#define release_thread(thread) do { } while (0)
54 51
55/* Prepare to copy thread state - unlazy all lazy status */ 52/* Prepare to copy thread state - unlazy all lazy status */
@@ -82,26 +79,8 @@ unsigned long thread_saved_pc(struct task_struct *t);
82#define KSTK_BLINK(tsk) KSTK_REG(tsk, 4) 79#define KSTK_BLINK(tsk) KSTK_REG(tsk, 4)
83#define KSTK_FP(tsk) KSTK_REG(tsk, 0) 80#define KSTK_FP(tsk) KSTK_REG(tsk, 0)
84 81
85/* 82extern void start_thread(struct pt_regs * regs, unsigned long pc,
86 * Do necessary setup to start up a newly executed thread. 83 unsigned long usp);
87 *
88 * E1,E2 so that Interrupts are enabled in user mode
89 * L set, so Loop inhibited to begin with
90 * lp_start and lp_end seeded with bogus non-zero values so to easily catch
91 * the ARC700 sr to lp_start hardware bug
92 */
93#define start_thread(_regs, _pc, _usp) \
94do { \
95 set_fs(USER_DS); /* reads from user space */ \
96 (_regs)->ret = (_pc); \
97 /* Interrupts enabled in User Mode */ \
98 (_regs)->status32 = STATUS_U_MASK | STATUS_L_MASK \
99 | STATUS_E1_MASK | STATUS_E2_MASK; \
100 (_regs)->sp = (_usp); \
101 /* bogus seed values for debugging */ \
102 (_regs)->lp_start = 0x10; \
103 (_regs)->lp_end = 0x80; \
104} while (0)
105 84
106extern unsigned int get_wchan(struct task_struct *p); 85extern unsigned int get_wchan(struct task_struct *p);
107 86
diff --git a/arch/arc/include/uapi/asm/Kbuild b/arch/arc/include/uapi/asm/Kbuild
index 18fefaea73fd..f50d02df78d5 100644
--- a/arch/arc/include/uapi/asm/Kbuild
+++ b/arch/arc/include/uapi/asm/Kbuild
@@ -2,11 +2,4 @@
2include include/uapi/asm-generic/Kbuild.asm 2include include/uapi/asm-generic/Kbuild.asm
3header-y += elf.h 3header-y += elf.h
4header-y += page.h 4header-y += page.h
5header-y += setup.h
6header-y += byteorder.h
7header-y += cachectl.h 5header-y += cachectl.h
8header-y += ptrace.h
9header-y += sigcontext.h
10header-y += signal.h
11header-y += swab.h
12header-y += unistd.h
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 29b82adbf0b4..83a046a7cd06 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -156,7 +156,7 @@ ARCFP_DATA int1_saved_reg
156int1_saved_reg: 156int1_saved_reg:
157 .zero 4 157 .zero 4
158 158
159/* Each Interrupt level needs it's own scratch */ 159/* Each Interrupt level needs its own scratch */
160#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS 160#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
161 161
162ARCFP_DATA int2_saved_reg 162ARCFP_DATA int2_saved_reg
@@ -473,7 +473,7 @@ trap_with_param:
473 lr r0, [efa] 473 lr r0, [efa]
474 mov r1, sp 474 mov r1, sp
475 475
476 ; Now that we have read EFA, its safe to do "fake" rtie 476 ; Now that we have read EFA, it is safe to do "fake" rtie
477 ; and get out of CPU exception mode 477 ; and get out of CPU exception mode
478 FAKE_RET_FROM_EXCPN r11 478 FAKE_RET_FROM_EXCPN r11
479 479
@@ -678,9 +678,9 @@ not_exception:
678 brne r9, event_IRQ2, 149f 678 brne r9, event_IRQ2, 149f
679 679
680 ;------------------------------------------------------------------ 680 ;------------------------------------------------------------------
681 ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier 681 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
682 ; so that sched doesnt move to new task, causing L1 to be delayed 682 ; so that sched doesn't move to new task, causing L1 to be delayed
683 ; undeterministically. Now that we've achieved that, lets reset 683 ; undeterministically. Now that we've achieved that, let's reset
684 ; things to what they were, before returning from L2 context 684 ; things to what they were, before returning from L2 context
685 ;---------------------------------------------------------------- 685 ;----------------------------------------------------------------
686 686
@@ -736,7 +736,7 @@ ENTRY(ret_from_fork)
736 ; put last task in scheduler queue 736 ; put last task in scheduler queue
737 bl @schedule_tail 737 bl @schedule_tail
738 738
739 ; If kernel thread, jump to it's entry-point 739 ; If kernel thread, jump to its entry-point
740 ld r9, [sp, PT_status32] 740 ld r9, [sp, PT_status32]
741 brne r9, 0, 1f 741 brne r9, 0, 1f
742 742
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 4ad04915dc6b..07a58f2d3077 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -12,10 +12,42 @@
12 * to skip certain things during boot on simulator 12 * to skip certain things during boot on simulator
13 */ 13 */
14 14
15#include <linux/linkage.h>
15#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
16#include <asm/entry.h> 17#include <asm/entry.h>
17#include <linux/linkage.h>
18#include <asm/arcregs.h> 18#include <asm/arcregs.h>
19#include <asm/cache.h>
20
21.macro CPU_EARLY_SETUP
22
23 ; Setting up Vectror Table (in case exception happens in early boot
24 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
25
26 ; Disable I-cache/D-cache if kernel so configured
27 lr r5, [ARC_REG_IC_BCR]
28 breq r5, 0, 1f ; I$ doesn't exist
29 lr r5, [ARC_REG_IC_CTRL]
30#ifdef CONFIG_ARC_HAS_ICACHE
31 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
32#else
33 bset r5, r5, 0 ; I$ exists, but is not used
34#endif
35 sr r5, [ARC_REG_IC_CTRL]
36
371:
38 lr r5, [ARC_REG_DC_BCR]
39 breq r5, 0, 1f ; D$ doesn't exist
40 lr r5, [ARC_REG_DC_CTRL]
41 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
42#ifdef CONFIG_ARC_HAS_DCACHE
43 bclr r5, r5, 0 ; Enable (+Inv)
44#else
45 bset r5, r5, 0 ; Disable (+Inv)
46#endif
47 sr r5, [ARC_REG_DC_CTRL]
48
491:
50.endm
19 51
20 .cpu A7 52 .cpu A7
21 53
@@ -27,7 +59,7 @@ stext:
27 ; Don't clobber r0-r2 yet. It might have bootloader provided info 59 ; Don't clobber r0-r2 yet. It might have bootloader provided info
28 ;------------------------------------------------------------------- 60 ;-------------------------------------------------------------------
29 61
30 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 62 CPU_EARLY_SETUP
31 63
32#ifdef CONFIG_SMP 64#ifdef CONFIG_SMP
33 ; Ensure Boot (Master) proceeds. Others wait in platform dependent way 65 ; Ensure Boot (Master) proceeds. Others wait in platform dependent way
@@ -90,7 +122,7 @@ stext:
90 122
91first_lines_of_secondary: 123first_lines_of_secondary:
92 124
93 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 125 CPU_EARLY_SETUP
94 126
95 ; setup per-cpu idle task as "current" on this CPU 127 ; setup per-cpu idle task as "current" on this CPU
96 ld r0, [@secondary_idle_tsk] 128 ld r0, [@secondary_idle_tsk]
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index a4b141ee9a6a..7d653c0d0773 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -150,24 +150,6 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
150 set_irq_regs(old_regs); 150 set_irq_regs(old_regs);
151} 151}
152 152
153int get_hw_config_num_irq(void)
154{
155 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
156
157 switch (val & 0x03) {
158 case 0:
159 return 16;
160 case 1:
161 return 32;
162 case 2:
163 return 8;
164 default:
165 return 0;
166 }
167
168 return 0;
169}
170
171/* 153/*
172 * arch_local_irq_enable - Enable interrupts. 154 * arch_local_irq_enable - Enable interrupts.
173 * 155 *
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 07a3a968fe49..fdd89715d2d3 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -151,6 +151,29 @@ int copy_thread(unsigned long clone_flags,
151} 151}
152 152
153/* 153/*
154 * Do necessary setup to start up a new user task
155 */
156void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
157{
158 set_fs(USER_DS); /* user space */
159
160 regs->sp = usp;
161 regs->ret = pc;
162
163 /*
164 * [U]ser Mode bit set
165 * [L] ZOL loop inhibited to begin with - cleared by a LP insn
166 * Interrupts enabled
167 */
168 regs->status32 = STATUS_U_MASK | STATUS_L_MASK |
169 STATUS_E1_MASK | STATUS_E2_MASK;
170
171 /* bogus seed values for debugging */
172 regs->lp_start = 0x10;
173 regs->lp_end = 0x80;
174}
175
176/*
154 * Some archs flush debug and FPU info here 177 * Some archs flush debug and FPU info here
155 */ 178 */
156void flush_thread(void) 179void flush_thread(void)
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 40859e5619f9..cf90b6f4d3e0 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -138,7 +138,7 @@ void start_kernel_secondary(void)
138 if (machine_desc->init_smp) 138 if (machine_desc->init_smp)
139 machine_desc->init_smp(smp_processor_id()); 139 machine_desc->init_smp(smp_processor_id());
140 140
141 arc_local_timer_setup(cpu); 141 arc_local_timer_setup();
142 142
143 local_irq_enable(); 143 local_irq_enable();
144 preempt_disable(); 144 preempt_disable();
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 71c42521c77f..36c2aa99436f 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -219,12 +219,13 @@ static struct irqaction arc_timer_irq = {
219/* 219/*
220 * Setup the local event timer for @cpu 220 * Setup the local event timer for @cpu
221 */ 221 */
222void arc_local_timer_setup(unsigned int cpu) 222void arc_local_timer_setup()
223{ 223{
224 struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu); 224 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
225 int cpu = smp_processor_id();
225 226
226 clk->cpumask = cpumask_of(cpu); 227 evt->cpumask = cpumask_of(cpu);
227 clockevents_config_and_register(clk, arc_get_core_freq(), 228 clockevents_config_and_register(evt, arc_get_core_freq(),
228 0, ARC_TIMER_MAX); 229 0, ARC_TIMER_MAX);
229 230
230 /* 231 /*
@@ -261,7 +262,7 @@ void __init time_init(void)
261 clocksource_register_hz(&arc_counter, arc_get_core_freq()); 262 clocksource_register_hz(&arc_counter, arc_get_core_freq());
262 263
263 /* sets up the periodic event timer */ 264 /* sets up the periodic event timer */
264 arc_local_timer_setup(smp_processor_id()); 265 arc_local_timer_setup();
265 266
266 if (machine_desc->init_time) 267 if (machine_desc->init_time)
267 machine_desc->init_time(); 268 machine_desc->init_time();
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 89edf7961a2f..1f676c4794e0 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -73,33 +73,6 @@
73#include <asm/cachectl.h> 73#include <asm/cachectl.h>
74#include <asm/setup.h> 74#include <asm/setup.h>
75 75
76/* Instruction cache related Auxiliary registers */
77#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78#define ARC_REG_IC_IVIC 0x10
79#define ARC_REG_IC_CTRL 0x11
80#define ARC_REG_IC_IVIL 0x19
81#if (CONFIG_ARC_MMU_VER > 2)
82#define ARC_REG_IC_PTAG 0x1E
83#endif
84
85/* Bit val in IC_CTRL */
86#define IC_CTRL_CACHE_DISABLE 0x1
87
88/* Data cache related Auxiliary registers */
89#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90#define ARC_REG_DC_IVDC 0x47
91#define ARC_REG_DC_CTRL 0x48
92#define ARC_REG_DC_IVDL 0x4A
93#define ARC_REG_DC_FLSH 0x4B
94#define ARC_REG_DC_FLDL 0x4C
95#if (CONFIG_ARC_MMU_VER > 2)
96#define ARC_REG_DC_PTAG 0x5C
97#endif
98
99/* Bit val in DC_CTRL */
100#define DC_CTRL_INV_MODE_FLUSH 0x40
101#define DC_CTRL_FLUSH_STATUS 0x100
102
103char *arc_cache_mumbojumbo(int c, char *buf, int len) 76char *arc_cache_mumbojumbo(int c, char *buf, int len)
104{ 77{
105 int n = 0; 78 int n = 0;
@@ -168,72 +141,43 @@ void read_decode_cache_bcr(void)
168 */ 141 */
169void arc_cache_init(void) 142void arc_cache_init(void)
170{ 143{
171 unsigned int cpu = smp_processor_id(); 144 unsigned int __maybe_unused cpu = smp_processor_id();
172 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; 145 struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc;
173 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
174 unsigned int dcache_does_alias, temp;
175 char str[256]; 146 char str[256];
176 147
177 printk(arc_cache_mumbojumbo(0, str, sizeof(str))); 148 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
178 149
179 if (!ic->ver)
180 goto chk_dc;
181
182#ifdef CONFIG_ARC_HAS_ICACHE
183 /* 1. Confirm some of I-cache params which Linux assumes */
184 if (ic->line_len != L1_CACHE_BYTES)
185 panic("Cache H/W doesn't match kernel Config");
186
187 if (ic->ver != CONFIG_ARC_MMU_VER)
188 panic("Cache ver doesn't match MMU ver\n");
189#endif
190
191 /* Enable/disable I-Cache */
192 temp = read_aux_reg(ARC_REG_IC_CTRL);
193
194#ifdef CONFIG_ARC_HAS_ICACHE 150#ifdef CONFIG_ARC_HAS_ICACHE
195 temp &= ~IC_CTRL_CACHE_DISABLE; 151 ic = &cpuinfo_arc700[cpu].icache;
196#else 152 if (ic->ver) {
197 temp |= IC_CTRL_CACHE_DISABLE; 153 if (ic->line_len != L1_CACHE_BYTES)
154 panic("ICache line [%d] != kernel Config [%d]",
155 ic->line_len, L1_CACHE_BYTES);
156
157 if (ic->ver != CONFIG_ARC_MMU_VER)
158 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
159 ic->ver, CONFIG_ARC_MMU_VER);
160 }
198#endif 161#endif
199 162
200 write_aux_reg(ARC_REG_IC_CTRL, temp);
201
202chk_dc:
203 if (!dc->ver)
204 return;
205
206#ifdef CONFIG_ARC_HAS_DCACHE 163#ifdef CONFIG_ARC_HAS_DCACHE
207 if (dc->line_len != L1_CACHE_BYTES) 164 dc = &cpuinfo_arc700[cpu].dcache;
208 panic("Cache H/W doesn't match kernel Config"); 165 if (dc->ver) {
166 unsigned int dcache_does_alias;
209 167
210 /* check for D-Cache aliasing */ 168 if (dc->line_len != L1_CACHE_BYTES)
211 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; 169 panic("DCache line [%d] != kernel Config [%d]",
170 dc->line_len, L1_CACHE_BYTES);
212 171
213 if (dcache_does_alias && !cache_is_vipt_aliasing()) 172 /* check for D-Cache aliasing */
214 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 173 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
215 else if (!dcache_does_alias && cache_is_vipt_aliasing())
216 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
217#endif
218
219 /* Set the default Invalidate Mode to "simpy discard dirty lines"
220 * as this is more frequent then flush before invalidate
221 * Ofcourse we toggle this default behviour when desired
222 */
223 temp = read_aux_reg(ARC_REG_DC_CTRL);
224 temp &= ~DC_CTRL_INV_MODE_FLUSH;
225 174
226#ifdef CONFIG_ARC_HAS_DCACHE 175 if (dcache_does_alias && !cache_is_vipt_aliasing())
227 /* Enable D-Cache: Clear Bit 0 */ 176 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
228 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); 177 else if (!dcache_does_alias && cache_is_vipt_aliasing())
229#else 178 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
230 /* Flush D cache */ 179 }
231 write_aux_reg(ARC_REG_DC_FLSH, 0x1);
232 /* Disable D cache */
233 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
234#endif 180#endif
235
236 return;
237} 181}
238 182
239#define OP_INV 0x1 183#define OP_INV 0x1
@@ -253,12 +197,16 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
253 197
254 if (cacheop == OP_INV_IC) { 198 if (cacheop == OP_INV_IC) {
255 aux_cmd = ARC_REG_IC_IVIL; 199 aux_cmd = ARC_REG_IC_IVIL;
200#if (CONFIG_ARC_MMU_VER > 2)
256 aux_tag = ARC_REG_IC_PTAG; 201 aux_tag = ARC_REG_IC_PTAG;
202#endif
257 } 203 }
258 else { 204 else {
259 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 205 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
260 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 206 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
207#if (CONFIG_ARC_MMU_VER > 2)
261 aux_tag = ARC_REG_DC_PTAG; 208 aux_tag = ARC_REG_DC_PTAG;
209#endif
262 } 210 }
263 211
264 /* Ensure we properly floor/ceil the non-line aligned/sized requests 212 /* Ensure we properly floor/ceil the non-line aligned/sized requests
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig
index 33058aa40e77..e27bb5cc3c1e 100644
--- a/arch/arc/plat-arcfpga/Kconfig
+++ b/arch/arc/plat-arcfpga/Kconfig
@@ -48,36 +48,4 @@ config ARC_SERIAL_BAUD
48 help 48 help
49 Baud rate for the ARC UART 49 Baud rate for the ARC UART
50 50
51menuconfig ARC_HAS_BVCI_LAT_UNIT
52 bool "BVCI Bus Latency Unit"
53 depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
54 help
55 IP to add artificial latency to BVCI Bus Based FPGA builds.
56 The default latency (even worst case) for FPGA is non-realistic
57 (~10 SDRAM, ~5 SSRAM).
58
59config BVCI_LAT_UNITS
60 hex "Latency Unit(s) Bitmap"
61 default "0x0"
62 depends on ARC_HAS_BVCI_LAT_UNIT
63 help
64 There are multiple Latency Units corresponding to the many
65 interfaces of the system bus arbiter (both CPU side as well as
66 the peripheral side).
67 To add latency to ALL memory transaction, choose Unit 0, otherwise
68 for finer grainer - interface wise latency, specify a bitmap (1 bit
69 per unit) of all units. e.g. 1,2,12 will be 0x1003
70
71 Unit 0 - System Arb and Mem Controller
72 Unit 1 - I$ and System Bus
73 Unit 2 - D$ and System Bus
74 ..
75 Unit 12 - IDE Disk controller and System Bus
76
77config BVCI_LAT_CYCLES
78 int "Latency Value in cycles"
79 range 0 63
80 default "30"
81 depends on ARC_HAS_BVCI_LAT_UNIT
82
83endif 51endif
diff --git a/arch/arc/plat-arcfpga/Makefile b/arch/arc/plat-arcfpga/Makefile
index a44e22ebc1b7..4d1bddc34b5b 100644
--- a/arch/arc/plat-arcfpga/Makefile
+++ b/arch/arc/plat-arcfpga/Makefile
@@ -9,4 +9,4 @@
9KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include 9KBUILD_CFLAGS += -Iarch/arc/plat-arcfpga/include
10 10
11obj-y := platform.o irq.o 11obj-y := platform.o irq.o
12obj-$(CONFIG_SMP) += smp.o 12obj-$(CONFIG_ISS_SMP_EXTN) += smp.o
diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c
index 19b76b61f44b..61c7e5997387 100644
--- a/arch/arc/plat-arcfpga/platform.c
+++ b/arch/arc/plat-arcfpga/platform.c
@@ -22,59 +22,6 @@
22#include <plat/smp.h> 22#include <plat/smp.h>
23#include <plat/irq.h> 23#include <plat/irq.h>
24 24
25/*-----------------------BVCI Latency Unit -----------------------------*/
26
27#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
28
29int lat_cycles = CONFIG_BVCI_LAT_CYCLES;
30
31/* BVCI Bus Profiler: Latency Unit */
32static void __init setup_bvci_lat_unit(void)
33{
34#define MAX_BVCI_UNITS 12
35
36 unsigned int i;
37 unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE;
38 const unsigned long units_req = CONFIG_BVCI_LAT_UNITS;
39 const unsigned int REG_UNIT = 21;
40 const unsigned int REG_VAL = 22;
41
42 /*
43 * There are multiple Latency Units corresponding to the many
44 * interfaces of the system bus arbiter (both CPU side as well as
45 * the peripheral side).
46 *
47 * Unit 0 - System Arb and Mem Controller - adds latency to all
48 * memory trasactions
49 * Unit 1 - I$ and System Bus
50 * Unit 2 - D$ and System Bus
51 * ..
52 * Unit 12 - IDE Disk controller and System Bus
53 *
54 * The programmers model requires writing to lat_unit reg first
55 * and then the latency value (cycles) to lat_value reg
56 */
57
58 if (CONFIG_BVCI_LAT_UNITS == 0) {
59 writel(0, base + REG_UNIT);
60 writel(lat_cycles, base + REG_VAL);
61 pr_info("BVCI Latency for all Memory Transactions %d cycles\n",
62 lat_cycles);
63 } else {
64 for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) {
65 writel(i + 1, base + REG_UNIT); /* loop is 0 based */
66 writel(lat_cycles, base + REG_VAL);
67 pr_info("BVCI Latency for Unit[%d] = %d cycles\n",
68 (i + 1), lat_cycles);
69 }
70 }
71}
72#else
73static void __init setup_bvci_lat_unit(void)
74{
75}
76#endif
77
78/*----------------------- Platform Devices -----------------------------*/ 25/*----------------------- Platform Devices -----------------------------*/
79 26
80#if IS_ENABLED(CONFIG_SERIAL_ARC) 27#if IS_ENABLED(CONFIG_SERIAL_ARC)
@@ -132,16 +79,11 @@ static void arc_fpga_serial_init(void)
132 ARRAY_SIZE(fpga_early_devs)); 79 ARRAY_SIZE(fpga_early_devs));
133 80
134 /* 81 /*
135 * ARC console driver registers itself as an early platform driver 82 * ARC console driver registers (build time) as an early platform driver
136 * of class "earlyprintk". 83 * of class "earlyprintk". However it needs explicit cmdline toggle
137 * Install it here, followed by probe of devices. 84 * "earlyprintk=ttyARC0" to be successfuly runtime registered.
138 * The installation here doesn't require earlyprintk in command line 85 * Otherwise the early probe below fails to find the driver
139 * To do so however, replace the lines below with
140 * parse_early_param();
141 * early_platform_driver_probe("earlyprintk", 1, 1);
142 * ^^
143 */ 86 */
144 early_platform_driver_register_all("earlyprintk");
145 early_platform_driver_probe("earlyprintk", 1, 0); 87 early_platform_driver_probe("earlyprintk", 1, 0);
146 88
147 /* 89 /*
@@ -165,11 +107,9 @@ static void __init plat_fpga_early_init(void)
165{ 107{
166 pr_info("[plat-arcfpga]: registering early dev resources\n"); 108 pr_info("[plat-arcfpga]: registering early dev resources\n");
167 109
168 setup_bvci_lat_unit();
169
170 arc_fpga_serial_init(); 110 arc_fpga_serial_init();
171 111
172#ifdef CONFIG_SMP 112#ifdef CONFIG_ISS_SMP_EXTN
173 iss_model_init_early_smp(); 113 iss_model_init_early_smp();
174#endif 114#endif
175} 115}
@@ -211,7 +151,7 @@ MACHINE_START(ANGEL4, "angel4")
211 .init_early = plat_fpga_early_init, 151 .init_early = plat_fpga_early_init,
212 .init_machine = plat_fpga_populate_dev, 152 .init_machine = plat_fpga_populate_dev,
213 .init_irq = plat_fpga_init_IRQ, 153 .init_irq = plat_fpga_init_IRQ,
214#ifdef CONFIG_SMP 154#ifdef CONFIG_ISS_SMP_EXTN
215 .init_smp = iss_model_init_smp, 155 .init_smp = iss_model_init_smp,
216#endif 156#endif
217MACHINE_END 157MACHINE_END
diff --git a/arch/arc/plat-arcfpga/smp.c b/arch/arc/plat-arcfpga/smp.c
index 8a12741f5f7a..92bad9122077 100644
--- a/arch/arc/plat-arcfpga/smp.c
+++ b/arch/arc/plat-arcfpga/smp.c
@@ -42,6 +42,24 @@ static void iss_model_smp_wakeup_cpu(int cpu, unsigned long pc)
42 42
43} 43}
44 44
45static inline int get_hw_config_num_irq(void)
46{
47 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
48
49 switch (val & 0x03) {
50 case 0:
51 return 16;
52 case 1:
53 return 32;
54 case 2:
55 return 8;
56 default:
57 return 0;
58 }
59
60 return 0;
61}
62
45/* 63/*
46 * Any SMP specific init any CPU does when it comes up. 64 * Any SMP specific init any CPU does when it comes up.
47 * Here we setup the CPU to enable Inter-Processor-Interrupts 65 * Here we setup the CPU to enable Inter-Processor-Interrupts
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-08 04:58:37 -0400