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authorMax Filippov <jcmvbkbc@gmail.com>2014-12-26 12:19:38 -0500
committerMark Brown <broonie@kernel.org>2015-01-08 14:52:11 -0500
commit57b7068de5d0cca8ac6e21085b843c1bbd49d3f4 (patch)
tree7f967c6eada43604a8dd30e88141f70bbc4e91b5 /Documentation/devicetree/bindings/sound
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
ASoC: add xtensa xtfpga I2S interface and platform
XTFPGA boards provides an audio subsystem that consists of TI CDCE706 clock synthesizer, I2S transmitter and TLV320AIC23 audio codec. I2S transmitter has MMIO-based interface that resembles that of the OpenCores I2S transmitter. I2S transmitter is always a master on I2S bus. There's no specialized audio DMA, sample data are transferred to I2S transmitter FIFO by CPU through memory-mapped queue interface. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/sound')
-rw-r--r--Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt18
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diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
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1Bindings for I2S controller built into xtfpga Xtensa bitstreams.
2
3Required properties:
4- compatible: shall be "cdns,xtfpga-i2s".
5- reg: memory region (address and length) with device registers.
6- interrupts: interrupt for the device.
7- clocks: phandle to the clk used as master clock. I2S bus clock
8 is derived from it.
9
10Examples:
11
12 i2s0: xtfpga-i2s@0d080000 {
13 #sound-dai-cells = <0>;
14 compatible = "cdns,xtfpga-i2s";
15 reg = <0x0d080000 0x40>;
16 interrupts = <2 1>;
17 clocks = <&cdce706 4>;
18 };