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-rw-r--r--Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt18
-rw-r--r--MAINTAINERS1
-rw-r--r--sound/soc/Kconfig1
-rw-r--r--sound/soc/Makefile1
-rw-r--r--sound/soc/xtensa/Kconfig7
-rw-r--r--sound/soc/xtensa/Makefile3
-rw-r--r--sound/soc/xtensa/xtfpga-i2s.c675
7 files changed, 706 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
new file mode 100644
index 000000000000..befd125d18bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
@@ -0,0 +1,18 @@
1Bindings for I2S controller built into xtfpga Xtensa bitstreams.
2
3Required properties:
4- compatible: shall be "cdns,xtfpga-i2s".
5- reg: memory region (address and length) with device registers.
6- interrupts: interrupt for the device.
7- clocks: phandle to the clk used as master clock. I2S bus clock
8 is derived from it.
9
10Examples:
11
12 i2s0: xtfpga-i2s@0d080000 {
13 #sound-dai-cells = <0>;
14 compatible = "cdns,xtfpga-i2s";
15 reg = <0x0d080000 0x40>;
16 interrupts = <2 1>;
17 clocks = <&cdce706 4>;
18 };
diff --git a/MAINTAINERS b/MAINTAINERS
index ddb9ac8d32b3..f1eb40f8926c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10628,6 +10628,7 @@ M: Max Filippov <jcmvbkbc@gmail.com>
10628L: linux-xtensa@linux-xtensa.org 10628L: linux-xtensa@linux-xtensa.org
10629S: Maintained 10629S: Maintained
10630F: drivers/spi/spi-xtensa-xtfpga.c 10630F: drivers/spi/spi-xtensa-xtfpga.c
10631F: sound/soc/xtensa/xtfpga-i2s.c
10631 10632
10632YAM DRIVER FOR AX.25 10633YAM DRIVER FOR AX.25
10633M: Jean-Paul Roubelat <jpr@f6fbb.org> 10634M: Jean-Paul Roubelat <jpr@f6fbb.org>
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 7d5d6444a837..dcc79aa0236b 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -55,6 +55,7 @@ source "sound/soc/spear/Kconfig"
55source "sound/soc/tegra/Kconfig" 55source "sound/soc/tegra/Kconfig"
56source "sound/soc/txx9/Kconfig" 56source "sound/soc/txx9/Kconfig"
57source "sound/soc/ux500/Kconfig" 57source "sound/soc/ux500/Kconfig"
58source "sound/soc/xtensa/Kconfig"
58 59
59# Supported codecs 60# Supported codecs
60source "sound/soc/codecs/Kconfig" 61source "sound/soc/codecs/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 865e090c8061..5b3c8f67c8db 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -36,3 +36,4 @@ obj-$(CONFIG_SND_SOC) += spear/
36obj-$(CONFIG_SND_SOC) += tegra/ 36obj-$(CONFIG_SND_SOC) += tegra/
37obj-$(CONFIG_SND_SOC) += txx9/ 37obj-$(CONFIG_SND_SOC) += txx9/
38obj-$(CONFIG_SND_SOC) += ux500/ 38obj-$(CONFIG_SND_SOC) += ux500/
39obj-$(CONFIG_SND_SOC) += xtensa/
diff --git a/sound/soc/xtensa/Kconfig b/sound/soc/xtensa/Kconfig
new file mode 100644
index 000000000000..c201beb36de6
--- /dev/null
+++ b/sound/soc/xtensa/Kconfig
@@ -0,0 +1,7 @@
1config SND_SOC_XTFPGA_I2S
2 tristate "XTFPGA I2S master"
3 select REGMAP_MMIO
4 help
5 Say Y or M if you want to add support for codecs attached to the
6 I2S interface on XTFPGA daughter board. You will also need to select
7 the drivers for the rest of XTFPGA audio subsystem.
diff --git a/sound/soc/xtensa/Makefile b/sound/soc/xtensa/Makefile
new file mode 100644
index 000000000000..15efbf914226
--- /dev/null
+++ b/sound/soc/xtensa/Makefile
@@ -0,0 +1,3 @@
1snd-soc-xtfpga-i2s-objs := xtfpga-i2s.o
2
3obj-$(CONFIG_SND_SOC_XTFPGA_I2S) += snd-soc-xtfpga-i2s.o
diff --git a/sound/soc/xtensa/xtfpga-i2s.c b/sound/soc/xtensa/xtfpga-i2s.c
new file mode 100644
index 000000000000..1cfb19e12949
--- /dev/null
+++ b/sound/soc/xtensa/xtfpga-i2s.c
@@ -0,0 +1,675 @@
1/*
2 * Xtfpga I2S controller driver
3 *
4 * Copyright (c) 2014 Cadence Design Systems Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19
20#define DRV_NAME "xtfpga-i2s"
21
22#define XTFPGA_I2S_VERSION 0x00
23#define XTFPGA_I2S_CONFIG 0x04
24#define XTFPGA_I2S_INT_MASK 0x08
25#define XTFPGA_I2S_INT_STATUS 0x0c
26#define XTFPGA_I2S_CHAN0_DATA 0x10
27#define XTFPGA_I2S_CHAN1_DATA 0x14
28#define XTFPGA_I2S_CHAN2_DATA 0x18
29#define XTFPGA_I2S_CHAN3_DATA 0x1c
30
31#define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
32#define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
33#define XTFPGA_I2S_CONFIG_LEFT 0x4
34#define XTFPGA_I2S_CONFIG_RATIO_BASE 8
35#define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
36#define XTFPGA_I2S_CONFIG_RES_BASE 16
37#define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
38#define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
39#define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
40#define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
41
42#define XTFPGA_I2S_INT_UNDERRUN 0x1
43#define XTFPGA_I2S_INT_LEVEL 0x2
44#define XTFPGA_I2S_INT_VALID 0x3
45
46#define XTFPGA_I2S_FIFO_SIZE 8192
47
48/*
49 * I2S controller operation:
50 *
51 * Enabling TX: output 1 period of zeros (starting with left channel)
52 * and then queued data.
53 *
54 * Level status and interrupt: whenever FIFO level is below FIFO trigger,
55 * level status is 1 and an IRQ is asserted (if enabled).
56 *
57 * Underrun status and interrupt: whenever FIFO is empty, underrun status
58 * is 1 and an IRQ is asserted (if enabled).
59 */
60struct xtfpga_i2s {
61 struct device *dev;
62 struct clk *clk;
63 struct regmap *regmap;
64 void __iomem *regs;
65
66 /* current playback substream. NULL if not playing.
67 *
68 * Access to that field is synchronized between the interrupt handler
69 * and userspace through RCU.
70 *
71 * Interrupt handler (threaded part) does PIO on substream data in RCU
72 * read-side critical section. Trigger callback sets and clears the
73 * pointer when the playback is started and stopped with
74 * rcu_assign_pointer. When userspace is about to free the playback
75 * stream in the pcm_close callback it synchronizes with the interrupt
76 * handler by means of synchronize_rcu call.
77 */
78 struct snd_pcm_substream *tx_substream;
79 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
80 struct snd_pcm_runtime *runtime,
81 unsigned tx_ptr);
82 unsigned tx_ptr; /* next frame index in the sample buffer */
83
84 /* current fifo level estimate.
85 * Doesn't have to be perfectly accurate, but must be not less than
86 * the actual FIFO level in order to avoid stall on push attempt.
87 */
88 unsigned tx_fifo_level;
89
90 /* FIFO level at which level interrupt occurs */
91 unsigned tx_fifo_low;
92
93 /* maximal FIFO level */
94 unsigned tx_fifo_high;
95};
96
97static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
98{
99 return reg >= XTFPGA_I2S_CONFIG;
100}
101
102static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
103{
104 return reg < XTFPGA_I2S_CHAN0_DATA;
105}
106
107static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
108{
109 return reg == XTFPGA_I2S_INT_STATUS;
110}
111
112static const struct regmap_config xtfpga_i2s_regmap_config = {
113 .reg_bits = 32,
114 .reg_stride = 4,
115 .val_bits = 32,
116 .max_register = XTFPGA_I2S_CHAN3_DATA,
117 .writeable_reg = xtfpga_i2s_wr_reg,
118 .readable_reg = xtfpga_i2s_rd_reg,
119 .volatile_reg = xtfpga_i2s_volatile_reg,
120 .cache_type = REGCACHE_FLAT,
121};
122
123/* Generate functions that do PIO from TX DMA area to FIFO for all supported
124 * stream formats.
125 * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
126 * xtfpga_pcm_tx_2x16 for 16-bit stereo.
127 *
128 * FIFO consists of 32-bit words, one word per channel, always 2 channels.
129 * If I2S interface is configured with smaller sample resolution, only
130 * the LSB of each word is used.
131 */
132#define xtfpga_pcm_tx_fn(channels, sample_bits) \
133static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
134 struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
135 unsigned tx_ptr) \
136{ \
137 const u##sample_bits (*p)[channels] = \
138 (void *)runtime->dma_area; \
139\
140 for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
141 i2s->tx_fifo_level += 2) { \
142 iowrite32(p[tx_ptr][0], \
143 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
144 iowrite32(p[tx_ptr][channels - 1], \
145 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
146 if (++tx_ptr >= runtime->buffer_size) \
147 tx_ptr = 0; \
148 } \
149 return tx_ptr; \
150}
151
152xtfpga_pcm_tx_fn(1, 16)
153xtfpga_pcm_tx_fn(2, 16)
154xtfpga_pcm_tx_fn(1, 32)
155xtfpga_pcm_tx_fn(2, 32)
156
157#undef xtfpga_pcm_tx_fn
158
159static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
160{
161 struct snd_pcm_substream *tx_substream;
162 bool tx_active;
163
164 rcu_read_lock();
165 tx_substream = rcu_dereference(i2s->tx_substream);
166 tx_active = tx_substream && snd_pcm_running(tx_substream);
167 if (tx_active) {
168 unsigned tx_ptr = ACCESS_ONCE(i2s->tx_ptr);
169 unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
170 tx_ptr);
171
172 cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
173 }
174 rcu_read_unlock();
175
176 return tx_active;
177}
178
179static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
180{
181 unsigned int_status;
182 unsigned i;
183
184 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
185 &int_status);
186
187 for (i = 0; i < 2; ++i) {
188 bool tx_active = xtfpga_pcm_push_tx(i2s);
189
190 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
191 XTFPGA_I2S_INT_VALID);
192 if (tx_active)
193 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
194 &int_status);
195
196 if (!tx_active ||
197 !(int_status & XTFPGA_I2S_INT_LEVEL))
198 break;
199
200 /* After the push the level IRQ is still asserted,
201 * means FIFO level is below tx_fifo_low. Estimate
202 * it as tx_fifo_low.
203 */
204 i2s->tx_fifo_level = i2s->tx_fifo_low;
205 }
206
207 if (!(int_status & XTFPGA_I2S_INT_LEVEL))
208 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
209 XTFPGA_I2S_INT_VALID);
210 else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
211 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
212 XTFPGA_I2S_INT_UNDERRUN);
213
214 if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
215 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
216 XTFPGA_I2S_CONFIG_INT_ENABLE |
217 XTFPGA_I2S_CONFIG_TX_ENABLE,
218 XTFPGA_I2S_CONFIG_INT_ENABLE |
219 XTFPGA_I2S_CONFIG_TX_ENABLE);
220 else
221 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
222 XTFPGA_I2S_CONFIG_INT_ENABLE |
223 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
224}
225
226static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
227{
228 struct xtfpga_i2s *i2s = dev_id;
229 struct snd_pcm_substream *tx_substream;
230 unsigned config, int_status, int_mask;
231
232 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
233 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
234 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
235
236 if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
237 !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
238 return IRQ_NONE;
239
240 /* Update FIFO level estimate in accordance with interrupt status
241 * register.
242 */
243 if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
244 i2s->tx_fifo_level = 0;
245 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
246 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
247 } else {
248 /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
249 * it as tx_fifo_low.
250 */
251 i2s->tx_fifo_level = i2s->tx_fifo_low;
252 }
253
254 rcu_read_lock();
255 tx_substream = rcu_dereference(i2s->tx_substream);
256
257 if (tx_substream && snd_pcm_running(tx_substream)) {
258 snd_pcm_period_elapsed(tx_substream);
259 if (int_status & XTFPGA_I2S_INT_UNDERRUN)
260 dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
261 __func__);
262 }
263 rcu_read_unlock();
264
265 /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
266 * not empty.
267 */
268 xtfpga_pcm_refill_fifo(i2s);
269
270 return IRQ_HANDLED;
271}
272
273static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
274 struct snd_soc_dai *dai)
275{
276 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
277
278 snd_soc_dai_set_dma_data(dai, substream, i2s);
279 return 0;
280}
281
282static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
285{
286 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
287 unsigned srate = params_rate(params);
288 unsigned channels = params_channels(params);
289 unsigned period_size = params_period_size(params);
290 unsigned sample_size = snd_pcm_format_width(params_format(params));
291 unsigned freq, ratio, level;
292 int err;
293
294 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
295 XTFPGA_I2S_CONFIG_RES_MASK,
296 sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
297
298 freq = 256 * srate;
299 err = clk_set_rate(i2s->clk, freq);
300 if (err < 0)
301 return err;
302
303 /* ratio field of the config register controls MCLK->I2S clock
304 * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
305 *
306 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
307 * and 2 for 16 bit stereo.
308 */
309 ratio = (freq - (srate * sample_size * 8)) /
310 (srate * sample_size * 4);
311
312 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
313 XTFPGA_I2S_CONFIG_RATIO_MASK,
314 ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
315
316 i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
317
318 /* period_size * 2: FIFO always gets 2 samples per frame */
319 for (level = 1;
320 i2s->tx_fifo_low / 2 >= period_size * 2 &&
321 level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
322 XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
323 i2s->tx_fifo_low /= 2;
324
325 i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
326
327 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
328 XTFPGA_I2S_CONFIG_LEVEL_MASK,
329 level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
330
331 dev_dbg(i2s->dev,
332 "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
333 __func__, srate, channels, sample_size, period_size);
334 dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
335 __func__, freq, ratio, level);
336
337 return 0;
338}
339
340static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
341 unsigned int fmt)
342{
343 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
344 return -EINVAL;
345 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
346 return -EINVAL;
347 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
348 return -EINVAL;
349
350 return 0;
351}
352
353/* PCM */
354
355static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
356 .info = SNDRV_PCM_INFO_INTERLEAVED |
357 SNDRV_PCM_INFO_MMAP_VALID |
358 SNDRV_PCM_INFO_BLOCK_TRANSFER,
359 .formats = SNDRV_PCM_FMTBIT_S16_LE |
360 SNDRV_PCM_FMTBIT_S32_LE,
361 .channels_min = 1,
362 .channels_max = 2,
363 .period_bytes_min = 2,
364 .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
365 .periods_min = 2,
366 .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
367 .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
368 .fifo_size = 16,
369};
370
371static int xtfpga_pcm_open(struct snd_pcm_substream *substream)
372{
373 struct snd_pcm_runtime *runtime = substream->runtime;
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 void *p;
376
377 snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
378 p = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
379 runtime->private_data = p;
380
381 return 0;
382}
383
384static int xtfpga_pcm_close(struct snd_pcm_substream *substream)
385{
386 synchronize_rcu();
387 return 0;
388}
389
390static int xtfpga_pcm_hw_params(struct snd_pcm_substream *substream,
391 struct snd_pcm_hw_params *hw_params)
392{
393 int ret;
394 struct snd_pcm_runtime *runtime = substream->runtime;
395 struct xtfpga_i2s *i2s = runtime->private_data;
396 unsigned channels = params_channels(hw_params);
397
398 switch (channels) {
399 case 1:
400 case 2:
401 break;
402
403 default:
404 return -EINVAL;
405
406 }
407
408 switch (params_format(hw_params)) {
409 case SNDRV_PCM_FORMAT_S16_LE:
410 i2s->tx_fn = (channels == 1) ?
411 xtfpga_pcm_tx_1x16 :
412 xtfpga_pcm_tx_2x16;
413 break;
414
415 case SNDRV_PCM_FORMAT_S32_LE:
416 i2s->tx_fn = (channels == 1) ?
417 xtfpga_pcm_tx_1x32 :
418 xtfpga_pcm_tx_2x32;
419 break;
420
421 default:
422 return -EINVAL;
423 }
424
425 ret = snd_pcm_lib_malloc_pages(substream,
426 params_buffer_bytes(hw_params));
427 return ret;
428}
429
430static int xtfpga_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
431{
432 int ret = 0;
433 struct snd_pcm_runtime *runtime = substream->runtime;
434 struct xtfpga_i2s *i2s = runtime->private_data;
435
436 switch (cmd) {
437 case SNDRV_PCM_TRIGGER_START:
438 case SNDRV_PCM_TRIGGER_RESUME:
439 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
440 ACCESS_ONCE(i2s->tx_ptr) = 0;
441 rcu_assign_pointer(i2s->tx_substream, substream);
442 xtfpga_pcm_refill_fifo(i2s);
443 break;
444
445 case SNDRV_PCM_TRIGGER_STOP:
446 case SNDRV_PCM_TRIGGER_SUSPEND:
447 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
448 rcu_assign_pointer(i2s->tx_substream, NULL);
449 break;
450
451 default:
452 ret = -EINVAL;
453 break;
454 }
455 return ret;
456}
457
458static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_pcm_substream *substream)
459{
460 struct snd_pcm_runtime *runtime = substream->runtime;
461 struct xtfpga_i2s *i2s = runtime->private_data;
462 snd_pcm_uframes_t pos = ACCESS_ONCE(i2s->tx_ptr);
463
464 return pos < runtime->buffer_size ? pos : 0;
465}
466
467static int xtfpga_pcm_new(struct snd_soc_pcm_runtime *rtd)
468{
469 struct snd_card *card = rtd->card->snd_card;
470 size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
471
472 return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
473 SNDRV_DMA_TYPE_DEV,
474 card->dev, size, size);
475}
476
477static void xtfpga_pcm_free(struct snd_pcm *pcm)
478{
479 snd_pcm_lib_preallocate_free_for_all(pcm);
480}
481
482static const struct snd_pcm_ops xtfpga_pcm_ops = {
483 .open = xtfpga_pcm_open,
484 .close = xtfpga_pcm_close,
485 .ioctl = snd_pcm_lib_ioctl,
486 .hw_params = xtfpga_pcm_hw_params,
487 .trigger = xtfpga_pcm_trigger,
488 .pointer = xtfpga_pcm_pointer,
489};
490
491static const struct snd_soc_platform_driver xtfpga_soc_platform = {
492 .pcm_new = xtfpga_pcm_new,
493 .pcm_free = xtfpga_pcm_free,
494 .ops = &xtfpga_pcm_ops,
495};
496
497static const struct snd_soc_component_driver xtfpga_i2s_component = {
498 .name = DRV_NAME,
499};
500
501static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
502 .startup = xtfpga_i2s_startup,
503 .hw_params = xtfpga_i2s_hw_params,
504 .set_fmt = xtfpga_i2s_set_fmt,
505};
506
507static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
508 {
509 .name = "xtfpga-i2s",
510 .id = 0,
511 .playback = {
512 .channels_min = 1,
513 .channels_max = 2,
514 .rates = SNDRV_PCM_RATE_8000_96000,
515 .formats = SNDRV_PCM_FMTBIT_S16_LE |
516 SNDRV_PCM_FMTBIT_S32_LE,
517 },
518 .ops = &xtfpga_i2s_dai_ops,
519 },
520};
521
522static int xtfpga_i2s_runtime_suspend(struct device *dev)
523{
524 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
525
526 clk_disable_unprepare(i2s->clk);
527 return 0;
528}
529
530static int xtfpga_i2s_runtime_resume(struct device *dev)
531{
532 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
533 int ret;
534
535 ret = clk_prepare_enable(i2s->clk);
536 if (ret) {
537 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
538 return ret;
539 }
540 return 0;
541}
542
543static int xtfpga_i2s_probe(struct platform_device *pdev)
544{
545 struct xtfpga_i2s *i2s;
546 struct resource *mem;
547 int err, irq;
548
549 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
550 if (!i2s) {
551 err = -ENOMEM;
552 goto err;
553 }
554 platform_set_drvdata(pdev, i2s);
555 i2s->dev = &pdev->dev;
556 dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
557
558 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
559 i2s->regs = devm_ioremap_resource(&pdev->dev, mem);
560 if (IS_ERR(i2s->regs)) {
561 err = PTR_ERR(i2s->regs);
562 goto err;
563 }
564
565 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
566 &xtfpga_i2s_regmap_config);
567 if (IS_ERR(i2s->regmap)) {
568 dev_err(&pdev->dev, "regmap init failed\n");
569 err = PTR_ERR(i2s->regmap);
570 goto err;
571 }
572
573 i2s->clk = devm_clk_get(&pdev->dev, NULL);
574 if (IS_ERR(i2s->clk)) {
575 dev_err(&pdev->dev, "couldn't get clock\n");
576 err = PTR_ERR(i2s->clk);
577 goto err;
578 }
579
580 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
581 (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
582 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
583 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
584
585 irq = platform_get_irq(pdev, 0);
586 if (irq < 0) {
587 dev_err(&pdev->dev, "No IRQ resource\n");
588 err = irq;
589 goto err;
590 }
591 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
592 xtfpga_i2s_threaded_irq_handler,
593 IRQF_SHARED | IRQF_ONESHOT,
594 pdev->name, i2s);
595 if (err < 0) {
596 dev_err(&pdev->dev, "request_irq failed\n");
597 goto err;
598 }
599
600 err = snd_soc_register_platform(&pdev->dev, &xtfpga_soc_platform);
601 if (err < 0) {
602 dev_err(&pdev->dev, "couldn't register platform\n");
603 goto err;
604 }
605 err = devm_snd_soc_register_component(&pdev->dev,
606 &xtfpga_i2s_component,
607 xtfpga_i2s_dai,
608 ARRAY_SIZE(xtfpga_i2s_dai));
609 if (err < 0) {
610 dev_err(&pdev->dev, "couldn't register component\n");
611 goto err_unregister_platform;
612 }
613
614 pm_runtime_enable(&pdev->dev);
615 if (!pm_runtime_enabled(&pdev->dev)) {
616 err = xtfpga_i2s_runtime_resume(&pdev->dev);
617 if (err)
618 goto err_pm_disable;
619 }
620 return 0;
621
622err_pm_disable:
623 pm_runtime_disable(&pdev->dev);
624err_unregister_platform:
625 snd_soc_unregister_platform(&pdev->dev);
626err:
627 dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
628 return err;
629}
630
631static int xtfpga_i2s_remove(struct platform_device *pdev)
632{
633 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
634
635 snd_soc_unregister_platform(&pdev->dev);
636 if (i2s->regmap && !IS_ERR(i2s->regmap)) {
637 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
638 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
639 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
640 XTFPGA_I2S_INT_VALID);
641 }
642 pm_runtime_disable(&pdev->dev);
643 if (!pm_runtime_status_suspended(&pdev->dev))
644 xtfpga_i2s_runtime_suspend(&pdev->dev);
645 return 0;
646}
647
648#ifdef CONFIG_OF
649static const struct of_device_id xtfpga_i2s_of_match[] = {
650 { .compatible = "cdns,xtfpga-i2s", },
651 {},
652};
653MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
654#endif
655
656static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
657 SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
658 xtfpga_i2s_runtime_resume, NULL)
659};
660
661static struct platform_driver xtfpga_i2s_driver = {
662 .probe = xtfpga_i2s_probe,
663 .remove = xtfpga_i2s_remove,
664 .driver = {
665 .name = "xtfpga-i2s",
666 .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
667 .pm = &xtfpga_i2s_pm_ops,
668 },
669};
670
671module_platform_driver(xtfpga_i2s_driver);
672
673MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
674MODULE_DESCRIPTION("xtfpga I2S controller driver");
675MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 03:02:17 -0500