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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 13:39:26 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 13:39:26 -0500
commitdb5b0ae00712b5176d7405e7a1dd2bfd6e8f5070 (patch)
tree4e874d81ca9037dda1007178bbc9613649d43305 /Documentation/devicetree/bindings/clock
parent6be35c700f742e911ecedd07fcc43d4439922334 (diff)
parent64507dd7028e3e0145077e73b8374bd75aea117c (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree conversions and enablement from Olof Johansson: "Continued device tree conversion and enablement across a number of platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other smaller series as well. ux500 has seen continued conversion for platforms. Several platforms have seen pinctrl-via-devicetree conversions for simpler multiplatform. Tegra is adding data for new devices/drivers, and Exynos has a bunch of new bindings and devices added as well. So, pretty much the same progression in the right direction as the last few releases." Fix up conflicts as per Olof. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits) ARM: ux500: Rename dbx500 cpufreq code to be more generic ARM: dts: add missing ux500 device trees ARM: ux500: Stop registering the PCM driver from platform code ARM: ux500: Move board specific GPIO info out to subordinate DTS files ARM: ux500: Disable the MMCI gpio-regulator by default ARM: Kirkwood: remove kirkwood_ehci_init() from new boards ARM: Kirkwood: Add support LED of OpenBlocks A6 ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6 ARM: kirkwood: Add NAND partiton map for OpenBlocks A6 ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6 ARM: kirkwood: Add support DT of second I2C bus ARM: kirkwood: Convert mplcec4 board to pinctrl ARM: Kirkwood: Convert km_kirkwood to pinctrl ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl ARM: Kirkwood: Convert IX2-200 to pinctrl. ARM: Kirkwood: Convert lsxl boards to pinctrl. ARM: Kirkwood: Convert ib62x0 to pinctrl. ARM: Kirkwood: Convert GoFlex Net to pinctrl. ARM: Kirkwood: Convert dreamplug to pinctrl. ARM: Kirkwood: Convert dockstar to pinctrl. ...
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/imx25-clock.txt162
-rw-r--r--Documentation/devicetree/bindings/clock/zynq-7000.txt55
2 files changed, 217 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 000000000000..c2a3525ecb4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
1* Clock bindings for Freescale i.MX25
2
3Required properties:
4- compatible: Should be "fsl,imx25-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX25
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 osc 1
17 mpll 2
18 upll 3
19 mpll_cpu_3_4 4
20 cpu_sel 5
21 cpu 6
22 ahb 7
23 usb_div 8
24 ipg 9
25 per0_sel 10
26 per1_sel 11
27 per2_sel 12
28 per3_sel 13
29 per4_sel 14
30 per5_sel 15
31 per6_sel 16
32 per7_sel 17
33 per8_sel 18
34 per9_sel 19
35 per10_sel 20
36 per11_sel 21
37 per12_sel 22
38 per13_sel 23
39 per14_sel 24
40 per15_sel 25
41 per0 26
42 per1 27
43 per2 28
44 per3 29
45 per4 30
46 per5 31
47 per6 32
48 per7 33
49 per8 34
50 per9 35
51 per10 36
52 per11 37
53 per12 38
54 per13 39
55 per14 40
56 per15 41
57 csi_ipg_per 42
58 epit_ipg_per 43
59 esai_ipg_per 44
60 esdhc1_ipg_per 45
61 esdhc2_ipg_per 46
62 gpt_ipg_per 47
63 i2c_ipg_per 48
64 lcdc_ipg_per 49
65 nfc_ipg_per 50
66 owire_ipg_per 51
67 pwm_ipg_per 52
68 sim1_ipg_per 53
69 sim2_ipg_per 54
70 ssi1_ipg_per 55
71 ssi2_ipg_per 56
72 uart_ipg_per 57
73 ata_ahb 58
74 reserved 59
75 csi_ahb 60
76 emi_ahb 61
77 esai_ahb 62
78 esdhc1_ahb 63
79 esdhc2_ahb 64
80 fec_ahb 65
81 lcdc_ahb 66
82 rtic_ahb 67
83 sdma_ahb 68
84 slcdc_ahb 69
85 usbotg_ahb 70
86 reserved 71
87 reserved 72
88 reserved 73
89 reserved 74
90 can1_ipg 75
91 can2_ipg 76
92 csi_ipg 77
93 cspi1_ipg 78
94 cspi2_ipg 79
95 cspi3_ipg 80
96 dryice_ipg 81
97 ect_ipg 82
98 epit1_ipg 83
99 epit2_ipg 84
100 reserved 85
101 esdhc1_ipg 86
102 esdhc2_ipg 87
103 fec_ipg 88
104 reserved 89
105 reserved 90
106 reserved 91
107 gpt1_ipg 92
108 gpt2_ipg 93
109 gpt3_ipg 94
110 gpt4_ipg 95
111 reserved 96
112 reserved 97
113 reserved 98
114 iim_ipg 99
115 reserved 100
116 reserved 101
117 kpp_ipg 102
118 lcdc_ipg 103
119 reserved 104
120 pwm1_ipg 105
121 pwm2_ipg 106
122 pwm3_ipg 107
123 pwm4_ipg 108
124 rngb_ipg 109
125 reserved 110
126 scc_ipg 111
127 sdma_ipg 112
128 sim1_ipg 113
129 sim2_ipg 114
130 slcdc_ipg 115
131 spba_ipg 116
132 ssi1_ipg 117
133 ssi2_ipg 118
134 tsc_ipg 119
135 uart1_ipg 120
136 uart2_ipg 121
137 uart3_ipg 122
138 uart4_ipg 123
139 uart5_ipg 124
140 reserved 125
141 wdt_ipg 126
142
143Examples:
144
145clks: ccm@53f80000 {
146 compatible = "fsl,imx25-ccm";
147 reg = <0x53f80000 0x4000>;
148 interrupts = <31>;
149 clock-output-names = ...
150 "uart_ipg",
151 "uart_serial",
152 ...;
153};
154
155uart1: serial@43f90000 {
156 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
157 reg = <0x43f90000 0x4000>;
158 interrupts = <45>;
159 clocks = <&clks 79>, <&clks 50>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162};
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
new file mode 100644
index 000000000000..23ae1db1bc13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -0,0 +1,55 @@
1Device Tree Clock bindings for the Zynq 7000 EPP
2
3The Zynq EPP has several different clk providers, each with there own bindings.
4The purpose of this document is to document their usage.
5
6See clock_bindings.txt for more information on the generic clock bindings.
7See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
9== PLLs ==
10
11Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
13Required properties:
14- #clock-cells : shall be 0 (only one clock is output from this node)
15- compatible : "xlnx,zynq-pll"
16- reg : pair of u32 values, which are the address offsets within the SLCR
17 of the relevant PLL_CTRL register and PLL_CFG register respectively
18- clocks : phandle for parent clock. should be the phandle for ps_clk
19
20Optional properties:
21- clock-output-names : name of the output clock
22
23Example:
24 armpll: armpll {
25 #clock-cells = <0>;
26 compatible = "xlnx,zynq-pll";
27 clocks = <&ps_clk>;
28 reg = <0x100 0x110>;
29 clock-output-names = "armpll";
30 };
31
32== Peripheral clocks ==
33
34Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
36Required properties:
37- #clock-cells : shall be 1
38- compatible : "xlnx,zynq-periph-clock"
39- reg : a single u32 value, describing the offset within the SLCR where
40 the CLK_CTRL register is found for this peripheral
41- clocks : phandle for parent clocks. should hold phandles for
42 the IO_PLL, ARM_PLL, and DDR_PLL in order
43- clock-output-names : names of the output clock(s). For peripherals that have
44 two output clocks (for example, the UART), two clocks
45 should be listed.
46
47Example:
48 uart_clk: uart_clk {
49 #clock-cells = <1>;
50 compatible = "xlnx,zynq-periph-clock";
51 clocks = <&iopll &armpll &ddrpll>;
52 reg = <0x154>;
53 clock-output-names = "uart0_ref_clk",
54 "uart1_ref_clk";
55 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 03:38:02 -0500