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-rw-r--r--Documentation/devicetree/bindings/arm/exynos/power_domain.txt15
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt4
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata-phy.txt14
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata.txt17
-rw-r--r--Documentation/devicetree/bindings/clock/imx25-clock.txt162
-rw-r--r--Documentation/devicetree/bindings/clock/zynq-7000.txt55
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmi.txt22
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt12
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt12
-rw-r--r--Documentation/devicetree/bindings/drm/exynos/mixer.txt15
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-poweroff.txt22
-rw-r--r--Documentation/devicetree/bindings/input/touchscreen/bu21013.txt28
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt23
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt39
-rw-r--r--Documentation/devicetree/bindings/usb/ehci-orion.txt15
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--Documentation/devicetree/bindings/watchdog/atmel-wdt.txt15
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/Kconfig.debug43
-rw-r--r--arch/arm/boot/dts/Makefile17
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi6
-rw-r--r--arch/arm/boot/dts/ccu9540.dts72
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi184
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi56
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts10
-rw-r--r--arch/arm/boot/dts/dove.dtsi19
-rw-r--r--arch/arm/boot/dts/evk-pro3.dts12
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi54
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts70
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi56
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts16
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts87
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi12
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts45
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi965
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi69
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts56
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts43
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi62
-rw-r--r--arch/arm/boot/dts/href.dtsi273
-rw-r--r--arch/arm/boot/dts/hrefprev60.dts48
-rw-r--r--arch/arm/boot/dts/hrefv60plus.dts217
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts23
-rw-r--r--arch/arm/boot/dts/imx23.dtsi13
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts44
-rw-r--r--arch/arm/boot/dts/imx25.dtsi515
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts89
-rw-r--r--arch/arm/boot/dts/imx27.dtsi5
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts85
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts154
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts46
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts33
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts13
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts169
-rw-r--r--arch/arm/boot/dts/imx28.dtsi35
-rw-r--r--arch/arm/boot/dts/imx51.dtsi43
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts62
-rw-r--r--arch/arm/boot/dts/imx53.dtsi92
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts64
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts18
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi114
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi44
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi45
-rw-r--r--arch/arm/boot/dts/kirkwood-98dx4122.dtsi31
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi140
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts37
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts21
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts73
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts40
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts51
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts89
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts17
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxl.dtsi95
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts59
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts59
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6281.dts31
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts31
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi17
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi7
-rw-r--r--arch/arm/boot/dts/snowball.dts140
-rw-r--r--arch/arm/boot/dts/stuib.dtsi78
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts25
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi88
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts9
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts54
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts90
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts21
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi137
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi37
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi147
-rw-r--r--arch/arm/boot/dts/u9540.dts72
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi166
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts63
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts44
-rw-r--r--arch/arm/configs/mxs_defconfig6
-rw-r--r--arch/arm/configs/u8500_defconfig1
-rw-r--r--arch/arm/include/debug/imx.S20
-rw-r--r--arch/arm/mach-davinci/Makefile.boot2
-rw-r--r--arch/arm/mach-exynos/Kconfig1
-rw-r--r--arch/arm/mach-exynos/Makefile1
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c4
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c21
-rw-r--r--arch/arm/mach-exynos/common.c7
-rw-r--r--arch/arm/mach-exynos/dev-drm.c29
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h2
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c4
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c42
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c3
-rw-r--r--arch/arm/mach-exynos/mach-origen.c3
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c3
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c3
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c3
-rw-r--r--arch/arm/mach-exynos/pm_domains.c93
-rw-r--r--arch/arm/mach-imx/Kconfig18
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/clk-imx25.c119
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c1
-rw-r--r--arch/arm/mach-imx/common.h1
-rw-r--r--arch/arm/mach-imx/imx25-dt.c48
-rw-r--r--arch/arm/mach-imx/lluart.c28
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c35
-rw-r--r--arch/arm/mach-imx/mx6q.h4
-rw-r--r--arch/arm/mach-kirkwood/Kconfig5
-rw-r--r--arch/arm/mach-kirkwood/board-dnskw.c54
-rw-r--r--arch/arm/mach-kirkwood/board-dockstar.c16
-rw-r--r--arch/arm/mach-kirkwood/board-dreamplug.c15
-rw-r--r--arch/arm/mach-kirkwood/board-goflexnet.c24
-rw-r--r--arch/arm/mach-kirkwood/board-ib62x0.c35
-rw-r--r--arch/arm/mach-kirkwood/board-iconnect.c18
-rw-r--r--arch/arm/mach-kirkwood/board-iomega_ix2_200.c26
-rw-r--r--arch/arm/mach-kirkwood/board-km_kirkwood.c13
-rw-r--r--arch/arm/mach-kirkwood/board-lsxl.c28
-rw-r--r--arch/arm/mach-kirkwood/board-mplcec4.c36
-rw-r--r--arch/arm/mach-kirkwood/board-ns2.c1
-rw-r--r--arch/arm/mach-kirkwood/board-nsa310.c4
-rw-r--r--arch/arm/mach-kirkwood/board-openblocks_a6.c5
-rw-r--r--arch/arm/mach-kirkwood/board-ts219.c26
-rw-r--r--arch/arm/mach-kirkwood/board-usi_topkick.c1
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c56
-rw-r--r--arch/arm/mach-mxs/timer.c10
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c16
-rw-r--r--arch/arm/mach-ux500/board-mop500-stuib.c22
-rw-r--r--arch/arm/mach-ux500/board-mop500.c146
-rw-r--r--arch/arm/mach-ux500/board-mop500.h10
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c109
-rw-r--r--arch/arm/mach-ux500/cpu.c3
-rw-r--r--arch/arm/mach-zynq/common.c33
-rw-r--r--arch/arm/mach-zynq/common.h4
-rw-r--r--arch/arm/mach-zynq/include/mach/zynq_soc.h16
-rw-r--r--arch/arm/mach-zynq/timer.c297
-rw-r--r--arch/arm/plat-orion/irq.c6
-rw-r--r--arch/arm/plat-samsung/devs.c1
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/mfc.h11
-rw-r--r--arch/arm/plat-samsung/s5p-dev-mfc.c34
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-zynq.c383
-rw-r--r--drivers/gpio/Kconfig2
-rw-r--r--drivers/gpio/gpio-samsung.c43
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c22
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c568
-rw-r--r--drivers/power/Kconfig3
-rw-r--r--drivers/power/Makefile1
-rw-r--r--drivers/power/reset/Kconfig15
-rw-r--r--drivers/power/reset/Makefile1
-rw-r--r--drivers/power/reset/gpio-poweroff.c129
-rw-r--r--drivers/usb/host/ehci-orion.c38
-rw-r--r--drivers/watchdog/at91sam9_wdt.c11
-rw-r--r--include/linux/clk/zynq.h24
178 files changed, 8121 insertions, 1444 deletions
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 6528e215c5fe..5216b419016a 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -4,14 +4,13 @@ Exynos processors include support for multiple power domains which are used
4to gate power to one or more peripherals on the processor. 4to gate power to one or more peripherals on the processor.
5 5
6Required Properties: 6Required Properties:
7- compatiable: should be one of the following. 7- compatible: should be one of the following.
8 * samsung,exynos4210-pd - for exynos4210 type power domain. 8 * samsung,exynos4210-pd - for exynos4210 type power domain.
9- reg: physical base address of the controller and length of memory mapped 9- reg: physical base address of the controller and length of memory mapped
10 region. 10 region.
11 11
12Optional Properties: 12Node of a device using power domains must have a samsung,power-domain property
13- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off 13defined with a phandle to respective power domain.
14 state during boot and remains to be turned-off until explicitly turned-on.
15 14
16Example: 15Example:
17 16
@@ -19,3 +18,11 @@ Example:
19 compatible = "samsung,exynos4210-pd"; 18 compatible = "samsung,exynos4210-pd";
20 reg = <0x10023C00 0x10>; 19 reg = <0x10023C00 0x10>;
21 }; 20 };
21
22Example of the node using power domain:
23
24 node {
25 /* ... */
26 samsung,power-domain = <&lcd0>;
27 /* ... */
28 };
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index ac9e7516756e..f79818711e83 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -41,6 +41,10 @@ i.MX6 Quad SABRE Smart Device Board
41Required root node properties: 41Required root node properties:
42 - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; 42 - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
43 43
44i.MX6 Quad SABRE Automotive Board
45Required root node properties:
46 - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
47
44Generic i.MX boards 48Generic i.MX boards
45------------------- 49-------------------
46 50
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
new file mode 100644
index 000000000000..37824fac688e
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
@@ -0,0 +1,14 @@
1* Samsung SATA PHY Controller
2
3SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
4Each SATA PHY controller should have its own node.
5
6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata-phy"
8- reg : <registers mapping>
9
10Example:
11 sata@ffe07000 {
12 compatible = "samsung,exynos5-sata-phy";
13 reg = <0xffe07000 0x1000>;
14 };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
new file mode 100644
index 000000000000..0849f1025e34
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -0,0 +1,17 @@
1* Samsung AHCI SATA Controller
2
3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node.
5
6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata"
8- interrupts : <interrupt mapping for SATA IRQ>
9- reg : <registers mapping>
10- samsung,sata-freq : <frequency in MHz>
11
12Example:
13 sata@ffe08000 {
14 compatible = "samsung,exynos5-sata";
15 reg = <0xffe08000 0x1000>;
16 interrupts = <115>;
17 };
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 000000000000..c2a3525ecb4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
1* Clock bindings for Freescale i.MX25
2
3Required properties:
4- compatible: Should be "fsl,imx25-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX25
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 osc 1
17 mpll 2
18 upll 3
19 mpll_cpu_3_4 4
20 cpu_sel 5
21 cpu 6
22 ahb 7
23 usb_div 8
24 ipg 9
25 per0_sel 10
26 per1_sel 11
27 per2_sel 12
28 per3_sel 13
29 per4_sel 14
30 per5_sel 15
31 per6_sel 16
32 per7_sel 17
33 per8_sel 18
34 per9_sel 19
35 per10_sel 20
36 per11_sel 21
37 per12_sel 22
38 per13_sel 23
39 per14_sel 24
40 per15_sel 25
41 per0 26
42 per1 27
43 per2 28
44 per3 29
45 per4 30
46 per5 31
47 per6 32
48 per7 33
49 per8 34
50 per9 35
51 per10 36
52 per11 37
53 per12 38
54 per13 39
55 per14 40
56 per15 41
57 csi_ipg_per 42
58 epit_ipg_per 43
59 esai_ipg_per 44
60 esdhc1_ipg_per 45
61 esdhc2_ipg_per 46
62 gpt_ipg_per 47
63 i2c_ipg_per 48
64 lcdc_ipg_per 49
65 nfc_ipg_per 50
66 owire_ipg_per 51
67 pwm_ipg_per 52
68 sim1_ipg_per 53
69 sim2_ipg_per 54
70 ssi1_ipg_per 55
71 ssi2_ipg_per 56
72 uart_ipg_per 57
73 ata_ahb 58
74 reserved 59
75 csi_ahb 60
76 emi_ahb 61
77 esai_ahb 62
78 esdhc1_ahb 63
79 esdhc2_ahb 64
80 fec_ahb 65
81 lcdc_ahb 66
82 rtic_ahb 67
83 sdma_ahb 68
84 slcdc_ahb 69
85 usbotg_ahb 70
86 reserved 71
87 reserved 72
88 reserved 73
89 reserved 74
90 can1_ipg 75
91 can2_ipg 76
92 csi_ipg 77
93 cspi1_ipg 78
94 cspi2_ipg 79
95 cspi3_ipg 80
96 dryice_ipg 81
97 ect_ipg 82
98 epit1_ipg 83
99 epit2_ipg 84
100 reserved 85
101 esdhc1_ipg 86
102 esdhc2_ipg 87
103 fec_ipg 88
104 reserved 89
105 reserved 90
106 reserved 91
107 gpt1_ipg 92
108 gpt2_ipg 93
109 gpt3_ipg 94
110 gpt4_ipg 95
111 reserved 96
112 reserved 97
113 reserved 98
114 iim_ipg 99
115 reserved 100
116 reserved 101
117 kpp_ipg 102
118 lcdc_ipg 103
119 reserved 104
120 pwm1_ipg 105
121 pwm2_ipg 106
122 pwm3_ipg 107
123 pwm4_ipg 108
124 rngb_ipg 109
125 reserved 110
126 scc_ipg 111
127 sdma_ipg 112
128 sim1_ipg 113
129 sim2_ipg 114
130 slcdc_ipg 115
131 spba_ipg 116
132 ssi1_ipg 117
133 ssi2_ipg 118
134 tsc_ipg 119
135 uart1_ipg 120
136 uart2_ipg 121
137 uart3_ipg 122
138 uart4_ipg 123
139 uart5_ipg 124
140 reserved 125
141 wdt_ipg 126
142
143Examples:
144
145clks: ccm@53f80000 {
146 compatible = "fsl,imx25-ccm";
147 reg = <0x53f80000 0x4000>;
148 interrupts = <31>;
149 clock-output-names = ...
150 "uart_ipg",
151 "uart_serial",
152 ...;
153};
154
155uart1: serial@43f90000 {
156 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
157 reg = <0x43f90000 0x4000>;
158 interrupts = <45>;
159 clocks = <&clks 79>, <&clks 50>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162};
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
new file mode 100644
index 000000000000..23ae1db1bc13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -0,0 +1,55 @@
1Device Tree Clock bindings for the Zynq 7000 EPP
2
3The Zynq EPP has several different clk providers, each with there own bindings.
4The purpose of this document is to document their usage.
5
6See clock_bindings.txt for more information on the generic clock bindings.
7See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
9== PLLs ==
10
11Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
13Required properties:
14- #clock-cells : shall be 0 (only one clock is output from this node)
15- compatible : "xlnx,zynq-pll"
16- reg : pair of u32 values, which are the address offsets within the SLCR
17 of the relevant PLL_CTRL register and PLL_CFG register respectively
18- clocks : phandle for parent clock. should be the phandle for ps_clk
19
20Optional properties:
21- clock-output-names : name of the output clock
22
23Example:
24 armpll: armpll {
25 #clock-cells = <0>;
26 compatible = "xlnx,zynq-pll";
27 clocks = <&ps_clk>;
28 reg = <0x100 0x110>;
29 clock-output-names = "armpll";
30 };
31
32== Peripheral clocks ==
33
34Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
36Required properties:
37- #clock-cells : shall be 1
38- compatible : "xlnx,zynq-periph-clock"
39- reg : a single u32 value, describing the offset within the SLCR where
40 the CLK_CTRL register is found for this peripheral
41- clocks : phandle for parent clocks. should hold phandles for
42 the IO_PLL, ARM_PLL, and DDR_PLL in order
43- clock-output-names : names of the output clock(s). For peripherals that have
44 two output clocks (for example, the UART), two clocks
45 should be listed.
46
47Example:
48 uart_clk: uart_clk {
49 #clock-cells = <1>;
50 compatible = "xlnx,zynq-periph-clock";
51 clocks = <&iopll &armpll &ddrpll>;
52 reg = <0x154>;
53 clock-output-names = "uart0_ref_clk",
54 "uart1_ref_clk";
55 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
new file mode 100644
index 000000000000..589edee37394
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
@@ -0,0 +1,22 @@
1Device-Tree bindings for drm hdmi driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmi".
5- reg: physical base address of the hdmi and length of memory mapped
6 region.
7- interrupts: interrupt number to the cpu.
8- hpd-gpio: following information about the hotplug gpio pin.
9 a) phandle of the gpio controller node.
10 b) pin number within the gpio controller.
11 c) pin function mode.
12 d) optional flags and pull up/down.
13 e) drive strength.
14
15Example:
16
17 hdmi {
18 compatible = "samsung,exynos5-hdmi";
19 reg = <0x14530000 0x100000>;
20 interrupts = <0 95 0>;
21 hpd-gpio = <&gpx3 7 0xf 1 3>;
22 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
new file mode 100644
index 000000000000..fa166d945809
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
@@ -0,0 +1,12 @@
1Device-Tree bindings for hdmiddc driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmiddc".
5- reg: I2C address of the hdmiddc device.
6
7Example:
8
9 hdmiddc {
10 compatible = "samsung,exynos5-hdmiddc";
11 reg = <0x50>;
12 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
new file mode 100644
index 000000000000..858f4f9b902f
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
@@ -0,0 +1,12 @@
1Device-Tree bindings for hdmiphy driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-hdmiphy".
5- reg: I2C address of the hdmiphy device.
6
7Example:
8
9 hdmiphy {
10 compatible = "samsung,exynos5-hdmiphy";
11 reg = <0x38>;
12 };
diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
new file mode 100644
index 000000000000..9b2ea0343566
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
@@ -0,0 +1,15 @@
1Device-Tree bindings for mixer driver
2
3Required properties:
4- compatible: value should be "samsung,exynos5-mixer".
5- reg: physical base address of the mixer and length of memory mapped
6 region.
7- interrupts: interrupt number to the cpu.
8
9Example:
10
11 mixer {
12 compatible = "samsung,exynos5-mixer";
13 reg = <0x14450000 0x10000>;
14 interrupts = <0 94 0>;
15 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
new file mode 100644
index 000000000000..558cdf3c9abc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
@@ -0,0 +1,22 @@
1GPIO line that should be set high/low to power off a device
2
3Required properties:
4- compatible : should be "gpio-poweroff".
5- gpios : The GPIO to set high/low, see "gpios property" in
6 Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
7 low to power down the board set it to "Active Low", otherwise set
8 gpio to "Active High".
9
10Optional properties:
11- input : Initially configure the GPIO line as an input. Only reconfigure
12 it to an output when the pm_power_off function is called. If this optional
13 property is not specified, the GPIO is initialized as an output in its
14 inactive state.
15
16
17Examples:
18
19gpio-poweroff {
20 compatible = "gpio-poweroff";
21 gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
22};
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
new file mode 100644
index 000000000000..ca5a2c86480c
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
@@ -0,0 +1,28 @@
1* Rohm BU21013 Touch Screen
2
3Required properties:
4 - compatible : "rohm,bu21013_tp"
5 - reg : I2C device address
6
7Optional properties:
8 - touch-gpio : GPIO pin registering a touch event
9 - <supply_name>-supply : Phandle to a regulator supply
10 - rohm,touch-max-x : Maximum outward permitted limit in the X axis
11 - rohm,touch-max-y : Maximum outward permitted limit in the Y axis
12 - rohm,flip-x : Flip touch coordinates on the X axis
13 - rohm,flip-y : Flip touch coordinates on the Y axis
14
15Example:
16
17 i2c@80110000 {
18 bu21013_tp@0x5c {
19 compatible = "rohm,bu21013_tp";
20 reg = <0x5c>;
21 touch-gpio = <&gpio2 20 0x4>;
22 avdd-supply = <&ab8500_ldo_aux1_reg>;
23
24 rohm,touch-max-x = <384>;
25 rohm,touch-max-y = <704>;
26 rohm,flip-y;
27 };
28 };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000000000000..67ec3d4ccc7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,23 @@
1* Samsung Multi Format Codec (MFC)
2
3Multi Format Codec (MFC) is the IP present in Samsung SoCs which
4supports high resolution decoding and encoding functionalities.
5The MFC device driver is a v4l2 driver which can encode/decode
6video raw/elementary streams and has support for all popular
7video codecs.
8
9Required properties:
10 - compatible : value should be either one among the following
11 (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12 (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13
14 - reg : Physical base address of the IP registers and length of memory
15 mapped region.
16
17 - interrupts : MFC interrupt number to the CPU.
18
19 - samsung,mfc-r : Base address of the first memory bank used by MFC
20 for DMA contiguous memory allocation and its size.
21
22 - samsung,mfc-l : Base address of the second memory bank used by MFC
23 for DMA contiguous memory allocation and its size.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 361bccb7ec89..95daf6335c37 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -7,8 +7,10 @@ Required properties:
7- compatible: "marvell,88f6180-pinctrl", 7- compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", 8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" 9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10 "marvell,98dx4122-pinctrl"
10 11
11This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. 12This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
12 14
13Available mpp pins/groups and functions: 15Available mpp pins/groups and functions:
14Note: brackets (x) are not part of the mpp name for marvell,function and given 16Note: brackets (x) are not part of the mpp name for marvell,function and given
@@ -277,3 +279,40 @@ mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
277mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) 279mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
278mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) 280mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
279mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) 281mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
282
283* Marvell Bobcat 98dx4122
284
285name pins functions
286================================================================================
287mpp0 0 gpio, nand(io2), spi(cs)
288mpp1 1 gpo, nand(io3), spi(mosi)
289mpp2 2 gpo, nand(io4), spi(sck)
290mpp3 3 gpo, nand(io5), spi(miso)
291mpp4 4 gpio, nand(io6), uart0(rxd)
292mpp5 5 gpo, nand(io7), uart0(txd)
293mpp6 6 sysrst(out), spi(mosi)
294mpp7 7 gpo, pex(rsto), spi(cs)
295mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts)
296mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts)
297mpp10 10 gpo, spi(sck), uart0(txd)
298mpp11 11 gpio, spi(miso), uart0(rxd)
299mpp13 13 gpio, uart1(txd)
300mpp14 14 gpio, uart1(rxd)
301mpp15 15 gpio, uart0(rts)
302mpp16 16 gpio, uart0(cts)
303mpp18 18 gpo, nand(io0)
304mpp19 19 gpo, nand(io1)
305mpp34 34 gpio
306mpp35 35 gpio
307mpp36 36 gpio
308mpp37 37 gpio
309mpp38 38 gpio
310mpp39 39 gpio
311mpp40 40 gpio
312mpp41 41 gpio
313mpp42 42 gpio
314mpp43 43 gpio
315mpp44 44 gpio
316mpp45 45 gpio
317mpp49 49 gpio
318
diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt
new file mode 100644
index 000000000000..6bc09ec14c4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt
@@ -0,0 +1,15 @@
1* EHCI controller, Orion Marvell variants
2
3Required properties:
4- compatible: must be "marvell,orion-ehci"
5- reg: physical base address of the controller and length of memory mapped
6 region.
7- interrupts: The EHCI interrupt
8
9Example:
10
11 ehci@50000 {
12 compatible = "marvell,orion-ehci";
13 reg = <0x50000 0x1000>;
14 interrupts = <19>;
15 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 770a0193ca1b..902b1b1f568e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -55,4 +55,5 @@ ti Texas Instruments
55via VIA Technologies, Inc. 55via VIA Technologies, Inc.
56wlf Wolfson Microelectronics 56wlf Wolfson Microelectronics
57wm Wondermedia Technologies, Inc. 57wm Wondermedia Technologies, Inc.
58winbond Winbond Electronics corp.
58xlnx Xilinx 59xlnx Xilinx
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
new file mode 100644
index 000000000000..2957ebb5aa71
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -0,0 +1,15 @@
1* Atmel Watchdog Timers
2
3** at91sam9-wdt
4
5Required properties:
6- compatible: must be "atmel,at91sam9260-wdt".
7- reg: physical base address of the controller and length of memory mapped
8 region.
9
10Example:
11
12 watchdog@fffffd40 {
13 compatible = "atmel,at91sam9260-wdt";
14 reg = <0xfffffd40 0x10>;
15 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08330d9e6a9c..3bb60c8adbff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -536,6 +536,8 @@ config ARCH_DOVE
536 select CPU_V7 536 select CPU_V7
537 select GENERIC_CLOCKEVENTS 537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI 538 select MIGHT_HAVE_PCI
539 select PINCTRL
540 select PINCTRL_DOVE
539 select PLAT_ORION_LEGACY 541 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI 542 select USB_ARCH_HAS_EHCI
541 help 543 help
@@ -548,6 +550,8 @@ config ARCH_KIRKWOOD
548 select GENERIC_CLOCKEVENTS 550 select GENERIC_CLOCKEVENTS
549 select PCI 551 select PCI
550 select PCI_QUIRKS 552 select PCI_QUIRKS
553 select PINCTRL
554 select PINCTRL_KIRKWOOD
551 select PLAT_ORION_LEGACY 555 select PLAT_ORION_LEGACY
552 help 556 help
553 Support for the following Marvell Kirkwood series SoCs: 557 Support for the following Marvell Kirkwood series SoCs:
@@ -962,6 +966,7 @@ config ARCH_ZYNQ
962 bool "Xilinx Zynq ARM Cortex A9 Platform" 966 bool "Xilinx Zynq ARM Cortex A9 Platform"
963 select ARM_AMBA 967 select ARM_AMBA
964 select ARM_GIC 968 select ARM_GIC
969 select COMMON_CLK
965 select CPU_V7 970 select CPU_V7
966 select GENERIC_CLOCKEVENTS 971 select GENERIC_CLOCKEVENTS
967 select ICST 972 select ICST
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 04a3f0d1d053..512b39438548 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -132,6 +132,23 @@ choice
132 their output to UART1 serial port on DaVinci TNETV107X 132 their output to UART1 serial port on DaVinci TNETV107X
133 devices. 133 devices.
134 134
135 config DEBUG_ZYNQ_UART0
136 bool "Kernel low-level debugging on Xilinx Zynq using UART0"
137 depends on ARCH_ZYNQ
138 help
139 Say Y here if you want the debug print routines to direct
140 their output to UART0 on the Zynq platform.
141
142 config DEBUG_ZYNQ_UART1
143 bool "Kernel low-level debugging on Xilinx Zynq using UART1"
144 depends on ARCH_ZYNQ
145 help
146 Say Y here if you want the debug print routines to direct
147 their output to UART1 on the Zynq platform.
148
149 If you have a ZC702 board and want early boot messages to
150 appear on the USB serial adaptor, select this option.
151
135 config DEBUG_DC21285_PORT 152 config DEBUG_DC21285_PORT
136 bool "Kernel low-level debugging messages via footbridge serial port" 153 bool "Kernel low-level debugging messages via footbridge serial port"
137 depends on FOOTBRIDGE 154 depends on FOOTBRIDGE
@@ -209,20 +226,12 @@ choice
209 Say Y here if you want kernel low-level debugging support 226 Say Y here if you want kernel low-level debugging support
210 on i.MX50 or i.MX53. 227 on i.MX50 or i.MX53.
211 228
212 config DEBUG_IMX6Q_UART2 229 config DEBUG_IMX6Q_UART
213 bool "i.MX6Q Debug UART2" 230 bool "i.MX6Q Debug UART"
214 depends on SOC_IMX6Q 231 depends on SOC_IMX6Q
215 help 232 help
216 Say Y here if you want kernel low-level debugging support 233 Say Y here if you want kernel low-level debugging support
217 on i.MX6Q UART2. This is correct for e.g. the SabreLite 234 on i.MX6Q.
218 board.
219
220 config DEBUG_IMX6Q_UART4
221 bool "i.MX6Q Debug UART4"
222 depends on SOC_IMX6Q
223 help
224 Say Y here if you want kernel low-level debugging support
225 on i.MX6Q UART4.
226 235
227 config DEBUG_MMP_UART2 236 config DEBUG_MMP_UART2
228 bool "Kernel low-level debugging message via MMP UART2" 237 bool "Kernel low-level debugging message via MMP UART2"
@@ -434,6 +443,15 @@ choice
434 443
435endchoice 444endchoice
436 445
446config DEBUG_IMX6Q_UART_PORT
447 int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART
448 range 1 5
449 default 1
450 depends on SOC_IMX6Q
451 help
452 Choose UART port on which kernel low-level debug messages
453 should be output.
454
437config DEBUG_LL_INCLUDE 455config DEBUG_LL_INCLUDE
438 string 456 string
439 default "debug/icedcc.S" if DEBUG_ICEDCC 457 default "debug/icedcc.S" if DEBUG_ICEDCC
@@ -443,8 +461,7 @@ config DEBUG_LL_INCLUDE
443 DEBUG_IMX31_IMX35_UART || \ 461 DEBUG_IMX31_IMX35_UART || \
444 DEBUG_IMX51_UART || \ 462 DEBUG_IMX51_UART || \
445 DEBUG_IMX50_IMX53_UART ||\ 463 DEBUG_IMX50_IMX53_UART ||\
446 DEBUG_IMX6Q_UART2 || \ 464 DEBUG_IMX6Q_UART
447 DEBUG_IMX6Q_UART4
448 default "debug/highbank.S" if DEBUG_HIGHBANK_UART 465 default "debug/highbank.S" if DEBUG_HIGHBANK_UART
449 default "debug/mvebu.S" if DEBUG_MVEBU_UART 466 default "debug/mvebu.S" if DEBUG_MVEBU_UART
450 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART 467 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f3f2f80cdf3b..2af359cfe985 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -34,6 +34,8 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
34 34
35dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 35dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
36dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb 36dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
37dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
38 da850-evm.dtb
37dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 39dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
38 dove-cubox.dtb \ 40 dove-cubox.dtb \
39 dove-dove-db.dtb 41 dove-dove-db.dtb
@@ -41,7 +43,10 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
41 exynos4210-smdkv310.dtb \ 43 exynos4210-smdkv310.dtb \
42 exynos4210-trats.dtb \ 44 exynos4210-trats.dtb \
43 exynos5250-smdk5250.dtb \ 45 exynos5250-smdk5250.dtb \
44 exynos5440-ssdk5440.dtb 46 exynos5440-ssdk5440.dtb \
47 exynos4412-smdk4412.dtb \
48 exynos5250-smdk5250.dtb \
49 exynos5250-snow.dtb
45dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 50dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
46 ecx-2000.dtb 51 ecx-2000.dtb
47dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 52dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@@ -79,16 +84,20 @@ dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
79 imx53-qsb.dtb \ 84 imx53-qsb.dtb \
80 imx53-smd.dtb \ 85 imx53-smd.dtb \
81 imx6q-arm2.dtb \ 86 imx6q-arm2.dtb \
87 imx6q-sabreauto.dtb \
82 imx6q-sabrelite.dtb \ 88 imx6q-sabrelite.dtb \
83 imx6q-sabresd.dtb 89 imx6q-sabresd.dtb
84dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 90dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
85 imx23-olinuxino.dtb \ 91 imx23-olinuxino.dtb \
86 imx23-stmp378x_devb.dtb \ 92 imx23-stmp378x_devb.dtb \
93 imx28-apf28.dtb \
94 imx28-apf28dev.dtb \
87 imx28-apx4devkit.dtb \ 95 imx28-apx4devkit.dtb \
88 imx28-cfa10036.dtb \ 96 imx28-cfa10036.dtb \
89 imx28-cfa10049.dtb \ 97 imx28-cfa10049.dtb \
90 imx28-evk.dtb \ 98 imx28-evk.dtb \
91 imx28-m28evk.dtb \ 99 imx28-m28evk.dtb \
100 imx28-sps1.dtb \
92 imx28-tx28.dtb 101 imx28-tx28.dtb
93dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 102dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
94 omap3-beagle.dtb \ 103 omap3-beagle.dtb \
@@ -105,7 +114,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
105 am335x-bone.dtb 114 am335x-bone.dtb
106dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 115dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
107dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 116dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
108dtb-$(CONFIG_ARCH_U8500) += snowball.dtb 117dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
118 hrefprev60.dtb \
119 hrefv60plus.dtb \
120 ccu9540.dtb
109dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 121dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
110 r8a7740-armadillo800eva.dtb \ 122 r8a7740-armadillo800eva.dtb \
111 sh73a0-kzm9g.dtb \ 123 sh73a0-kzm9g.dtb \
@@ -137,6 +149,7 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
137dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 149dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
138 wm8505-ref.dtb \ 150 wm8505-ref.dtb \
139 wm8650-mid.dtb 151 wm8650-mid.dtb
152dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
140 153
141targets += dtbs 154targets += dtbs
142endif 155endif
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index b1d3fab60e0a..c528b4b429b9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -479,6 +479,12 @@
479 trigger-external; 479 trigger-external;
480 }; 480 };
481 }; 481 };
482
483 watchdog@fffffd40 {
484 compatible = "atmel,at91sam9260-wdt";
485 reg = <0xfffffd40 0x10>;
486 status = "disabled";
487 };
482 }; 488 };
483 489
484 nand0: nand@40000000 { 490 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 66106eecf1ed..00485e1dff93 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -404,6 +404,12 @@
404 #size-cells = <0>; 404 #size-cells = <0>;
405 status = "disabled"; 405 status = "disabled";
406 }; 406 };
407
408 watchdog@fffffd40 {
409 compatible = "atmel,at91sam9260-wdt";
410 reg = <0xfffffd40 0x10>;
411 status = "disabled";
412 };
407 }; 413 };
408 414
409 nand0: nand@40000000 { 415 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 0741caeeced1..485fc395efc6 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -473,6 +473,12 @@
473 #size-cells = <0>; 473 #size-cells = <0>;
474 status = "disabled"; 474 status = "disabled";
475 }; 475 };
476
477 watchdog@fffffd40 {
478 compatible = "atmel,at91sam9260-wdt";
479 reg = <0xfffffd40 0x10>;
480 status = "disabled";
481 };
476 }; 482 };
477 483
478 nand0: nand@40000000 { 484 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
new file mode 100644
index 000000000000..04305463f00d
--- /dev/null
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -0,0 +1,72 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson CCU9540 platform with Device Tree";
17 compatible = "st-ericsson,ccu9540", "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
new file mode 100644
index 000000000000..fddd17417433
--- /dev/null
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -0,0 +1,184 @@
1/*
2 * Common device tree include for all Exynos 5250 boards based off of Daisy.
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/ {
12 aliases {
13 };
14
15 memory {
16 reg = <0x40000000 0x80000000>;
17 };
18
19 chosen {
20 };
21
22 i2c@12C60000 {
23 samsung,i2c-sda-delay = <100>;
24 samsung,i2c-max-bus-freq = <378000>;
25 gpios = <&gpb3 0 2 3 0>,
26 <&gpb3 1 2 3 0>;
27 };
28
29 i2c@12C70000 {
30 samsung,i2c-sda-delay = <100>;
31 samsung,i2c-max-bus-freq = <378000>;
32 gpios = <&gpb3 2 2 3 0>,
33 <&gpb3 3 2 3 0>;
34 };
35
36 i2c@12C80000 {
37 samsung,i2c-sda-delay = <100>;
38 samsung,i2c-max-bus-freq = <66000>;
39
40 /*
41 * Disabled pullups since external part has its own pullups and
42 * double-pulling gets us out of spec in some cases.
43 */
44 gpios = <&gpa0 6 3 0 0>,
45 <&gpa0 7 3 0 0>;
46
47 hdmiddc@50 {
48 compatible = "samsung,exynos5-hdmiddc";
49 reg = <0x50>;
50 };
51 };
52
53 i2c@12C90000 {
54 samsung,i2c-sda-delay = <100>;
55 samsung,i2c-max-bus-freq = <66000>;
56 gpios = <&gpa1 2 3 3 0>,
57 <&gpa1 3 3 3 0>;
58 };
59
60 i2c@12CA0000 {
61 status = "disabled";
62 };
63
64 i2c@12CB0000 {
65 samsung,i2c-sda-delay = <100>;
66 samsung,i2c-max-bus-freq = <66000>;
67 gpios = <&gpa2 2 3 3 0>,
68 <&gpa2 3 3 3 0>;
69 };
70
71 i2c@12CC0000 {
72 status = "disabled";
73 };
74
75 i2c@12CD0000 {
76 samsung,i2c-sda-delay = <100>;
77 samsung,i2c-max-bus-freq = <66000>;
78 gpios = <&gpb2 2 3 3 0>,
79 <&gpb2 3 3 3 0>;
80 };
81
82 i2c@12CE0000 {
83 samsung,i2c-sda-delay = <100>;
84 samsung,i2c-max-bus-freq = <378000>;
85
86 hdmiphy@38 {
87 compatible = "samsung,exynos5-hdmiphy";
88 reg = <0x38>;
89 };
90 };
91
92 dwmmc0@12200000 {
93 num-slots = <1>;
94 supports-highspeed;
95 broken-cd;
96 fifo-depth = <0x80>;
97 card-detect-delay = <200>;
98 samsung,dw-mshc-ciu-div = <3>;
99 samsung,dw-mshc-sdr-timing = <2 3 3>;
100 samsung,dw-mshc-ddr-timing = <1 2 3>;
101
102 slot@0 {
103 reg = <0>;
104 bus-width = <8>;
105 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
106 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
107 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
108 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
109 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
110 };
111 };
112
113 dwmmc1@12210000 {
114 status = "disabled";
115 };
116
117 dwmmc2@12220000 {
118 num-slots = <1>;
119 supports-highspeed;
120 fifo-depth = <0x80>;
121 card-detect-delay = <200>;
122 samsung,dw-mshc-ciu-div = <3>;
123 samsung,dw-mshc-sdr-timing = <2 3 3>;
124 samsung,dw-mshc-ddr-timing = <1 2 3>;
125
126 slot@0 {
127 reg = <0>;
128 bus-width = <4>;
129 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
130 wp-gpios = <&gpc2 1 0 0 3>;
131 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
132 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
133 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
134 };
135 };
136
137 dwmmc3@12230000 {
138 num-slots = <1>;
139 supports-highspeed;
140 broken-cd;
141 fifo-depth = <0x80>;
142 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3 3>;
145 samsung,dw-mshc-ddr-timing = <1 2 3>;
146
147 slot@0 {
148 reg = <0>;
149 bus-width = <4>;
150 /* See board-specific dts files for GPIOs */
151 };
152 };
153
154 spi_0: spi@12d20000 {
155 status = "disabled";
156 };
157
158 spi_1: spi@12d30000 {
159 gpios = <&gpa2 4 2 3 0>,
160 <&gpa2 6 2 3 0>,
161 <&gpa2 7 2 3 0>;
162 samsung,spi-src-clk = <0>;
163 num-cs = <1>;
164 };
165
166 spi_2: spi@12d40000 {
167 status = "disabled";
168 };
169
170 hdmi {
171 hpd-gpio = <&gpx3 7 0xf 1 3>;
172 };
173
174 gpio-keys {
175 compatible = "gpio-keys";
176
177 power {
178 label = "Power";
179 gpios = <&gpx1 3 0 0x10000 0>;
180 linux,code = <116>; /* KEY_POWER */
181 gpio-key,wakeup;
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 731086b2fca2..0d69322f689f 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -217,123 +217,103 @@
217 // DB8500_REGULATOR_VAPE 217 // DB8500_REGULATOR_VAPE
218 db8500_vape_reg: db8500_vape { 218 db8500_vape_reg: db8500_vape {
219 regulator-compatible = "db8500_vape"; 219 regulator-compatible = "db8500_vape";
220 regulator-name = "db8500-vape";
221 regulator-always-on; 220 regulator-always-on;
222 }; 221 };
223 222
224 // DB8500_REGULATOR_VARM 223 // DB8500_REGULATOR_VARM
225 db8500_varm_reg: db8500_varm { 224 db8500_varm_reg: db8500_varm {
226 regulator-compatible = "db8500_varm"; 225 regulator-compatible = "db8500_varm";
227 regulator-name = "db8500-varm";
228 }; 226 };
229 227
230 // DB8500_REGULATOR_VMODEM 228 // DB8500_REGULATOR_VMODEM
231 db8500_vmodem_reg: db8500_vmodem { 229 db8500_vmodem_reg: db8500_vmodem {
232 regulator-compatible = "db8500_vmodem"; 230 regulator-compatible = "db8500_vmodem";
233 regulator-name = "db8500-vmodem";
234 }; 231 };
235 232
236 // DB8500_REGULATOR_VPLL 233 // DB8500_REGULATOR_VPLL
237 db8500_vpll_reg: db8500_vpll { 234 db8500_vpll_reg: db8500_vpll {
238 regulator-compatible = "db8500_vpll"; 235 regulator-compatible = "db8500_vpll";
239 regulator-name = "db8500-vpll";
240 }; 236 };
241 237
242 // DB8500_REGULATOR_VSMPS1 238 // DB8500_REGULATOR_VSMPS1
243 db8500_vsmps1_reg: db8500_vsmps1 { 239 db8500_vsmps1_reg: db8500_vsmps1 {
244 regulator-compatible = "db8500_vsmps1"; 240 regulator-compatible = "db8500_vsmps1";
245 regulator-name = "db8500-vsmps1";
246 }; 241 };
247 242
248 // DB8500_REGULATOR_VSMPS2 243 // DB8500_REGULATOR_VSMPS2
249 db8500_vsmps2_reg: db8500_vsmps2 { 244 db8500_vsmps2_reg: db8500_vsmps2 {
250 regulator-compatible = "db8500_vsmps2"; 245 regulator-compatible = "db8500_vsmps2";
251 regulator-name = "db8500-vsmps2";
252 }; 246 };
253 247
254 // DB8500_REGULATOR_VSMPS3 248 // DB8500_REGULATOR_VSMPS3
255 db8500_vsmps3_reg: db8500_vsmps3 { 249 db8500_vsmps3_reg: db8500_vsmps3 {
256 regulator-compatible = "db8500_vsmps3"; 250 regulator-compatible = "db8500_vsmps3";
257 regulator-name = "db8500-vsmps3";
258 }; 251 };
259 252
260 // DB8500_REGULATOR_VRF1 253 // DB8500_REGULATOR_VRF1
261 db8500_vrf1_reg: db8500_vrf1 { 254 db8500_vrf1_reg: db8500_vrf1 {
262 regulator-compatible = "db8500_vrf1"; 255 regulator-compatible = "db8500_vrf1";
263 regulator-name = "db8500-vrf1";
264 }; 256 };
265 257
266 // DB8500_REGULATOR_SWITCH_SVAMMDSP 258 // DB8500_REGULATOR_SWITCH_SVAMMDSP
267 db8500_sva_mmdsp_reg: db8500_sva_mmdsp { 259 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
268 regulator-compatible = "db8500_sva_mmdsp"; 260 regulator-compatible = "db8500_sva_mmdsp";
269 regulator-name = "db8500-sva-mmdsp";
270 }; 261 };
271 262
272 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET 263 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
273 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { 264 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
274 regulator-compatible = "db8500_sva_mmdsp_ret"; 265 regulator-compatible = "db8500_sva_mmdsp_ret";
275 regulator-name = "db8500-sva-mmdsp-ret";
276 }; 266 };
277 267
278 // DB8500_REGULATOR_SWITCH_SVAPIPE 268 // DB8500_REGULATOR_SWITCH_SVAPIPE
279 db8500_sva_pipe_reg: db8500_sva_pipe { 269 db8500_sva_pipe_reg: db8500_sva_pipe {
280 regulator-compatible = "db8500_sva_pipe"; 270 regulator-compatible = "db8500_sva_pipe";
281 regulator-name = "db8500_sva_pipe";
282 }; 271 };
283 272
284 // DB8500_REGULATOR_SWITCH_SIAMMDSP 273 // DB8500_REGULATOR_SWITCH_SIAMMDSP
285 db8500_sia_mmdsp_reg: db8500_sia_mmdsp { 274 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
286 regulator-compatible = "db8500_sia_mmdsp"; 275 regulator-compatible = "db8500_sia_mmdsp";
287 regulator-name = "db8500_sia_mmdsp";
288 }; 276 };
289 277
290 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET 278 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
291 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { 279 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
292 regulator-name = "db8500-sia-mmdsp-ret";
293 }; 280 };
294 281
295 // DB8500_REGULATOR_SWITCH_SIAPIPE 282 // DB8500_REGULATOR_SWITCH_SIAPIPE
296 db8500_sia_pipe_reg: db8500_sia_pipe { 283 db8500_sia_pipe_reg: db8500_sia_pipe {
297 regulator-compatible = "db8500_sia_pipe"; 284 regulator-compatible = "db8500_sia_pipe";
298 regulator-name = "db8500-sia-pipe";
299 }; 285 };
300 286
301 // DB8500_REGULATOR_SWITCH_SGA 287 // DB8500_REGULATOR_SWITCH_SGA
302 db8500_sga_reg: db8500_sga { 288 db8500_sga_reg: db8500_sga {
303 regulator-compatible = "db8500_sga"; 289 regulator-compatible = "db8500_sga";
304 regulator-name = "db8500-sga";
305 vin-supply = <&db8500_vape_reg>; 290 vin-supply = <&db8500_vape_reg>;
306 }; 291 };
307 292
308 // DB8500_REGULATOR_SWITCH_B2R2_MCDE 293 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
309 db8500_b2r2_mcde_reg: db8500_b2r2_mcde { 294 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
310 regulator-compatible = "db8500_b2r2_mcde"; 295 regulator-compatible = "db8500_b2r2_mcde";
311 regulator-name = "db8500-b2r2-mcde";
312 vin-supply = <&db8500_vape_reg>; 296 vin-supply = <&db8500_vape_reg>;
313 }; 297 };
314 298
315 // DB8500_REGULATOR_SWITCH_ESRAM12 299 // DB8500_REGULATOR_SWITCH_ESRAM12
316 db8500_esram12_reg: db8500_esram12 { 300 db8500_esram12_reg: db8500_esram12 {
317 regulator-compatible = "db8500_esram12"; 301 regulator-compatible = "db8500_esram12";
318 regulator-name = "db8500-esram12";
319 }; 302 };
320 303
321 // DB8500_REGULATOR_SWITCH_ESRAM12RET 304 // DB8500_REGULATOR_SWITCH_ESRAM12RET
322 db8500_esram12_ret_reg: db8500_esram12_ret { 305 db8500_esram12_ret_reg: db8500_esram12_ret {
323 regulator-compatible = "db8500_esram12_ret"; 306 regulator-compatible = "db8500_esram12_ret";
324 regulator-name = "db8500-esram12-ret";
325 }; 307 };
326 308
327 // DB8500_REGULATOR_SWITCH_ESRAM34 309 // DB8500_REGULATOR_SWITCH_ESRAM34
328 db8500_esram34_reg: db8500_esram34 { 310 db8500_esram34_reg: db8500_esram34 {
329 regulator-compatible = "db8500_esram34"; 311 regulator-compatible = "db8500_esram34";
330 regulator-name = "db8500-esram34";
331 }; 312 };
332 313
333 // DB8500_REGULATOR_SWITCH_ESRAM34RET 314 // DB8500_REGULATOR_SWITCH_ESRAM34RET
334 db8500_esram34_ret_reg: db8500_esram34_ret { 315 db8500_esram34_ret_reg: db8500_esram34_ret {
335 regulator-compatible = "db8500_esram34_ret"; 316 regulator-compatible = "db8500_esram34_ret";
336 regulator-name = "db8500-esram34-ret";
337 }; 317 };
338 }; 318 };
339 319
@@ -412,7 +392,6 @@
412 // supplies to the display/camera 392 // supplies to the display/camera
413 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 393 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
414 regulator-compatible = "ab8500_ldo_aux1"; 394 regulator-compatible = "ab8500_ldo_aux1";
415 regulator-name = "V-DISPLAY";
416 regulator-min-microvolt = <2500000>; 395 regulator-min-microvolt = <2500000>;
417 regulator-max-microvolt = <2900000>; 396 regulator-max-microvolt = <2900000>;
418 regulator-boot-on; 397 regulator-boot-on;
@@ -423,7 +402,6 @@
423 // supplies to the on-board eMMC 402 // supplies to the on-board eMMC
424 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { 403 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
425 regulator-compatible = "ab8500_ldo_aux2"; 404 regulator-compatible = "ab8500_ldo_aux2";
426 regulator-name = "V-eMMC1";
427 regulator-min-microvolt = <1100000>; 405 regulator-min-microvolt = <1100000>;
428 regulator-max-microvolt = <3300000>; 406 regulator-max-microvolt = <3300000>;
429 }; 407 };
@@ -431,7 +409,6 @@
431 // supply for VAUX3; SDcard slots 409 // supply for VAUX3; SDcard slots
432 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { 410 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
433 regulator-compatible = "ab8500_ldo_aux3"; 411 regulator-compatible = "ab8500_ldo_aux3";
434 regulator-name = "V-MMC-SD";
435 regulator-min-microvolt = <1100000>; 412 regulator-min-microvolt = <1100000>;
436 regulator-max-microvolt = <3300000>; 413 regulator-max-microvolt = <3300000>;
437 }; 414 };
@@ -439,49 +416,41 @@
439 // supply for v-intcore12; VINTCORE12 LDO 416 // supply for v-intcore12; VINTCORE12 LDO
440 ab8500_ldo_initcore_reg: ab8500_ldo_initcore { 417 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
441 regulator-compatible = "ab8500_ldo_initcore"; 418 regulator-compatible = "ab8500_ldo_initcore";
442 regulator-name = "V-INTCORE";
443 }; 419 };
444 420
445 // supply for tvout; gpadc; TVOUT LDO 421 // supply for tvout; gpadc; TVOUT LDO
446 ab8500_ldo_tvout_reg: ab8500_ldo_tvout { 422 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
447 regulator-compatible = "ab8500_ldo_tvout"; 423 regulator-compatible = "ab8500_ldo_tvout";
448 regulator-name = "V-TVOUT";
449 }; 424 };
450 425
451 // supply for ab8500-usb; USB LDO 426 // supply for ab8500-usb; USB LDO
452 ab8500_ldo_usb_reg: ab8500_ldo_usb { 427 ab8500_ldo_usb_reg: ab8500_ldo_usb {
453 regulator-compatible = "ab8500_ldo_usb"; 428 regulator-compatible = "ab8500_ldo_usb";
454 regulator-name = "dummy";
455 }; 429 };
456 430
457 // supply for ab8500-vaudio; VAUDIO LDO 431 // supply for ab8500-vaudio; VAUDIO LDO
458 ab8500_ldo_audio_reg: ab8500_ldo_audio { 432 ab8500_ldo_audio_reg: ab8500_ldo_audio {
459 regulator-compatible = "ab8500_ldo_audio"; 433 regulator-compatible = "ab8500_ldo_audio";
460 regulator-name = "V-AUD";
461 }; 434 };
462 435
463 // supply for v-anamic1 VAMic1-LDO 436 // supply for v-anamic1 VAMic1-LDO
464 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { 437 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
465 regulator-compatible = "ab8500_ldo_anamic1"; 438 regulator-compatible = "ab8500_ldo_anamic1";
466 regulator-name = "V-AMIC1";
467 }; 439 };
468 440
469 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 441 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
470 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { 442 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
471 regulator-compatible = "ab8500_ldo_amamic2"; 443 regulator-compatible = "ab8500_ldo_amamic2";
472 regulator-name = "V-AMIC2";
473 }; 444 };
474 445
475 // supply for v-dmic; VDMIC LDO 446 // supply for v-dmic; VDMIC LDO
476 ab8500_ldo_dmic_reg: ab8500_ldo_dmic { 447 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
477 regulator-compatible = "ab8500_ldo_dmic"; 448 regulator-compatible = "ab8500_ldo_dmic";
478 regulator-name = "V-DMIC";
479 }; 449 };
480 450
481 // supply for U8500 CSI/DSI; VANA LDO 451 // supply for U8500 CSI/DSI; VANA LDO
482 ab8500_ldo_ana_reg: ab8500_ldo_ana { 452 ab8500_ldo_ana_reg: ab8500_ldo_ana {
483 regulator-compatible = "ab8500_ldo_ana"; 453 regulator-compatible = "ab8500_ldo_ana";
484 regulator-name = "V-CSI/DSI";
485 }; 454 };
486 }; 455 };
487 }; 456 };
@@ -585,42 +554,42 @@
585 status = "disabled"; 554 status = "disabled";
586 }; 555 };
587 556
588 sdi@80126000 { 557 sdi0_per1@80126000 {
589 compatible = "arm,pl18x", "arm,primecell"; 558 compatible = "arm,pl18x", "arm,primecell";
590 reg = <0x80126000 0x1000>; 559 reg = <0x80126000 0x1000>;
591 interrupts = <0 60 0x4>; 560 interrupts = <0 60 0x4>;
592 status = "disabled"; 561 status = "disabled";
593 }; 562 };
594 563
595 sdi@80118000 { 564 sdi1_per2@80118000 {
596 compatible = "arm,pl18x", "arm,primecell"; 565 compatible = "arm,pl18x", "arm,primecell";
597 reg = <0x80118000 0x1000>; 566 reg = <0x80118000 0x1000>;
598 interrupts = <0 50 0x4>; 567 interrupts = <0 50 0x4>;
599 status = "disabled"; 568 status = "disabled";
600 }; 569 };
601 570
602 sdi@80005000 { 571 sdi2_per3@80005000 {
603 compatible = "arm,pl18x", "arm,primecell"; 572 compatible = "arm,pl18x", "arm,primecell";
604 reg = <0x80005000 0x1000>; 573 reg = <0x80005000 0x1000>;
605 interrupts = <0 41 0x4>; 574 interrupts = <0 41 0x4>;
606 status = "disabled"; 575 status = "disabled";
607 }; 576 };
608 577
609 sdi@80119000 { 578 sdi3_per2@80119000 {
610 compatible = "arm,pl18x", "arm,primecell"; 579 compatible = "arm,pl18x", "arm,primecell";
611 reg = <0x80119000 0x1000>; 580 reg = <0x80119000 0x1000>;
612 interrupts = <0 59 0x4>; 581 interrupts = <0 59 0x4>;
613 status = "disabled"; 582 status = "disabled";
614 }; 583 };
615 584
616 sdi@80114000 { 585 sdi4_per2@80114000 {
617 compatible = "arm,pl18x", "arm,primecell"; 586 compatible = "arm,pl18x", "arm,primecell";
618 reg = <0x80114000 0x1000>; 587 reg = <0x80114000 0x1000>;
619 interrupts = <0 99 0x4>; 588 interrupts = <0 99 0x4>;
620 status = "disabled"; 589 status = "disabled";
621 }; 590 };
622 591
623 sdi@80008000 { 592 sdi5_per3@80008000 {
624 compatible = "arm,pl18x", "arm,primecell"; 593 compatible = "arm,pl18x", "arm,primecell";
625 reg = <0x80008000 0x1000>; 594 reg = <0x80008000 0x1000>;
626 interrupts = <0 100 0x4>; 595 interrupts = <0 100 0x4>;
@@ -674,5 +643,18 @@
674 status = "disabled"; 643 status = "disabled";
675 }; 644 };
676 645
646 vmmci: regulator-gpio {
647 compatible = "regulator-gpio";
648
649 regulator-min-microvolt = <1800000>;
650 regulator-max-microvolt = <2600000>;
651 regulator-name = "mmci-reg";
652 regulator-type = "voltage";
653
654 states = <1800000 0x1
655 2900000 0x0>;
656
657 status = "disabled";
658 };
677 }; 659 };
678}; 660};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 0adbd5a38095..fed7d3f9f431 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -40,3 +40,13 @@
40 reg = <0>; 40 reg = <0>;
41 }; 41 };
42}; 42};
43
44&pinctrl {
45 pinctrl-0 = <&pmx_gpio_18>;
46 pinctrl-names = "default";
47
48 pmx_gpio_18: pmx-gpio-18 {
49 marvell,pins = "mpp18";
50 marvell,function = "gpio";
51 };
52};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 5a00022383e7..61f391412a5a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -4,6 +4,12 @@
4 compatible = "marvell,dove"; 4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 5 model = "Marvell Armada 88AP510 SoC";
6 6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
7 soc@f1000000 { 13 soc@f1000000 {
8 compatible = "simple-bus"; 14 compatible = "simple-bus";
9 #address-cells = <1>; 15 #address-cells = <1>;
@@ -72,7 +78,8 @@
72 #gpio-cells = <2>; 78 #gpio-cells = <2>;
73 gpio-controller; 79 gpio-controller;
74 reg = <0xd0400 0x20>; 80 reg = <0xd0400 0x20>;
75 ngpio = <32>; 81 ngpios = <32>;
82 interrupt-controller;
76 interrupts = <12>, <13>, <14>, <60>; 83 interrupts = <12>, <13>, <14>, <60>;
77 }; 84 };
78 85
@@ -81,7 +88,8 @@
81 #gpio-cells = <2>; 88 #gpio-cells = <2>;
82 gpio-controller; 89 gpio-controller;
83 reg = <0xd0420 0x20>; 90 reg = <0xd0420 0x20>;
84 ngpio = <32>; 91 ngpios = <32>;
92 interrupt-controller;
85 interrupts = <61>; 93 interrupts = <61>;
86 }; 94 };
87 95
@@ -90,7 +98,12 @@
90 #gpio-cells = <2>; 98 #gpio-cells = <2>;
91 gpio-controller; 99 gpio-controller;
92 reg = <0xe8400 0x0c>; 100 reg = <0xe8400 0x0c>;
93 ngpio = <8>; 101 ngpios = <8>;
102 };
103
104 pinctrl: pinctrl@d0200 {
105 compatible = "marvell,dove-pinctrl";
106 reg = <0xd0200 0x10>;
94 }; 107 };
95 108
96 spi0: spi@10600 { 109 spi0: spi@10600 {
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index b7354e6506de..96e50f569433 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -22,10 +22,22 @@
22 status = "okay"; 22 status = "okay";
23 }; 23 };
24 24
25 usart0: serial@fffb0000 {
26 status = "okay";
27 };
28
29 usart2: serial@fffb8000 {
30 status = "okay";
31 };
32
25 usb1: gadget@fffa4000 { 33 usb1: gadget@fffa4000 {
26 atmel,vbus-gpio = <&pioC 5 0>; 34 atmel,vbus-gpio = <&pioC 5 0>;
27 status = "okay"; 35 status = "okay";
28 }; 36 };
37
38 watchdog@fffffd40 {
39 status = "okay";
40 };
29 }; 41 };
30 42
31 usb0: ohci@00500000 { 43 usb0: ohci@00500000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 96d4462730fb..e1347fceb5bc 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -28,6 +28,44 @@
28 spi0 = &spi_0; 28 spi0 = &spi_0;
29 spi1 = &spi_1; 29 spi1 = &spi_1;
30 spi2 = &spi_2; 30 spi2 = &spi_2;
31 i2c0 = &i2c_0;
32 i2c1 = &i2c_1;
33 i2c2 = &i2c_2;
34 i2c3 = &i2c_3;
35 i2c4 = &i2c_4;
36 i2c5 = &i2c_5;
37 i2c6 = &i2c_6;
38 i2c7 = &i2c_7;
39 };
40
41 pd_mfc: mfc-power-domain@10023C40 {
42 compatible = "samsung,exynos4210-pd";
43 reg = <0x10023C40 0x20>;
44 };
45
46 pd_g3d: g3d-power-domain@10023C60 {
47 compatible = "samsung,exynos4210-pd";
48 reg = <0x10023C60 0x20>;
49 };
50
51 pd_lcd0: lcd0-power-domain@10023C80 {
52 compatible = "samsung,exynos4210-pd";
53 reg = <0x10023C80 0x20>;
54 };
55
56 pd_tv: tv-power-domain@10023C20 {
57 compatible = "samsung,exynos4210-pd";
58 reg = <0x10023C20 0x20>;
59 };
60
61 pd_cam: cam-power-domain@10023C00 {
62 compatible = "samsung,exynos4210-pd";
63 reg = <0x10023C00 0x20>;
64 };
65
66 pd_gps: gps-power-domain@10023CE0 {
67 compatible = "samsung,exynos4210-pd";
68 reg = <0x10023CE0 0x20>;
31 }; 69 };
32 70
33 gic:interrupt-controller@10490000 { 71 gic:interrupt-controller@10490000 {
@@ -121,7 +159,7 @@
121 status = "disabled"; 159 status = "disabled";
122 }; 160 };
123 161
124 i2c@13860000 { 162 i2c_0: i2c@13860000 {
125 #address-cells = <1>; 163 #address-cells = <1>;
126 #size-cells = <0>; 164 #size-cells = <0>;
127 compatible = "samsung,s3c2440-i2c"; 165 compatible = "samsung,s3c2440-i2c";
@@ -130,7 +168,7 @@
130 status = "disabled"; 168 status = "disabled";
131 }; 169 };
132 170
133 i2c@13870000 { 171 i2c_1: i2c@13870000 {
134 #address-cells = <1>; 172 #address-cells = <1>;
135 #size-cells = <0>; 173 #size-cells = <0>;
136 compatible = "samsung,s3c2440-i2c"; 174 compatible = "samsung,s3c2440-i2c";
@@ -139,7 +177,7 @@
139 status = "disabled"; 177 status = "disabled";
140 }; 178 };
141 179
142 i2c@13880000 { 180 i2c_2: i2c@13880000 {
143 #address-cells = <1>; 181 #address-cells = <1>;
144 #size-cells = <0>; 182 #size-cells = <0>;
145 compatible = "samsung,s3c2440-i2c"; 183 compatible = "samsung,s3c2440-i2c";
@@ -148,7 +186,7 @@
148 status = "disabled"; 186 status = "disabled";
149 }; 187 };
150 188
151 i2c@13890000 { 189 i2c_3: i2c@13890000 {
152 #address-cells = <1>; 190 #address-cells = <1>;
153 #size-cells = <0>; 191 #size-cells = <0>;
154 compatible = "samsung,s3c2440-i2c"; 192 compatible = "samsung,s3c2440-i2c";
@@ -157,7 +195,7 @@
157 status = "disabled"; 195 status = "disabled";
158 }; 196 };
159 197
160 i2c@138A0000 { 198 i2c_4: i2c@138A0000 {
161 #address-cells = <1>; 199 #address-cells = <1>;
162 #size-cells = <0>; 200 #size-cells = <0>;
163 compatible = "samsung,s3c2440-i2c"; 201 compatible = "samsung,s3c2440-i2c";
@@ -166,7 +204,7 @@
166 status = "disabled"; 204 status = "disabled";
167 }; 205 };
168 206
169 i2c@138B0000 { 207 i2c_5: i2c@138B0000 {
170 #address-cells = <1>; 208 #address-cells = <1>;
171 #size-cells = <0>; 209 #size-cells = <0>;
172 compatible = "samsung,s3c2440-i2c"; 210 compatible = "samsung,s3c2440-i2c";
@@ -175,7 +213,7 @@
175 status = "disabled"; 213 status = "disabled";
176 }; 214 };
177 215
178 i2c@138C0000 { 216 i2c_6: i2c@138C0000 {
179 #address-cells = <1>; 217 #address-cells = <1>;
180 #size-cells = <0>; 218 #size-cells = <0>;
181 compatible = "samsung,s3c2440-i2c"; 219 compatible = "samsung,s3c2440-i2c";
@@ -184,7 +222,7 @@
184 status = "disabled"; 222 status = "disabled";
185 }; 223 };
186 224
187 i2c@138D0000 { 225 i2c_7: i2c@138D0000 {
188 #address-cells = <1>; 226 #address-cells = <1>;
189 #size-cells = <0>; 227 #size-cells = <0>;
190 compatible = "samsung,s3c2440-i2c"; 228 compatible = "samsung,s3c2440-i2c";
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 3e68f52e8454..f2710018e84e 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -22,38 +22,54 @@
22 compatible = "insignal,origen", "samsung,exynos4210"; 22 compatible = "insignal,origen", "samsung,exynos4210";
23 23
24 memory { 24 memory {
25 reg = <0x40000000 0x40000000>; 25 reg = <0x40000000 0x10000000
26 0x50000000 0x10000000
27 0x60000000 0x10000000
28 0x70000000 0x10000000>;
26 }; 29 };
27 30
28 chosen { 31 chosen {
29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 32 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30 }; 33 };
31 34
35 mmc_reg: voltage-regulator {
36 compatible = "regulator-fixed";
37 regulator-name = "VMEM_VDD_2.8V";
38 regulator-min-microvolt = <2800000>;
39 regulator-max-microvolt = <2800000>;
40 gpio = <&gpx1 1 0>;
41 enable-active-high;
42 };
43
32 sdhci@12530000 { 44 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>; 45 bus-width = <4>;
34 linux,mmc_cap_4_bit_data; 46 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
35 samsung,sdhci-cd-internal; 47 pinctrl-names = "default";
36 gpio-cd = <&gpk2 2 2 3 3>; 48 vmmc-supply = <&mmc_reg>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 status = "okay"; 49 status = "okay";
44 }; 50 };
45 51
46 sdhci@12510000 { 52 sdhci@12510000 {
47 samsung,sdhci-bus-width = <4>; 53 bus-width = <4>;
48 linux,mmc_cap_4_bit_data; 54 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
49 samsung,sdhci-cd-internal; 55 pinctrl-names = "default";
50 gpio-cd = <&gpk0 2 2 3 3>; 56 vmmc-supply = <&mmc_reg>;
51 gpios = <&gpk0 0 2 0 3>, 57 status = "okay";
52 <&gpk0 1 2 0 3>, 58 };
53 <&gpk0 3 2 3 3>, 59
54 <&gpk0 4 2 3 3>, 60 serial@13800000 {
55 <&gpk0 5 2 3 3>, 61 status = "okay";
56 <&gpk0 6 2 3 3>; 62 };
63
64 serial@13810000 {
65 status = "okay";
66 };
67
68 serial@13820000 {
69 status = "okay";
70 };
71
72 serial@13830000 {
57 status = "okay"; 73 status = "okay";
58 }; 74 };
59 75
@@ -64,35 +80,35 @@
64 80
65 up { 81 up {
66 label = "Up"; 82 label = "Up";
67 gpios = <&gpx2 0 0 0x10000 2>; 83 gpios = <&gpx2 0 1>;
68 linux,code = <103>; 84 linux,code = <103>;
69 gpio-key,wakeup; 85 gpio-key,wakeup;
70 }; 86 };
71 87
72 down { 88 down {
73 label = "Down"; 89 label = "Down";
74 gpios = <&gpx2 1 0 0x10000 2>; 90 gpios = <&gpx2 1 1>;
75 linux,code = <108>; 91 linux,code = <108>;
76 gpio-key,wakeup; 92 gpio-key,wakeup;
77 }; 93 };
78 94
79 back { 95 back {
80 label = "Back"; 96 label = "Back";
81 gpios = <&gpx1 7 0 0x10000 2>; 97 gpios = <&gpx1 7 1>;
82 linux,code = <158>; 98 linux,code = <158>;
83 gpio-key,wakeup; 99 gpio-key,wakeup;
84 }; 100 };
85 101
86 home { 102 home {
87 label = "Home"; 103 label = "Home";
88 gpios = <&gpx1 6 0 0x10000 2>; 104 gpios = <&gpx1 6 1>;
89 linux,code = <102>; 105 linux,code = <102>;
90 gpio-key,wakeup; 106 gpio-key,wakeup;
91 }; 107 };
92 108
93 menu { 109 menu {
94 label = "Menu"; 110 label = "Menu";
95 gpios = <&gpx1 5 0 0x10000 2>; 111 gpios = <&gpx1 5 1>;
96 linux,code = <139>; 112 linux,code = <139>;
97 gpio-key,wakeup; 113 gpio-key,wakeup;
98 }; 114 };
@@ -101,7 +117,7 @@
101 leds { 117 leds {
102 compatible = "gpio-leds"; 118 compatible = "gpio-leds";
103 status { 119 status {
104 gpios = <&gpx1 3 0 0x10000 2>; 120 gpios = <&gpx1 3 1>;
105 linux,default-trigger = "heartbeat"; 121 linux,default-trigger = "heartbeat";
106 }; 122 };
107 }; 123 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 6a4a1a04221c..55a2efb763d1 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -482,196 +482,196 @@
482 samsung,pins = "gpk0-0"; 482 samsung,pins = "gpk0-0";
483 samsung,pin-function = <2>; 483 samsung,pin-function = <2>;
484 samsung,pin-pud = <0>; 484 samsung,pin-pud = <0>;
485 samsung,pin-drv = <0>; 485 samsung,pin-drv = <3>;
486 }; 486 };
487 487
488 sd0_cmd: sd0-cmd { 488 sd0_cmd: sd0-cmd {
489 samsung,pins = "gpk0-1"; 489 samsung,pins = "gpk0-1";
490 samsung,pin-function = <2>; 490 samsung,pin-function = <2>;
491 samsung,pin-pud = <0>; 491 samsung,pin-pud = <0>;
492 samsung,pin-drv = <0>; 492 samsung,pin-drv = <3>;
493 }; 493 };
494 494
495 sd0_cd: sd0-cd { 495 sd0_cd: sd0-cd {
496 samsung,pins = "gpk0-2"; 496 samsung,pins = "gpk0-2";
497 samsung,pin-function = <2>; 497 samsung,pin-function = <2>;
498 samsung,pin-pud = <3>; 498 samsung,pin-pud = <3>;
499 samsung,pin-drv = <0>; 499 samsung,pin-drv = <3>;
500 }; 500 };
501 501
502 sd0_bus1: sd0-bus-width1 { 502 sd0_bus1: sd0-bus-width1 {
503 samsung,pins = "gpk0-3"; 503 samsung,pins = "gpk0-3";
504 samsung,pin-function = <2>; 504 samsung,pin-function = <2>;
505 samsung,pin-pud = <3>; 505 samsung,pin-pud = <3>;
506 samsung,pin-drv = <0>; 506 samsung,pin-drv = <3>;
507 }; 507 };
508 508
509 sd0_bus4: sd0-bus-width4 { 509 sd0_bus4: sd0-bus-width4 {
510 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 510 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
511 samsung,pin-function = <2>; 511 samsung,pin-function = <2>;
512 samsung,pin-pud = <3>; 512 samsung,pin-pud = <3>;
513 samsung,pin-drv = <0>; 513 samsung,pin-drv = <3>;
514 }; 514 };
515 515
516 sd0_bus8: sd0-bus-width8 { 516 sd0_bus8: sd0-bus-width8 {
517 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 517 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
518 samsung,pin-function = <3>; 518 samsung,pin-function = <3>;
519 samsung,pin-pud = <3>; 519 samsung,pin-pud = <3>;
520 samsung,pin-drv = <0>; 520 samsung,pin-drv = <3>;
521 }; 521 };
522 522
523 sd4_clk: sd4-clk { 523 sd4_clk: sd4-clk {
524 samsung,pins = "gpk0-0"; 524 samsung,pins = "gpk0-0";
525 samsung,pin-function = <3>; 525 samsung,pin-function = <3>;
526 samsung,pin-pud = <0>; 526 samsung,pin-pud = <0>;
527 samsung,pin-drv = <0>; 527 samsung,pin-drv = <3>;
528 }; 528 };
529 529
530 sd4_cmd: sd4-cmd { 530 sd4_cmd: sd4-cmd {
531 samsung,pins = "gpk0-1"; 531 samsung,pins = "gpk0-1";
532 samsung,pin-function = <3>; 532 samsung,pin-function = <3>;
533 samsung,pin-pud = <0>; 533 samsung,pin-pud = <0>;
534 samsung,pin-drv = <0>; 534 samsung,pin-drv = <3>;
535 }; 535 };
536 536
537 sd4_cd: sd4-cd { 537 sd4_cd: sd4-cd {
538 samsung,pins = "gpk0-2"; 538 samsung,pins = "gpk0-2";
539 samsung,pin-function = <3>; 539 samsung,pin-function = <3>;
540 samsung,pin-pud = <3>; 540 samsung,pin-pud = <3>;
541 samsung,pin-drv = <0>; 541 samsung,pin-drv = <3>;
542 }; 542 };
543 543
544 sd4_bus1: sd4-bus-width1 { 544 sd4_bus1: sd4-bus-width1 {
545 samsung,pins = "gpk0-3"; 545 samsung,pins = "gpk0-3";
546 samsung,pin-function = <3>; 546 samsung,pin-function = <3>;
547 samsung,pin-pud = <3>; 547 samsung,pin-pud = <3>;
548 samsung,pin-drv = <0>; 548 samsung,pin-drv = <3>;
549 }; 549 };
550 550
551 sd4_bus4: sd4-bus-width4 { 551 sd4_bus4: sd4-bus-width4 {
552 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 552 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
553 samsung,pin-function = <3>; 553 samsung,pin-function = <3>;
554 samsung,pin-pud = <3>; 554 samsung,pin-pud = <3>;
555 samsung,pin-drv = <0>; 555 samsung,pin-drv = <3>;
556 }; 556 };
557 557
558 sd4_bus8: sd4-bus-width8 { 558 sd4_bus8: sd4-bus-width8 {
559 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 559 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
560 samsung,pin-function = <3>; 560 samsung,pin-function = <3>;
561 samsung,pin-pud = <4>; 561 samsung,pin-pud = <4>;
562 samsung,pin-drv = <0>; 562 samsung,pin-drv = <3>;
563 }; 563 };
564 564
565 sd1_clk: sd1-clk { 565 sd1_clk: sd1-clk {
566 samsung,pins = "gpk1-0"; 566 samsung,pins = "gpk1-0";
567 samsung,pin-function = <2>; 567 samsung,pin-function = <2>;
568 samsung,pin-pud = <0>; 568 samsung,pin-pud = <0>;
569 samsung,pin-drv = <0>; 569 samsung,pin-drv = <3>;
570 }; 570 };
571 571
572 sd1_cmd: sd1-cmd { 572 sd1_cmd: sd1-cmd {
573 samsung,pins = "gpk1-1"; 573 samsung,pins = "gpk1-1";
574 samsung,pin-function = <2>; 574 samsung,pin-function = <2>;
575 samsung,pin-pud = <0>; 575 samsung,pin-pud = <0>;
576 samsung,pin-drv = <0>; 576 samsung,pin-drv = <3>;
577 }; 577 };
578 578
579 sd1_cd: sd1-cd { 579 sd1_cd: sd1-cd {
580 samsung,pins = "gpk1-2"; 580 samsung,pins = "gpk1-2";
581 samsung,pin-function = <2>; 581 samsung,pin-function = <2>;
582 samsung,pin-pud = <3>; 582 samsung,pin-pud = <3>;
583 samsung,pin-drv = <0>; 583 samsung,pin-drv = <3>;
584 }; 584 };
585 585
586 sd1_bus1: sd1-bus-width1 { 586 sd1_bus1: sd1-bus-width1 {
587 samsung,pins = "gpk1-3"; 587 samsung,pins = "gpk1-3";
588 samsung,pin-function = <2>; 588 samsung,pin-function = <2>;
589 samsung,pin-pud = <3>; 589 samsung,pin-pud = <3>;
590 samsung,pin-drv = <0>; 590 samsung,pin-drv = <3>;
591 }; 591 };
592 592
593 sd1_bus4: sd1-bus-width4 { 593 sd1_bus4: sd1-bus-width4 {
594 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 594 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
595 samsung,pin-function = <2>; 595 samsung,pin-function = <2>;
596 samsung,pin-pud = <3>; 596 samsung,pin-pud = <3>;
597 samsung,pin-drv = <0>; 597 samsung,pin-drv = <3>;
598 }; 598 };
599 599
600 sd2_clk: sd2-clk { 600 sd2_clk: sd2-clk {
601 samsung,pins = "gpk2-0"; 601 samsung,pins = "gpk2-0";
602 samsung,pin-function = <2>; 602 samsung,pin-function = <2>;
603 samsung,pin-pud = <0>; 603 samsung,pin-pud = <0>;
604 samsung,pin-drv = <0>; 604 samsung,pin-drv = <3>;
605 }; 605 };
606 606
607 sd2_cmd: sd2-cmd { 607 sd2_cmd: sd2-cmd {
608 samsung,pins = "gpk2-1"; 608 samsung,pins = "gpk2-1";
609 samsung,pin-function = <2>; 609 samsung,pin-function = <2>;
610 samsung,pin-pud = <0>; 610 samsung,pin-pud = <0>;
611 samsung,pin-drv = <0>; 611 samsung,pin-drv = <3>;
612 }; 612 };
613 613
614 sd2_cd: sd2-cd { 614 sd2_cd: sd2-cd {
615 samsung,pins = "gpk2-2"; 615 samsung,pins = "gpk2-2";
616 samsung,pin-function = <2>; 616 samsung,pin-function = <2>;
617 samsung,pin-pud = <3>; 617 samsung,pin-pud = <3>;
618 samsung,pin-drv = <0>; 618 samsung,pin-drv = <3>;
619 }; 619 };
620 620
621 sd2_bus1: sd2-bus-width1 { 621 sd2_bus1: sd2-bus-width1 {
622 samsung,pins = "gpk2-3"; 622 samsung,pins = "gpk2-3";
623 samsung,pin-function = <2>; 623 samsung,pin-function = <2>;
624 samsung,pin-pud = <3>; 624 samsung,pin-pud = <3>;
625 samsung,pin-drv = <0>; 625 samsung,pin-drv = <3>;
626 }; 626 };
627 627
628 sd2_bus4: sd2-bus-width4 { 628 sd2_bus4: sd2-bus-width4 {
629 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 629 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
630 samsung,pin-function = <2>; 630 samsung,pin-function = <2>;
631 samsung,pin-pud = <3>; 631 samsung,pin-pud = <3>;
632 samsung,pin-drv = <0>; 632 samsung,pin-drv = <3>;
633 }; 633 };
634 634
635 sd2_bus8: sd2-bus-width8 { 635 sd2_bus8: sd2-bus-width8 {
636 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 636 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
637 samsung,pin-function = <3>; 637 samsung,pin-function = <3>;
638 samsung,pin-pud = <3>; 638 samsung,pin-pud = <3>;
639 samsung,pin-drv = <0>; 639 samsung,pin-drv = <3>;
640 }; 640 };
641 641
642 sd3_clk: sd3-clk { 642 sd3_clk: sd3-clk {
643 samsung,pins = "gpk3-0"; 643 samsung,pins = "gpk3-0";
644 samsung,pin-function = <2>; 644 samsung,pin-function = <2>;
645 samsung,pin-pud = <0>; 645 samsung,pin-pud = <0>;
646 samsung,pin-drv = <0>; 646 samsung,pin-drv = <3>;
647 }; 647 };
648 648
649 sd3_cmd: sd3-cmd { 649 sd3_cmd: sd3-cmd {
650 samsung,pins = "gpk3-1"; 650 samsung,pins = "gpk3-1";
651 samsung,pin-function = <2>; 651 samsung,pin-function = <2>;
652 samsung,pin-pud = <0>; 652 samsung,pin-pud = <0>;
653 samsung,pin-drv = <0>; 653 samsung,pin-drv = <3>;
654 }; 654 };
655 655
656 sd3_cd: sd3-cd { 656 sd3_cd: sd3-cd {
657 samsung,pins = "gpk3-2"; 657 samsung,pins = "gpk3-2";
658 samsung,pin-function = <2>; 658 samsung,pin-function = <2>;
659 samsung,pin-pud = <3>; 659 samsung,pin-pud = <3>;
660 samsung,pin-drv = <0>; 660 samsung,pin-drv = <3>;
661 }; 661 };
662 662
663 sd3_bus1: sd3-bus-width1 { 663 sd3_bus1: sd3-bus-width1 {
664 samsung,pins = "gpk3-3"; 664 samsung,pins = "gpk3-3";
665 samsung,pin-function = <2>; 665 samsung,pin-function = <2>;
666 samsung,pin-pud = <3>; 666 samsung,pin-pud = <3>;
667 samsung,pin-drv = <0>; 667 samsung,pin-drv = <3>;
668 }; 668 };
669 669
670 sd3_bus4: sd3-bus-width4 { 670 sd3_bus4: sd3-bus-width4 {
671 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 671 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
672 samsung,pin-function = <2>; 672 samsung,pin-function = <2>;
673 samsung,pin-pud = <3>; 673 samsung,pin-pud = <3>;
674 samsung,pin-drv = <0>; 674 samsung,pin-drv = <3>;
675 }; 675 };
676 676
677 eint0: ext-int0 { 677 eint0: ext-int0 {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 63610c3ba3af..9b23a8255e39 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,22 @@
43 status = "okay"; 43 status = "okay";
44 }; 44 };
45 45
46 serial@13800000 {
47 status = "okay";
48 };
49
50 serial@13810000 {
51 status = "okay";
52 };
53
54 serial@13820000 {
55 status = "okay";
56 };
57
58 serial@13830000 {
59 status = "okay";
60 };
61
46 keypad@100A0000 { 62 keypad@100A0000 {
47 samsung,keypad-num-rows = <2>; 63 samsung,keypad-num-rows = <2>;
48 samsung,keypad-num-columns = <8>; 64 samsung,keypad-num-columns = <8>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index a21511c14071..c346b64dff55 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -35,24 +35,15 @@
35 regulator-name = "VMEM_VDD_2.8V"; 35 regulator-name = "VMEM_VDD_2.8V";
36 regulator-min-microvolt = <2800000>; 36 regulator-min-microvolt = <2800000>;
37 regulator-max-microvolt = <2800000>; 37 regulator-max-microvolt = <2800000>;
38 gpio = <&gpk0 2 1 0 0>; 38 gpio = <&gpk0 2 0>;
39 enable-active-high; 39 enable-active-high;
40 }; 40 };
41 41
42 sdhci_emmc: sdhci@12510000 { 42 sdhci_emmc: sdhci@12510000 {
43 bus-width = <8>; 43 bus-width = <8>;
44 non-removable; 44 non-removable;
45 broken-voltage; 45 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
46 gpios = <&gpk0 0 2 0 3>, 46 pinctrl-names = "default";
47 <&gpk0 1 2 0 3>,
48 <&gpk0 3 2 2 3>,
49 <&gpk0 4 2 2 3>,
50 <&gpk0 5 2 2 3>,
51 <&gpk0 6 2 2 3>,
52 <&gpk1 3 3 3 3>,
53 <&gpk1 4 3 3 3>,
54 <&gpk1 5 3 3 3>,
55 <&gpk1 6 3 3 3>;
56 vmmc-supply = <&vemmc_reg>; 47 vmmc-supply = <&vemmc_reg>;
57 status = "okay"; 48 status = "okay";
58 }; 49 };
@@ -73,12 +64,74 @@
73 status = "okay"; 64 status = "okay";
74 }; 65 };
75 66
67 gpio-keys {
68 compatible = "gpio-keys";
69
70 vol-down-key {
71 gpios = <&gpx2 1 1>;
72 linux,code = <114>;
73 label = "volume down";
74 debounce-interval = <10>;
75 };
76
77 vol-up-key {
78 gpios = <&gpx2 0 1>;
79 linux,code = <115>;
80 label = "volume up";
81 debounce-interval = <10>;
82 };
83
84 power-key {
85 gpios = <&gpx2 7 1>;
86 linux,code = <116>;
87 label = "power";
88 debounce-interval = <10>;
89 gpio-key,wakeup;
90 };
91
92 ok-key {
93 gpios = <&gpx3 5 1>;
94 linux,code = <352>;
95 label = "ok";
96 debounce-interval = <10>;
97 };
98 };
99
100 tsp_reg: voltage-regulator {
101 compatible = "regulator-fixed";
102 regulator-name = "TSP_FIXED_VOLTAGES";
103 regulator-min-microvolt = <2800000>;
104 regulator-max-microvolt = <2800000>;
105 gpio = <&gpl0 3 0>;
106 enable-active-high;
107 };
108
109 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>;
112 samsung,i2c-max-bus-freq = <400000>;
113 pinctrl-0 = <&i2c3_bus>;
114 pinctrl-names = "default";
115 status = "okay";
116
117 mms114-touchscreen@48 {
118 compatible = "melfas,mms114";
119 reg = <0x48>;
120 interrupt-parent = <&gpx0>;
121 interrupts = <4 2>;
122 x-size = <720>;
123 y-size = <1280>;
124 avdd-supply = <&tsp_reg>;
125 vdd-supply = <&tsp_reg>;
126 };
127 };
128
76 i2c@138B0000 { 129 i2c@138B0000 {
77 samsung,i2c-sda-delay = <100>; 130 samsung,i2c-sda-delay = <100>;
78 samsung,i2c-slave-addr = <0x10>; 131 samsung,i2c-slave-addr = <0x10>;
79 samsung,i2c-max-bus-freq = <100000>; 132 samsung,i2c-max-bus-freq = <100000>;
80 gpios = <&gpb 6 3 3 0>, 133 pinctrl-0 = <&i2c5_bus>;
81 <&gpb 7 3 3 0>; 134 pinctrl-names = "default";
82 status = "okay"; 135 status = "okay";
83 136
84 max8997_pmic@66 { 137 max8997_pmic@66 {
@@ -93,9 +146,9 @@
93 max8997,pmic-ignore-gpiodvs-side-effect; 146 max8997,pmic-ignore-gpiodvs-side-effect;
94 max8997,pmic-buck125-default-dvs-idx = <0>; 147 max8997,pmic-buck125-default-dvs-idx = <0>;
95 148
96 max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>, 149 max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>,
97 <&gpx0 6 1 0 0>, 150 <&gpx0 6 0>,
98 <&gpl0 0 1 0 0>; 151 <&gpl0 0 0>;
99 152
100 max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, 153 max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
101 <1250000>, <1200000>, 154 <1250000>, <1200000>,
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index d877dbe7ac0e..e31bfc4a6f09 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,11 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>;
37 };
38
34 gic:interrupt-controller@10490000 { 39 gic:interrupt-controller@10490000 {
35 cpu-offset = <0x8000>; 40 cpu-offset = <0x8000>;
36 }; 41 };
@@ -64,4 +69,11 @@
64 compatible = "samsung,pinctrl-exynos4210"; 69 compatible = "samsung,pinctrl-exynos4210";
65 reg = <0x03860000 0x1000>; 70 reg = <0x03860000 0x1000>;
66 }; 71 };
72
73 tmu@100C0000 {
74 compatible = "samsung,exynos4210-tmu";
75 interrupt-parent = <&combiner>;
76 reg = <0x100C0000 0x100>;
77 interrupts = <2 4>;
78 };
67}; 79};
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
new file mode 100644
index 000000000000..c6ae2005961f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Samsung's Exynos4212 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4212";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x8000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
new file mode 100644
index 000000000000..f05bf575cc45
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -0,0 +1,45 @@
1/*
2 * Samsung's Exynos4412 based SMDK board device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's SMDK4412 board which is based on
8 * Samsung's Exynos4412 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16/include/ "exynos4412.dtsi"
17
18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412";
20 compatible = "samsung,smdk4412", "samsung,exynos4412";
21
22 memory {
23 reg = <0x40000000 0x40000000>;
24 };
25
26 chosen {
27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28 };
29
30 serial@13800000 {
31 status = "okay";
32 };
33
34 serial@13810000 {
35 status = "okay";
36 };
37
38 serial@13820000 {
39 status = "okay";
40 };
41
42 serial@13830000 {
43 status = "okay";
44 };
45};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
new file mode 100644
index 000000000000..d7dfe312772a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4412";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x4000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
new file mode 100644
index 000000000000..8e6115adcd97
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -0,0 +1,965 @@
1/*
2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@11400000 {
17 gpa0: gpa0 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpa1: gpa1 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 #interrupt-cells = <2>;
31 };
32
33 gpb: gpb {
34 gpio-controller;
35 #gpio-cells = <2>;
36
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 };
40
41 gpc0: gpc0 {
42 gpio-controller;
43 #gpio-cells = <2>;
44
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 };
48
49 gpc1: gpc1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 };
56
57 gpd0: gpd0 {
58 gpio-controller;
59 #gpio-cells = <2>;
60
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 };
64
65 gpd1: gpd1 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpf0: gpf0 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpf1: gpf1 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpf2: gpf2 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpf3: gpf3 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpj0: gpj0 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpj1: gpj1 {
114 gpio-controller;
115 #gpio-cells = <2>;
116
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 uart0_data: uart0-data {
122 samsung,pins = "gpa0-0", "gpa0-1";
123 samsung,pin-function = <0x2>;
124 samsung,pin-pud = <0>;
125 samsung,pin-drv = <0>;
126 };
127
128 uart0_fctl: uart0-fctl {
129 samsung,pins = "gpa0-2", "gpa0-3";
130 samsung,pin-function = <2>;
131 samsung,pin-pud = <0>;
132 samsung,pin-drv = <0>;
133 };
134
135 uart1_data: uart1-data {
136 samsung,pins = "gpa0-4", "gpa0-5";
137 samsung,pin-function = <2>;
138 samsung,pin-pud = <0>;
139 samsung,pin-drv = <0>;
140 };
141
142 uart1_fctl: uart1-fctl {
143 samsung,pins = "gpa0-6", "gpa0-7";
144 samsung,pin-function = <2>;
145 samsung,pin-pud = <0>;
146 samsung,pin-drv = <0>;
147 };
148
149 i2c2_bus: i2c2-bus {
150 samsung,pins = "gpa0-6", "gpa0-7";
151 samsung,pin-function = <3>;
152 samsung,pin-pud = <3>;
153 samsung,pin-drv = <0>;
154 };
155
156 uart2_data: uart2-data {
157 samsung,pins = "gpa1-0", "gpa1-1";
158 samsung,pin-function = <2>;
159 samsung,pin-pud = <0>;
160 samsung,pin-drv = <0>;
161 };
162
163 uart2_fctl: uart2-fctl {
164 samsung,pins = "gpa1-2", "gpa1-3";
165 samsung,pin-function = <2>;
166 samsung,pin-pud = <0>;
167 samsung,pin-drv = <0>;
168 };
169
170 uart_audio_a: uart-audio-a {
171 samsung,pins = "gpa1-0", "gpa1-1";
172 samsung,pin-function = <4>;
173 samsung,pin-pud = <0>;
174 samsung,pin-drv = <0>;
175 };
176
177 i2c3_bus: i2c3-bus {
178 samsung,pins = "gpa1-2", "gpa1-3";
179 samsung,pin-function = <3>;
180 samsung,pin-pud = <3>;
181 samsung,pin-drv = <0>;
182 };
183
184 uart3_data: uart3-data {
185 samsung,pins = "gpa1-4", "gpa1-5";
186 samsung,pin-function = <2>;
187 samsung,pin-pud = <0>;
188 samsung,pin-drv = <0>;
189 };
190
191 uart_audio_b: uart-audio-b {
192 samsung,pins = "gpa1-4", "gpa1-5";
193 samsung,pin-function = <4>;
194 samsung,pin-pud = <0>;
195 samsung,pin-drv = <0>;
196 };
197
198 spi0_bus: spi0-bus {
199 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
200 samsung,pin-function = <2>;
201 samsung,pin-pud = <3>;
202 samsung,pin-drv = <0>;
203 };
204
205 i2c4_bus: i2c4-bus {
206 samsung,pins = "gpb-0", "gpb-1";
207 samsung,pin-function = <3>;
208 samsung,pin-pud = <3>;
209 samsung,pin-drv = <0>;
210 };
211
212 spi1_bus: spi1-bus {
213 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
214 samsung,pin-function = <2>;
215 samsung,pin-pud = <3>;
216 samsung,pin-drv = <0>;
217 };
218
219 i2c5_bus: i2c5-bus {
220 samsung,pins = "gpb-2", "gpb-3";
221 samsung,pin-function = <3>;
222 samsung,pin-pud = <3>;
223 samsung,pin-drv = <0>;
224 };
225
226 i2s1_bus: i2s1-bus {
227 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
228 "gpc0-4";
229 samsung,pin-function = <2>;
230 samsung,pin-pud = <0>;
231 samsung,pin-drv = <0>;
232 };
233
234 pcm1_bus: pcm1-bus {
235 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
236 "gpc0-4";
237 samsung,pin-function = <3>;
238 samsung,pin-pud = <0>;
239 samsung,pin-drv = <0>;
240 };
241
242 ac97_bus: ac97-bus {
243 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
244 "gpc0-4";
245 samsung,pin-function = <4>;
246 samsung,pin-pud = <0>;
247 samsung,pin-drv = <0>;
248 };
249
250 i2s2_bus: i2s2-bus {
251 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
252 "gpc1-4";
253 samsung,pin-function = <2>;
254 samsung,pin-pud = <0>;
255 samsung,pin-drv = <0>;
256 };
257
258 pcm2_bus: pcm2-bus {
259 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
260 "gpc1-4";
261 samsung,pin-function = <3>;
262 samsung,pin-pud = <0>;
263 samsung,pin-drv = <0>;
264 };
265
266 spdif_bus: spdif-bus {
267 samsung,pins = "gpc1-0", "gpc1-1";
268 samsung,pin-function = <4>;
269 samsung,pin-pud = <0>;
270 samsung,pin-drv = <0>;
271 };
272
273 i2c6_bus: i2c6-bus {
274 samsung,pins = "gpc1-3", "gpc1-4";
275 samsung,pin-function = <4>;
276 samsung,pin-pud = <3>;
277 samsung,pin-drv = <0>;
278 };
279
280 spi2_bus: spi2-bus {
281 samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
282 samsung,pin-function = <5>;
283 samsung,pin-pud = <3>;
284 samsung,pin-drv = <0>;
285 };
286
287 pwm0_out: pwm0-out {
288 samsung,pins = "gpd0-0";
289 samsung,pin-function = <2>;
290 samsung,pin-pud = <0>;
291 samsung,pin-drv = <0>;
292 };
293
294 pwm1_out: pwm1-out {
295 samsung,pins = "gpd0-1";
296 samsung,pin-function = <2>;
297 samsung,pin-pud = <0>;
298 samsung,pin-drv = <0>;
299 };
300
301 lcd_ctrl: lcd-ctrl {
302 samsung,pins = "gpd0-0", "gpd0-1";
303 samsung,pin-function = <3>;
304 samsung,pin-pud = <0>;
305 samsung,pin-drv = <0>;
306 };
307
308 i2c7_bus: i2c7-bus {
309 samsung,pins = "gpd0-2", "gpd0-3";
310 samsung,pin-function = <3>;
311 samsung,pin-pud = <3>;
312 samsung,pin-drv = <0>;
313 };
314
315 pwm2_out: pwm2-out {
316 samsung,pins = "gpd0-2";
317 samsung,pin-function = <2>;
318 samsung,pin-pud = <0>;
319 samsung,pin-drv = <0>;
320 };
321
322 pwm3_out: pwm3-out {
323 samsung,pins = "gpd0-3";
324 samsung,pin-function = <2>;
325 samsung,pin-pud = <0>;
326 samsung,pin-drv = <0>;
327 };
328
329 i2c0_bus: i2c0-bus {
330 samsung,pins = "gpd1-0", "gpd1-1";
331 samsung,pin-function = <2>;
332 samsung,pin-pud = <3>;
333 samsung,pin-drv = <0>;
334 };
335
336 mipi0_clk: mipi0-clk {
337 samsung,pins = "gpd1-0", "gpd1-1";
338 samsung,pin-function = <3>;
339 samsung,pin-pud = <0>;
340 samsung,pin-drv = <0>;
341 };
342
343 i2c1_bus: i2c1-bus {
344 samsung,pins = "gpd1-2", "gpd1-3";
345 samsung,pin-function = <2>;
346 samsung,pin-pud = <3>;
347 samsung,pin-drv = <0>;
348 };
349
350 mipi1_clk: mipi1-clk {
351 samsung,pins = "gpd1-2", "gpd1-3";
352 samsung,pin-function = <3>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 lcd_clk: lcd-clk {
358 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
359 samsung,pin-function = <2>;
360 samsung,pin-pud = <0>;
361 samsung,pin-drv = <0>;
362 };
363
364 lcd_data16: lcd-data-width16 {
365 samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
366 "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
367 "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
368 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
369 samsung,pin-function = <2>;
370 samsung,pin-pud = <0>;
371 samsung,pin-drv = <0>;
372 };
373
374 lcd_data18: lcd-data-width18 {
375 samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
376 "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
377 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
378 "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
379 "gpf3-2", "gpf3-3";
380 samsung,pin-function = <2>;
381 samsung,pin-pud = <0>;
382 samsung,pin-drv = <0>;
383 };
384
385 lcd_data24: lcd-data-width24 {
386 samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
387 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
388 "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
389 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
390 "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
391 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
392 samsung,pin-function = <2>;
393 samsung,pin-pud = <0>;
394 samsung,pin-drv = <0>;
395 };
396
397 lcd_ldi: lcd-ldi {
398 samsung,pins = "gpf3-4";
399 samsung,pin-function = <2>;
400 samsung,pin-pud = <0>;
401 samsung,pin-drv = <0>;
402 };
403
404 cam_port_a: cam-port-a {
405 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
406 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
407 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
408 "gpj1-4";
409 samsung,pin-function = <2>;
410 samsung,pin-pud = <3>;
411 samsung,pin-drv = <0>;
412 };
413 };
414
415 pinctrl@11000000 {
416 gpk0: gpk0 {
417 gpio-controller;
418 #gpio-cells = <2>;
419
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpk1: gpk1 {
425 gpio-controller;
426 #gpio-cells = <2>;
427
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 };
431
432 gpk2: gpk2 {
433 gpio-controller;
434 #gpio-cells = <2>;
435
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 };
439
440 gpk3: gpk3 {
441 gpio-controller;
442 #gpio-cells = <2>;
443
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 };
447
448 gpl0: gpl0 {
449 gpio-controller;
450 #gpio-cells = <2>;
451
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 };
455
456 gpl1: gpl1 {
457 gpio-controller;
458 #gpio-cells = <2>;
459
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 };
463
464 gpl2: gpl2 {
465 gpio-controller;
466 #gpio-cells = <2>;
467
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 };
471
472 gpm0: gpm0 {
473 gpio-controller;
474 #gpio-cells = <2>;
475
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
479
480 gpm1: gpm1 {
481 gpio-controller;
482 #gpio-cells = <2>;
483
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 };
487
488 gpm2: gpm2 {
489 gpio-controller;
490 #gpio-cells = <2>;
491
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
495
496 gpm3: gpm3 {
497 gpio-controller;
498 #gpio-cells = <2>;
499
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 };
503
504 gpm4: gpm4 {
505 gpio-controller;
506 #gpio-cells = <2>;
507
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 };
511
512 gpy0: gpy0 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 };
516
517 gpy1: gpy1 {
518 gpio-controller;
519 #gpio-cells = <2>;
520 };
521
522 gpy2: gpy2 {
523 gpio-controller;
524 #gpio-cells = <2>;
525 };
526
527 gpy3: gpy3 {
528 gpio-controller;
529 #gpio-cells = <2>;
530 };
531
532 gpy4: gpy4 {
533 gpio-controller;
534 #gpio-cells = <2>;
535 };
536
537 gpy5: gpy5 {
538 gpio-controller;
539 #gpio-cells = <2>;
540 };
541
542 gpy6: gpy6 {
543 gpio-controller;
544 #gpio-cells = <2>;
545 };
546
547 gpx0: gpx0 {
548 gpio-controller;
549 #gpio-cells = <2>;
550
551 interrupt-controller;
552 interrupt-parent = <&gic>;
553 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
554 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
555 #interrupt-cells = <2>;
556 };
557
558 gpx1: gpx1 {
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 interrupt-controller;
563 interrupt-parent = <&gic>;
564 interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
565 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
566 #interrupt-cells = <2>;
567 };
568
569 gpx2: gpx2 {
570 gpio-controller;
571 #gpio-cells = <2>;
572
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
576
577 gpx3: gpx3 {
578 gpio-controller;
579 #gpio-cells = <2>;
580
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
584
585 sd0_clk: sd0-clk {
586 samsung,pins = "gpk0-0";
587 samsung,pin-function = <2>;
588 samsung,pin-pud = <0>;
589 samsung,pin-drv = <3>;
590 };
591
592 sd0_cmd: sd0-cmd {
593 samsung,pins = "gpk0-1";
594 samsung,pin-function = <2>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <3>;
597 };
598
599 sd0_cd: sd0-cd {
600 samsung,pins = "gpk0-2";
601 samsung,pin-function = <2>;
602 samsung,pin-pud = <3>;
603 samsung,pin-drv = <3>;
604 };
605
606 sd0_bus1: sd0-bus-width1 {
607 samsung,pins = "gpk0-3";
608 samsung,pin-function = <2>;
609 samsung,pin-pud = <3>;
610 samsung,pin-drv = <3>;
611 };
612
613 sd0_bus4: sd0-bus-width4 {
614 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
615 samsung,pin-function = <2>;
616 samsung,pin-pud = <3>;
617 samsung,pin-drv = <3>;
618 };
619
620 sd0_bus8: sd0-bus-width8 {
621 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
622 samsung,pin-function = <3>;
623 samsung,pin-pud = <3>;
624 samsung,pin-drv = <3>;
625 };
626
627 sd4_clk: sd4-clk {
628 samsung,pins = "gpk0-0";
629 samsung,pin-function = <3>;
630 samsung,pin-pud = <0>;
631 samsung,pin-drv = <3>;
632 };
633
634 sd4_cmd: sd4-cmd {
635 samsung,pins = "gpk0-1";
636 samsung,pin-function = <3>;
637 samsung,pin-pud = <0>;
638 samsung,pin-drv = <3>;
639 };
640
641 sd4_cd: sd4-cd {
642 samsung,pins = "gpk0-2";
643 samsung,pin-function = <3>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <3>;
646 };
647
648 sd4_bus1: sd4-bus-width1 {
649 samsung,pins = "gpk0-3";
650 samsung,pin-function = <3>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <3>;
653 };
654
655 sd4_bus4: sd4-bus-width4 {
656 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
657 samsung,pin-function = <3>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <3>;
660 };
661
662 sd4_bus8: sd4-bus-width8 {
663 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
664 samsung,pin-function = <3>;
665 samsung,pin-pud = <4>;
666 samsung,pin-drv = <3>;
667 };
668
669 sd1_clk: sd1-clk {
670 samsung,pins = "gpk1-0";
671 samsung,pin-function = <2>;
672 samsung,pin-pud = <0>;
673 samsung,pin-drv = <3>;
674 };
675
676 sd1_cmd: sd1-cmd {
677 samsung,pins = "gpk1-1";
678 samsung,pin-function = <2>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <3>;
681 };
682
683 sd1_cd: sd1-cd {
684 samsung,pins = "gpk1-2";
685 samsung,pin-function = <2>;
686 samsung,pin-pud = <3>;
687 samsung,pin-drv = <3>;
688 };
689
690 sd1_bus1: sd1-bus-width1 {
691 samsung,pins = "gpk1-3";
692 samsung,pin-function = <2>;
693 samsung,pin-pud = <3>;
694 samsung,pin-drv = <3>;
695 };
696
697 sd1_bus4: sd1-bus-width4 {
698 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
699 samsung,pin-function = <2>;
700 samsung,pin-pud = <3>;
701 samsung,pin-drv = <3>;
702 };
703
704 sd2_clk: sd2-clk {
705 samsung,pins = "gpk2-0";
706 samsung,pin-function = <2>;
707 samsung,pin-pud = <0>;
708 samsung,pin-drv = <3>;
709 };
710
711 sd2_cmd: sd2-cmd {
712 samsung,pins = "gpk2-1";
713 samsung,pin-function = <2>;
714 samsung,pin-pud = <0>;
715 samsung,pin-drv = <3>;
716 };
717
718 sd2_cd: sd2-cd {
719 samsung,pins = "gpk2-2";
720 samsung,pin-function = <2>;
721 samsung,pin-pud = <3>;
722 samsung,pin-drv = <3>;
723 };
724
725 sd2_bus1: sd2-bus-width1 {
726 samsung,pins = "gpk2-3";
727 samsung,pin-function = <2>;
728 samsung,pin-pud = <3>;
729 samsung,pin-drv = <3>;
730 };
731
732 sd2_bus4: sd2-bus-width4 {
733 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
734 samsung,pin-function = <2>;
735 samsung,pin-pud = <3>;
736 samsung,pin-drv = <3>;
737 };
738
739 sd2_bus8: sd2-bus-width8 {
740 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
741 samsung,pin-function = <3>;
742 samsung,pin-pud = <3>;
743 samsung,pin-drv = <3>;
744 };
745
746 sd3_clk: sd3-clk {
747 samsung,pins = "gpk3-0";
748 samsung,pin-function = <2>;
749 samsung,pin-pud = <0>;
750 samsung,pin-drv = <3>;
751 };
752
753 sd3_cmd: sd3-cmd {
754 samsung,pins = "gpk3-1";
755 samsung,pin-function = <2>;
756 samsung,pin-pud = <0>;
757 samsung,pin-drv = <3>;
758 };
759
760 sd3_cd: sd3-cd {
761 samsung,pins = "gpk3-2";
762 samsung,pin-function = <2>;
763 samsung,pin-pud = <3>;
764 samsung,pin-drv = <3>;
765 };
766
767 sd3_bus1: sd3-bus-width1 {
768 samsung,pins = "gpk3-3";
769 samsung,pin-function = <2>;
770 samsung,pin-pud = <3>;
771 samsung,pin-drv = <3>;
772 };
773
774 sd3_bus4: sd3-bus-width4 {
775 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
776 samsung,pin-function = <2>;
777 samsung,pin-pud = <3>;
778 samsung,pin-drv = <3>;
779 };
780
781 keypad_col0: keypad-col0 {
782 samsung,pins = "gpl2-0";
783 samsung,pin-function = <3>;
784 samsung,pin-pud = <0>;
785 samsung,pin-drv = <0>;
786 };
787
788 keypad_col1: keypad-col1 {
789 samsung,pins = "gpl2-1";
790 samsung,pin-function = <3>;
791 samsung,pin-pud = <0>;
792 samsung,pin-drv = <0>;
793 };
794
795 keypad_col2: keypad-col2 {
796 samsung,pins = "gpl2-2";
797 samsung,pin-function = <3>;
798 samsung,pin-pud = <0>;
799 samsung,pin-drv = <0>;
800 };
801
802 keypad_col3: keypad-col3 {
803 samsung,pins = "gpl2-3";
804 samsung,pin-function = <3>;
805 samsung,pin-pud = <0>;
806 samsung,pin-drv = <0>;
807 };
808
809 keypad_col4: keypad-col4 {
810 samsung,pins = "gpl2-4";
811 samsung,pin-function = <3>;
812 samsung,pin-pud = <0>;
813 samsung,pin-drv = <0>;
814 };
815
816 keypad_col5: keypad-col5 {
817 samsung,pins = "gpl2-5";
818 samsung,pin-function = <3>;
819 samsung,pin-pud = <0>;
820 samsung,pin-drv = <0>;
821 };
822
823 keypad_col6: keypad-col6 {
824 samsung,pins = "gpl2-6";
825 samsung,pin-function = <3>;
826 samsung,pin-pud = <0>;
827 samsung,pin-drv = <0>;
828 };
829
830 keypad_col7: keypad-col7 {
831 samsung,pins = "gpl2-7";
832 samsung,pin-function = <3>;
833 samsung,pin-pud = <0>;
834 samsung,pin-drv = <0>;
835 };
836
837 cam_port_b: cam-port-b {
838 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
839 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
840 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
841 "gpm2-2";
842 samsung,pin-function = <3>;
843 samsung,pin-pud = <3>;
844 samsung,pin-drv = <0>;
845 };
846
847 eint0: ext-int0 {
848 samsung,pins = "gpx0-0";
849 samsung,pin-function = <0xf>;
850 samsung,pin-pud = <0>;
851 samsung,pin-drv = <0>;
852 };
853
854 eint8: ext-int8 {
855 samsung,pins = "gpx1-0";
856 samsung,pin-function = <0xf>;
857 samsung,pin-pud = <0>;
858 samsung,pin-drv = <0>;
859 };
860
861 eint15: ext-int15 {
862 samsung,pins = "gpx1-7";
863 samsung,pin-function = <0xf>;
864 samsung,pin-pud = <0>;
865 samsung,pin-drv = <0>;
866 };
867
868 eint16: ext-int16 {
869 samsung,pins = "gpx2-0";
870 samsung,pin-function = <0xf>;
871 samsung,pin-pud = <0>;
872 samsung,pin-drv = <0>;
873 };
874
875 eint31: ext-int31 {
876 samsung,pins = "gpx3-7";
877 samsung,pin-function = <0xf>;
878 samsung,pin-pud = <0>;
879 samsung,pin-drv = <0>;
880 };
881 };
882
883 pinctrl@03860000 {
884 gpz: gpz {
885 gpio-controller;
886 #gpio-cells = <2>;
887
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 };
891
892 i2s0_bus: i2s0-bus {
893 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
894 "gpz-4", "gpz-5", "gpz-6";
895 samsung,pin-function = <0x2>;
896 samsung,pin-pud = <0>;
897 samsung,pin-drv = <0>;
898 };
899
900 pcm0_bus: pcm0-bus {
901 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
902 "gpz-4";
903 samsung,pin-function = <0x3>;
904 samsung,pin-pud = <0>;
905 samsung,pin-drv = <0>;
906 };
907 };
908
909 pinctrl@106E0000 {
910 gpv0: gpv0 {
911 gpio-controller;
912 #gpio-cells = <2>;
913
914 interrupt-controller;
915 #interrupt-cells = <2>;
916 };
917
918 gpv1: gpv1 {
919 gpio-controller;
920 #gpio-cells = <2>;
921
922 interrupt-controller;
923 #interrupt-cells = <2>;
924 };
925
926 gpv2: gpv2 {
927 gpio-controller;
928 #gpio-cells = <2>;
929
930 interrupt-controller;
931 #interrupt-cells = <2>;
932 };
933
934 gpv3: gpv3 {
935 gpio-controller;
936 #gpio-cells = <2>;
937
938 interrupt-controller;
939 #interrupt-cells = <2>;
940 };
941
942 gpv4: gpv4 {
943 gpio-controller;
944 #gpio-cells = <2>;
945
946 interrupt-controller;
947 #interrupt-cells = <2>;
948 };
949
950 c2c_bus: c2c-bus {
951 samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
952 "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
953 "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
954 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
955 "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
956 "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
957 "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
958 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
959 "gpv4-0", "gpv4-1";
960 samsung,pin-function = <0x2>;
961 samsung,pin-pud = <0>;
962 samsung,pin-drv = <0>;
963 };
964 };
965};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
new file mode 100644
index 000000000000..179a62e46c9d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -0,0 +1,69 @@
1/*
2 * Samsung's Exynos4x12 SoCs device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4.dtsi"
21/include/ "exynos4x12-pinctrl.dtsi"
22
23/ {
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 };
30
31 combiner:interrupt-controller@10440000 {
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37 };
38
39 pinctrl_0: pinctrl@11400000 {
40 compatible = "samsung,pinctrl-exynos4x12";
41 reg = <0x11400000 0x1000>;
42 interrupts = <0 47 0>;
43 };
44
45 pinctrl_1: pinctrl@11000000 {
46 compatible = "samsung,pinctrl-exynos4x12";
47 reg = <0x11000000 0x1000>;
48 interrupts = <0 46 0>;
49
50 wakup_eint: wakeup-interrupt-controller {
51 compatible = "samsung,exynos4210-wakeup-eint";
52 interrupt-parent = <&gic>;
53 interrupts = <0 32 0>;
54 };
55 };
56
57 pinctrl_2: pinctrl@03860000 {
58 compatible = "samsung,pinctrl-exynos4x12";
59 reg = <0x03860000 0x1000>;
60 interrupt-parent = <&combiner>;
61 interrupts = <10 0>;
62 };
63
64 pinctrl_3: pinctrl@106E0000 {
65 compatible = "samsung,pinctrl-exynos4x12";
66 reg = <0x106E0000 0x1000>;
67 interrupts = <0 72 0>;
68 };
69};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a352df403b7a..942d5761ca97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -17,10 +17,6 @@
17 compatible = "samsung,smdk5250", "samsung,exynos5250"; 17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18 18
19 aliases { 19 aliases {
20 mshc0 = &dwmmc_0;
21 mshc1 = &dwmmc_1;
22 mshc2 = &dwmmc_2;
23 mshc3 = &dwmmc_3;
24 }; 20 };
25 21
26 memory { 22 memory {
@@ -55,8 +51,31 @@
55 }; 51 };
56 }; 52 };
57 53
54 i2c@121D0000 {
55 samsung,i2c-sda-delay = <100>;
56 samsung,i2c-max-bus-freq = <40000>;
57 samsung,i2c-slave-addr = <0x38>;
58
59 sata-phy {
60 compatible = "samsung,sata-phy";
61 reg = <0x38>;
62 };
63 };
64
65 sata@122F0000 {
66 samsung,sata-freq = <66>;
67 };
68
58 i2c@12C80000 { 69 i2c@12C80000 {
59 status = "disabled"; 70 samsung,i2c-sda-delay = <100>;
71 samsung,i2c-max-bus-freq = <66000>;
72 gpios = <&gpa0 6 3 3 0>,
73 <&gpa0 7 3 3 0>;
74
75 hdmiddc@50 {
76 compatible = "samsung,exynos5-hdmiddc";
77 reg = <0x50>;
78 };
60 }; 79 };
61 80
62 i2c@12C90000 { 81 i2c@12C90000 {
@@ -79,7 +98,17 @@
79 status = "disabled"; 98 status = "disabled";
80 }; 99 };
81 100
82 dwmmc_0: dwmmc0@12200000 { 101 i2c@12CE0000 {
102 samsung,i2c-sda-delay = <100>;
103 samsung,i2c-max-bus-freq = <66000>;
104
105 hdmiphy@38 {
106 compatible = "samsung,exynos5-hdmiphy";
107 reg = <0x38>;
108 };
109 };
110
111 dwmmc0@12200000 {
83 num-slots = <1>; 112 num-slots = <1>;
84 supports-highspeed; 113 supports-highspeed;
85 broken-cd; 114 broken-cd;
@@ -100,11 +129,11 @@
100 }; 129 };
101 }; 130 };
102 131
103 dwmmc_1: dwmmc1@12210000 { 132 dwmmc1@12210000 {
104 status = "disabled"; 133 status = "disabled";
105 }; 134 };
106 135
107 dwmmc_2: dwmmc2@12220000 { 136 dwmmc2@12220000 {
108 num-slots = <1>; 137 num-slots = <1>;
109 supports-highspeed; 138 supports-highspeed;
110 fifo-depth = <0x80>; 139 fifo-depth = <0x80>;
@@ -125,7 +154,7 @@
125 }; 154 };
126 }; 155 };
127 156
128 dwmmc_3: dwmmc3@12230000 { 157 dwmmc3@12230000 {
129 status = "disabled"; 158 status = "disabled";
130 }; 159 };
131 160
@@ -166,4 +195,13 @@
166 spi_2: spi@12d40000 { 195 spi_2: spi@12d40000 {
167 status = "disabled"; 196 status = "disabled";
168 }; 197 };
198
199 hdmi {
200 hpd-gpio = <&gpx3 7 0xf 1 3>;
201 };
202
203 codec@11000000 {
204 samsung,mfc-r = <0x43000000 0x800000>;
205 samsung,mfc-l = <0x51000000 0x800000>;
206 };
169}; 207};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
new file mode 100644
index 000000000000..17dd951c1cd2
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -0,0 +1,43 @@
1/*
2 * Google Snow board device tree source
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/dts-v1/;
12/include/ "exynos5250.dtsi"
13/include/ "cros5250-common.dtsi"
14
15/ {
16 model = "Google Snow";
17 compatible = "google,snow", "samsung,exynos5250";
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 lid-switch {
23 label = "Lid";
24 gpios = <&gpx3 5 0 0x10000 0>;
25 linux,input-type = <5>; /* EV_SW */
26 linux,code = <0>; /* SW_LID */
27 debounce-interval = <1>;
28 gpio-key,wakeup;
29 };
30 };
31
32 /*
33 * On Snow we've got SIP WiFi and so can keep drive strengths low to
34 * reduce EMI.
35 */
36 dwmmc3@12230000 {
37 slot@0 {
38 gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
39 <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41 };
42 };
43};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e444dc..36d8246ea50e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -31,6 +31,10 @@
31 gsc1 = &gsc_1; 31 gsc1 = &gsc_1;
32 gsc2 = &gsc_2; 32 gsc2 = &gsc_2;
33 gsc3 = &gsc_3; 33 gsc3 = &gsc_3;
34 mshc0 = &dwmmc_0;
35 mshc1 = &dwmmc_1;
36 mshc2 = &dwmmc_2;
37 mshc3 = &dwmmc_3;
34 }; 38 };
35 39
36 gic:interrupt-controller@10481000 { 40 gic:interrupt-controller@10481000 {
@@ -62,12 +66,24 @@
62 interrupts = <0 42 0>; 66 interrupts = <0 42 0>;
63 }; 67 };
64 68
69 codec@11000000 {
70 compatible = "samsung,mfc-v6";
71 reg = <0x11000000 0x10000>;
72 interrupts = <0 96 0>;
73 };
74
65 rtc { 75 rtc {
66 compatible = "samsung,s3c6410-rtc"; 76 compatible = "samsung,s3c6410-rtc";
67 reg = <0x101E0000 0x100>; 77 reg = <0x101E0000 0x100>;
68 interrupts = <0 43 0>, <0 44 0>; 78 interrupts = <0 43 0>, <0 44 0>;
69 }; 79 };
70 80
81 tmu@10060000 {
82 compatible = "samsung,exynos5250-tmu";
83 reg = <0x10060000 0x100>;
84 interrupts = <0 65 0>;
85 };
86
71 serial@12C00000 { 87 serial@12C00000 {
72 compatible = "samsung,exynos4210-uart"; 88 compatible = "samsung,exynos4210-uart";
73 reg = <0x12C00000 0x100>; 89 reg = <0x12C00000 0x100>;
@@ -92,6 +108,17 @@
92 interrupts = <0 54 0>; 108 interrupts = <0 54 0>;
93 }; 109 };
94 110
111 sata@122F0000 {
112 compatible = "samsung,exynos5-sata-ahci";
113 reg = <0x122F0000 0x1ff>;
114 interrupts = <0 115 0>;
115 };
116
117 sata-phy@12170000 {
118 compatible = "samsung,exynos5-sata-phy";
119 reg = <0x12170000 0x1ff>;
120 };
121
95 i2c@12C60000 { 122 i2c@12C60000 {
96 compatible = "samsung,s3c2440-i2c"; 123 compatible = "samsung,s3c2440-i2c";
97 reg = <0x12C60000 0x100>; 124 reg = <0x12C60000 0x100>;
@@ -156,6 +183,21 @@
156 #size-cells = <0>; 183 #size-cells = <0>;
157 }; 184 };
158 185
186 i2c@12CE0000 {
187 compatible = "samsung,s3c2440-hdmiphy-i2c";
188 reg = <0x12CE0000 0x1000>;
189 interrupts = <0 64 0>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192 };
193
194 i2c@121D0000 {
195 compatible = "samsung,exynos5-sata-phy-i2c";
196 reg = <0x121D0000 0x100>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 };
200
159 spi_0: spi@12d20000 { 201 spi_0: spi@12d20000 {
160 compatible = "samsung,exynos4210-spi"; 202 compatible = "samsung,exynos4210-spi";
161 reg = <0x12d20000 0x100>; 203 reg = <0x12d20000 0x100>;
@@ -186,7 +228,7 @@
186 #size-cells = <0>; 228 #size-cells = <0>;
187 }; 229 };
188 230
189 dwmmc0@12200000 { 231 dwmmc_0: dwmmc0@12200000 {
190 compatible = "samsung,exynos5250-dw-mshc"; 232 compatible = "samsung,exynos5250-dw-mshc";
191 reg = <0x12200000 0x1000>; 233 reg = <0x12200000 0x1000>;
192 interrupts = <0 75 0>; 234 interrupts = <0 75 0>;
@@ -194,7 +236,7 @@
194 #size-cells = <0>; 236 #size-cells = <0>;
195 }; 237 };
196 238
197 dwmmc1@12210000 { 239 dwmmc_1: dwmmc1@12210000 {
198 compatible = "samsung,exynos5250-dw-mshc"; 240 compatible = "samsung,exynos5250-dw-mshc";
199 reg = <0x12210000 0x1000>; 241 reg = <0x12210000 0x1000>;
200 interrupts = <0 76 0>; 242 interrupts = <0 76 0>;
@@ -202,7 +244,7 @@
202 #size-cells = <0>; 244 #size-cells = <0>;
203 }; 245 };
204 246
205 dwmmc2@12220000 { 247 dwmmc_2: dwmmc2@12220000 {
206 compatible = "samsung,exynos5250-dw-mshc"; 248 compatible = "samsung,exynos5250-dw-mshc";
207 reg = <0x12220000 0x1000>; 249 reg = <0x12220000 0x1000>;
208 interrupts = <0 77 0>; 250 interrupts = <0 77 0>;
@@ -210,7 +252,7 @@
210 #size-cells = <0>; 252 #size-cells = <0>;
211 }; 253 };
212 254
213 dwmmc3@12230000 { 255 dwmmc_3: dwmmc3@12230000 {
214 compatible = "samsung,exynos5250-dw-mshc"; 256 compatible = "samsung,exynos5250-dw-mshc";
215 reg = <0x12230000 0x1000>; 257 reg = <0x12230000 0x1000>;
216 interrupts = <0 78 0>; 258 interrupts = <0 78 0>;
@@ -520,4 +562,16 @@
520 reg = <0x13e30000 0x1000>; 562 reg = <0x13e30000 0x1000>;
521 interrupts = <0 88 0>; 563 interrupts = <0 88 0>;
522 }; 564 };
565
566 hdmi {
567 compatible = "samsung,exynos5-hdmi";
568 reg = <0x14530000 0x100000>;
569 interrupts = <0 95 0>;
570 };
571
572 mixer {
573 compatible = "samsung,exynos5-mixer";
574 reg = <0x14450000 0x10000>;
575 interrupts = <0 94 0>;
576 };
523}; 577};
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
new file mode 100644
index 000000000000..592fb9dc35bd
--- /dev/null
+++ b/arch/arm/boot/dts/href.dtsi
@@ -0,0 +1,273 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "dbx5x0.dtsi"
13
14/ {
15 memory {
16 reg = <0x00000000 0x20000000>;
17 };
18
19 gpio_keys {
20 compatible = "gpio-keys";
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 button@1 {
25 linux,code = <11>;
26 label = "SFH7741 Proximity Sensor";
27 };
28 };
29
30 soc-u9500 {
31 uart@80120000 {
32 status = "okay";
33 };
34
35 uart@80121000 {
36 status = "okay";
37 };
38
39 uart@80007000 {
40 status = "okay";
41 };
42
43 i2c@80004000 {
44 tc3589x@42 {
45 compatible = "tc3589x";
46 reg = <0x42>;
47 interrupt-parent = <&gpio6>;
48 interrupts = <25 0x1>;
49
50 interrupt-controller;
51 #interrupt-cells = <2>;
52
53 tc3589x_gpio: tc3589x_gpio {
54 compatible = "tc3589x-gpio";
55 interrupts = <0 0x1>;
56
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 gpio-controller;
60 #gpio-cells = <2>;
61 };
62 };
63 };
64
65 i2c@80128000 {
66 lp5521@0x33 {
67 compatible = "lp5521";
68 reg = <0x33>;
69 };
70
71 lp5521@0x34 {
72 compatible = "lp5521";
73 reg = <0x34>;
74 };
75
76 bh1780@0x29 {
77 compatible = "rohm,bh1780gli";
78 reg = <0x33>;
79 };
80 };
81
82 // External Micro SD slot
83 sdi0_per1@80126000 {
84 arm,primecell-periphid = <0x10480180>;
85 max-frequency = <50000000>;
86 bus-width = <4>;
87 mmc-cap-sd-highspeed;
88 mmc-cap-mmc-highspeed;
89 vmmc-supply = <&ab8500_ldo_aux3_reg>;
90
91 cd-gpios = <&tc3589x_gpio 3 0x4>;
92
93 status = "okay";
94 };
95
96 // WLAN SDIO channel
97 sdi1_per2@80118000 {
98 arm,primecell-periphid = <0x10480180>;
99 max-frequency = <50000000>;
100 bus-width = <4>;
101
102 status = "okay";
103 };
104
105 // PoP:ed eMMC
106 sdi2_per3@80005000 {
107 arm,primecell-periphid = <0x10480180>;
108 max-frequency = <50000000>;
109 bus-width = <8>;
110 mmc-cap-mmc-highspeed;
111
112 status = "okay";
113 };
114
115 // On-board eMMC
116 sdi4_per2@80114000 {
117 arm,primecell-periphid = <0x10480180>;
118 max-frequency = <50000000>;
119 bus-width = <8>;
120 mmc-cap-mmc-highspeed;
121 vmmc-supply = <&ab8500_ldo_aux2_reg>;
122
123 status = "okay";
124 };
125
126 sound {
127 compatible = "stericsson,snd-soc-mop500";
128
129 stericsson,cpu-dai = <&msp1 &msp3>;
130 stericsson,audio-codec = <&codec>;
131 };
132
133 msp1: msp@80124000 {
134 status = "okay";
135 };
136
137 msp3: msp@80125000 {
138 status = "okay";
139 };
140
141 prcmu@80157000 {
142 db8500-prcmu-regulators {
143 db8500_vape_reg: db8500_vape {
144 regulator-name = "db8500-vape";
145 };
146
147 db8500_varm_reg: db8500_varm {
148 regulator-name = "db8500-varm";
149 };
150
151 db8500_vmodem_reg: db8500_vmodem {
152 regulator-name = "db8500-vmodem";
153 };
154
155 db8500_vpll_reg: db8500_vpll {
156 regulator-name = "db8500-vpll";
157 };
158
159 db8500_vsmps1_reg: db8500_vsmps1 {
160 regulator-name = "db8500-vsmps1";
161 };
162
163 db8500_vsmps2_reg: db8500_vsmps2 {
164 regulator-name = "db8500-vsmps2";
165 };
166
167 db8500_vsmps3_reg: db8500_vsmps3 {
168 regulator-name = "db8500-vsmps3";
169 };
170
171 db8500_vrf1_reg: db8500_vrf1 {
172 regulator-name = "db8500-vrf1";
173 };
174
175 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
176 regulator-name = "db8500-sva-mmdsp";
177 };
178
179 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
180 regulator-name = "db8500-sva-mmdsp-ret";
181 };
182
183 db8500_sva_pipe_reg: db8500_sva_pipe {
184 regulator-name = "db8500_sva_pipe";
185 };
186
187 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
188 regulator-name = "db8500_sia_mmdsp";
189 };
190
191 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
192 regulator-name = "db8500-sia-mmdsp-ret";
193 };
194
195 db8500_sia_pipe_reg: db8500_sia_pipe {
196 regulator-name = "db8500-sia-pipe";
197 };
198
199 db8500_sga_reg: db8500_sga {
200 regulator-name = "db8500-sga";
201 };
202
203 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
204 regulator-name = "db8500-b2r2-mcde";
205 };
206
207 db8500_esram12_reg: db8500_esram12 {
208 regulator-name = "db8500-esram12";
209 };
210
211 db8500_esram12_ret_reg: db8500_esram12_ret {
212 regulator-name = "db8500-esram12-ret";
213 };
214
215 db8500_esram34_reg: db8500_esram34 {
216 regulator-name = "db8500-esram34";
217 };
218
219 db8500_esram34_ret_reg: db8500_esram34_ret {
220 regulator-name = "db8500-esram34-ret";
221 };
222 };
223
224 ab8500@5 {
225 ab8500-regulators {
226 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
227 regulator-name = "V-DISPLAY";
228 };
229
230 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
231 regulator-name = "V-eMMC1";
232 };
233
234 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
235 regulator-name = "V-MMC-SD";
236 };
237
238 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
239 regulator-name = "V-INTCORE";
240 };
241
242 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
243 regulator-name = "V-TVOUT";
244 };
245
246 ab8500_ldo_usb_reg: ab8500_ldo_usb {
247 regulator-name = "dummy";
248 };
249
250 ab8500_ldo_audio_reg: ab8500_ldo_audio {
251 regulator-name = "V-AUD";
252 };
253
254 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
255 regulator-name = "V-AMIC1";
256 };
257
258 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
259 regulator-name = "V-AMIC2";
260 };
261
262 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
263 regulator-name = "V-DMIC";
264 };
265
266 ab8500_ldo_ana_reg: ab8500_ldo_ana {
267 regulator-name = "V-CSI/DSI";
268 };
269 };
270 };
271 };
272 };
273};
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
new file mode 100644
index 000000000000..eec29c4a86dc
--- /dev/null
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
16
17/ {
18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
19 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
20
21 gpio_keys {
22 button@1 {
23 gpios = <&tc3589x_gpio 7 0x4>;
24 };
25 };
26
27 soc-u9500 {
28 i2c@80004000 {
29 tps61052@33 {
30 compatible = "tps61052";
31 reg = <0x33>;
32 };
33 };
34
35 i2c@80110000 {
36 bu21013_tp@0x5c {
37 reset-gpio = <&tc3589x_gpio 13 0x4>;
38 };
39 };
40
41 vmmci: regulator-gpio {
42 gpios = <&tc3589x_gpio 18 0x4>;
43 gpio-enable = <&tc3589x_gpio 17 0x4>;
44
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2131d77dc9c9..55f4191a626e 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -11,85 +11,200 @@
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "dbx5x0.dtsi" 13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
14 16
15/ { 17/ {
16 model = "ST-Ericsson HREF platform with Device Tree"; 18 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
17 compatible = "st-ericsson,hrefv60+"; 19 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
18 20
19 memory { 21 gpio_keys {
20 reg = <0x00000000 0x20000000>; 22 button@1 {
23 gpios = <&gpio6 25 0x4>;
24 };
21 }; 25 };
22 26
23 soc-u9500 { 27 soc-u9500 {
24 uart@80120000 { 28 i2c@80110000 {
29 bu21013_tp@0x5c {
30 reset-gpio = <&gpio4 15 0x4>;
31 };
32 };
33
34 // External Micro SD slot
35 sdi0_per1@80126000 {
36 arm,primecell-periphid = <0x10480180>;
37 max-frequency = <50000000>;
38 bus-width = <4>;
39 mmc-cap-sd-highspeed;
40 mmc-cap-mmc-highspeed;
41 vmmc-supply = <&ab8500_ldo_aux3_reg>;
42
43 cd-gpios = <&tc3589x_gpio 3 0x4>;
44
25 status = "okay"; 45 status = "okay";
26 }; 46 };
27 47
28 uart@80121000 { 48 // WLAN SDIO channel
49 sdi1_per2@80118000 {
50 arm,primecell-periphid = <0x10480180>;
51 max-frequency = <50000000>;
52 bus-width = <4>;
53
29 status = "okay"; 54 status = "okay";
30 }; 55 };
31 56
32 uart@80007000 { 57 // PoP:ed eMMC
58 sdi2_per3@80005000 {
59 arm,primecell-periphid = <0x10480180>;
60 max-frequency = <50000000>;
61 bus-width = <8>;
62 mmc-cap-mmc-highspeed;
63
33 status = "okay"; 64 status = "okay";
34 }; 65 };
35 66
36 i2c@80004000 { 67 // On-board eMMC
37 tc3589x@42 { 68 sdi4_per2@80114000 {
38 compatible = "tc3589x"; 69 arm,primecell-periphid = <0x10480180>;
39 reg = <0x42>; 70 max-frequency = <50000000>;
40 interrupt-parent = <&gpio6>; 71 bus-width = <8>;
41 interrupts = <25 0x1>; 72 mmc-cap-mmc-highspeed;
73 vmmc-supply = <&ab8500_ldo_aux2_reg>;
42 74
43 interrupt-controller; 75 status = "okay";
44 #interrupt-cells = <2>; 76 };
45 77
46 tc3589x_gpio: tc3589x_gpio { 78 prcmu@80157000 {
47 compatible = "tc3589x-gpio"; 79 db8500-prcmu-regulators {
48 interrupts = <0 0x1>; 80 db8500_vape_reg: db8500_vape {
81 regulator-name = "db8500-vape";
82 };
49 83
50 interrupt-controller; 84 db8500_varm_reg: db8500_varm {
51 #interrupt-cells = <2>; 85 regulator-name = "db8500-varm";
52 gpio-controller;
53 #gpio-cells = <2>;
54 }; 86 };
55 };
56 87
57 tps61052@33 { 88 db8500_vmodem_reg: db8500_vmodem {
58 compatible = "tps61052"; 89 regulator-name = "db8500-vmodem";
59 reg = <0x33>; 90 };
60 };
61 };
62 91
63 i2c@80128000 { 92 db8500_vpll_reg: db8500_vpll {
64 lp5521@0x33 { 93 regulator-name = "db8500-vpll";
65 compatible = "lp5521"; 94 };
66 reg = <0x33>;
67 };
68 95
69 lp5521@0x34 { 96 db8500_vsmps1_reg: db8500_vsmps1 {
70 compatible = "lp5521"; 97 regulator-name = "db8500-vsmps1";
71 reg = <0x34>; 98 };
72 }; 99
100 db8500_vsmps2_reg: db8500_vsmps2 {
101 regulator-name = "db8500-vsmps2";
102 };
103
104 db8500_vsmps3_reg: db8500_vsmps3 {
105 regulator-name = "db8500-vsmps3";
106 };
107
108 db8500_vrf1_reg: db8500_vrf1 {
109 regulator-name = "db8500-vrf1";
110 };
111
112 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
113 regulator-name = "db8500-sva-mmdsp";
114 };
115
116 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
117 regulator-name = "db8500-sva-mmdsp-ret";
118 };
119
120 db8500_sva_pipe_reg: db8500_sva_pipe {
121 regulator-name = "db8500_sva_pipe";
122 };
73 123
74 bh1780@0x29 { 124 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
75 compatible = "rohm,bh1780gli"; 125 regulator-name = "db8500_sia_mmdsp";
76 reg = <0x33>; 126 };
127
128 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
129 regulator-name = "db8500-sia-mmdsp-ret";
130 };
131
132 db8500_sia_pipe_reg: db8500_sia_pipe {
133 regulator-name = "db8500-sia-pipe";
134 };
135
136 db8500_sga_reg: db8500_sga {
137 regulator-name = "db8500-sga";
138 };
139
140 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
141 regulator-name = "db8500-b2r2-mcde";
142 };
143
144 db8500_esram12_reg: db8500_esram12 {
145 regulator-name = "db8500-esram12";
146 };
147
148 db8500_esram12_ret_reg: db8500_esram12_ret {
149 regulator-name = "db8500-esram12-ret";
150 };
151
152 db8500_esram34_reg: db8500_esram34 {
153 regulator-name = "db8500-esram34";
154 };
155
156 db8500_esram34_ret_reg: db8500_esram34_ret {
157 regulator-name = "db8500-esram34-ret";
158 };
77 }; 159 };
78 };
79 160
80 sound { 161 ab8500@5 {
81 compatible = "stericsson,snd-soc-mop500"; 162 ab8500-regulators {
163 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
164 regulator-name = "V-DISPLAY";
165 };
82 166
83 stericsson,cpu-dai = <&msp1 &msp3>; 167 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
84 stericsson,audio-codec = <&codec>; 168 regulator-name = "V-eMMC1";
85 }; 169 };
86 170
87 msp1: msp@80124000 { 171 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
88 status = "okay"; 172 regulator-name = "V-MMC-SD";
89 }; 173 };
90 174
91 msp3: msp@80125000 { 175 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
92 status = "okay"; 176 regulator-name = "V-INTCORE";
177 };
178
179 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
180 regulator-name = "V-TVOUT";
181 };
182
183 ab8500_ldo_usb_reg: ab8500_ldo_usb {
184 regulator-name = "dummy";
185 };
186
187 ab8500_ldo_audio_reg: ab8500_ldo_audio {
188 regulator-name = "V-AUD";
189 };
190
191 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
192 regulator-name = "V-AMIC1";
193 };
194
195 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
196 regulator-name = "V-AMIC2";
197 };
198
199 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
200 regulator-name = "V-DMIC";
201 };
202
203 ab8500_ldo_ana_reg: ab8500_ldo_ana {
204 regulator-name = "V-CSI/DSI";
205 };
206 };
207 };
93 }; 208 };
94 }; 209 };
95}; 210};
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 384d8b66f337..7c43b8e70b9f 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -40,6 +40,15 @@
40 reg = <0>; 40 reg = <0>;
41 fsl,pinmux-ids = < 41 fsl,pinmux-ids = <
42 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ 42 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48
49 led_pin_gpio0_17: led_gpio0_17@0 {
50 reg = <0>;
51 fsl,pinmux-ids = <
43 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ 52 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
44 >; 53 >;
45 fsl,drive-strength = <0>; 54 fsl,drive-strength = <0>;
@@ -47,6 +56,15 @@
47 fsl,pull-up = <0>; 56 fsl,pull-up = <0>;
48 }; 57 };
49 }; 58 };
59
60 ssp1: ssp@80034000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx23-spi";
64 pinctrl-names = "default";
65 pinctrl-0 = <&spi2_pins_a>;
66 status = "okay";
67 };
50 }; 68 };
51 69
52 apbx@80040000 { 70 apbx@80040000 {
@@ -91,11 +109,12 @@
91 109
92 leds { 110 leds {
93 compatible = "gpio-leds"; 111 compatible = "gpio-leds";
112 pinctrl-names = "default";
113 pinctrl-0 = <&led_pin_gpio0_17>;
94 114
95 user { 115 user {
96 label = "green"; 116 label = "green";
97 gpios = <&gpio2 1 0>; 117 gpios = <&gpio2 1 1>;
98 linux,default-trigger = "default-on";
99 }; 118 };
100 }; 119 };
101}; 120};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 6d31aa383460..65415c598a5e 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -279,6 +279,19 @@
279 fsl,voltage = <1>; 279 fsl,voltage = <1>;
280 fsl,pull-up = <0>; 280 fsl,pull-up = <0>;
281 }; 281 };
282
283 spi2_pins_a: spi2@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
287 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
288 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
289 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
290 >;
291 fsl,drive-strength = <1>;
292 fsl,voltage = <1>;
293 fsl,pull-up = <1>;
294 };
282 }; 295 };
283 296
284 digctl@8001c000 { 297 digctl@8001c000 {
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
new file mode 100644
index 000000000000..d81f8a0b9794
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx25.dtsi"
14
15/ {
16 model = "Ka-Ro TX25";
17 compatible = "karo,imx25-tx25", "fsl,imx25";
18
19 memory {
20 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21 };
22
23 soc {
24 aips@43f00000 {
25 uart1: serial@43f90000 {
26 status = "okay";
27 };
28 };
29
30 spba@50000000 {
31 fec: ethernet@50038000 {
32 status = "okay";
33 phy-mode = "rmii";
34 };
35 };
36
37 emi@80000000 {
38 nand@bb000000 {
39 nand-on-flash-bbt;
40 status = "okay";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
new file mode 100644
index 000000000000..e1b13ebc96d6
--- /dev/null
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -0,0 +1,515 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 usb0 = &usbotg;
26 usb1 = &usbhost1;
27 };
28
29 asic: asic-interrupt-controller@68000000 {
30 compatible = "fsl,imx25-asic", "fsl,avic";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0x68000000 0x8000000>;
34 };
35
36 clocks {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 osc {
41 compatible = "fsl,imx-osc", "fixed-clock";
42 clock-frequency = <24000000>;
43 };
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 interrupt-parent = <&asic>;
51 ranges;
52
53 aips@43f00000 { /* AIPS1 */
54 compatible = "fsl,aips-bus", "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0x43f00000 0x100000>;
58 ranges;
59
60 i2c1: i2c@43f80000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
64 reg = <0x43f80000 0x4000>;
65 clocks = <&clks 48>;
66 clock-names = "";
67 interrupts = <3>;
68 status = "disabled";
69 };
70
71 i2c3: i2c@43f84000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
75 reg = <0x43f84000 0x4000>;
76 clocks = <&clks 48>;
77 clock-names = "";
78 interrupts = <10>;
79 status = "disabled";
80 };
81
82 can1: can@43f88000 {
83 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
84 reg = <0x43f88000 0x4000>;
85 interrupts = <43>;
86 clocks = <&clks 75>, <&clks 75>;
87 clock-names = "ipg", "per";
88 status = "disabled";
89 };
90
91 can2: can@43f8c000 {
92 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
93 reg = <0x43f8c000 0x4000>;
94 interrupts = <44>;
95 clocks = <&clks 76>, <&clks 76>;
96 clock-names = "ipg", "per";
97 status = "disabled";
98 };
99
100 uart1: serial@43f90000 {
101 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
102 reg = <0x43f90000 0x4000>;
103 interrupts = <45>;
104 clocks = <&clks 120>, <&clks 57>;
105 clock-names = "ipg", "per";
106 status = "disabled";
107 };
108
109 uart2: serial@43f94000 {
110 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
111 reg = <0x43f94000 0x4000>;
112 interrupts = <32>;
113 clocks = <&clks 121>, <&clks 57>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 i2c2: i2c@43f98000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
122 reg = <0x43f98000 0x4000>;
123 clocks = <&clks 48>;
124 clock-names = "";
125 interrupts = <4>;
126 status = "disabled";
127 };
128
129 owire@43f9c000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x43f9c000 0x4000>;
133 clocks = <&clks 51>;
134 clock-names = "";
135 interrupts = <2>;
136 status = "disabled";
137 };
138
139 spi1: cspi@43fa4000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
143 reg = <0x43fa4000 0x4000>;
144 clocks = <&clks 62>;
145 clock-names = "ipg";
146 interrupts = <14>;
147 status = "disabled";
148 };
149
150 kpp@43fa8000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0x43fa8000 0x4000>;
154 clocks = <&clks 102>;
155 clock-names = "";
156 interrupts = <24>;
157 status = "disabled";
158 };
159
160 iomuxc@43fac000{
161 compatible = "fsl,imx25-iomuxc";
162 reg = <0x43fac000 0x4000>;
163 };
164
165 audmux@43fb0000 {
166 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
167 reg = <0x43fb0000 0x4000>;
168 status = "disabled";
169 };
170 };
171
172 spba@50000000 {
173 compatible = "fsl,spba-bus", "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0x50000000 0x40000>;
177 ranges;
178
179 spi3: cspi@50004000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
183 reg = <0x50004000 0x4000>;
184 interrupts = <0>;
185 clocks = <&clks 80>;
186 clock-names = "ipg";
187 status = "disabled";
188 };
189
190 uart4: serial@50008000 {
191 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
192 reg = <0x50008000 0x4000>;
193 interrupts = <5>;
194 clocks = <&clks 123>, <&clks 57>;
195 clock-names = "ipg", "per";
196 status = "disabled";
197 };
198
199 uart3: serial@5000c000 {
200 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
201 reg = <0x5000c000 0x4000>;
202 interrupts = <18>;
203 clocks = <&clks 122>, <&clks 57>;
204 clock-names = "ipg", "per";
205 status = "disabled";
206 };
207
208 spi2: cspi@50010000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
212 reg = <0x50010000 0x4000>;
213 clocks = <&clks 79>;
214 clock-names = "ipg";
215 interrupts = <13>;
216 status = "disabled";
217 };
218
219 ssi2: ssi@50014000 {
220 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
221 reg = <0x50014000 0x4000>;
222 interrupts = <11>;
223 status = "disabled";
224 };
225
226 esai@50018000 {
227 reg = <0x50018000 0x4000>;
228 interrupts = <7>;
229 };
230
231 uart5: serial@5002c000 {
232 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
233 reg = <0x5002c000 0x4000>;
234 interrupts = <40>;
235 clocks = <&clks 124>, <&clks 57>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 tsc: tsc@50030000 {
241 compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
242 reg = <0x50030000 0x4000>;
243 interrupts = <46>;
244 clocks = <&clks 119>;
245 clock-names = "ipg";
246 status = "disabled";
247 };
248
249 ssi1: ssi@50034000 {
250 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
251 reg = <0x50034000 0x4000>;
252 interrupts = <12>;
253 status = "disabled";
254 };
255
256 fec: ethernet@50038000 {
257 compatible = "fsl,imx25-fec";
258 reg = <0x50038000 0x4000>;
259 interrupts = <57>;
260 clocks = <&clks 88>, <&clks 65>;
261 clock-names = "ipg", "ahb";
262 status = "disabled";
263 };
264 };
265
266 aips@53f00000 { /* AIPS2 */
267 compatible = "fsl,aips-bus", "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
270 reg = <0x53f00000 0x100000>;
271 ranges;
272
273 clks: ccm@53f80000 {
274 compatible = "fsl,imx25-ccm";
275 reg = <0x53f80000 0x4000>;
276 interrupts = <31>;
277 #clock-cells = <1>;
278 };
279
280 gpt4: timer@53f84000 {
281 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
282 reg = <0x53f84000 0x4000>;
283 clocks = <&clks 9>, <&clks 45>;
284 clock-names = "ipg", "per";
285 interrupts = <1>;
286 };
287
288 gpt3: timer@53f88000 {
289 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
290 reg = <0x53f88000 0x4000>;
291 clocks = <&clks 9>, <&clks 47>;
292 clock-names = "ipg", "per";
293 interrupts = <29>;
294 };
295
296 gpt2: timer@53f8c000 {
297 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
298 reg = <0x53f8c000 0x4000>;
299 clocks = <&clks 9>, <&clks 47>;
300 clock-names = "ipg", "per";
301 interrupts = <53>;
302 };
303
304 gpt1: timer@53f90000 {
305 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
306 reg = <0x53f90000 0x4000>;
307 clocks = <&clks 9>, <&clks 47>;
308 clock-names = "ipg", "per";
309 interrupts = <54>;
310 };
311
312 epit1: timer@53f94000 {
313 compatible = "fsl,imx25-epit";
314 reg = <0x53f94000 0x4000>;
315 interrupts = <28>;
316 };
317
318 epit2: timer@53f98000 {
319 compatible = "fsl,imx25-epit";
320 reg = <0x53f98000 0x4000>;
321 interrupts = <27>;
322 };
323
324 gpio4: gpio@53f9c000 {
325 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
326 reg = <0x53f9c000 0x4000>;
327 interrupts = <23>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 pwm2: pwm@53fa0000 {
335 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
336 #pwm-cells = <2>;
337 reg = <0x53fa0000 0x4000>;
338 clocks = <&clks 106>, <&clks 36>;
339 clock-names = "ipg", "per";
340 interrupts = <36>;
341 };
342
343 gpio3: gpio@53fa4000 {
344 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
345 reg = <0x53fa4000 0x4000>;
346 interrupts = <16>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
352
353 pwm3: pwm@53fa8000 {
354 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
355 #pwm-cells = <2>;
356 reg = <0x53fa8000 0x4000>;
357 clocks = <&clks 107>, <&clks 36>;
358 clock-names = "ipg", "per";
359 interrupts = <41>;
360 };
361
362 esdhc1: esdhc@53fb4000 {
363 compatible = "fsl,imx25-esdhc";
364 reg = <0x53fb4000 0x4000>;
365 interrupts = <9>;
366 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
367 clock-names = "ipg", "ahb", "per";
368 status = "disabled";
369 };
370
371 esdhc2: esdhc@53fb8000 {
372 compatible = "fsl,imx25-esdhc";
373 reg = <0x53fb8000 0x4000>;
374 interrupts = <8>;
375 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
376 clock-names = "ipg", "ahb", "per";
377 status = "disabled";
378 };
379
380 lcdc@53fbc000 {
381 reg = <0x53fbc000 0x4000>;
382 interrupts = <39>;
383 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
384 clock-names = "ipg", "ahb", "per";
385 status = "disabled";
386 };
387
388 slcdc@53fc0000 {
389 reg = <0x53fc0000 0x4000>;
390 interrupts = <38>;
391 status = "disabled";
392 };
393
394 pwm4: pwm@53fc8000 {
395 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
396 reg = <0x53fc8000 0x4000>;
397 clocks = <&clks 108>, <&clks 36>;
398 clock-names = "ipg", "per";
399 interrupts = <42>;
400 };
401
402 gpio1: gpio@53fcc000 {
403 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404 reg = <0x53fcc000 0x4000>;
405 interrupts = <52>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpio2: gpio@53fd0000 {
413 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
414 reg = <0x53fd0000 0x4000>;
415 interrupts = <51>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 };
421
422 sdma@53fd4000 {
423 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
424 reg = <0x53fd4000 0x4000>;
425 clocks = <&clks 112>, <&clks 68>;
426 clock-names = "ipg", "ahb";
427 interrupts = <34>;
428 };
429
430 wdog@53fdc000 {
431 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
432 reg = <0x53fdc000 0x4000>;
433 clocks = <&clks 126>;
434 clock-names = "";
435 interrupts = <55>;
436 };
437
438 pwm1: pwm@53fe0000 {
439 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
440 #pwm-cells = <2>;
441 reg = <0x53fe0000 0x4000>;
442 clocks = <&clks 105>, <&clks 36>;
443 clock-names = "ipg", "per";
444 interrupts = <26>;
445 };
446
447 usbphy1: usbphy@1 {
448 compatible = "nop-usbphy";
449 status = "disabled";
450 };
451
452 usbphy2: usbphy@2 {
453 compatible = "nop-usbphy";
454 status = "disabled";
455 };
456
457 usbotg: usb@53ff4000 {
458 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
459 reg = <0x53ff4000 0x0200>;
460 interrupts = <37>;
461 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
462 clock-names = "ipg", "ahb", "per";
463 fsl,usbmisc = <&usbmisc 0>;
464 status = "disabled";
465 };
466
467 usbhost1: usb@53ff4400 {
468 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
469 reg = <0x53ff4400 0x0200>;
470 interrupts = <35>;
471 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
472 clock-names = "ipg", "ahb", "per";
473 fsl,usbmisc = <&usbmisc 1>;
474 status = "disabled";
475 };
476
477 usbmisc: usbmisc@53ff4600 {
478 #index-cells = <1>;
479 compatible = "fsl,imx25-usbmisc";
480 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
481 clock-names = "ipg", "ahb", "per";
482 reg = <0x53ff4600 0x00f>;
483 status = "disabled";
484 };
485
486 dryice@53ffc000 {
487 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
488 reg = <0x53ffc000 0x4000>;
489 clocks = <&clks 81>;
490 clock-names = "ipg";
491 interrupts = <25>;
492 };
493 };
494
495 emi@80000000 {
496 compatible = "fsl,emi-bus", "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x80000000 0x3b002000>;
500 ranges;
501
502 nand@bb000000 {
503 #address-cells = <1>;
504 #size-cells = <1>;
505
506 compatible = "fsl,imx25-nand";
507 reg = <0xbb000000 0x2000>;
508 clocks = <&clks 50>;
509 clock-names = "";
510 interrupts = <33>;
511 status = "disabled";
512 };
513 };
514 };
515};
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
new file mode 100644
index 000000000000..c0327c054de2
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
3 * Copyright 2012 Armadeus Systems <support@armadeus.com>
4 *
5 * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
16/include/ "imx27.dtsi"
17
18/ {
19 model = "Armadeus Systems APF27 module";
20 compatible = "armadeus,imx27-apf27", "fsl,imx27";
21
22 memory {
23 reg = <0xa0000000 0x04000000>;
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 osc26m {
31 compatible = "fsl,imx-osc26m", "fixed-clock";
32 clock-frequency = <0>;
33 };
34 };
35
36 soc {
37 aipi@10000000 {
38 serial@1000a000 {
39 status = "okay";
40 };
41
42 ethernet@1002b000 {
43 status = "okay";
44 };
45 };
46
47 nand@d8000000 {
48 status = "okay";
49 nand-bus-width = <16>;
50 nand-ecc-mode = "hw";
51 nand-on-flash-bbt;
52
53 partition@0 {
54 label = "u-boot";
55 reg = <0x0 0x100000>;
56 };
57
58 partition@100000 {
59 label = "env";
60 reg = <0x100000 0x80000>;
61 };
62
63 partition@180000 {
64 label = "env2";
65 reg = <0x180000 0x80000>;
66 };
67
68 partition@200000 {
69 label = "firmware";
70 reg = <0x200000 0x80000>;
71 };
72
73 partition@280000 {
74 label = "dtb";
75 reg = <0x280000 0x80000>;
76 };
77
78 partition@300000 {
79 label = "kernel";
80 reg = <0x300000 0x500000>;
81 };
82
83 partition@800000 {
84 label = "rootfs";
85 reg = <0x800000 0xf800000>;
86 };
87 };
88 };
89};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 67d672792b0d..b8d3905915ac 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -58,7 +58,7 @@
58 reg = <0x10000000 0x10000000>; 58 reg = <0x10000000 0x10000000>;
59 ranges; 59 ranges;
60 60
61 wdog@10002000 { 61 wdog: wdog@10002000 {
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>; 63 reg = <0x10002000 0x4000>;
64 interrupts = <27>; 64 interrupts = <27>;
@@ -218,7 +218,8 @@
218 status = "disabled"; 218 status = "disabled";
219 }; 219 };
220 }; 220 };
221 nand@d8000000 { 221
222 nfc: nand@d8000000 {
222 #address-cells = <1>; 223 #address-cells = <1>;
223 #size-cells = <1>; 224 #size-cells = <1>;
224 225
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
new file mode 100644
index 000000000000..7eb075876c4c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -0,0 +1,85 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Armadeus Systems APF28 module";
17 compatible = "armadeus,imx28-apf28", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 status = "okay";
29
30 partition@0 {
31 label = "u-boot";
32 reg = <0x0 0x300000>;
33 };
34
35 partition@300000 {
36 label = "env";
37 reg = <0x300000 0x80000>;
38 };
39
40 partition@380000 {
41 label = "env2";
42 reg = <0x380000 0x80000>;
43 };
44
45 partition@400000 {
46 label = "dtb";
47 reg = <0x400000 0x80000>;
48 };
49
50 partition@480000 {
51 label = "splash";
52 reg = <0x480000 0x80000>;
53 };
54
55 partition@500000 {
56 label = "kernel";
57 reg = <0x500000 0x800000>;
58 };
59
60 partition@d00000 {
61 label = "rootfs";
62 reg = <0xd00000 0xf300000>;
63 };
64 };
65 };
66
67 apbx@80040000 {
68 duart: serial@80074000 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&duart_pins_a>;
71 status = "okay";
72 };
73 };
74 };
75
76 ahb@80080000 {
77 mac0: ethernet@800f0000 {
78 phy-mode = "rmii";
79 pinctrl-names = "default";
80 pinctrl-0 = <&mac0_pins_a>;
81 phy-reset-gpios = <&gpio4 13 0>;
82 status = "okay";
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
new file mode 100644
index 000000000000..6d8865bfb4b7
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -0,0 +1,154 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF28Dev is a docking board for the APF28 SOM */
13/include/ "imx28-apf28.dts"
14
15/ {
16 model = "Armadeus Systems APF28Dev docking/development board";
17 compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
18
19 apb@80000000 {
20 apbh@80000000 {
21 ssp0: ssp@80010000 {
22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_4bit_pins_a
25 &mmc0_cd_cfg &mmc0_sck_cfg>;
26 bus-width = <4>;
27 status = "okay";
28 };
29
30 ssp2: ssp@80014000 {
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi2_pins_a>;
34 status = "okay";
35 };
36
37 pinctrl@80018000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&hog_pins_apf28dev>;
40
41 hog_pins_apf28dev: hog@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */
45 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */
46 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */
47 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */
48 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */
49 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
50 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
51 >;
52 fsl,drive-strength = <0>;
53 fsl,voltage = <1>;
54 fsl,pull-up = <0>;
55 };
56
57 lcdif_pins_apf28dev: lcdif-apf28dev@0 {
58 reg = <0>;
59 fsl,pinmux-ids = <
60 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
61 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
62 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
63 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
64 >;
65 fsl,drive-strength = <0>;
66 fsl,voltage = <1>;
67 fsl,pull-up = <0>;
68 };
69 };
70
71 lcdif@80030000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&lcdif_16bit_pins_a
74 &lcdif_pins_apf28dev>;
75 status = "okay";
76 };
77 };
78
79 apbx@80040000 {
80 lradc@80050000 {
81 status = "okay";
82 };
83
84 i2c0: i2c@80058000 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&i2c0_pins_a>;
87 status = "okay";
88 };
89
90 pwm: pwm@80064000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
93 status = "okay";
94 };
95
96 usbphy0: usbphy@8007c000 {
97 status = "okay";
98 };
99
100 usbphy1: usbphy@8007e000 {
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 status = "okay";
110 };
111
112 usb1: usb@80090000 {
113 status = "okay";
114 };
115
116 mac1: ethernet@800f4000 {
117 phy-mode = "rmii";
118 pinctrl-names = "default";
119 pinctrl-0 = <&mac1_pins_a>;
120 phy-reset-gpios = <&gpio0 23 0>;
121 status = "okay";
122 };
123 };
124
125 regulators {
126 compatible = "simple-bus";
127
128 reg_usb0_vbus: usb0_vbus {
129 compatible = "regulator-fixed";
130 regulator-name = "usb0_vbus";
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio1 23 1>;
134 };
135 };
136
137 leds {
138 compatible = "gpio-leds";
139
140 user {
141 label = "Heartbeat";
142 gpios = <&gpio0 21 0>;
143 linux,default-trigger = "heartbeat";
144 };
145 };
146
147 backlight {
148 compatible = "pwm-backlight";
149
150 pwms = <&pwm 3 191000>;
151 brightness-levels = <0 4 8 16 32 64 128 255>;
152 default-brightness-level = <6>;
153 };
154};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index c03a577beca3..1594694532b9 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -22,6 +22,31 @@
22 22
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_cfa10036>;
28
29 hog_pins_cfa10036: hog-10036@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
33 >;
34 fsl,drive-strength = <0>;
35 fsl,voltage = <1>;
36 fsl,pull-up = <0>;
37 };
38
39 led_pins_cfa10036: leds-10036@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48 };
49
25 ssp0: ssp@80010000 { 50 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc"; 51 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default"; 52 pinctrl-names = "default";
@@ -33,16 +58,37 @@
33 }; 58 };
34 59
35 apbx@80040000 { 60 apbx@80040000 {
61 pwm: pwm@80064000 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pwm4_pins_a>;
64 status = "okay";
65 };
66
36 duart: serial@80074000 { 67 duart: serial@80074000 {
37 pinctrl-names = "default"; 68 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_b>; 69 pinctrl-0 = <&duart_pins_b>;
39 status = "okay"; 70 status = "okay";
40 }; 71 };
72
73 i2c0: i2c@80058000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c0_pins_b>;
76 status = "okay";
77
78 ssd1307: oled@3c {
79 compatible = "solomon,ssd1307fb-i2c";
80 reg = <0x3c>;
81 pwms = <&pwm 4 3000>;
82 reset-gpios = <&gpio2 7 0>;
83 };
84 };
41 }; 85 };
42 }; 86 };
43 87
44 leds { 88 leds {
45 compatible = "gpio-leds"; 89 compatible = "gpio-leds";
90 pinctrl-names = "default";
91 pinctrl-0 = <&led_pins_cfa10036>;
46 92
47 power { 93 power {
48 gpios = <&gpio3 4 1>; 94 gpios = <&gpio3 4 1>;
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 05c892e931e3..b222614ac9e0 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -22,6 +22,22 @@
22 apb@80000000 { 22 apb@80000000 {
23 apbh@80000000 { 23 apbh@80000000 {
24 pinctrl@80018000 { 24 pinctrl@80018000 {
25 pinctrl-names = "default", "default";
26 pinctrl-1 = <&hog_pins_cfa10049>;
27
28 hog_pins_cfa10049: hog-10049@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
32 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
33 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
34 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
25 spi3_pins_cfa10049: spi3-cfa10049@0 { 41 spi3_pins_cfa10049: spi3-cfa10049@0 {
26 reg = <0>; 42 reg = <0>;
27 fsl,pinmux-ids = < 43 fsl,pinmux-ids = <
@@ -29,6 +45,7 @@
29 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ 45 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
30 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ 46 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
31 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ 47 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
48 0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
32 >; 49 >;
33 fsl,drive-strength = <1>; 50 fsl,drive-strength = <1>;
34 fsl,voltage = <1>; 51 fsl,voltage = <1>;
@@ -60,6 +77,11 @@
60 spi-max-frequency = <100000>; 77 spi-max-frequency = <100000>;
61 }; 78 };
62 79
80 dac0: dh2228@2 {
81 compatible = "rohm,dh2228fv";
82 reg = <2>;
83 spi-max-frequency = <100000>;
84 };
63 }; 85 };
64 }; 86 };
65 87
@@ -96,4 +118,15 @@
96 gpio = <&gpio0 7 1>; 118 gpio = <&gpio0 7 1>;
97 }; 119 };
98 }; 120 };
121
122 ahb@80080000 {
123 mac0: ethernet@800f0000 {
124 phy-mode = "rmii";
125 pinctrl-names = "default";
126 pinctrl-0 = <&mac0_pins_a>;
127 phy-reset-gpios = <&gpio2 21 0>;
128 phy-reset-duration = <100>;
129 status = "okay";
130 };
131 };
99}; 132};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index a0ad71ca3a44..2da316e04409 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -76,7 +76,6 @@
76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ 76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
79 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
80 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ 79 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
81 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ 80 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
82 >; 81 >;
@@ -85,6 +84,16 @@
85 fsl,pull-up = <0>; 84 fsl,pull-up = <0>;
86 }; 85 };
87 86
87 led_pin_gpio3_5: led_gpio3_5@0 {
88 reg = <0>;
89 fsl,pinmux-ids = <
90 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
91 >;
92 fsl,drive-strength = <0>;
93 fsl,voltage = <1>;
94 fsl,pull-up = <0>;
95 };
96
88 gpmi_pins_evk: gpmi-nand-evk@0 { 97 gpmi_pins_evk: gpmi-nand-evk@0 {
89 reg = <0>; 98 reg = <0>;
90 fsl,pinmux-ids = < 99 fsl,pinmux-ids = <
@@ -288,6 +297,8 @@
288 297
289 leds { 298 leds {
290 compatible = "gpio-leds"; 299 compatible = "gpio-leds";
300 pinctrl-names = "default";
301 pinctrl-0 = <&led_pin_gpio3_5>;
291 302
292 user { 303 user {
293 label = "Heartbeat"; 304 label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
new file mode 100644
index 000000000000..e6cde8aa7fff
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "SchulerControl GmbH, SC SPS 1";
17 compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_a>;
28
29 hog_pins_a: hog-gpios@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
33 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
34 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
41 };
42
43 ssp0: ssp@80010000 {
44 compatible = "fsl,imx28-mmc";
45 pinctrl-names = "default";
46 pinctrl-0 = <&mmc0_4bit_pins_a>;
47 bus-width = <4>;
48 status = "okay";
49 };
50
51 ssp2: ssp@80014000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "fsl,imx28-spi";
55 pinctrl-names = "default";
56 pinctrl-0 = <&spi2_pins_a>;
57 status = "okay";
58
59 flash: m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "everspin,mr25h256", "mr25h256";
63 spi-max-frequency = <40000000>;
64 reg = <0>;
65 };
66 };
67 };
68
69 apbx@80040000 {
70 i2c0: i2c@80058000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c0_pins_a>;
73 clock-frequency = <400000>;
74 status = "okay";
75
76 rtc: rtc@51 {
77 compatible = "nxp,pcf8563";
78 reg = <0x51>;
79 };
80
81 eeprom: eeprom@52 {
82 compatible = "atmel,24c64";
83 reg = <0x52>;
84 pagesize = <32>;
85 };
86 };
87
88 duart: serial@80074000 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&duart_pins_a>;
91 status = "okay";
92 };
93
94 usbphy0: usbphy@8007c000 {
95 status = "okay";
96 };
97
98 auart0: serial@8006a000 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&auart0_pins_a>;
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&usbphy0_pins_b>;
111 status = "okay";
112 };
113
114 mac0: ethernet@800f0000 {
115 phy-mode = "rmii";
116 pinctrl-names = "default";
117 pinctrl-0 = <&mac0_pins_a>;
118 status = "okay";
119 };
120
121 mac1: ethernet@800f4000 {
122 phy-mode = "rmii";
123 pinctrl-names = "default";
124 pinctrl-0 = <&mac1_pins_a>;
125 status = "okay";
126 };
127 };
128
129 regulators {
130 compatible = "simple-bus";
131
132 reg_usb0_vbus: usb0_vbus {
133 compatible = "regulator-fixed";
134 regulator-name = "usb0_vbus";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
137 gpio = <&gpio3 9 0>;
138 };
139 };
140
141 leds {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "gpio-leds";
145 status = "okay";
146
147 led@1 {
148 label = "sps1-1:yellow:user";
149 gpios = <&gpio0 6 0>;
150 linux,default-trigger = "heartbeat";
151 reg = <0>;
152 };
153
154 led@2 {
155 label = "sps1-2:red:user";
156 gpios = <&gpio0 3 0>;
157 linux,default-trigger = "heartbeat";
158 reg = <1>;
159 };
160
161 led@3 {
162 label = "sps1-3:red:user";
163 gpios = <&gpio0 0 0>;
164 default-trigger = "heartbeat";
165 reg = <2>;
166 };
167
168 };
169};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index b4587b27ae42..13b7053d799e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -492,6 +492,16 @@
492 fsl,pull-up = <0>; 492 fsl,pull-up = <0>;
493 }; 493 };
494 494
495 pwm3_pins_a: pwm3@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499 >;
500 fsl,drive-strength = <0>;
501 fsl,voltage = <1>;
502 fsl,pull-up = <0>;
503 };
504
495 pwm4_pins_a: pwm4@0 { 505 pwm4_pins_a: pwm4@0 {
496 reg = <0>; 506 reg = <0>;
497 fsl,pinmux-ids = < 507 fsl,pinmux-ids = <
@@ -535,6 +545,31 @@
535 fsl,pull-up = <0>; 545 fsl,pull-up = <0>;
536 }; 546 };
537 547
548 lcdif_16bit_pins_a: lcdif-16bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
552 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
553 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
554 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
555 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
556 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
557 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
558 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
559 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
560 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
561 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
562 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
563 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
564 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
565 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
566 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
567 >;
568 fsl,drive-strength = <0>;
569 fsl,voltage = <1>;
570 fsl,pull-up = <0>;
571 };
572
538 can0_pins_a: can0@0 { 573 can0_pins_a: can0@0 {
539 reg = <0>; 574 reg = <0>;
540 fsl,pinmux-ids = < 575 fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 2781e47cff0d..1f5d45eff45e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -83,7 +83,7 @@
83 reg = <0x70000000 0x40000>; 83 reg = <0x70000000 0x40000>;
84 ranges; 84 ranges;
85 85
86 esdhc@70004000 { /* ESDHC1 */ 86 esdhc1: esdhc@70004000 {
87 compatible = "fsl,imx51-esdhc"; 87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>; 88 reg = <0x70004000 0x4000>;
89 interrupts = <1>; 89 interrupts = <1>;
@@ -92,12 +92,13 @@
92 status = "disabled"; 92 status = "disabled";
93 }; 93 };
94 94
95 esdhc@70008000 { /* ESDHC2 */ 95 esdhc2: esdhc@70008000 {
96 compatible = "fsl,imx51-esdhc"; 96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>; 97 reg = <0x70008000 0x4000>;
98 interrupts = <2>; 98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per"; 100 clock-names = "ipg", "ahb", "per";
101 bus-width = <4>;
101 status = "disabled"; 102 status = "disabled";
102 }; 103 };
103 104
@@ -110,7 +111,7 @@
110 status = "disabled"; 111 status = "disabled";
111 }; 112 };
112 113
113 ecspi@70010000 { /* ECSPI1 */ 114 ecspi1: ecspi@70010000 {
114 #address-cells = <1>; 115 #address-cells = <1>;
115 #size-cells = <0>; 116 #size-cells = <0>;
116 compatible = "fsl,imx51-ecspi"; 117 compatible = "fsl,imx51-ecspi";
@@ -131,47 +132,49 @@
131 status = "disabled"; 132 status = "disabled";
132 }; 133 };
133 134
134 esdhc@70020000 { /* ESDHC3 */ 135 esdhc3: esdhc@70020000 {
135 compatible = "fsl,imx51-esdhc"; 136 compatible = "fsl,imx51-esdhc";
136 reg = <0x70020000 0x4000>; 137 reg = <0x70020000 0x4000>;
137 interrupts = <3>; 138 interrupts = <3>;
138 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
139 clock-names = "ipg", "ahb", "per"; 140 clock-names = "ipg", "ahb", "per";
141 bus-width = <4>;
140 status = "disabled"; 142 status = "disabled";
141 }; 143 };
142 144
143 esdhc@70024000 { /* ESDHC4 */ 145 esdhc4: esdhc@70024000 {
144 compatible = "fsl,imx51-esdhc"; 146 compatible = "fsl,imx51-esdhc";
145 reg = <0x70024000 0x4000>; 147 reg = <0x70024000 0x4000>;
146 interrupts = <4>; 148 interrupts = <4>;
147 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
148 clock-names = "ipg", "ahb", "per"; 150 clock-names = "ipg", "ahb", "per";
151 bus-width = <4>;
149 status = "disabled"; 152 status = "disabled";
150 }; 153 };
151 }; 154 };
152 155
153 usb@73f80000 { 156 usbotg: usb@73f80000 {
154 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
155 reg = <0x73f80000 0x0200>; 158 reg = <0x73f80000 0x0200>;
156 interrupts = <18>; 159 interrupts = <18>;
157 status = "disabled"; 160 status = "disabled";
158 }; 161 };
159 162
160 usb@73f80200 { 163 usbh1: usb@73f80200 {
161 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
162 reg = <0x73f80200 0x0200>; 165 reg = <0x73f80200 0x0200>;
163 interrupts = <14>; 166 interrupts = <14>;
164 status = "disabled"; 167 status = "disabled";
165 }; 168 };
166 169
167 usb@73f80400 { 170 usbh2: usb@73f80400 {
168 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
169 reg = <0x73f80400 0x0200>; 172 reg = <0x73f80400 0x0200>;
170 interrupts = <16>; 173 interrupts = <16>;
171 status = "disabled"; 174 status = "disabled";
172 }; 175 };
173 176
174 usb@73f80600 { 177 usbh3: usb@73f80600 {
175 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
176 reg = <0x73f80600 0x0200>; 179 reg = <0x73f80600 0x0200>;
177 interrupts = <17>; 180 interrupts = <17>;
@@ -218,14 +221,14 @@
218 #interrupt-cells = <2>; 221 #interrupt-cells = <2>;
219 }; 222 };
220 223
221 wdog@73f98000 { /* WDOG1 */ 224 wdog1: wdog@73f98000 {
222 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
223 reg = <0x73f98000 0x4000>; 226 reg = <0x73f98000 0x4000>;
224 interrupts = <58>; 227 interrupts = <58>;
225 clocks = <&clks 0>; 228 clocks = <&clks 0>;
226 }; 229 };
227 230
228 wdog@73f9c000 { /* WDOG2 */ 231 wdog2: wdog@73f9c000 {
229 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 232 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
230 reg = <0x73f9c000 0x4000>; 233 reg = <0x73f9c000 0x4000>;
231 interrupts = <59>; 234 interrupts = <59>;
@@ -233,7 +236,7 @@
233 status = "disabled"; 236 status = "disabled";
234 }; 237 };
235 238
236 iomuxc@73fa8000 { 239 iomuxc: iomuxc@73fa8000 {
237 compatible = "fsl,imx51-iomuxc"; 240 compatible = "fsl,imx51-iomuxc";
238 reg = <0x73fa8000 0x4000>; 241 reg = <0x73fa8000 0x4000>;
239 242
@@ -460,7 +463,7 @@
460 reg = <0x80000000 0x10000000>; 463 reg = <0x80000000 0x10000000>;
461 ranges; 464 ranges;
462 465
463 ecspi@83fac000 { /* ECSPI2 */ 466 ecspi2: ecspi@83fac000 {
464 #address-cells = <1>; 467 #address-cells = <1>;
465 #size-cells = <0>; 468 #size-cells = <0>;
466 compatible = "fsl,imx51-ecspi"; 469 compatible = "fsl,imx51-ecspi";
@@ -471,7 +474,7 @@
471 status = "disabled"; 474 status = "disabled";
472 }; 475 };
473 476
474 sdma@83fb0000 { 477 sdma: sdma@83fb0000 {
475 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
476 reg = <0x83fb0000 0x4000>; 479 reg = <0x83fb0000 0x4000>;
477 interrupts = <6>; 480 interrupts = <6>;
@@ -480,7 +483,7 @@
480 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
481 }; 484 };
482 485
483 cspi@83fc0000 { 486 cspi: cspi@83fc0000 {
484 #address-cells = <1>; 487 #address-cells = <1>;
485 #size-cells = <0>; 488 #size-cells = <0>;
486 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
@@ -491,7 +494,7 @@
491 status = "disabled"; 494 status = "disabled";
492 }; 495 };
493 496
494 i2c@83fc4000 { /* I2C2 */ 497 i2c2: i2c@83fc4000 {
495 #address-cells = <1>; 498 #address-cells = <1>;
496 #size-cells = <0>; 499 #size-cells = <0>;
497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
@@ -501,7 +504,7 @@
501 status = "disabled"; 504 status = "disabled";
502 }; 505 };
503 506
504 i2c@83fc8000 { /* I2C1 */ 507 i2c1: i2c@83fc8000 {
505 #address-cells = <1>; 508 #address-cells = <1>;
506 #size-cells = <0>; 509 #size-cells = <0>;
507 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 510 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
@@ -521,13 +524,13 @@
521 status = "disabled"; 524 status = "disabled";
522 }; 525 };
523 526
524 audmux@83fd0000 { 527 audmux: audmux@83fd0000 {
525 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 528 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
526 reg = <0x83fd0000 0x4000>; 529 reg = <0x83fd0000 0x4000>;
527 status = "disabled"; 530 status = "disabled";
528 }; 531 };
529 532
530 nand@83fdb000 { 533 nfc: nand@83fdb000 {
531 compatible = "fsl,imx51-nand"; 534 compatible = "fsl,imx51-nand";
532 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 535 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
533 interrupts = <8>; 536 interrupts = <8>;
@@ -545,7 +548,7 @@
545 status = "disabled"; 548 status = "disabled";
546 }; 549 };
547 550
548 ethernet@83fec000 { 551 fec: ethernet@83fec000 {
549 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 552 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
550 reg = <0x83fec000 0x4000>; 553 reg = <0x83fec000 0x4000>;
551 interrupts = <87>; 554 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 08948af86d1a..b0075537195b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -60,10 +60,17 @@
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ 62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64 >;
65 };
66
67 led_pin_gpio7_7: led_gpio7_7@0 {
68 fsl,pins = <
63 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ 69 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
64 >; 70 >;
65 }; 71 };
66 }; 72 };
73
67 }; 74 };
68 75
69 uart1: serial@53fbc000 { 76 uart1: serial@53fbc000 {
@@ -100,76 +107,93 @@
100 pmic: dialog@48 { 107 pmic: dialog@48 {
101 compatible = "dlg,da9053-aa", "dlg,da9052"; 108 compatible = "dlg,da9053-aa", "dlg,da9052";
102 reg = <0x48>; 109 reg = <0x48>;
110 interrupt-parent = <&gpio7>;
111 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
103 112
104 regulators { 113 regulators {
105 buck0 { 114 buck1_reg: buck1 {
106 regulator-min-microvolt = <500000>; 115 regulator-min-microvolt = <500000>;
107 regulator-max-microvolt = <2075000>; 116 regulator-max-microvolt = <2075000>;
117 regulator-always-on;
108 }; 118 };
109 119
110 buck1 { 120 buck2_reg: buck2 {
111 regulator-min-microvolt = <500000>; 121 regulator-min-microvolt = <500000>;
112 regulator-max-microvolt = <2075000>; 122 regulator-max-microvolt = <2075000>;
123 regulator-always-on;
113 }; 124 };
114 125
115 buck2 { 126 buck3_reg: buck3 {
116 regulator-min-microvolt = <925000>; 127 regulator-min-microvolt = <925000>;
117 regulator-max-microvolt = <2500000>; 128 regulator-max-microvolt = <2500000>;
129 regulator-always-on;
118 }; 130 };
119 131
120 buck3 { 132 buck4_reg: buck4 {
121 regulator-min-microvolt = <925000>; 133 regulator-min-microvolt = <925000>;
122 regulator-max-microvolt = <2500000>; 134 regulator-max-microvolt = <2500000>;
135 regulator-always-on;
123 }; 136 };
124 137
125 ldo4 { 138 ldo1_reg: ldo1 {
126 regulator-min-microvolt = <600000>; 139 regulator-min-microvolt = <600000>;
127 regulator-max-microvolt = <1800000>; 140 regulator-max-microvolt = <1800000>;
141 regulator-boot-on;
142 regulator-always-on;
128 }; 143 };
129 144
130 ldo5 { 145 ldo2_reg: ldo2 {
146 regulator-min-microvolt = <600000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-always-on;
149 };
150
151 ldo3_reg: ldo3 {
131 regulator-min-microvolt = <600000>; 152 regulator-min-microvolt = <600000>;
132 regulator-max-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>;
154 regulator-always-on;
133 }; 155 };
134 156
135 ldo6 { 157 ldo4_reg: ldo4 {
136 regulator-min-microvolt = <1725000>; 158 regulator-min-microvolt = <1725000>;
137 regulator-max-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
138 }; 161 };
139 162
140 ldo7 { 163 ldo5_reg: ldo5 {
141 regulator-min-microvolt = <1725000>; 164 regulator-min-microvolt = <1725000>;
142 regulator-max-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
143 }; 167 };
144 168
145 ldo8 { 169 ldo6_reg: ldo6 {
146 regulator-min-microvolt = <1200000>; 170 regulator-min-microvolt = <1200000>;
147 regulator-max-microvolt = <3600000>; 171 regulator-max-microvolt = <3600000>;
172 regulator-always-on;
148 }; 173 };
149 174
150 ldo9 { 175 ldo7_reg: ldo7 {
151 regulator-min-microvolt = <1200000>; 176 regulator-min-microvolt = <1200000>;
152 regulator-max-microvolt = <3600000>; 177 regulator-max-microvolt = <3600000>;
178 regulator-always-on;
153 }; 179 };
154 180
155 ldo10 { 181 ldo8_reg: ldo8 {
156 regulator-min-microvolt = <1200000>; 182 regulator-min-microvolt = <1200000>;
157 regulator-max-microvolt = <3600000>; 183 regulator-max-microvolt = <3600000>;
184 regulator-always-on;
158 }; 185 };
159 186
160 ldo11 { 187 ldo9_reg: ldo9 {
161 regulator-min-microvolt = <1200000>; 188 regulator-min-microvolt = <1200000>;
162 regulator-max-microvolt = <3600000>; 189 regulator-max-microvolt = <3600000>;
190 regulator-always-on;
163 }; 191 };
164 192
165 ldo12 { 193 ldo10_reg: ldo10 {
166 regulator-min-microvolt = <1250000>; 194 regulator-min-microvolt = <1250000>;
167 regulator-max-microvolt = <3650000>; 195 regulator-max-microvolt = <3650000>;
168 }; 196 regulator-always-on;
169
170 ldo13 {
171 regulator-min-microvolt = <1200000>;
172 regulator-max-microvolt = <3600000>;
173 }; 197 };
174 }; 198 };
175 }; 199 };
@@ -216,6 +240,8 @@
216 240
217 leds { 241 leds {
218 compatible = "gpio-leds"; 242 compatible = "gpio-leds";
243 pinctrl-names = "default";
244 pinctrl-0 = <&led_pin_gpio7_7>;
219 245
220 user { 246 user {
221 label = "Heartbeat"; 247 label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index da9a047ce4cf..552aed4ff982 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -88,21 +88,23 @@
88 reg = <0x50000000 0x40000>; 88 reg = <0x50000000 0x40000>;
89 ranges; 89 ranges;
90 90
91 esdhc@50004000 { /* ESDHC1 */ 91 esdhc1: esdhc@50004000 {
92 compatible = "fsl,imx53-esdhc"; 92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>; 93 reg = <0x50004000 0x4000>;
94 interrupts = <1>; 94 interrupts = <1>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>; 95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per"; 96 clock-names = "ipg", "ahb", "per";
97 bus-width = <4>;
97 status = "disabled"; 98 status = "disabled";
98 }; 99 };
99 100
100 esdhc@50008000 { /* ESDHC2 */ 101 esdhc2: esdhc@50008000 {
101 compatible = "fsl,imx53-esdhc"; 102 compatible = "fsl,imx53-esdhc";
102 reg = <0x50008000 0x4000>; 103 reg = <0x50008000 0x4000>;
103 interrupts = <2>; 104 interrupts = <2>;
104 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
105 clock-names = "ipg", "ahb", "per"; 106 clock-names = "ipg", "ahb", "per";
107 bus-width = <4>;
106 status = "disabled"; 108 status = "disabled";
107 }; 109 };
108 110
@@ -115,7 +117,7 @@
115 status = "disabled"; 117 status = "disabled";
116 }; 118 };
117 119
118 ecspi@50010000 { /* ECSPI1 */ 120 ecspi1: ecspi@50010000 {
119 #address-cells = <1>; 121 #address-cells = <1>;
120 #size-cells = <0>; 122 #size-cells = <0>;
121 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -136,47 +138,49 @@
136 status = "disabled"; 138 status = "disabled";
137 }; 139 };
138 140
139 esdhc@50020000 { /* ESDHC3 */ 141 esdhc3: esdhc@50020000 {
140 compatible = "fsl,imx53-esdhc"; 142 compatible = "fsl,imx53-esdhc";
141 reg = <0x50020000 0x4000>; 143 reg = <0x50020000 0x4000>;
142 interrupts = <3>; 144 interrupts = <3>;
143 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
144 clock-names = "ipg", "ahb", "per"; 146 clock-names = "ipg", "ahb", "per";
147 bus-width = <4>;
145 status = "disabled"; 148 status = "disabled";
146 }; 149 };
147 150
148 esdhc@50024000 { /* ESDHC4 */ 151 esdhc4: esdhc@50024000 {
149 compatible = "fsl,imx53-esdhc"; 152 compatible = "fsl,imx53-esdhc";
150 reg = <0x50024000 0x4000>; 153 reg = <0x50024000 0x4000>;
151 interrupts = <4>; 154 interrupts = <4>;
152 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
153 clock-names = "ipg", "ahb", "per"; 156 clock-names = "ipg", "ahb", "per";
157 bus-width = <4>;
154 status = "disabled"; 158 status = "disabled";
155 }; 159 };
156 }; 160 };
157 161
158 usb@53f80000 { 162 usbotg: usb@53f80000 {
159 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
160 reg = <0x53f80000 0x0200>; 164 reg = <0x53f80000 0x0200>;
161 interrupts = <18>; 165 interrupts = <18>;
162 status = "disabled"; 166 status = "disabled";
163 }; 167 };
164 168
165 usb@53f80200 { 169 usbh1: usb@53f80200 {
166 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
167 reg = <0x53f80200 0x0200>; 171 reg = <0x53f80200 0x0200>;
168 interrupts = <14>; 172 interrupts = <14>;
169 status = "disabled"; 173 status = "disabled";
170 }; 174 };
171 175
172 usb@53f80400 { 176 usbh2: usb@53f80400 {
173 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
174 reg = <0x53f80400 0x0200>; 178 reg = <0x53f80400 0x0200>;
175 interrupts = <16>; 179 interrupts = <16>;
176 status = "disabled"; 180 status = "disabled";
177 }; 181 };
178 182
179 usb@53f80600 { 183 usbh3: usb@53f80600 {
180 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
181 reg = <0x53f80600 0x0200>; 185 reg = <0x53f80600 0x0200>;
182 interrupts = <17>; 186 interrupts = <17>;
@@ -223,14 +227,14 @@
223 #interrupt-cells = <2>; 227 #interrupt-cells = <2>;
224 }; 228 };
225 229
226 wdog@53f98000 { /* WDOG1 */ 230 wdog1: wdog@53f98000 {
227 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
228 reg = <0x53f98000 0x4000>; 232 reg = <0x53f98000 0x4000>;
229 interrupts = <58>; 233 interrupts = <58>;
230 clocks = <&clks 0>; 234 clocks = <&clks 0>;
231 }; 235 };
232 236
233 wdog@53f9c000 { /* WDOG2 */ 237 wdog2: wdog@53f9c000 {
234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
235 reg = <0x53f9c000 0x4000>; 239 reg = <0x53f9c000 0x4000>;
236 interrupts = <59>; 240 interrupts = <59>;
@@ -238,7 +242,7 @@
238 status = "disabled"; 242 status = "disabled";
239 }; 243 };
240 244
241 iomuxc@53fa8000 { 245 iomuxc: iomuxc@53fa8000 {
242 compatible = "fsl,imx53-iomuxc"; 246 compatible = "fsl,imx53-iomuxc";
243 reg = <0x53fa8000 0x4000>; 247 reg = <0x53fa8000 0x4000>;
244 248
@@ -338,6 +342,24 @@
338 }; 342 };
339 }; 343 };
340 344
345 can1 {
346 pinctrl_can1_1: can1grp-1 {
347 fsl,pins = <
348 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
349 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
350 >;
351 };
352 };
353
354 can2 {
355 pinctrl_can2_1: can2grp-1 {
356 fsl,pins = <
357 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
358 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
359 >;
360 };
361 };
362
341 i2c1 { 363 i2c1 {
342 pinctrl_i2c1_1: i2c1grp-1 { 364 pinctrl_i2c1_1: i2c1grp-1 {
343 fsl,pins = < 365 fsl,pins = <
@@ -356,6 +378,15 @@
356 }; 378 };
357 }; 379 };
358 380
381 i2c3 {
382 pinctrl_i2c3_1: i2c3grp-1 {
383 fsl,pins = <
384 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
385 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
386 >;
387 };
388 };
389
359 uart1 { 390 uart1 {
360 pinctrl_uart1_1: uart1grp-1 { 391 pinctrl_uart1_1: uart1grp-1 {
361 fsl,pins = < 392 fsl,pins = <
@@ -391,6 +422,25 @@
391 >; 422 >;
392 }; 423 };
393 }; 424 };
425
426 uart4 {
427 pinctrl_uart4_1: uart4grp-1 {
428 fsl,pins = <
429 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
430 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
431 >;
432 };
433 };
434
435 uart5 {
436 pinctrl_uart5_1: uart5grp-1 {
437 fsl,pins = <
438 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
439 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
440 >;
441 };
442 };
443
394 }; 444 };
395 445
396 pwm1: pwm@53fb4000 { 446 pwm1: pwm@53fb4000 {
@@ -484,7 +534,7 @@
484 #interrupt-cells = <2>; 534 #interrupt-cells = <2>;
485 }; 535 };
486 536
487 i2c@53fec000 { /* I2C3 */ 537 i2c3: i2c@53fec000 {
488 #address-cells = <1>; 538 #address-cells = <1>;
489 #size-cells = <0>; 539 #size-cells = <0>;
490 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 540 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
@@ -520,7 +570,7 @@
520 status = "disabled"; 570 status = "disabled";
521 }; 571 };
522 572
523 ecspi@63fac000 { /* ECSPI2 */ 573 ecspi2: ecspi@63fac000 {
524 #address-cells = <1>; 574 #address-cells = <1>;
525 #size-cells = <0>; 575 #size-cells = <0>;
526 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 576 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -531,7 +581,7 @@
531 status = "disabled"; 581 status = "disabled";
532 }; 582 };
533 583
534 sdma@63fb0000 { 584 sdma: sdma@63fb0000 {
535 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 585 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
536 reg = <0x63fb0000 0x4000>; 586 reg = <0x63fb0000 0x4000>;
537 interrupts = <6>; 587 interrupts = <6>;
@@ -540,7 +590,7 @@
540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
541 }; 591 };
542 592
543 cspi@63fc0000 { 593 cspi: cspi@63fc0000 {
544 #address-cells = <1>; 594 #address-cells = <1>;
545 #size-cells = <0>; 595 #size-cells = <0>;
546 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 596 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
@@ -551,7 +601,7 @@
551 status = "disabled"; 601 status = "disabled";
552 }; 602 };
553 603
554 i2c@63fc4000 { /* I2C2 */ 604 i2c2: i2c@63fc4000 {
555 #address-cells = <1>; 605 #address-cells = <1>;
556 #size-cells = <0>; 606 #size-cells = <0>;
557 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 607 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
@@ -561,7 +611,7 @@
561 status = "disabled"; 611 status = "disabled";
562 }; 612 };
563 613
564 i2c@63fc8000 { /* I2C1 */ 614 i2c1: i2c@63fc8000 {
565 #address-cells = <1>; 615 #address-cells = <1>;
566 #size-cells = <0>; 616 #size-cells = <0>;
567 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 617 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
@@ -581,13 +631,13 @@
581 status = "disabled"; 631 status = "disabled";
582 }; 632 };
583 633
584 audmux@63fd0000 { 634 audmux: audmux@63fd0000 {
585 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 635 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
586 reg = <0x63fd0000 0x4000>; 636 reg = <0x63fd0000 0x4000>;
587 status = "disabled"; 637 status = "disabled";
588 }; 638 };
589 639
590 nand@63fdb000 { 640 nfc: nand@63fdb000 {
591 compatible = "fsl,imx53-nand"; 641 compatible = "fsl,imx53-nand";
592 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 642 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
593 interrupts = <8>; 643 interrupts = <8>;
@@ -605,7 +655,7 @@
605 status = "disabled"; 655 status = "disabled";
606 }; 656 };
607 657
608 ethernet@63fec000 { 658 fec: ethernet@63fec000 {
609 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 659 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
610 reg = <0x63fec000 0x4000>; 660 reg = <0x63fec000 0x4000>;
611 interrupts = <87>; 661 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000000..826e4ad1477e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,64 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x80000000>;
22 };
23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 iomuxc@020e0000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_hog>;
29
30 hog {
31 pinctrl_hog: hoggrp {
32 fsl,pins = <
33 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35 >;
36 };
37 };
38 };
39 };
40
41 aips-bus@02100000 { /* AIPS2 */
42 uart4: serial@021f0000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart4_1>;
45 status = "okay";
46 };
47
48 ethernet@02188000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_enet_2>;
51 phy-mode = "rgmii";
52 status = "okay";
53 };
54
55 usdhc@02198000 { /* uSDHC3 */
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usdhc3_1>;
58 cd-gpios = <&gpio6 15 0>;
59 wp-gpios = <&gpio1 13 0>;
60 status = "okay";
61 };
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index e596c28c214d..a42402562b7b 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -38,6 +38,8 @@
38 hog { 38 hog {
39 pinctrl_hog: hoggrp { 39 pinctrl_hog: hoggrp {
40 fsl,pins = < 40 fsl,pins = <
41 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
41 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ 43 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
42 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ 44 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
43 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ 45 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
@@ -73,4 +75,20 @@
73 }; 75 };
74 }; 76 };
75 }; 77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 volume-up {
83 label = "Volume Up";
84 gpios = <&gpio1 4 0>;
85 linux,code = <115>; /* KEY_VOLUMEUP */
86 };
87
88 volume-down {
89 label = "Volume Down";
90 gpios = <&gpio1 5 0>;
91 linux,code = <114>; /* KEY_VOLUMEDOWN */
92 };
93 };
76}; 94};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index cce1d874c7a5..d6265ca97119 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -36,6 +36,14 @@
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <0>; 37 reg = <0>;
38 next-level-cache = <&L2>; 38 next-level-cache = <&L2>;
39 operating-points = <
40 /* kHz uV */
41 792000 1100000
42 396000 950000
43 198000 850000
44 >;
45 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>;
39 }; 47 };
40 48
41 cpu@1 { 49 cpu@1 {
@@ -100,7 +108,7 @@
100 clocks = <&clks 106>; 108 clocks = <&clks 106>;
101 }; 109 };
102 110
103 gpmi-nand@00112000 { 111 nfc: gpmi-nand@00112000 {
104 compatible = "fsl,imx6q-gpmi-nand"; 112 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>; 113 #address-cells = <1>;
106 #size-cells = <1>; 114 #size-cells = <1>;
@@ -144,12 +152,12 @@
144 reg = <0x02000000 0x40000>; 152 reg = <0x02000000 0x40000>;
145 ranges; 153 ranges;
146 154
147 spdif@02004000 { 155 spdif: spdif@02004000 {
148 reg = <0x02004000 0x4000>; 156 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>; 157 interrupts = <0 52 0x04>;
150 }; 158 };
151 159
152 ecspi@02008000 { /* eCSPI1 */ 160 ecspi1: ecspi@02008000 {
153 #address-cells = <1>; 161 #address-cells = <1>;
154 #size-cells = <0>; 162 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -160,7 +168,7 @@
160 status = "disabled"; 168 status = "disabled";
161 }; 169 };
162 170
163 ecspi@0200c000 { /* eCSPI2 */ 171 ecspi2: ecspi@0200c000 {
164 #address-cells = <1>; 172 #address-cells = <1>;
165 #size-cells = <0>; 173 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -171,7 +179,7 @@
171 status = "disabled"; 179 status = "disabled";
172 }; 180 };
173 181
174 ecspi@02010000 { /* eCSPI3 */ 182 ecspi3: ecspi@02010000 {
175 #address-cells = <1>; 183 #address-cells = <1>;
176 #size-cells = <0>; 184 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -182,7 +190,7 @@
182 status = "disabled"; 190 status = "disabled";
183 }; 191 };
184 192
185 ecspi@02014000 { /* eCSPI4 */ 193 ecspi4: ecspi@02014000 {
186 #address-cells = <1>; 194 #address-cells = <1>;
187 #size-cells = <0>; 195 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -193,7 +201,7 @@
193 status = "disabled"; 201 status = "disabled";
194 }; 202 };
195 203
196 ecspi@02018000 { /* eCSPI5 */ 204 ecspi5: ecspi@02018000 {
197 #address-cells = <1>; 205 #address-cells = <1>;
198 #size-cells = <0>; 206 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -213,7 +221,7 @@
213 status = "disabled"; 221 status = "disabled";
214 }; 222 };
215 223
216 esai@02024000 { 224 esai: esai@02024000 {
217 reg = <0x02024000 0x4000>; 225 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>; 226 interrupts = <0 51 0x04>;
219 }; 227 };
@@ -248,7 +256,7 @@
248 status = "disabled"; 256 status = "disabled";
249 }; 257 };
250 258
251 asrc@02034000 { 259 asrc: asrc@02034000 {
252 reg = <0x02034000 0x4000>; 260 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>; 261 interrupts = <0 50 0x04>;
254 }; 262 };
@@ -258,7 +266,7 @@
258 }; 266 };
259 }; 267 };
260 268
261 vpu@02040000 { 269 vpu: vpu@02040000 {
262 reg = <0x02040000 0x3c000>; 270 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>; 271 interrupts = <0 3 0x04 0 12 0x04>;
264 }; 272 };
@@ -267,7 +275,7 @@
267 reg = <0x0207c000 0x4000>; 275 reg = <0x0207c000 0x4000>;
268 }; 276 };
269 277
270 pwm@02080000 { /* PWM1 */ 278 pwm1: pwm@02080000 {
271 #pwm-cells = <2>; 279 #pwm-cells = <2>;
272 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 280 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
273 reg = <0x02080000 0x4000>; 281 reg = <0x02080000 0x4000>;
@@ -276,7 +284,7 @@
276 clock-names = "ipg", "per"; 284 clock-names = "ipg", "per";
277 }; 285 };
278 286
279 pwm@02084000 { /* PWM2 */ 287 pwm2: pwm@02084000 {
280 #pwm-cells = <2>; 288 #pwm-cells = <2>;
281 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 289 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
282 reg = <0x02084000 0x4000>; 290 reg = <0x02084000 0x4000>;
@@ -285,7 +293,7 @@
285 clock-names = "ipg", "per"; 293 clock-names = "ipg", "per";
286 }; 294 };
287 295
288 pwm@02088000 { /* PWM3 */ 296 pwm3: pwm@02088000 {
289 #pwm-cells = <2>; 297 #pwm-cells = <2>;
290 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 298 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
291 reg = <0x02088000 0x4000>; 299 reg = <0x02088000 0x4000>;
@@ -294,7 +302,7 @@
294 clock-names = "ipg", "per"; 302 clock-names = "ipg", "per";
295 }; 303 };
296 304
297 pwm@0208c000 { /* PWM4 */ 305 pwm4: pwm@0208c000 {
298 #pwm-cells = <2>; 306 #pwm-cells = <2>;
299 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 307 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
300 reg = <0x0208c000 0x4000>; 308 reg = <0x0208c000 0x4000>;
@@ -303,17 +311,17 @@
303 clock-names = "ipg", "per"; 311 clock-names = "ipg", "per";
304 }; 312 };
305 313
306 flexcan@02090000 { /* CAN1 */ 314 can1: flexcan@02090000 {
307 reg = <0x02090000 0x4000>; 315 reg = <0x02090000 0x4000>;
308 interrupts = <0 110 0x04>; 316 interrupts = <0 110 0x04>;
309 }; 317 };
310 318
311 flexcan@02094000 { /* CAN2 */ 319 can2: flexcan@02094000 {
312 reg = <0x02094000 0x4000>; 320 reg = <0x02094000 0x4000>;
313 interrupts = <0 111 0x04>; 321 interrupts = <0 111 0x04>;
314 }; 322 };
315 323
316 gpt@02098000 { 324 gpt: gpt@02098000 {
317 compatible = "fsl,imx6q-gpt"; 325 compatible = "fsl,imx6q-gpt";
318 reg = <0x02098000 0x4000>; 326 reg = <0x02098000 0x4000>;
319 interrupts = <0 55 0x04>; 327 interrupts = <0 55 0x04>;
@@ -389,19 +397,19 @@
389 #interrupt-cells = <2>; 397 #interrupt-cells = <2>;
390 }; 398 };
391 399
392 kpp@020b8000 { 400 kpp: kpp@020b8000 {
393 reg = <0x020b8000 0x4000>; 401 reg = <0x020b8000 0x4000>;
394 interrupts = <0 82 0x04>; 402 interrupts = <0 82 0x04>;
395 }; 403 };
396 404
397 wdog@020bc000 { /* WDOG1 */ 405 wdog1: wdog@020bc000 {
398 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 406 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
399 reg = <0x020bc000 0x4000>; 407 reg = <0x020bc000 0x4000>;
400 interrupts = <0 80 0x04>; 408 interrupts = <0 80 0x04>;
401 clocks = <&clks 0>; 409 clocks = <&clks 0>;
402 }; 410 };
403 411
404 wdog@020c0000 { /* WDOG2 */ 412 wdog2: wdog@020c0000 {
405 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
406 reg = <0x020c0000 0x4000>; 414 reg = <0x020c0000 0x4000>;
407 interrupts = <0 81 0x04>; 415 interrupts = <0 81 0x04>;
@@ -463,7 +471,7 @@
463 anatop-max-voltage = <2750000>; 471 anatop-max-voltage = <2750000>;
464 }; 472 };
465 473
466 regulator-vddcore@140 { 474 reg_cpu: regulator-vddcore@140 {
467 compatible = "fsl,anatop-regulator"; 475 compatible = "fsl,anatop-regulator";
468 regulator-name = "cpu"; 476 regulator-name = "cpu";
469 regulator-min-microvolt = <725000>; 477 regulator-min-microvolt = <725000>;
@@ -521,27 +529,35 @@
521 }; 529 };
522 530
523 snvs@020cc000 { 531 snvs@020cc000 {
524 reg = <0x020cc000 0x4000>; 532 compatible = "fsl,sec-v4.0-mon", "simple-bus";
525 interrupts = <0 19 0x04 0 20 0x04>; 533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges = <0 0x020cc000 0x4000>;
536
537 snvs-rtc-lp@34 {
538 compatible = "fsl,sec-v4.0-mon-rtc-lp";
539 reg = <0x34 0x58>;
540 interrupts = <0 19 0x04 0 20 0x04>;
541 };
526 }; 542 };
527 543
528 epit@020d0000 { /* EPIT1 */ 544 epit1: epit@020d0000 { /* EPIT1 */
529 reg = <0x020d0000 0x4000>; 545 reg = <0x020d0000 0x4000>;
530 interrupts = <0 56 0x04>; 546 interrupts = <0 56 0x04>;
531 }; 547 };
532 548
533 epit@020d4000 { /* EPIT2 */ 549 epit2: epit@020d4000 { /* EPIT2 */
534 reg = <0x020d4000 0x4000>; 550 reg = <0x020d4000 0x4000>;
535 interrupts = <0 57 0x04>; 551 interrupts = <0 57 0x04>;
536 }; 552 };
537 553
538 src@020d8000 { 554 src: src@020d8000 {
539 compatible = "fsl,imx6q-src"; 555 compatible = "fsl,imx6q-src";
540 reg = <0x020d8000 0x4000>; 556 reg = <0x020d8000 0x4000>;
541 interrupts = <0 91 0x04 0 96 0x04>; 557 interrupts = <0 91 0x04 0 96 0x04>;
542 }; 558 };
543 559
544 gpc@020dc000 { 560 gpc: gpc@020dc000 {
545 compatible = "fsl,imx6q-gpc"; 561 compatible = "fsl,imx6q-gpc";
546 reg = <0x020dc000 0x4000>; 562 reg = <0x020dc000 0x4000>;
547 interrupts = <0 89 0x04 0 90 0x04>; 563 interrupts = <0 89 0x04 0 90 0x04>;
@@ -552,7 +568,7 @@
552 reg = <0x020e0000 0x38>; 568 reg = <0x020e0000 0x38>;
553 }; 569 };
554 570
555 iomuxc@020e0000 { 571 iomuxc: iomuxc@020e0000 {
556 compatible = "fsl,imx6q-iomuxc"; 572 compatible = "fsl,imx6q-iomuxc";
557 reg = <0x020e0000 0x4000>; 573 reg = <0x020e0000 0x4000>;
558 574
@@ -765,17 +781,17 @@
765 }; 781 };
766 }; 782 };
767 783
768 dcic@020e4000 { /* DCIC1 */ 784 dcic1: dcic@020e4000 {
769 reg = <0x020e4000 0x4000>; 785 reg = <0x020e4000 0x4000>;
770 interrupts = <0 124 0x04>; 786 interrupts = <0 124 0x04>;
771 }; 787 };
772 788
773 dcic@020e8000 { /* DCIC2 */ 789 dcic2: dcic@020e8000 {
774 reg = <0x020e8000 0x4000>; 790 reg = <0x020e8000 0x4000>;
775 interrupts = <0 125 0x04>; 791 interrupts = <0 125 0x04>;
776 }; 792 };
777 793
778 sdma@020ec000 { 794 sdma: sdma@020ec000 {
779 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 795 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
780 reg = <0x020ec000 0x4000>; 796 reg = <0x020ec000 0x4000>;
781 interrupts = <0 2 0x04>; 797 interrupts = <0 2 0x04>;
@@ -801,7 +817,7 @@
801 reg = <0x0217c000 0x4000>; 817 reg = <0x0217c000 0x4000>;
802 }; 818 };
803 819
804 usb@02184000 { /* USB OTG */ 820 usbotg: usb@02184000 {
805 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 821 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
806 reg = <0x02184000 0x200>; 822 reg = <0x02184000 0x200>;
807 interrupts = <0 43 0x04>; 823 interrupts = <0 43 0x04>;
@@ -811,7 +827,7 @@
811 status = "disabled"; 827 status = "disabled";
812 }; 828 };
813 829
814 usb@02184200 { /* USB1 */ 830 usbh1: usb@02184200 {
815 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 831 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
816 reg = <0x02184200 0x200>; 832 reg = <0x02184200 0x200>;
817 interrupts = <0 40 0x04>; 833 interrupts = <0 40 0x04>;
@@ -821,7 +837,7 @@
821 status = "disabled"; 837 status = "disabled";
822 }; 838 };
823 839
824 usb@02184400 { /* USB2 */ 840 usbh2: usb@02184400 {
825 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 841 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
826 reg = <0x02184400 0x200>; 842 reg = <0x02184400 0x200>;
827 interrupts = <0 41 0x04>; 843 interrupts = <0 41 0x04>;
@@ -830,7 +846,7 @@
830 status = "disabled"; 846 status = "disabled";
831 }; 847 };
832 848
833 usb@02184600 { /* USB3 */ 849 usbh3: usb@02184600 {
834 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 850 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
835 reg = <0x02184600 0x200>; 851 reg = <0x02184600 0x200>;
836 interrupts = <0 42 0x04>; 852 interrupts = <0 42 0x04>;
@@ -839,14 +855,14 @@
839 status = "disabled"; 855 status = "disabled";
840 }; 856 };
841 857
842 usbmisc: usbmisc@02184800 { 858 usbmisc: usbmisc: usbmisc@02184800 {
843 #index-cells = <1>; 859 #index-cells = <1>;
844 compatible = "fsl,imx6q-usbmisc"; 860 compatible = "fsl,imx6q-usbmisc";
845 reg = <0x02184800 0x200>; 861 reg = <0x02184800 0x200>;
846 clocks = <&clks 162>; 862 clocks = <&clks 162>;
847 }; 863 };
848 864
849 ethernet@02188000 { 865 fec: ethernet@02188000 {
850 compatible = "fsl,imx6q-fec"; 866 compatible = "fsl,imx6q-fec";
851 reg = <0x02188000 0x4000>; 867 reg = <0x02188000 0x4000>;
852 interrupts = <0 118 0x04 0 119 0x04>; 868 interrupts = <0 118 0x04 0 119 0x04>;
@@ -860,43 +876,47 @@
860 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; 876 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
861 }; 877 };
862 878
863 usdhc@02190000 { /* uSDHC1 */ 879 usdhc1: usdhc@02190000 {
864 compatible = "fsl,imx6q-usdhc"; 880 compatible = "fsl,imx6q-usdhc";
865 reg = <0x02190000 0x4000>; 881 reg = <0x02190000 0x4000>;
866 interrupts = <0 22 0x04>; 882 interrupts = <0 22 0x04>;
867 clocks = <&clks 163>, <&clks 163>, <&clks 163>; 883 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
868 clock-names = "ipg", "ahb", "per"; 884 clock-names = "ipg", "ahb", "per";
885 bus-width = <4>;
869 status = "disabled"; 886 status = "disabled";
870 }; 887 };
871 888
872 usdhc@02194000 { /* uSDHC2 */ 889 usdhc2: usdhc@02194000 {
873 compatible = "fsl,imx6q-usdhc"; 890 compatible = "fsl,imx6q-usdhc";
874 reg = <0x02194000 0x4000>; 891 reg = <0x02194000 0x4000>;
875 interrupts = <0 23 0x04>; 892 interrupts = <0 23 0x04>;
876 clocks = <&clks 164>, <&clks 164>, <&clks 164>; 893 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
877 clock-names = "ipg", "ahb", "per"; 894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
878 status = "disabled"; 896 status = "disabled";
879 }; 897 };
880 898
881 usdhc@02198000 { /* uSDHC3 */ 899 usdhc3: usdhc@02198000 {
882 compatible = "fsl,imx6q-usdhc"; 900 compatible = "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>; 901 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 0x04>; 902 interrupts = <0 24 0x04>;
885 clocks = <&clks 165>, <&clks 165>, <&clks 165>; 903 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
886 clock-names = "ipg", "ahb", "per"; 904 clock-names = "ipg", "ahb", "per";
905 bus-width = <4>;
887 status = "disabled"; 906 status = "disabled";
888 }; 907 };
889 908
890 usdhc@0219c000 { /* uSDHC4 */ 909 usdhc4: usdhc@0219c000 {
891 compatible = "fsl,imx6q-usdhc"; 910 compatible = "fsl,imx6q-usdhc";
892 reg = <0x0219c000 0x4000>; 911 reg = <0x0219c000 0x4000>;
893 interrupts = <0 25 0x04>; 912 interrupts = <0 25 0x04>;
894 clocks = <&clks 166>, <&clks 166>, <&clks 166>; 913 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
895 clock-names = "ipg", "ahb", "per"; 914 clock-names = "ipg", "ahb", "per";
915 bus-width = <4>;
896 status = "disabled"; 916 status = "disabled";
897 }; 917 };
898 918
899 i2c@021a0000 { /* I2C1 */ 919 i2c1: i2c@021a0000 {
900 #address-cells = <1>; 920 #address-cells = <1>;
901 #size-cells = <0>; 921 #size-cells = <0>;
902 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -906,7 +926,7 @@
906 status = "disabled"; 926 status = "disabled";
907 }; 927 };
908 928
909 i2c@021a4000 { /* I2C2 */ 929 i2c2: i2c@021a4000 {
910 #address-cells = <1>; 930 #address-cells = <1>;
911 #size-cells = <0>; 931 #size-cells = <0>;
912 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -916,7 +936,7 @@
916 status = "disabled"; 936 status = "disabled";
917 }; 937 };
918 938
919 i2c@021a8000 { /* I2C3 */ 939 i2c3: i2c@021a8000 {
920 #address-cells = <1>; 940 #address-cells = <1>;
921 #size-cells = <0>; 941 #size-cells = <0>;
922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@@ -930,12 +950,12 @@
930 reg = <0x021ac000 0x4000>; 950 reg = <0x021ac000 0x4000>;
931 }; 951 };
932 952
933 mmdc@021b0000 { /* MMDC0 */ 953 mmdc0: mmdc@021b0000 { /* MMDC0 */
934 compatible = "fsl,imx6q-mmdc"; 954 compatible = "fsl,imx6q-mmdc";
935 reg = <0x021b0000 0x4000>; 955 reg = <0x021b0000 0x4000>;
936 }; 956 };
937 957
938 mmdc@021b4000 { /* MMDC1 */ 958 mmdc1: mmdc@021b4000 { /* MMDC1 */
939 reg = <0x021b4000 0x4000>; 959 reg = <0x021b4000 0x4000>;
940 }; 960 };
941 961
@@ -963,7 +983,7 @@
963 interrupts = <0 109 0x04>; 983 interrupts = <0 109 0x04>;
964 }; 984 };
965 985
966 audmux@021d8000 { 986 audmux: audmux@021d8000 {
967 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 987 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
968 reg = <0x021d8000 0x4000>; 988 reg = <0x021d8000 0x4000>;
969 status = "disabled"; 989 status = "disabled";
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
new file mode 100644
index 000000000000..d6c9d65cbaeb
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -0,0 +1,44 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_sata0: pmx-sata0 {
14 marvell,pins = "mpp5", "mpp21", "mpp23";
15 marvell,function = "sata0";
16 };
17 pmx_sata1: pmx-sata1 {
18 marvell,pins = "mpp4", "mpp20", "mpp22";
19 marvell,function = "sata1";
20 };
21 pmx_spi: pmx-spi {
22 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
23 marvell,function = "spi";
24 };
25 pmx_twsi0: pmx-twsi0 {
26 marvell,pins = "mpp8", "mpp9";
27 marvell,function = "twsi0";
28 };
29 pmx_uart0: pmx-uart0 {
30 marvell,pins = "mpp10", "mpp11";
31 marvell,function = "uart0";
32 };
33 pmx_uart1: pmx-uart1 {
34 marvell,pins = "mpp13", "mpp14";
35 marvell,function = "uart1";
36 };
37 pmx_sdio: pmx-sdio {
38 marvell,pins = "mpp12", "mpp13", "mpp14",
39 "mpp15", "mpp16", "mpp17";
40 marvell,function = "sdio";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
new file mode 100644
index 000000000000..9ae2004d5675
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -0,0 +1,45 @@
1/ {
2 ocp@f1000000 {
3
4 pinctrl: pinctrl@10000 {
5 compatible = "marvell,88f6282-pinctrl";
6 reg = <0x10000 0x20>;
7
8 pmx_sata0: pmx-sata0 {
9 marvell,pins = "mpp5", "mpp21", "mpp23";
10 marvell,function = "sata0";
11 };
12 pmx_sata1: pmx-sata1 {
13 marvell,pins = "mpp4", "mpp20", "mpp22";
14 marvell,function = "sata1";
15 };
16 pmx_spi: pmx-spi {
17 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
18 marvell,function = "spi";
19 };
20 pmx_twsi0: pmx-twsi0 {
21 marvell,pins = "mpp8", "mpp9";
22 marvell,function = "twsi0";
23 };
24 pmx_uart0: pmx-uart0 {
25 marvell,pins = "mpp10", "mpp11";
26 marvell,function = "uart0";
27 };
28
29 pmx_uart1: pmx-uart1 {
30 marvell,pins = "mpp13", "mpp14";
31 marvell,function = "uart1";
32 };
33 };
34
35 i2c@11100 {
36 compatible = "marvell,mv64xxx-i2c";
37 reg = <0x11100 0x20>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <32>;
41 clock-frequency = <100000>;
42 status = "disabled";
43 };
44 };
45};
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
new file mode 100644
index 000000000000..3271e4c8ea07
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -0,0 +1,31 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,98dx4122-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_spi: pmx-spi {
14 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
15 marvell,function = "spi";
16 };
17 pmx_twsi0: pmx-twsi0 {
18 marvell,pins = "mpp8", "mpp9";
19 marvell,function = "twsi0";
20 };
21 pmx_uart0: pmx-uart0 {
22 marvell,pins = "mpp10", "mpp11";
23 marvell,function = "uart0";
24 };
25 pmx_uart1: pmx-uart1 {
26 marvell,pins = "mpp13", "mpp14";
27 marvell,function = "uart1";
28 };
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 9b32d0272825..6875ac00c174 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,4 +1,5 @@
1/include/ "kirkwood.dtsi" 1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
2 3
3/ { 4/ {
4 model = "D-Link DNS NASes (kirkwood-based)"; 5 model = "D-Link DNS NASes (kirkwood-based)";
@@ -35,7 +36,116 @@
35 6000 2>; 36 6000 2>;
36 }; 37 };
37 38
39 gpio_poweroff {
40 compatible = "gpio-poweroff";
41 gpios = <&gpio1 4 0>;
42 };
43
38 ocp@f1000000 { 44 ocp@f1000000 {
45 pinctrl: pinctrl@10000 {
46
47 pinctrl-0 = < &pmx_nand &pmx_uart1
48 &pmx_sata0 &pmx_sata1
49 &pmx_led_power
50 &pmx_led_red_right_hdd
51 &pmx_led_red_left_hdd
52 &pmx_led_red_usb_325
53 &pmx_button_power
54 &pmx_led_red_usb_320
55 &pmx_power_off &pmx_power_back_on
56 &pmx_power_sata0 &pmx_power_sata1
57 &pmx_present_sata0 &pmx_present_sata1
58 &pmx_led_white_usb &pmx_fan_tacho
59 &pmx_fan_high_speed &pmx_fan_low_speed
60 &pmx_button_unmount &pmx_button_reset
61 &pmx_temp_alarm >;
62 pinctrl-names = "default";
63
64 pmx_sata0: pmx-sata0 {
65 marvell,pins = "mpp20";
66 marvell,function = "sata1";
67 };
68 pmx_sata1: pmx-sata1 {
69 marvell,pins = "mpp21";
70 marvell,function = "sata0";
71 };
72 pmx_led_power: pmx-led-power {
73 marvell,pins = "mpp26";
74 marvell,function = "gpio";
75 };
76 pmx_led_red_right_hdd: pmx-led-red-right-hdd {
77 marvell,pins = "mpp27";
78 marvell,function = "gpio";
79 };
80 pmx_led_red_left_hdd: pmx-led-red-left-hdd {
81 marvell,pins = "mpp28";
82 marvell,function = "gpio";
83 };
84 pmx_led_red_usb_325: pmx-led-red-usb-325 {
85 marvell,pins = "mpp29";
86 marvell,function = "gpio";
87 };
88 pmx_button_power: pmx-button-power {
89 marvell,pins = "mpp34";
90 marvell,function = "gpio";
91 };
92 pmx_led_red_usb_320: pmx-led-red-usb-320 {
93 marvell,pins = "mpp35";
94 marvell,function = "gpio";
95 };
96 pmx_power_off: pmx-power-off {
97 marvell,pins = "mpp36";
98 marvell,function = "gpio";
99 };
100 pmx_power_back_on: pmx-power-back-on {
101 marvell,pins = "mpp37";
102 marvell,function = "gpio";
103 };
104 pmx_power_sata0: pmx-power-sata0 {
105 marvell,pins = "mpp39";
106 marvell,function = "gpio";
107 };
108 pmx_power_sata1: pmx-power-sata1 {
109 marvell,pins = "mpp40";
110 marvell,function = "gpio";
111 };
112 pmx_present_sata0: pmx-present-sata0 {
113 marvell,pins = "mpp41";
114 marvell,function = "gpio";
115 };
116 pmx_present_sata1: pmx-present-sata1 {
117 marvell,pins = "mpp42";
118 marvell,function = "gpio";
119 };
120 pmx_led_white_usb: pmx-led-white-usb {
121 marvell,pins = "mpp43";
122 marvell,function = "gpio";
123 };
124 pmx_fan_tacho: pmx-fan-tacho {
125 marvell,pins = "mpp44";
126 marvell,function = "gpio";
127 };
128 pmx_fan_high_speed: pmx-fan-high-speed {
129 marvell,pins = "mpp45";
130 marvell,function = "gpio";
131 };
132 pmx_fan_low_speed: pmx-fan-low-speed {
133 marvell,pins = "mpp46";
134 marvell,function = "gpio";
135 };
136 pmx_button_unmount: pmx-button-unmount {
137 marvell,pins = "mpp47";
138 marvell,function = "gpio";
139 };
140 pmx_button_reset: pmx-button-reset {
141 marvell,pins = "mpp48";
142 marvell,function = "gpio";
143 };
144 pmx_temp_alarm: pmx-temp-alarm {
145 marvell,pins = "mpp49";
146 marvell,function = "gpio";
147 };
148 };
39 sata@80000 { 149 sata@80000 {
40 status = "okay"; 150 status = "okay";
41 nr-ports = <2>; 151 nr-ports = <2>;
@@ -43,6 +153,7 @@
43 153
44 nand@3000000 { 154 nand@3000000 {
45 status = "okay"; 155 status = "okay";
156 chip-delay = <35>;
46 157
47 partition@0 { 158 partition@0 {
48 label = "u-boot"; 159 label = "u-boot";
@@ -76,4 +187,33 @@
76 }; 187 };
77 }; 188 };
78 }; 189 };
190
191 regulators {
192 compatible = "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 sata0_power: regulator@1 {
197 compatible = "regulator-fixed";
198 reg = <1>;
199 regulator-name = "SATA0 Power";
200 regulator-min-microvolt = <5000000>;
201 regulator-max-microvolt = <5000000>;
202 enable-active-high;
203 regulator-always-on;
204 regulator-boot-on;
205 gpio = <&gpio1 7 0>;
206 };
207 sata1_power: regulator@2 {
208 compatible = "regulator-fixed";
209 reg = <2>;
210 regulator-name = "SATA1 Power";
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5000000>;
213 enable-active-high;
214 regulator-always-on;
215 regulator-boot-on;
216 gpio = <&gpio1 8 0>;
217 };
218 };
79}; 219};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 08a582414b88..2e3dd34e21a5 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Seagate FreeAgent Dockstar"; 7 model = "Seagate FreeAgent Dockstar";
@@ -16,6 +17,25 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable
23 &pmx_led_green &pmx_led_orange >;
24 pinctrl-names = "default";
25
26 pmx_usb_power_enable: pmx-usb-power-enable {
27 marvell,pins = "mpp29";
28 marvell,function = "gpio";
29 };
30 pmx_led_green: pmx-led-green {
31 marvell,pins = "mpp46";
32 marvell,function = "gpio";
33 };
34 pmx_led_orange: pmx-led-orange {
35 marvell,pins = "mpp47";
36 marvell,function = "gpio";
37 };
38 };
19 serial@12000 { 39 serial@12000 {
20 clock-frequency = <200000000>; 40 clock-frequency = <200000000>;
21 status = "ok"; 41 status = "ok";
@@ -54,4 +74,21 @@
54 gpios = <&gpio1 15 1>; 74 gpios = <&gpio1 15 1>;
55 }; 75 };
56 }; 76 };
77 regulators {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 usb_power: regulator@1 {
83 compatible = "regulator-fixed";
84 reg = <1>;
85 regulator-name = "USB Power";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 enable-active-high;
89 regulator-always-on;
90 regulator-boot-on;
91 gpio = <&gpio0 29 0>;
92 };
93 };
57}; 94};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 26e281fbf6bc..f2d386c95b07 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Globalscale Technologies Dreamplug"; 7 model = "Globalscale Technologies Dreamplug";
@@ -16,6 +17,26 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_spi
23 &pmx_led_bluetooth &pmx_led_wifi
24 &pmx_led_wifi_ap >;
25 pinctrl-names = "default";
26
27 pmx_led_bluetooth: pmx-led-bluetooth {
28 marvell,pins = "mpp47";
29 marvell,function = "gpio";
30 };
31 pmx_led_wifi: pmx-led-wifi {
32 marvell,pins = "mpp48";
33 marvell,function = "gpio";
34 };
35 pmx_led_wifi_ap: pmx-led-wifi-ap {
36 marvell,pins = "mpp49";
37 marvell,function = "gpio";
38 };
39 };
19 serial@12000 { 40 serial@12000 {
20 clock-frequency = <200000000>; 41 clock-frequency = <200000000>;
21 status = "ok"; 42 status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 7c8238fbb6f9..1b133e0c566e 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Seagate GoFlex Net"; 7 model = "Seagate GoFlex Net";
@@ -16,6 +17,61 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
23 &pmx_led_left_cap_0 &pmx_led_left_cap_1
24 &pmx_led_left_cap_2 &pmx_led_left_cap_3
25 &pmx_led_right_cap_0 &pmx_led_right_cap_1
26 &pmx_led_right_cap_2 &pmx_led_right_cap_3
27 >;
28 pinctrl-names = "default";
29
30 pmx_usb_power_enable: pmx-usb-power-enable {
31 marvell,pins = "mpp29";
32 marvell,function = "gpio";
33 };
34 pmx_led_right_cap_0: pmx-led_right_cap_0 {
35 marvell,pins = "mpp38";
36 marvell,function = "gpio";
37 };
38 pmx_led_right_cap_1: pmx-led_right_cap_1 {
39 marvell,pins = "mpp39";
40 marvell,function = "gpio";
41 };
42 pmx_led_right_cap_2: pmx-led_right_cap_2 {
43 marvell,pins = "mpp40";
44 marvell,function = "gpio";
45 };
46 pmx_led_right_cap_3: pmx-led_right_cap_3 {
47 marvell,pins = "mpp41";
48 marvell,function = "gpio";
49 };
50 pmx_led_left_cap_0: pmx-led_left_cap_0 {
51 marvell,pins = "mpp42";
52 marvell,function = "gpio";
53 };
54 pmx_led_left_cap_1: pmx-led_left_cap_1 {
55 marvell,pins = "mpp43";
56 marvell,function = "gpio";
57 };
58 pmx_led_left_cap_2: pmx-led_left_cap_2 {
59 marvell,pins = "mpp44";
60 marvell,function = "gpio";
61 };
62 pmx_led_left_cap_3: pmx-led_left_cap_3 {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66 pmx_led_green: pmx-led_green {
67 marvell,pins = "mpp46";
68 marvell,function = "gpio";
69 };
70 pmx_led_orange: pmx-led_orange {
71 marvell,pins = "mpp47";
72 marvell,function = "gpio";
73 };
74 };
19 serial@12000 { 75 serial@12000 {
20 clock-frequency = <200000000>; 76 clock-frequency = <200000000>;
21 status = "ok"; 77 status = "ok";
@@ -96,4 +152,21 @@
96 gpios = <&gpio1 9 0>; 152 gpios = <&gpio1 9 0>;
97 }; 153 };
98 }; 154 };
155 regulators {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 usb_power: regulator@1 {
161 compatible = "regulator-fixed";
162 reg = <1>;
163 regulator-name = "USB Power";
164 regulator-min-microvolt = <5000000>;
165 regulator-max-microvolt = <5000000>;
166 enable-active-high;
167 regulator-always-on;
168 regulator-boot-on;
169 gpio = <&gpio0 29 0>;
170 };
171 };
99}; 172};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed75ff1..71902da33d63 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; 7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
@@ -16,6 +17,39 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand
23 &pmx_led_os_red &pmx_power_off
24 &pmx_led_os_green &pmx_led_usb_transfer
25 &pmx_button_reset &pmx_button_usb_copy >;
26 pinctrl-names = "default";
27
28 pmx_led_os_red: pmx-led-os-red {
29 marvell,pins = "mpp22";
30 marvell,function = "gpio";
31 };
32 pmx_power_off: pmx-power-off {
33 marvell,pins = "mpp24";
34 marvell,function = "gpio";
35 };
36 pmx_led_os_green: pmx-led-os-green {
37 marvell,pins = "mpp25";
38 marvell,function = "gpio";
39 };
40 pmx_led_usb_transfer: pmx-led-usb-transfer {
41 marvell,pins = "mpp27";
42 marvell,function = "gpio";
43 };
44 pmx_button_reset: pmx-button-reset {
45 marvell,pins = "mpp28";
46 marvell,function = "gpio";
47 };
48 pmx_button_usb_copy: pmx-button-usb-copy {
49 marvell,pins = "mpp29";
50 marvell,function = "gpio";
51 };
52 };
19 serial@12000 { 53 serial@12000 {
20 clock-frequency = <200000000>; 54 clock-frequency = <200000000>;
21 status = "okay"; 55 status = "okay";
@@ -79,4 +113,10 @@
79 gpios = <&gpio0 27 0>; 113 gpios = <&gpio0 27 0>;
80 }; 114 };
81 }; 115 };
116 gpio_poweroff {
117 compatible = "gpio-poweroff";
118 gpios = <&gpio0 24 0>;
119 };
120
121
82}; 122};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index d97cd9d4753e..504f16be8b54 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Iomega Iconnect"; 7 model = "Iomega Iconnect";
@@ -18,6 +19,56 @@
18 }; 19 };
19 20
20 ocp@f1000000 { 21 ocp@f1000000 {
22 pinctrl: pinctrl@10000 {
23
24 pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
25 &pmx_gpio_41 &pmx_gpio_42
26 &pmx_gpio_43 &pmx_gpio_44
27 &pmx_gpio_45 &pmx_gpio_46
28 &pmx_gpio_47 &pmx_gpio_48 >;
29 pinctrl-names = "default";
30
31 pmx_gpio_12: pmx-gpio-12 {
32 marvell,pins = "mpp12";
33 marvell,function = "gpio";
34 };
35 pmx_gpio_35: pmx-gpio-35 {
36 marvell,pins = "mpp35";
37 marvell,function = "gpio";
38 };
39 pmx_gpio_41: pmx-gpio-41 {
40 marvell,pins = "mpp41";
41 marvell,function = "gpio";
42 };
43 pmx_gpio_42: pmx-gpio-42 {
44 marvell,pins = "mpp42";
45 marvell,function = "gpio";
46 };
47 pmx_gpio_43: pmx-gpio-43 {
48 marvell,pins = "mpp43";
49 marvell,function = "gpio";
50 };
51 pmx_gpio_44: pmx-gpio-44 {
52 marvell,pins = "mpp44";
53 marvell,function = "gpio";
54 };
55 pmx_gpio_45: pmx-gpio-45 {
56 marvell,pins = "mpp45";
57 marvell,function = "gpio";
58 };
59 pmx_gpio_46: pmx-gpio-46 {
60 marvell,pins = "mpp46";
61 marvell,function = "gpio";
62 };
63 pmx_gpio_47: pmx-gpio-47 {
64 marvell,pins = "mpp47";
65 marvell,function = "gpio";
66 };
67 pmx_gpio_48: pmx-gpio-48 {
68 marvell,pins = "mpp48";
69 marvell,function = "gpio";
70 };
71 };
21 i2c@11000 { 72 i2c@11000 {
22 status = "okay"; 73 status = "okay";
23 74
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 865aeec40a26..6cae4599c4b3 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "Iomega StorCenter ix2-200"; 7 model = "Iomega StorCenter ix2-200";
@@ -16,6 +17,94 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_button_reset &pmx_button_power
23 &pmx_led_backup &pmx_led_power
24 &pmx_button_otb &pmx_led_rebuild
25 &pmx_led_health
26 &pmx_led_sata_brt_ctrl_1
27 &pmx_led_sata_brt_ctrl_2
28 &pmx_led_backup_brt_ctrl_1
29 &pmx_led_backup_brt_ctrl_2
30 &pmx_led_power_brt_ctrl_1
31 &pmx_led_power_brt_ctrl_2
32 &pmx_led_health_brt_ctrl_1
33 &pmx_led_health_brt_ctrl_2
34 &pmx_led_rebuild_brt_ctrl_1
35 &pmx_led_rebuild_brt_ctrl_2 >;
36 pinctrl-names = "default";
37
38 pmx_button_reset: pmx-button-reset {
39 marvell,pins = "mpp12";
40 marvell,function = "gpio";
41 };
42 pmx_button_power: pmx-button-power {
43 marvell,pins = "mpp14";
44 marvell,function = "gpio";
45 };
46 pmx_led_backup: pmx-led-backup {
47 marvell,pins = "mpp15";
48 marvell,function = "gpio";
49 };
50 pmx_led_power: pmx-led-power {
51 marvell,pins = "mpp16";
52 marvell,function = "gpio";
53 };
54 pmx_button_otb: pmx-button-otb {
55 marvell,pins = "mpp35";
56 marvell,function = "gpio";
57 };
58 pmx_led_rebuild: pmx-led-rebuild {
59 marvell,pins = "mpp36";
60 marvell,function = "gpio";
61 };
62 pmx_led_health: pmx-led_health {
63 marvell,pins = "mpp37";
64 marvell,function = "gpio";
65 };
66 pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
67 marvell,pins = "mpp38";
68 marvell,function = "gpio";
69 };
70 pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
71 marvell,pins = "mpp39";
72 marvell,function = "gpio";
73 };
74 pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
75 marvell,pins = "mpp40";
76 marvell,function = "gpio";
77 };
78 pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
79 marvell,pins = "mpp41";
80 marvell,function = "gpio";
81 };
82 pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
83 marvell,pins = "mpp42";
84 marvell,function = "gpio";
85 };
86 pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
87 marvell,pins = "mpp43";
88 marvell,function = "gpio";
89 };
90 pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
91 marvell,pins = "mpp44";
92 marvell,function = "gpio";
93 };
94 pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
95 marvell,pins = "mpp45";
96 marvell,function = "gpio";
97 };
98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 marvell,pins = "mpp44";
100 marvell,function = "gpio";
101 };
102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
103 marvell,pins = "mpp45";
104 marvell,function = "gpio";
105 };
106
107 };
19 i2c@11000 { 108 i2c@11000 {
20 status = "okay"; 109 status = "okay";
21 110
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 75bdb93fed26..8db3123ac80f 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-98dx4122.dtsi"
4 5
5/ { 6/ {
6 model = "Keymile Kirkwood Reference Design"; 7 model = "Keymile Kirkwood Reference Design";
@@ -16,6 +17,22 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
23 &pmx_i2c_gpio_scl >;
24 pinctrl-names = "default";
25
26 pmx_i2c_gpio_sda: pmx-gpio-sda {
27 marvell,pins = "mpp8";
28 marvell,function = "gpio";
29 };
30 pmx_i2c_gpio_scl: pmx-gpio-scl {
31 marvell,pins = "mpp9";
32 marvell,function = "gpio";
33 };
34 };
35
19 serial@12000 { 36 serial@12000 {
20 clock-frequency = <200000000>; 37 clock-frequency = <200000000>;
21 status = "ok"; 38 status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 798e60eeedf3..37d45c4f88fb 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,4 +1,5 @@
1/include/ "kirkwood.dtsi" 1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
2 3
3/ { 4/ {
4 chosen { 5 chosen {
@@ -6,6 +7,71 @@
6 }; 7 };
7 8
8 ocp@f1000000 { 9 ocp@f1000000 {
10 pinctrl: pinctrl@10000 {
11
12 pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
13 &pmx_fan_low &pmx_fan_high
14 &pmx_led_function_red &pmx_led_alarm
15 &pmx_led_info &pmx_led_power
16 &pmx_fan_lock &pmx_button_function
17 &pmx_power_switch &pmx_power_auto_switch
18 &pmx_led_function_blue >;
19 pinctrl-names = "default";
20
21 pmx_power_hdd: pmx-power-hdd {
22 marvell,pins = "mpp10";
23 marvell,function = "gpo";
24 };
25 pmx_usb_vbus: pmx-usb-vbus {
26 marvell,pins = "mpp11";
27 marvell,function = "gpio";
28 };
29 pmx_fan_high: pmx-fan-high {
30 marvell,pins = "mpp18";
31 marvell,function = "gpo";
32 };
33 pmx_fan_low: pmx-fan-low {
34 marvell,pins = "mpp19";
35 marvell,function = "gpo";
36 };
37 pmx_led_function_blue: pmx-led-function-blue {
38 marvell,pins = "mpp36";
39 marvell,function = "gpio";
40 };
41 pmx_led_alarm: pmx-led-alarm {
42 marvell,pins = "mpp37";
43 marvell,function = "gpio";
44 };
45 pmx_led_info: pmx-led-info {
46 marvell,pins = "mpp38";
47 marvell,function = "gpio";
48 };
49 pmx_led_power: pmx-led-power {
50 marvell,pins = "mpp39";
51 marvell,function = "gpio";
52 };
53 pmx_fan_lock: pmx-fan-lock {
54 marvell,pins = "mpp40";
55 marvell,function = "gpio";
56 };
57 pmx_button_function: pmx-button-function {
58 marvell,pins = "mpp41";
59 marvell,function = "gpio";
60 };
61 pmx_power_switch: pmx-power-switch {
62 marvell,pins = "mpp42";
63 marvell,function = "gpio";
64 };
65 pmx_power_auto_switch: pmx-power-auto-switch {
66 marvell,pins = "mpp43";
67 marvell,function = "gpio";
68 };
69 pmx_led_function_red: pmx-led-function_red {
70 marvell,pins = "mpp48";
71 marvell,function = "gpio";
72 };
73
74 };
9 sata@80000 { 75 sata@80000 {
10 status = "okay"; 76 status = "okay";
11 nr-ports = <1>; 77 nr-ports = <1>;
@@ -105,4 +171,33 @@
105 5000 0>; 171 5000 0>;
106 alarm-gpios = <&gpio1 8 0>; 172 alarm-gpios = <&gpio1 8 0>;
107 }; 173 };
174
175 regulators {
176 compatible = "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 usb_power: regulator@1 {
181 compatible = "regulator-fixed";
182 reg = <1>;
183 regulator-name = "USB Power";
184 regulator-min-microvolt = <5000000>;
185 regulator-max-microvolt = <5000000>;
186 enable-active-high;
187 regulator-always-on;
188 regulator-boot-on;
189 gpio = <&gpio0 11 0>;
190 };
191 hdd_power: regulator@2 {
192 compatible = "regulator-fixed";
193 reg = <2>;
194 regulator-name = "HDD Power";
195 regulator-min-microvolt = <5000000>;
196 regulator-max-microvolt = <5000000>;
197 enable-active-high;
198 regulator-always-on;
199 regulator-boot-on;
200 gpio = <&gpio0 10 0>;
201 };
202 };
108}; 203};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index ac3c080bed21..262c65403760 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
6 model = "MPL CEC4"; 7 model = "MPL CEC4";
@@ -16,6 +17,64 @@
16 }; 17 };
17 18
18 ocp@f1000000 { 19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_uart0
23 &pmx_led_health &pmx_sdio
24 &pmx_sata0 &pmx_sata1
25 &pmx_led_user1o
26 &pmx_led_user1g &pmx_led_user0o
27 &pmx_led_user0g &pmx_led_misc
28 &pmx_sdio_cd
29 >;
30 pinctrl-names = "default";
31
32 pmx_led_health: pmx-led-health {
33 marvell,pins = "mpp7";
34 marvell,function = "gpo";
35 };
36
37 pmx_sata1: pmx-sata1 {
38 marvell,pins = "mpp34";
39 marvell,function = "sata1";
40 };
41
42 pmx_sata0: pmx-sata0 {
43 marvell,pins = "mpp35";
44 marvell,function = "sata0";
45 };
46
47 pmx_led_user1o: pmx-led-user1o {
48 marvell,pins = "mpp40";
49 marvell,function = "gpio";
50 };
51
52 pmx_led_user1g: pmx-led-user1g {
53 marvell,pins = "mpp41";
54 marvell,function = "gpio";
55 };
56
57 pmx_led_user0o: pmx-led-user0o {
58 marvell,pins = "mpp44";
59 marvell,function = "gpio";
60 };
61
62 pmx_led_user0g: pmx-led-user0g {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66
67 pmx_led_misc: pmx-led-misc {
68 marvell,pins = "mpp46";
69 marvell,function = "gpio";
70 };
71
72 pmx_sdio_cd: pmx-sdio-cd {
73 marvell,pins = "mpp47";
74 marvell,function = "gpio";
75 };
76 };
77
19 i2c@11000 { 78 i2c@11000 {
20 status = "okay"; 79 status = "okay";
21 80
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 9a2606c8b78f..49d3d74d4d38 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi"
4 5
5/ { 6/ {
6 model = "Plat'Home OpenBlocksA6"; 7 model = "Plat'Home OpenBlocksA6";
@@ -29,11 +30,69 @@
29 nand@3000000 { 30 nand@3000000 {
30 chip-delay = <25>; 31 chip-delay = <25>;
31 status = "okay"; 32 status = "okay";
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0 0x90000>;
37 };
38
39 partition@90000 {
40 label = "env";
41 reg = <0x90000 0x44000>;
42 };
43
44 partition@d4000 {
45 label = "test";
46 reg = <0xd4000 0x24000>;
47 };
48
49 partition@f4000 {
50 label = "conf";
51 reg = <0xf4000 0x400000>;
52 };
53
54 partition@4f4000 {
55 label = "linux";
56 reg = <0x4f4000 0x1d20000>;
57 };
58
59 partition@2214000 {
60 label = "user";
61 reg = <0x2214000 0x1dec000>;
62 };
32 }; 63 };
33 64
34 sata@80000 { 65 sata@80000 {
35 nr-ports = <1>; 66 nr-ports = <1>;
36 status = "okay"; 67 status = "okay";
37 }; 68 };
69
70 i2c@11100 {
71 status = "okay";
72
73 s35390a: s35390a@30 {
74 compatible = "s35390a";
75 reg = <0x30>;
76 };
77 };
38 }; 78 };
79
80 gpio-leds {
81 compatible = "gpio-leds";
82
83 led-red {
84 label = "obsa6:red:stat";
85 gpios = <&gpio1 9 1>;
86 };
87
88 led-green {
89 label = "obsa6:green:stat";
90 gpios = <&gpio1 10 1>;
91 };
92
93 led-yellow {
94 label = "obsa6:yellow:stat";
95 gpios = <&gpio1 11 1>;
96 };
97 };
39}; 98};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index ccbf32757800..8295c833887f 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,39 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ts219.dtsi" 3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6281.dtsi"
4 5
5/ { 6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_USB_copy_button: pmx-USB-copy-button {
22 marvell,pins = "mpp15";
23 marvell,function = "gpio";
24 };
25 pmx_reset_button: pmx-reset-button {
26 marvell,pins = "mpp16";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
6 gpio_keys { 37 gpio_keys {
7 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
8 #address-cells = <1>; 39 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index fbe9932161a1..df3f95dfba33 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,8 +1,39 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ts219.dtsi" 3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6282.dtsi"
4 5
5/ { 6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_reset_button: pmx-reset-button {
22 marvell,pins = "mpp37";
23 marvell,function = "gpio";
24 };
25 pmx_USB_copy_button: pmx-USB-copy-button {
26 marvell,pins = "mpp43";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
6 gpio_keys { 37 gpio_keys {
7 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
8 #address-cells = <1>; 39 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 4e5b8154a5be..a990c30f0a26 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,10 @@
4 compatible = "marvell,kirkwood"; 4 compatible = "marvell,kirkwood";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
7 intc: interrupt-controller { 11 intc: interrupt-controller {
8 compatible = "marvell,orion-intc", "marvell,intc"; 12 compatible = "marvell,orion-intc", "marvell,intc";
9 interrupt-controller; 13 interrupt-controller;
@@ -24,7 +28,8 @@
24 #gpio-cells = <2>; 28 #gpio-cells = <2>;
25 gpio-controller; 29 gpio-controller;
26 reg = <0x10100 0x40>; 30 reg = <0x10100 0x40>;
27 ngpio = <32>; 31 ngpios = <32>;
32 interrupt-controller;
28 interrupts = <35>, <36>, <37>, <38>; 33 interrupts = <35>, <36>, <37>, <38>;
29 }; 34 };
30 35
@@ -33,7 +38,8 @@
33 #gpio-cells = <2>; 38 #gpio-cells = <2>;
34 gpio-controller; 39 gpio-controller;
35 reg = <0x10140 0x40>; 40 reg = <0x10140 0x40>;
36 ngpio = <18>; 41 ngpios = <18>;
42 interrupt-controller;
37 interrupts = <39>, <40>, <41>; 43 interrupts = <39>, <40>, <41>;
38 }; 44 };
39 45
@@ -77,6 +83,13 @@
77 status = "okay"; 83 status = "okay";
78 }; 84 };
79 85
86 ehci@50000 {
87 compatible = "marvell,orion-ehci";
88 reg = <0x50000 0x1000>;
89 interrupts = <19>;
90 status = "okay";
91 };
92
80 sata@80000 { 93 sata@80000 {
81 compatible = "marvell,orion-sata"; 94 compatible = "marvell,orion-sata";
82 reg = <0x80000 0x5000>; 95 reg = <0x80000 0x5000>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index e5ffe960dbf3..1582f484a867 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -182,6 +182,13 @@
182 pnx,timeout = <0x64>; 182 pnx,timeout = <0x64>;
183 }; 183 };
184 184
185 mpwm: mpwm@400E8000 {
186 compatible = "nxp,lpc3220-motor-pwm";
187 reg = <0x400E8000 0x78>;
188 status = "disabled";
189 #pwm-cells = <2>;
190 };
191
185 i2cusb: i2c@31020300 { 192 i2cusb: i2c@31020300 {
186 compatible = "nxp,pnx-i2c"; 193 compatible = "nxp,pnx-i2c";
187 reg = <0x31020300 0x100>; 194 reg = <0x31020300 0x100>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index c6f85f0bc531..27f31a5fa494 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "Calao Systems Snowball platform with device tree"; 16 model = "Calao Systems Snowball platform with device tree";
17 compatible = "calaosystems,snowball-a9500"; 17 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
18 18
19 memory { 19 memory {
20 reg = <0x00000000 0x20000000>; 20 reg = <0x00000000 0x20000000>;
@@ -147,10 +147,10 @@
147 }; 147 };
148 148
149 // External Micro SD slot 149 // External Micro SD slot
150 sdi@80126000 { 150 sdi0_per1@80126000 {
151 arm,primecell-periphid = <0x10480180>; 151 arm,primecell-periphid = <0x10480180>;
152 max-frequency = <50000000>; 152 max-frequency = <50000000>;
153 bus-width = <8>; 153 bus-width = <4>;
154 mmc-cap-mmc-highspeed; 154 mmc-cap-mmc-highspeed;
155 vmmc-supply = <&ab8500_ldo_aux3_reg>; 155 vmmc-supply = <&ab8500_ldo_aux3_reg>;
156 156
@@ -161,7 +161,7 @@
161 }; 161 };
162 162
163 // On-board eMMC 163 // On-board eMMC
164 sdi@80114000 { 164 sdi4_per2@80114000 {
165 arm,primecell-periphid = <0x10480180>; 165 arm,primecell-periphid = <0x10480180>;
166 max-frequency = <50000000>; 166 max-frequency = <50000000>;
167 bus-width = <8>; 167 bus-width = <8>;
@@ -214,5 +214,137 @@
214 cpufreq-cooling { 214 cpufreq-cooling {
215 status = "okay"; 215 status = "okay";
216 }; 216 };
217
218 prcmu@80157000 {
219 db8500-prcmu-regulators {
220 db8500_vape_reg: db8500_vape {
221 regulator-name = "db8500-vape";
222 };
223
224 db8500_varm_reg: db8500_varm {
225 regulator-name = "db8500-varm";
226 };
227
228 db8500_vmodem_reg: db8500_vmodem {
229 regulator-name = "db8500-vmodem";
230 };
231
232 db8500_vpll_reg: db8500_vpll {
233 regulator-name = "db8500-vpll";
234 };
235
236 db8500_vsmps1_reg: db8500_vsmps1 {
237 regulator-name = "db8500-vsmps1";
238 };
239
240 db8500_vsmps2_reg: db8500_vsmps2 {
241 regulator-name = "db8500-vsmps2";
242 };
243
244 db8500_vsmps3_reg: db8500_vsmps3 {
245 regulator-name = "db8500-vsmps3";
246 };
247
248 db8500_vrf1_reg: db8500_vrf1 {
249 regulator-name = "db8500-vrf1";
250 };
251
252 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
253 regulator-name = "db8500-sva-mmdsp";
254 };
255
256 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
257 regulator-name = "db8500-sva-mmdsp-ret";
258 };
259
260 db8500_sva_pipe_reg: db8500_sva_pipe {
261 regulator-name = "db8500_sva_pipe";
262 };
263
264 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
265 regulator-name = "db8500_sia_mmdsp";
266 };
267
268 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
269 regulator-name = "db8500-sia-mmdsp-ret";
270 };
271
272 db8500_sia_pipe_reg: db8500_sia_pipe {
273 regulator-name = "db8500-sia-pipe";
274 };
275
276 db8500_sga_reg: db8500_sga {
277 regulator-name = "db8500-sga";
278 };
279
280 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
281 regulator-name = "db8500-b2r2-mcde";
282 };
283
284 db8500_esram12_reg: db8500_esram12 {
285 regulator-name = "db8500-esram12";
286 };
287
288 db8500_esram12_ret_reg: db8500_esram12_ret {
289 regulator-name = "db8500-esram12-ret";
290 };
291
292 db8500_esram34_reg: db8500_esram34 {
293 regulator-name = "db8500-esram34";
294 };
295
296 db8500_esram34_ret_reg: db8500_esram34_ret {
297 regulator-name = "db8500-esram34-ret";
298 };
299 };
300
301 ab8500@5 {
302 ab8500-regulators {
303 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
304 regulator-name = "V-DISPLAY";
305 };
306
307 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
308 regulator-name = "V-eMMC1";
309 };
310
311 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
312 regulator-name = "V-MMC-SD";
313 };
314
315 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
316 regulator-name = "V-INTCORE";
317 };
318
319 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
320 regulator-name = "V-TVOUT";
321 };
322
323 ab8500_ldo_usb_reg: ab8500_ldo_usb {
324 regulator-name = "dummy";
325 };
326
327 ab8500_ldo_audio_reg: ab8500_ldo_audio {
328 regulator-name = "V-AUD";
329 };
330
331 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
332 regulator-name = "V-AMIC1";
333 };
334
335 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
336 regulator-name = "V-AMIC2";
337 };
338
339 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
340 regulator-name = "V-DMIC";
341 };
342
343 ab8500_ldo_ana_reg: ab8500_ldo_ana {
344 regulator-name = "V-CSI/DSI";
345 };
346 };
347 };
348 };
217 }; 349 };
218}; 350};
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
new file mode 100644
index 000000000000..39446a247e79
--- /dev/null
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc-u9500 {
14 i2c@80004000 {
15 stmpe1601: stmpe1601@40 {
16 compatible = "st,stmpe1601";
17 reg = <0x40>;
18 interrupts = <26 0x1>;
19 interrupt-parent = <&gpio6>;
20 interrupt-controller;
21
22 wakeup-source;
23 st,autosleep-timeout = <1024>;
24
25 stmpe_keypad {
26 compatible = "st,stmpe-keypad";
27
28 debounce-interval = <64>;
29 st,scan-count = <8>;
30 st,no-autorepeat;
31
32 linux,keymap = <0x205006b
33 0x4010074
34 0x3050072
35 0x1030004
36 0x502006a
37 0x500000a
38 0x5008b
39 0x706001c
40 0x405000b
41 0x6070003
42 0x3040067
43 0x303006c
44 0x60400e7
45 0x602009e
46 0x4020073
47 0x5050002
48 0x4030069
49 0x3020008>;
50 };
51 };
52 };
53
54 i2c@80110000 {
55 bu21013_tp@0x5c {
56 compatible = "rhom,bu21013_tp";
57 reg = <0x5c>;
58 touch-gpio = <&gpio2 20 0x4>;
59 avdd-supply = <&ab8500_ldo_aux1_reg>;
60
61 rhom,touch-max-x = <384>;
62 rhom,touch-max-y = <704>;
63 rhom,flip-y;
64 };
65
66 bu21013_tp@0x5d {
67 compatible = "rhom,bu21013_tp";
68 reg = <0x5d>;
69 touch-gpio = <&gpio2 20 0x4>;
70 avdd-supply = <&ab8500_ldo_aux1_reg>;
71
72 rhom,touch-max-x = <384>;
73 rhom,touch-max-y = <704>;
74 rhom,flip-y;
75 };
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 74b8a47adf91..43eb72af8948 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
262 }; 274 };
263 }; 275 };
264 276
265 i2c@7000c400 { 277 hdmi_ddc: i2c@7000c400 {
266 status = "okay"; 278 status = "okay";
267 clock-frequency = <400000>; 279 clock-frequency = <100000>;
268 }; 280 };
269 281
270 i2c@7000c500 { 282 i2c@7000c500 {
@@ -369,13 +381,13 @@
369 regulator-max-microvolt = <1800000>; 381 regulator-max-microvolt = <1800000>;
370 }; 382 };
371 383
372 ldo7 { 384 hdmi_vdd_reg: ldo7 {
373 regulator-name = "vdd_ldo7,avdd_hdmi"; 385 regulator-name = "vdd_ldo7,avdd_hdmi";
374 regulator-min-microvolt = <3300000>; 386 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>; 387 regulator-max-microvolt = <3300000>;
376 }; 388 };
377 389
378 ldo8 { 390 hdmi_pll_reg: ldo8 {
379 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 391 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
380 regulator-min-microvolt = <1800000>; 392 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <1800000>; 393 regulator-max-microvolt = <1800000>;
@@ -396,6 +408,11 @@
396 }; 408 };
397 }; 409 };
398 }; 410 };
411
412 temperature-sensor@4c {
413 compatible = "adi,adt7461";
414 reg = <0x4c>;
415 };
399 }; 416 };
400 417
401 pmc { 418 pmc {
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 331a3ef24d59..289480026fbf 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,6 +6,12 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
9 i2c@7000c000 { 15 i2c@7000c000 {
10 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index e58a0e60f711..420459825b46 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -561,6 +561,12 @@
561 status = "okay"; 561 status = "okay";
562 }; 562 };
563 563
564 sdhci@c8000000 {
565 status = "okay";
566 power-gpios = <&gpio 86 0>; /* gpio PK6 */
567 bus-width = <4>;
568 };
569
564 sdhci@c8000400 { 570 sdhci@c8000400 {
565 status = "okay"; 571 status = "okay";
566 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 572 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 5b3d8b157b33..a239ccdfaa52 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,6 +8,16 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
11 pinmux { 21 pinmux {
12 pinctrl-names = "default"; 22 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>; 23 pinctrl-0 = <&state_default>;
@@ -62,10 +72,6 @@
62 nvidia,pins = "dap4"; 72 nvidia,pins = "dap4";
63 nvidia,function = "dap4"; 73 nvidia,function = "dap4";
64 }; 74 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta { 75 dta {
70 nvidia,pins = "dta", "dtd"; 76 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2"; 77 nvidia,function = "sdio2";
@@ -91,7 +97,7 @@
91 nvidia,function = "pcie"; 97 nvidia,function = "pcie";
92 }; 98 };
93 hdint { 99 hdint {
94 nvidia,pins = "hdint", "pta"; 100 nvidia,pins = "hdint";
95 nvidia,function = "hdmi"; 101 nvidia,function = "hdmi";
96 }; 102 };
97 i2cp { 103 i2cp {
@@ -230,6 +236,39 @@
230 nvidia,pull = <1>; 236 nvidia,pull = <1>;
231 }; 237 };
232 }; 238 };
239
240 state_i2cmux_ddc: pinmux_i2cmux_ddc {
241 ddc {
242 nvidia,pins = "ddc";
243 nvidia,function = "i2c2";
244 };
245 pta {
246 nvidia,pins = "pta";
247 nvidia,function = "rsvd4";
248 };
249 };
250
251 state_i2cmux_pta: pinmux_i2cmux_pta {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "rsvd4";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "i2c2";
259 };
260 };
261
262 state_i2cmux_idle: pinmux_i2cmux_idle {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "rsvd4";
270 };
271 };
233 }; 272 };
234 273
235 i2s@70002800 { 274 i2s@70002800 {
@@ -246,6 +285,36 @@
246 status = "okay"; 285 status = "okay";
247 }; 286 };
248 287
288 i2c@7000c400 {
289 clock-frequency = <100000>;
290 status = "okay";
291 };
292
293 i2cmux {
294 compatible = "i2c-mux-pinctrl";
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c-parent = <&{/i2c@7000c400}>;
299
300 pinctrl-names = "ddc", "pta", "idle";
301 pinctrl-0 = <&state_i2cmux_ddc>;
302 pinctrl-1 = <&state_i2cmux_pta>;
303 pinctrl-2 = <&state_i2cmux_idle>;
304
305 hdmi_ddc: i2c@0 {
306 reg = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 i2c@1 {
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317
249 i2c@7000d000 { 318 i2c@7000d000 {
250 clock-frequency = <400000>; 319 clock-frequency = <400000>;
251 status = "okay"; 320 status = "okay";
@@ -348,13 +417,13 @@
348 regulator-max-microvolt = <2850000>; 417 regulator-max-microvolt = <2850000>;
349 }; 418 };
350 419
351 ldo7 { 420 hdmi_vdd_reg: ldo7 {
352 regulator-name = "vdd_ldo7,avdd_hdmi"; 421 regulator-name = "vdd_ldo7,avdd_hdmi";
353 regulator-min-microvolt = <3300000>; 422 regulator-min-microvolt = <3300000>;
354 regulator-max-microvolt = <3300000>; 423 regulator-max-microvolt = <3300000>;
355 }; 424 };
356 425
357 ldo8 { 426 hdmi_pll_reg: ldo8 {
358 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 427 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
359 regulator-min-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>;
360 regulator-max-microvolt = <1800000>; 429 regulator-max-microvolt = <1800000>;
@@ -381,6 +450,11 @@
381 }; 450 };
382 }; 451 };
383 }; 452 };
453
454 temperature-sensor@4c {
455 compatible = "onnn,nct1008";
456 reg = <0x4c>;
457 };
384 }; 458 };
385 459
386 pmc { 460 pmc {
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9aff31b0fe4a..402b21004bef 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,10 +6,13 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 i2c@7000c000 { 9 host1x {
10 clock-frequency = <400000>; 10 hdmi {
11 status = "okay"; 11 status = "okay";
12 };
13 };
12 14
15 i2c@7000c000 {
13 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
14 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
15 reg = <0x1a>; 18 reg = <0x1a>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 27fb8a67ea42..b70b4cb754c8 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -249,14 +261,24 @@
249 clock-frequency = <216000000>; 261 clock-frequency = <216000000>;
250 }; 262 };
251 263
252 i2c@7000c000 { 264 dvi_ddc: i2c@7000c000 {
253 status = "okay"; 265 status = "okay";
254 clock-frequency = <400000>; 266 clock-frequency = <100000>;
255 }; 267 };
256 268
257 i2c@7000c400 { 269 spi@7000c380 {
258 status = "okay"; 270 status = "okay";
259 clock-frequency = <400000>; 271 spi-max-frequency = <48000000>;
272 spi-flash@0 {
273 compatible = "winbond,w25q80bl";
274 reg = <0>;
275 spi-max-frequency = <48000000>;
276 };
277 };
278
279 hdmi_ddc: i2c@7000c400 {
280 status = "okay";
281 clock-frequency = <100000>;
260 }; 282 };
261 283
262 i2c@7000c500 { 284 i2c@7000c500 {
@@ -300,6 +322,30 @@
300 bus-width = <4>; 322 bus-width = <4>;
301 }; 323 };
302 324
325 regulators {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 hdmi_vdd_reg: regulator@0 {
331 compatible = "regulator-fixed";
332 reg = <0>;
333 regulator-name = "avdd_hdmi";
334 regulator-min-microvolt = <3300000>;
335 regulator-max-microvolt = <3300000>;
336 regulator-always-on;
337 };
338
339 hdmi_pll_reg: regulator@1 {
340 compatible = "regulator-fixed";
341 reg = <1>;
342 regulator-name = "avdd_hdmi_pll";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 };
347 };
348
303 sound { 349 sound {
304 compatible = "nvidia,tegra-audio-trimslice"; 350 compatible = "nvidia,tegra-audio-trimslice";
305 nvidia,i2s-controller = <&tegra_i2s1>; 351 nvidia,i2s-controller = <&tegra_i2s1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 86854f1abd58..adc47547eaae 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -64,11 +64,6 @@
64 nvidia,pins = "dap4"; 64 nvidia,pins = "dap4";
65 nvidia,function = "dap4"; 65 nvidia,function = "dap4";
66 }; 66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta { 67 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi"; 69 nvidia,function = "vi";
@@ -98,7 +93,7 @@
98 nvidia,function = "pcie"; 93 nvidia,function = "pcie";
99 }; 94 };
100 hdint { 95 hdint {
101 nvidia,pins = "hdint", "pta"; 96 nvidia,pins = "hdint";
102 nvidia,function = "hdmi"; 97 nvidia,function = "hdmi";
103 }; 98 };
104 i2cp { 99 i2cp {
@@ -129,6 +124,10 @@
129 "lspi", "lvp1", "lvs"; 124 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya"; 125 nvidia,function = "displaya";
131 }; 126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
132 pmc { 131 pmc {
133 nvidia,pins = "pmc"; 132 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on"; 133 nvidia,function = "pwr_on";
@@ -237,6 +236,49 @@
237 "ld23_22"; 236 "ld23_22";
238 nvidia,pull = <1>; 237 nvidia,pull = <1>;
239 }; 238 };
239 drive_sdio1 {
240 nvidia,pins = "drive_sdio1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <3>;
244 nvidia,pull-down-strength = <31>;
245 nvidia,pull-up-strength = <31>;
246 nvidia,slew-rate-rising = <3>;
247 nvidia,slew-rate-falling = <3>;
248 };
249 };
250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
240 }; 282 };
241 }; 283 };
242 284
@@ -281,6 +323,31 @@
281 clock-frequency = <400000>; 323 clock-frequency = <400000>;
282 }; 324 };
283 325
326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
284 i2c@7000c500 { 351 i2c@7000c500 {
285 status = "okay"; 352 status = "okay";
286 clock-frequency = <400000>; 353 clock-frequency = <400000>;
@@ -406,6 +473,11 @@
406 }; 473 };
407 }; 474 };
408 }; 475 };
476
477 temperature-sensor@4c {
478 compatible = "onnn,nct1008";
479 reg = <0x4c>;
480 };
409 }; 481 };
410 482
411 pmc { 483 pmc {
@@ -425,6 +497,12 @@
425 status = "okay"; 497 status = "okay";
426 }; 498 };
427 499
500 sdhci@c8000000 {
501 status = "okay";
502 power-gpios = <&gpio 86 0>; /* gpio PK6 */
503 bus-width = <4>;
504 };
505
428 sdhci@c8000400 { 506 sdhci@c8000400 {
429 status = "okay"; 507 status = "okay";
430 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 508 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 94a71c91beb5..20d576ecd555 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
246 clock-frequency = <216000000>; 258 clock-frequency = <216000000>;
247 }; 259 };
248 260
261 hdmi_ddc: i2c@7000c400 {
262 status = "okay";
263 clock-frequency = <100000>;
264 };
265
249 i2c@7000d000 { 266 i2c@7000d000 {
250 status = "okay"; 267 status = "okay";
251 clock-frequency = <100000>; 268 clock-frequency = <100000>;
@@ -356,7 +373,7 @@
356 regulator-always-on; 373 regulator-always-on;
357 }; 374 };
358 375
359 ldo6 { 376 hdmi_pll_reg: ldo6 {
360 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; 377 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
361 regulator-min-microvolt = <1800000>; 378 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
@@ -388,7 +405,7 @@
388 regulator-always-on; 405 regulator-always-on;
389 }; 406 };
390 407
391 ldo11 { 408 hdmi_vdd_reg: ldo11 {
392 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; 409 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
393 regulator-min-microvolt = <3300000>; 410 regulator-min-microvolt = <3300000>;
394 regulator-max-microvolt = <3300000>; 411 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f40cfbaa7c7e..fba998e3954a 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,93 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
7 cache-controller@50043000 { 94 cache-controller@50043000 {
8 compatible = "arm,pl310-cache"; 95 compatible = "arm,pl310-cache";
9 reg = <0x50043000 0x1000>; 96 reg = <0x50043000 0x1000>;
@@ -147,6 +234,16 @@
147 status = "disabled"; 234 status = "disabled";
148 }; 235 };
149 236
237 spi@7000c380 {
238 compatible = "nvidia,tegra20-sflash";
239 reg = <0x7000c380 0x80>;
240 interrupts = <0 39 0x04>;
241 nvidia,dma-request-selector = <&apbdma 11>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 status = "disabled";
245 };
246
150 i2c@7000c400 { 247 i2c@7000c400 {
151 compatible = "nvidia,tegra20-i2c"; 248 compatible = "nvidia,tegra20-i2c";
152 reg = <0x7000c400 0x100>; 249 reg = <0x7000c400 0x100>;
@@ -174,6 +271,46 @@
174 status = "disabled"; 271 status = "disabled";
175 }; 272 };
176 273
274 spi@7000d400 {
275 compatible = "nvidia,tegra20-slink";
276 reg = <0x7000d400 0x200>;
277 interrupts = <0 59 0x04>;
278 nvidia,dma-request-selector = <&apbdma 15>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 status = "disabled";
282 };
283
284 spi@7000d600 {
285 compatible = "nvidia,tegra20-slink";
286 reg = <0x7000d600 0x200>;
287 interrupts = <0 82 0x04>;
288 nvidia,dma-request-selector = <&apbdma 16>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 status = "disabled";
292 };
293
294 spi@7000d800 {
295 compatible = "nvidia,tegra20-slink";
296 reg = <0x7000d480 0x200>;
297 interrupts = <0 83 0x04>;
298 nvidia,dma-request-selector = <&apbdma 17>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
303
304 spi@7000da00 {
305 compatible = "nvidia,tegra20-slink";
306 reg = <0x7000da00 0x200>;
307 interrupts = <0 93 0x04>;
308 nvidia,dma-request-selector = <&apbdma 18>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
177 pmc { 314 pmc {
178 compatible = "nvidia,tegra20-pmc"; 315 compatible = "nvidia,tegra20-pmc";
179 reg = <0x7000e400 0x400>; 316 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index dd4222f00eca..adc88aa50eb6 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -83,5 +83,11 @@
83 gpio = <&gpio 83 0>; /* GPIO PK3 */ 83 gpio = <&gpio 83 0>; /* GPIO PK3 */
84 }; 84 };
85 }; 85 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */
90 bus-width = <4>;
91 };
86}; 92};
87 93
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 0828f097ca86..08163e145d57 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -95,4 +95,10 @@
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */ 95 gpio = <&gpio 232 0>; /* GPIO PDD0 */
96 }; 96 };
97 }; 97 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */
102 bus-width = <4>;
103 };
98}; 104};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index b1271a894327..bdb2a660f376 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -52,6 +52,22 @@
52 nvidia,pull = <2>; 52 nvidia,pull = <2>;
53 nvidia,tristate = <0>; 53 nvidia,tristate = <0>;
54 }; 54 };
55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
55 sdmmc4_clk_pcc4 { 71 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4", 72 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3"; 73 "sdmmc4_rst_n_pcc3";
@@ -81,6 +97,15 @@
81 nvidia,pull = <0>; 97 nvidia,pull = <0>;
82 nvidia,tristate = <0>; 98 nvidia,tristate = <0>;
83 }; 99 };
100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
84 }; 109 };
85 }; 110 };
86 111
@@ -250,6 +275,16 @@
250 }; 275 };
251 }; 276 };
252 277
278 spi@7000da00 {
279 status = "okay";
280 spi-max-frequency = <25000000>;
281 spi-flash@1 {
282 compatible = "winbond,w25q32";
283 reg = <1>;
284 spi-max-frequency = <20000000>;
285 };
286 };
287
253 ahub { 288 ahub {
254 i2s@70080400 { 289 i2s@70080400 {
255 status = "okay"; 290 status = "okay";
@@ -384,6 +419,8 @@
384 regulator-name = "vdd_com"; 419 regulator-name = "vdd_com";
385 regulator-min-microvolt = <3300000>; 420 regulator-min-microvolt = <3300000>;
386 regulator-max-microvolt = <3300000>; 421 regulator-max-microvolt = <3300000>;
422 regulator-always-on;
423 regulator-boot-on;
387 enable-active-high; 424 enable-active-high;
388 gpio = <&gpio 24 0>; /* gpio PD0 */ 425 gpio = <&gpio 24 0>; /* gpio PD0 */
389 vin-supply = <&sys_3v3_reg>; 426 vin-supply = <&sys_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index fed8dca1692d..efa603d47a6a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,93 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
7 cache-controller@50043000 { 94 cache-controller@50043000 {
8 compatible = "arm,pl310-cache"; 95 compatible = "arm,pl310-cache";
9 reg = <0x50043000 0x1000>; 96 reg = <0x50043000 0x1000>;
@@ -177,6 +264,66 @@
177 status = "disabled"; 264 status = "disabled";
178 }; 265 };
179 266
267 spi@7000d400 {
268 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
269 reg = <0x7000d400 0x200>;
270 interrupts = <0 59 0x04>;
271 nvidia,dma-request-selector = <&apbdma 15>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 status = "disabled";
275 };
276
277 spi@7000d600 {
278 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
279 reg = <0x7000d600 0x200>;
280 interrupts = <0 82 0x04>;
281 nvidia,dma-request-selector = <&apbdma 16>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 status = "disabled";
285 };
286
287 spi@7000d800 {
288 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
289 reg = <0x7000d480 0x200>;
290 interrupts = <0 83 0x04>;
291 nvidia,dma-request-selector = <&apbdma 17>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 spi@7000da00 {
298 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
299 reg = <0x7000da00 0x200>;
300 interrupts = <0 93 0x04>;
301 nvidia,dma-request-selector = <&apbdma 18>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 spi@7000dc00 {
308 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
309 reg = <0x7000dc00 0x200>;
310 interrupts = <0 94 0x04>;
311 nvidia,dma-request-selector = <&apbdma 27>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 spi@7000de00 {
318 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
319 reg = <0x7000de00 0x200>;
320 interrupts = <0 79 0x04>;
321 nvidia,dma-request-selector = <&apbdma 28>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
180 pmc { 327 pmc {
181 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 328 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
182 reg = <0x7000e400 0x400>; 329 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
new file mode 100644
index 000000000000..95892ec6c342
--- /dev/null
+++ b/arch/arm/boot/dts/u9540.dts
@@ -0,0 +1,72 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson U9540 platform with Device Tree";
17 compatible = "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
new file mode 100644
index 000000000000..401c1262d4ed
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14
15/ {
16 compatible = "xlnx,zynq-7000";
17
18 amba {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&intc>;
23 ranges;
24
25 intc: interrupt-controller@f8f01000 {
26 compatible = "arm,cortex-a9-gic";
27 #interrupt-cells = <3>;
28 #address-cells = <1>;
29 interrupt-controller;
30 reg = <0xF8F01000 0x1000>,
31 <0xF8F00100 0x100>;
32 };
33
34 L2: cache-controller {
35 compatible = "arm,pl310-cache";
36 reg = <0xF8F02000 0x1000>;
37 arm,data-latency = <2 3 2>;
38 arm,tag-latency = <2 3 2>;
39 cache-unified;
40 cache-level = <2>;
41 };
42
43 uart0: uart@e0000000 {
44 compatible = "xlnx,xuartps";
45 reg = <0xE0000000 0x1000>;
46 interrupts = <0 27 4>;
47 clock = <50000000>;
48 };
49
50 uart1: uart@e0001000 {
51 compatible = "xlnx,xuartps";
52 reg = <0xE0001000 0x1000>;
53 interrupts = <0 50 4>;
54 clock = <50000000>;
55 };
56
57 slcr: slcr@f8000000 {
58 compatible = "xlnx,zynq-slcr";
59 reg = <0xF8000000 0x1000>;
60
61 clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ps_clk: ps_clk {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 /* clock-frequency set in board-specific file */
69 clock-output-names = "ps_clk";
70 };
71 armpll: armpll {
72 #clock-cells = <0>;
73 compatible = "xlnx,zynq-pll";
74 clocks = <&ps_clk>;
75 reg = <0x100 0x110>;
76 clock-output-names = "armpll";
77 };
78 ddrpll: ddrpll {
79 #clock-cells = <0>;
80 compatible = "xlnx,zynq-pll";
81 clocks = <&ps_clk>;
82 reg = <0x104 0x114>;
83 clock-output-names = "ddrpll";
84 };
85 iopll: iopll {
86 #clock-cells = <0>;
87 compatible = "xlnx,zynq-pll";
88 clocks = <&ps_clk>;
89 reg = <0x108 0x118>;
90 clock-output-names = "iopll";
91 };
92 uart_clk: uart_clk {
93 #clock-cells = <1>;
94 compatible = "xlnx,zynq-periph-clock";
95 clocks = <&iopll &armpll &ddrpll>;
96 reg = <0x154>;
97 clock-output-names = "uart0_ref_clk",
98 "uart1_ref_clk";
99 };
100 cpu_clk: cpu_clk {
101 #clock-cells = <1>;
102 compatible = "xlnx,zynq-cpu-clock";
103 clocks = <&iopll &armpll &ddrpll>;
104 reg = <0x120 0x1C4>;
105 clock-output-names = "cpu_6x4x",
106 "cpu_3x2x",
107 "cpu_2x",
108 "cpu_1x";
109 };
110 };
111 };
112
113 ttc0: ttc0@f8001000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "xlnx,ttc";
117 reg = <0xF8001000 0x1000>;
118 clocks = <&cpu_clk 3>;
119 clock-names = "cpu_1x";
120 clock-ranges;
121
122 ttc0_0: ttc0.0 {
123 status = "disabled";
124 reg = <0>;
125 interrupts = <0 10 4>;
126 };
127 ttc0_1: ttc0.1 {
128 status = "disabled";
129 reg = <1>;
130 interrupts = <0 11 4>;
131 };
132 ttc0_2: ttc0.2 {
133 status = "disabled";
134 reg = <2>;
135 interrupts = <0 12 4>;
136 };
137 };
138
139 ttc1: ttc1@f8002000 {
140 #interrupt-parent = <&intc>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "xlnx,ttc";
144 reg = <0xF8002000 0x1000>;
145 clocks = <&cpu_clk 3>;
146 clock-names = "cpu_1x";
147 clock-ranges;
148
149 ttc1_0: ttc1.0 {
150 status = "disabled";
151 reg = <0>;
152 interrupts = <0 37 4>;
153 };
154 ttc1_1: ttc1.1 {
155 status = "disabled";
156 reg = <1>;
157 interrupts = <0 38 4>;
158 };
159 ttc1_2: ttc1.2 {
160 status = "disabled";
161 reg = <2>;
162 interrupts = <0 39 4>;
163 };
164 };
165 };
166};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
deleted file mode 100644
index 574bc044f572..000000000000
--- a/arch/arm/boot/dts/zynq-ep107.dts
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/ {
16 model = "Xilinx Zynq EP107";
17 compatible = "xlnx,zynq-ep107";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
21
22 memory {
23 device_type = "memory";
24 reg = <0x0 0x10000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
29 linux,stdout-path = &uart0;
30 };
31
32 amba {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 intc: interrupt-controller@f8f01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 interrupt-controller;
43 reg = <0xF8F01000 0x1000>,
44 <0xF8F00100 0x100>;
45 };
46
47 L2: cache-controller {
48 compatible = "arm,pl310-cache";
49 reg = <0xF8F02000 0x1000>;
50 arm,data-latency = <2 3 2>;
51 arm,tag-latency = <2 3 2>;
52 cache-unified;
53 cache-level = <2>;
54 };
55
56 uart0: uart@e0000000 {
57 compatible = "xlnx,xuartps";
58 reg = <0xE0000000 0x1000>;
59 interrupts = <0 27 4>;
60 clock = <50000000>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
new file mode 100644
index 000000000000..c772942a399a
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x40000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyPS1,115200 earlyprintk";
28 };
29
30};
31
32&ps_clk {
33 clock-frequency = <33333330>;
34};
35
36&ttc0_0 {
37 status = "ok";
38 compatible = "xlnx,ttc-counter-clocksource";
39};
40
41&ttc0_1 {
42 status = "ok";
43 compatible = "xlnx,ttc-counter-clockevent";
44};
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 048aaca60814..7bf535104e26 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -61,6 +61,8 @@ CONFIG_MTD_NAND_GPMI_NAND=y
61CONFIG_NETDEVICES=y 61CONFIG_NETDEVICES=y
62CONFIG_NET_ETHERNET=y 62CONFIG_NET_ETHERNET=y
63CONFIG_ENC28J60=y 63CONFIG_ENC28J60=y
64CONFIG_USB_USBNET=y
65CONFIG_USB_NET_SMSC95XX=y
64# CONFIG_NETDEV_1000 is not set 66# CONFIG_NETDEV_1000 is not set
65# CONFIG_NETDEV_10000 is not set 67# CONFIG_NETDEV_10000 is not set
66# CONFIG_WLAN is not set 68# CONFIG_WLAN is not set
@@ -158,6 +160,10 @@ CONFIG_NFS_V3=y
158CONFIG_NFS_V3_ACL=y 160CONFIG_NFS_V3_ACL=y
159CONFIG_NFS_V4=y 161CONFIG_NFS_V4=y
160CONFIG_ROOT_NFS=y 162CONFIG_ROOT_NFS=y
163CONFIG_NLS_CODEPAGE_437=y
164CONFIG_NLS_CODEPAGE_850=y
165CONFIG_NLS_ISO8859_1=y
166CONFIG_NLS_ISO8859_15=y
161CONFIG_PRINTK_TIME=y 167CONFIG_PRINTK_TIME=y
162CONFIG_FRAME_WARN=2048 168CONFIG_FRAME_WARN=2048
163CONFIG_MAGIC_SYSRQ=y 169CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 250625d5223f..231dca604737 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -78,6 +78,7 @@ CONFIG_AB8500_CORE=y
78CONFIG_REGULATOR=y 78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_AB8500=y 79CONFIG_REGULATOR_AB8500=y
80CONFIG_REGULATOR_FIXED_VOLTAGE=y 80CONFIG_REGULATOR_FIXED_VOLTAGE=y
81CONFIG_REGULATOR_GPIO=y
81# CONFIG_HID_SUPPORT is not set 82# CONFIG_HID_SUPPORT is not set
82CONFIG_USB_GADGET=y 83CONFIG_USB_GADGET=y
83CONFIG_AB8500_USB=y 84CONFIG_AB8500_USB=y
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index 0b65d792f664..0c4e17d4d359 100644
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -10,6 +10,20 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX6Q_UART1_BASE_ADDR 0x02020000
14#define IMX6Q_UART2_BASE_ADDR 0x021e8000
15#define IMX6Q_UART3_BASE_ADDR 0x021ec000
16#define IMX6Q_UART4_BASE_ADDR 0x021f0000
17#define IMX6Q_UART5_BASE_ADDR 0x021f4000
18
19/*
20 * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
21 * of IMX6Q_UART##n##_BASE_ADDR.
22 */
23#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
24#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
25#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
26
13#ifdef CONFIG_DEBUG_IMX1_UART 27#ifdef CONFIG_DEBUG_IMX1_UART
14#define UART_PADDR 0x00206000 28#define UART_PADDR 0x00206000
15#elif defined (CONFIG_DEBUG_IMX25_UART) 29#elif defined (CONFIG_DEBUG_IMX25_UART)
@@ -22,10 +36,8 @@
22#define UART_PADDR 0x73fbc000 36#define UART_PADDR 0x73fbc000
23#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) 37#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
24#define UART_PADDR 0x53fbc000 38#define UART_PADDR 0x53fbc000
25#elif defined (CONFIG_DEBUG_IMX6Q_UART2) 39#elif defined (CONFIG_DEBUG_IMX6Q_UART)
26#define UART_PADDR 0x021e8000 40#define UART_PADDR IMX6Q_DEBUG_UART_BASE
27#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
28#define UART_PADDR 0x021f0000
29#endif 41#endif
30 42
31/* 43/*
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
index 5c5a95a9d7d2..04a6c4e67b14 100644
--- a/arch/arm/mach-davinci/Makefile.boot
+++ b/arch/arm/mach-davinci/Makefile.boot
@@ -11,5 +11,3 @@ else
11params_phys-y := 0x80000100 11params_phys-y := 0x80000100
12initrd_phys-y := 0x80800000 12initrd_phys-y := 0x80800000
13endif 13endif
14
15dtb-$(CONFIG_MACH_DA8XX_DT) += da850-enbw-cmc.dtb da850-evm.dtb
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 070c7b6d3d86..91d5b6f1d5af 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select S5P_PM if PM 64 select S5P_PM if PM
65 select S5P_SLEEP if PM 65 select S5P_SLEEP if PM
66 select S5P_DEV_MFC
66 select SAMSUNG_DMADEV 67 select SAMSUNG_DMADEV
67 help 68 help
68 Enable EXYNOS5250 SoC support 69 Enable EXYNOS5250 SoC support
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 66135eedf491..b189881657ec 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o 53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
55obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
56obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o 55obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
57 56
58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 57obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index fa8a13405c94..efead60b9436 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -576,6 +576,10 @@ static struct clk exynos4_init_clocks_off[] = {
576 .enable = exynos4_clk_ip_peril_ctrl, 576 .enable = exynos4_clk_ip_peril_ctrl,
577 .ctrlbit = (1 << 15), 577 .ctrlbit = (1 << 15),
578 }, { 578 }, {
579 .name = "tmu_apbif",
580 .enable = exynos4_clk_ip_perir_ctrl,
581 .ctrlbit = (1 << 17),
582 }, {
579 .name = "keypad", 583 .name = "keypad",
580 .enable = exynos4_clk_ip_perir_ctrl, 584 .enable = exynos4_clk_ip_perir_ctrl,
581 .ctrlbit = (1 << 16), 585 .ctrlbit = (1 << 16),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 4478757b9301..7652f5d78a56 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -196,6 +196,11 @@ static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
196 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable); 196 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
197} 197}
198 198
199static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
200{
201 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
202}
203
199/* Core list of CMU_CPU side */ 204/* Core list of CMU_CPU side */
200 205
201static struct clksrc_clk exynos5_clk_mout_apll = { 206static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -616,6 +621,11 @@ static struct clk exynos5_init_clocks_off[] = {
616 .enable = exynos5_clk_ip_peric_ctrl, 621 .enable = exynos5_clk_ip_peric_ctrl,
617 .ctrlbit = (1 << 24), 622 .ctrlbit = (1 << 24),
618 }, { 623 }, {
624 .name = "tmu_apbif",
625 .parent = &exynos5_clk_aclk_66.clk,
626 .enable = exynos5_clk_ip_peris_ctrl,
627 .ctrlbit = (1 << 21),
628 }, {
619 .name = "rtc", 629 .name = "rtc",
620 .parent = &exynos5_clk_aclk_66.clk, 630 .parent = &exynos5_clk_aclk_66.clk,
621 .enable = exynos5_clk_ip_peris_ctrl, 631 .enable = exynos5_clk_ip_peris_ctrl,
@@ -664,17 +674,22 @@ static struct clk exynos5_init_clocks_off[] = {
664 .ctrlbit = (1 << 25), 674 .ctrlbit = (1 << 25),
665 }, { 675 }, {
666 .name = "mfc", 676 .name = "mfc",
667 .devname = "s5p-mfc", 677 .devname = "s5p-mfc-v6",
668 .enable = exynos5_clk_ip_mfc_ctrl, 678 .enable = exynos5_clk_ip_mfc_ctrl,
669 .ctrlbit = (1 << 0), 679 .ctrlbit = (1 << 0),
670 }, { 680 }, {
671 .name = "hdmi", 681 .name = "hdmi",
672 .devname = "exynos4-hdmi", 682 .devname = "exynos5-hdmi",
673 .enable = exynos5_clk_ip_disp1_ctrl, 683 .enable = exynos5_clk_ip_disp1_ctrl,
674 .ctrlbit = (1 << 6), 684 .ctrlbit = (1 << 6),
675 }, { 685 }, {
686 .name = "hdmiphy",
687 .devname = "exynos5-hdmi",
688 .enable = exynos5_clk_hdmiphy_ctrl,
689 .ctrlbit = (1 << 0),
690 }, {
676 .name = "mixer", 691 .name = "mixer",
677 .devname = "s5p-mixer", 692 .devname = "exynos5-mixer",
678 .enable = exynos5_clk_ip_disp1_ctrl, 693 .enable = exynos5_clk_ip_disp1_ctrl,
679 .ctrlbit = (1 << 5), 694 .ctrlbit = (1 << 5),
680 }, { 695 }, {
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index e05f6cca2c9b..3f257e76bfde 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -1020,11 +1020,14 @@ static int __init exynos_init_irq_eint(void)
1020 * platforms switch over to using the pinctrl driver, the wakeup 1020 * platforms switch over to using the pinctrl driver, the wakeup
1021 * interrupt support code here can be completely removed. 1021 * interrupt support code here can be completely removed.
1022 */ 1022 */
1023 static const struct of_device_id exynos_pinctrl_ids[] = {
1024 { .compatible = "samsung,pinctrl-exynos4210", },
1025 { .compatible = "samsung,pinctrl-exynos4x12", },
1026 };
1023 struct device_node *pctrl_np, *wkup_np; 1027 struct device_node *pctrl_np, *wkup_np;
1024 const char *pctrl_compat = "samsung,pinctrl-exynos4210";
1025 const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; 1028 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1026 1029
1027 for_each_compatible_node(pctrl_np, NULL, pctrl_compat) { 1030 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
1028 if (of_device_is_available(pctrl_np)) { 1031 if (of_device_is_available(pctrl_np)) {
1029 wkup_np = of_find_compatible_node(pctrl_np, NULL, 1032 wkup_np = of_find_compatible_node(pctrl_np, NULL,
1030 wkup_compat); 1033 wkup_compat);
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
deleted file mode 100644
index 17c9c6ecc2e0..000000000000
--- a/arch/arm/mach-exynos/dev-drm.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos/dev-drm.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS - core DRM device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20
21static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
22
23struct platform_device exynos_device_drm = {
24 .name = "exynos-drm",
25 .dev = {
26 .dma_mask = &exynos_drm_dma_mask,
27 .coherent_dma_mask = DMA_BIT_MASK(32),
28 }
29};
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index e0f0ae3e0cf9..1f4dc35cd4b9 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -136,6 +136,9 @@
136#define EXYNOS4_IRQ_TSI IRQ_SPI(115) 136#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
137#define EXYNOS4_IRQ_SATA IRQ_SPI(116) 137#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
138 138
139#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
140#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
141
139#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 142#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
140#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) 143#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
141#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) 144#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 61b74e12d12b..1df6abbf53b8 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,6 +89,8 @@
89#define EXYNOS4_PA_TWD 0x10500600 89#define EXYNOS4_PA_TWD 0x10500600
90#define EXYNOS4_PA_L2CC 0x10502000 90#define EXYNOS4_PA_L2CC 0x10502000
91 91
92#define EXYNOS4_PA_TMU 0x100C0000
93
92#define EXYNOS4_PA_MDMA0 0x10810000 94#define EXYNOS4_PA_MDMA0 0x10810000
93#define EXYNOS4_PA_MDMA1 0x12850000 95#define EXYNOS4_PA_MDMA1 0x12850000
94#define EXYNOS4_PA_S_MDMA1 0x12840000 96#define EXYNOS4_PA_S_MDMA1 0x12840000
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 6df99c06419d..92757ff817ae 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -78,6 +78,8 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
78 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), 78 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
79 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), 79 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
80 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL), 80 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
81 OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
82 "exynos-tmu", NULL),
81 {}, 83 {},
82}; 84};
83 85
@@ -95,6 +97,8 @@ static void __init exynos4_dt_machine_init(void)
95 97
96static char const *exynos4_dt_compat[] __initdata = { 98static char const *exynos4_dt_compat[] __initdata = {
97 "samsung,exynos4210", 99 "samsung,exynos4210",
100 "samsung,exynos4212",
101 "samsung,exynos4412",
98 NULL 102 NULL
99}; 103};
100 104
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f1326be80b91..929de766d490 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -12,6 +12,8 @@
12#include <linux/of_platform.h> 12#include <linux/of_platform.h>
13#include <linux/of_fdt.h> 13#include <linux/of_fdt.h>
14#include <linux/serial_core.h> 14#include <linux/serial_core.h>
15#include <linux/memblock.h>
16#include <linux/of_fdt.h>
15 17
16#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
17#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
@@ -19,6 +21,7 @@
19 21
20#include <plat/cpu.h> 22#include <plat/cpu.h>
21#include <plat/regs-serial.h> 23#include <plat/regs-serial.h>
24#include <plat/mfc.h>
22 25
23#include "common.h" 26#include "common.h"
24 27
@@ -48,6 +51,20 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
48 "s3c2440-i2c.0", NULL), 51 "s3c2440-i2c.0", NULL),
49 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), 52 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
50 "s3c2440-i2c.1", NULL), 53 "s3c2440-i2c.1", NULL),
54 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
55 "s3c2440-i2c.2", NULL),
56 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
57 "s3c2440-i2c.3", NULL),
58 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
59 "s3c2440-i2c.4", NULL),
60 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
61 "s3c2440-i2c.5", NULL),
62 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
63 "s3c2440-i2c.6", NULL),
64 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
65 "s3c2440-i2c.7", NULL),
66 OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
67 "s3c2440-hdmiphy-i2c", NULL),
51 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0, 68 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
52 "dw_mmc.0", NULL), 69 "dw_mmc.0", NULL),
53 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1, 70 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
@@ -62,6 +79,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
62 "exynos4210-spi.1", NULL), 79 "exynos4210-spi.1", NULL),
63 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, 80 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
64 "exynos4210-spi.2", NULL), 81 "exynos4210-spi.2", NULL),
82 OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
83 "exynos5-sata", NULL),
84 OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
85 "exynos5-sata-phy", NULL),
86 OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
87 "exynos5-sata-phy-i2c", NULL),
65 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), 88 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
66 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), 89 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
67 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), 90 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
@@ -73,6 +96,13 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
73 "exynos-gsc.2", NULL), 96 "exynos-gsc.2", NULL),
74 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3, 97 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
75 "exynos-gsc.3", NULL), 98 "exynos-gsc.3", NULL),
99 OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
100 "exynos5-hdmi", NULL),
101 OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
102 "exynos5-mixer", NULL),
103 OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
104 OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
105 "exynos-tmu", NULL),
76 {}, 106 {},
77}; 107};
78 108
@@ -108,6 +138,17 @@ static char const *exynos5_dt_compat[] __initdata = {
108 NULL 138 NULL
109}; 139};
110 140
141static void __init exynos5_reserve(void)
142{
143 struct s5p_mfc_dt_meminfo mfc_mem;
144
145 /* Reserve memory for MFC only if it's available */
146 mfc_mem.compatible = "samsung,mfc-v6";
147 if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
148 s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
149 mfc_mem.lsize);
150}
151
111DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") 152DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
112 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 153 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
113 .init_irq = exynos5_init_irq, 154 .init_irq = exynos5_init_irq,
@@ -119,4 +160,5 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
119 .timer = &exynos4_timer, 160 .timer = &exynos4_timer,
120 .dt_compat = exynos5_dt_compat, 161 .dt_compat = exynos5_dt_compat,
121 .restart = exynos5_restart, 162 .restart = exynos5_restart,
163 .reserve = exynos5_reserve,
122MACHINE_END 164MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 69359a0c8a1c..27d4ed8b116e 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1326,9 +1326,6 @@ static struct platform_device *nuri_devices[] __initdata = {
1326 &cam_vdda_fixed_rdev, 1326 &cam_vdda_fixed_rdev,
1327 &cam_8m_12v_fixed_rdev, 1327 &cam_8m_12v_fixed_rdev,
1328 &exynos4_bus_devfreq, 1328 &exynos4_bus_devfreq,
1329#ifdef CONFIG_DRM_EXYNOS
1330 &exynos_device_drm,
1331#endif
1332}; 1329};
1333 1330
1334static void __init nuri_map_io(void) 1331static void __init nuri_map_io(void)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index c606080b5dfa..e6f4191cd14c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -711,9 +711,6 @@ static struct platform_device *origen_devices[] __initdata = {
711 &s5p_device_mfc_l, 711 &s5p_device_mfc_l,
712 &s5p_device_mfc_r, 712 &s5p_device_mfc_r,
713 &s5p_device_mixer, 713 &s5p_device_mixer,
714#ifdef CONFIG_DRM_EXYNOS
715 &exynos_device_drm,
716#endif
717 &exynos4_device_ohci, 714 &exynos4_device_ohci,
718 &origen_device_gpiokeys, 715 &origen_device_gpiokeys,
719 &origen_lcd_hv070wsa, 716 &origen_lcd_hv070wsa,
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index ddb92631252d..a1555a73c7af 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -317,9 +317,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
317 &s5p_device_mfc, 317 &s5p_device_mfc,
318 &s5p_device_mfc_l, 318 &s5p_device_mfc_l,
319 &s5p_device_mfc_r, 319 &s5p_device_mfc_r,
320#ifdef CONFIG_DRM_EXYNOS
321 &exynos_device_drm,
322#endif
323 &samsung_device_keypad, 320 &samsung_device_keypad,
324}; 321};
325 322
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 8dd6a1e8030d..063cb94b934d 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -300,9 +300,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
300 &s5p_device_fimc_md, 300 &s5p_device_fimc_md,
301 &s5p_device_g2d, 301 &s5p_device_g2d,
302 &s5p_device_jpeg, 302 &s5p_device_jpeg,
303#ifdef CONFIG_DRM_EXYNOS
304 &exynos_device_drm,
305#endif
306 &exynos4_device_ac97, 303 &exynos4_device_ac97,
307 &exynos4_device_i2s0, 304 &exynos4_device_i2s0,
308 &exynos4_device_ohci, 305 &exynos4_device_ohci,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 2d6bc83d5c99..9e3340f18950 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1080,9 +1080,6 @@ static struct platform_device *universal_devices[] __initdata = {
1080 &s5p_device_onenand, 1080 &s5p_device_onenand,
1081 &s5p_device_fimd0, 1081 &s5p_device_fimd0,
1082 &s5p_device_jpeg, 1082 &s5p_device_jpeg,
1083#ifdef CONFIG_DRM_EXYNOS
1084 &exynos_device_drm,
1085#endif
1086 &s3c_device_usb_hsotg, 1083 &s3c_device_usb_hsotg,
1087 &s5p_device_mfc, 1084 &s5p_device_mfc,
1088 &s5p_device_mfc_l, 1085 &s5p_device_mfc_l,
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index c0bc83a7663e..9f1351de52f7 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -19,6 +19,8 @@
19#include <linux/pm_domain.h> 19#include <linux/pm_domain.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/of_platform.h>
23#include <linux/sched.h>
22 24
23#include <mach/regs-pmu.h> 25#include <mach/regs-pmu.h>
24#include <plat/devs.h> 26#include <plat/devs.h>
@@ -83,12 +85,88 @@ static struct exynos_pm_domain PD = { \
83} 85}
84 86
85#ifdef CONFIG_OF 87#ifdef CONFIG_OF
88static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
89 struct device *dev)
90{
91 int ret;
92
93 dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
94
95 while (1) {
96 ret = pm_genpd_add_device(&pd->pd, dev);
97 if (ret != -EAGAIN)
98 break;
99 cond_resched();
100 }
101
102 pm_genpd_dev_need_restore(dev, true);
103}
104
105static void exynos_remove_device_from_domain(struct device *dev)
106{
107 struct generic_pm_domain *genpd = dev_to_genpd(dev);
108 int ret;
109
110 dev_dbg(dev, "removing from power domain %s\n", genpd->name);
111
112 while (1) {
113 ret = pm_genpd_remove_device(genpd, dev);
114 if (ret != -EAGAIN)
115 break;
116 cond_resched();
117 }
118}
119
120static void exynos_read_domain_from_dt(struct device *dev)
121{
122 struct platform_device *pd_pdev;
123 struct exynos_pm_domain *pd;
124 struct device_node *node;
125
126 node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
127 if (!node)
128 return;
129 pd_pdev = of_find_device_by_node(node);
130 if (!pd_pdev)
131 return;
132 pd = platform_get_drvdata(pd_pdev);
133 exynos_add_device_to_domain(pd, dev);
134}
135
136static int exynos_pm_notifier_call(struct notifier_block *nb,
137 unsigned long event, void *data)
138{
139 struct device *dev = data;
140
141 switch (event) {
142 case BUS_NOTIFY_BIND_DRIVER:
143 if (dev->of_node)
144 exynos_read_domain_from_dt(dev);
145
146 break;
147
148 case BUS_NOTIFY_UNBOUND_DRIVER:
149 exynos_remove_device_from_domain(dev);
150
151 break;
152 }
153 return NOTIFY_DONE;
154}
155
156static struct notifier_block platform_nb = {
157 .notifier_call = exynos_pm_notifier_call,
158};
159
86static __init int exynos_pm_dt_parse_domains(void) 160static __init int exynos_pm_dt_parse_domains(void)
87{ 161{
162 struct platform_device *pdev;
88 struct device_node *np; 163 struct device_node *np;
89 164
90 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { 165 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
91 struct exynos_pm_domain *pd; 166 struct exynos_pm_domain *pd;
167 int on;
168
169 pdev = of_find_device_by_node(np);
92 170
93 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 171 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
94 if (!pd) { 172 if (!pd) {
@@ -97,15 +175,22 @@ static __init int exynos_pm_dt_parse_domains(void)
97 return -ENOMEM; 175 return -ENOMEM;
98 } 176 }
99 177
100 if (of_get_property(np, "samsung,exynos4210-pd-off", NULL)) 178 pd->pd.name = kstrdup(np->name, GFP_KERNEL);
101 pd->is_off = true; 179 pd->name = pd->pd.name;
102 pd->name = np->name;
103 pd->base = of_iomap(np, 0); 180 pd->base = of_iomap(np, 0);
104 pd->pd.power_off = exynos_pd_power_off; 181 pd->pd.power_off = exynos_pd_power_off;
105 pd->pd.power_on = exynos_pd_power_on; 182 pd->pd.power_on = exynos_pd_power_on;
106 pd->pd.of_node = np; 183 pd->pd.of_node = np;
107 pm_genpd_init(&pd->pd, NULL, false); 184
185 platform_set_drvdata(pdev, pd);
186
187 on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
188
189 pm_genpd_init(&pd->pd, NULL, !on);
108 } 190 }
191
192 bus_register_notifier(&platform_bus_type, &platform_nb);
193
109 return 0; 194 return 0;
110} 195}
111#else 196#else
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4e24b8c77eb4..1ad0d76de8c7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -272,6 +272,13 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
272 272
273endchoice 273endchoice
274 274
275config MACH_IMX25_DT
276 bool "Support i.MX25 platforms from device tree"
277 select SOC_IMX25
278 help
279 Include support for Freescale i.MX25 based platforms
280 using the device tree for discovery
281
275comment "MX27 platforms:" 282comment "MX27 platforms:"
276 283
277config MACH_MX27ADS 284config MACH_MX27ADS
@@ -831,7 +838,14 @@ config SOC_IMX53
831 838
832config SOC_IMX6Q 839config SOC_IMX6Q
833 bool "i.MX6 Quad support" 840 bool "i.MX6 Quad support"
841 select ARCH_HAS_CPUFREQ
842 select ARCH_HAS_OPP
834 select ARM_CPU_SUSPEND if PM 843 select ARM_CPU_SUSPEND if PM
844 select ARM_ERRATA_743622
845 select ARM_ERRATA_751472
846 select ARM_ERRATA_754322
847 select ARM_ERRATA_764369 if SMP
848 select ARM_ERRATA_775420
835 select ARM_GIC 849 select ARM_GIC
836 select COMMON_CLK 850 select COMMON_CLK
837 select CPU_V7 851 select CPU_V7
@@ -843,6 +857,10 @@ config SOC_IMX6Q
843 select MFD_SYSCON 857 select MFD_SYSCON
844 select PINCTRL 858 select PINCTRL
845 select PINCTRL_IMX6Q 859 select PINCTRL_IMX6Q
860 select PL310_ERRATA_588369 if CACHE_PL310
861 select PL310_ERRATA_727915 if CACHE_PL310
862 select PL310_ERRATA_769419 if CACHE_PL310
863 select PM_OPP if PM
846 864
847 help 865 help
848 This enables support for Freescale i.MX6 Quad processor. 866 This enables support for Freescale i.MX6 Quad processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fe47b71469c9..0634b3152c24 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
50obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o 50obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
51obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o 51obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
52obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o 52obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
53obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
53 54
54# i.MX27 based machines 55# i.MX27 based machines
55obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 56obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index bc885801cd68..b197aa73dc4b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -23,6 +23,9 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
26 29
27#include "clk.h" 30#include "clk.h"
28#include "common.h" 31#include "common.h"
@@ -55,6 +58,8 @@
55 58
56#define ccm(x) (CRM_BASE + (x)) 59#define ccm(x) (CRM_BASE + (x))
57 60
61static struct clk_onecell_data clk_data;
62
58static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", }; 63static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
59static const char *per_sel_clks[] = { "ahb", "upll", }; 64static const char *per_sel_clks[] = { "ahb", "upll", };
60 65
@@ -64,24 +69,30 @@ enum mx25_clks {
64 per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, 69 per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
65 per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, 70 per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
66 per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, 71 per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
67 csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per, 72 csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
68 lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per, 73 gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
69 csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb, 74 pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
70 usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg, 75 uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
71 cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg, 76 esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
72 kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg, 77 reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
73 ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg, 78 cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
74 uart4_ipg, uart5_ipg, wdt_ipg, clk_max 79 reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
80 gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
81 iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
82 pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
83 sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
84 uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
85 wdt_ipg, clk_max
75}; 86};
76 87
77static struct clk *clk[clk_max]; 88static struct clk *clk[clk_max];
78 89
79int __init mx25_clocks_init(void) 90static int __init __mx25_clocks_init(unsigned long osc_rate)
80{ 91{
81 int i; 92 int i;
82 93
83 clk[dummy] = imx_clk_fixed("dummy", 0); 94 clk[dummy] = imx_clk_fixed("dummy", 0);
84 clk[osc] = imx_clk_fixed("osc", 24000000); 95 clk[osc] = imx_clk_fixed("osc", osc_rate);
85 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); 96 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
86 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); 97 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
87 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); 98 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@@ -123,22 +134,36 @@ int __init mx25_clocks_init(void)
123 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6); 134 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
124 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6); 135 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
125 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); 136 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
137 clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1);
138 clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2);
126 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); 139 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
127 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); 140 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
128 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); 141 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
129 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); 142 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
130 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); 143 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
131 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); 144 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
145 clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9);
146 clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10);
147 clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11);
148 clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12);
132 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); 149 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
133 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); 150 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
134 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); 151 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
152 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
153 /* CCM_CGCR0(17): reserved */
135 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); 154 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
155 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
156 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
136 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); 157 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
137 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22); 158 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
138 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); 159 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
139 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24); 160 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
161 clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
140 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26); 162 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
163 clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
141 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28); 164 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
165 /* CCM_CGCR0(29-31): reserved */
166 /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
142 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); 167 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
143 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); 168 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
144 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); 169 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
@@ -146,17 +171,41 @@ int __init mx25_clocks_init(void)
146 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); 171 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
147 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); 172 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
148 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); 173 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
174 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9);
175 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10);
176 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11);
177 /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
149 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); 178 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
150 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); 179 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
151 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); 180 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
181 /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
182 /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
183 /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
184 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
185 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
186 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
187 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
188 /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
189 /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
190 /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
152 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); 191 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
192 /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
193 /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
153 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); 194 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
154 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); 195 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
196 /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
155 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); 197 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
156 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); 198 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
157 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); 199 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
158 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); 200 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
201 clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3);
202 /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
203 clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5);
159 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); 204 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
205 clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7);
206 clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8);
207 clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9);
208 clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10);
160 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); 209 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
161 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); 210 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
162 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); 211 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
@@ -165,6 +214,7 @@ int __init mx25_clocks_init(void)
165 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); 214 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
166 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); 215 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
167 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); 216 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
217 /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
168 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); 218 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
169 219
170 for (i = 0; i < ARRAY_SIZE(clk); i++) 220 for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -172,6 +222,18 @@ int __init mx25_clocks_init(void)
172 pr_err("i.MX25 clk %d: register failed with %ld\n", 222 pr_err("i.MX25 clk %d: register failed with %ld\n",
173 i, PTR_ERR(clk[i])); 223 i, PTR_ERR(clk[i]));
174 224
225 clk_prepare_enable(clk[emi_ahb]);
226
227 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
228 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
229
230 return 0;
231}
232
233int __init mx25_clocks_init(void)
234{
235 __mx25_clocks_init(24000000);
236
175 /* i.mx25 has the i.mx21 type uart */ 237 /* i.mx25 has the i.mx21 type uart */
176 clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); 238 clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
177 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); 239 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@@ -183,8 +245,6 @@ int __init mx25_clocks_init(void)
183 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3"); 245 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
184 clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4"); 246 clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
185 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4"); 247 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
186 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
187 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
188 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); 248 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
189 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0"); 249 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
190 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); 250 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
@@ -242,5 +302,40 @@ int __init mx25_clocks_init(void)
242 clk_register_clkdev(clk[iim_ipg], "iim", NULL); 302 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
243 303
244 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); 304 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
305
306 return 0;
307}
308
309int __init mx25_clocks_init_dt(void)
310{
311 struct device_node *np;
312 void __iomem *base;
313 int irq;
314 unsigned long osc_rate = 24000000;
315
316 /* retrieve the freqency of fixed clocks from device tree */
317 for_each_compatible_node(np, NULL, "fixed-clock") {
318 u32 rate;
319 if (of_property_read_u32(np, "clock-frequency", &rate))
320 continue;
321
322 if (of_device_is_compatible(np, "fsl,imx-osc"))
323 osc_rate = rate;
324 }
325
326 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
327 clk_data.clks = clk;
328 clk_data.clk_num = ARRAY_SIZE(clk);
329 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
330
331 __mx25_clocks_init(osc_rate);
332
333 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
334 base = of_iomap(np, 0);
335 WARN_ON(!base);
336 irq = irq_of_parse_and_map(np, 0);
337
338 mxc_timer_init(base, irq);
339
245 return 0; 340 return 0;
246} 341}
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 448476958e7f..7f2c10c7413a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -424,6 +424,7 @@ int __init mx6q_clocks_init(void)
424 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 424 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
425 clk_register_clkdev(clk[ahb], "ahb", NULL); 425 clk_register_clkdev(clk[ahb], "ahb", NULL);
426 clk_register_clkdev(clk[cko1], "cko1", NULL); 426 clk_register_clkdev(clk[cko1], "cko1", NULL);
427 clk_register_clkdev(clk[arm], NULL, "cpu0");
427 428
428 /* 429 /*
429 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 430 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index ef8db6b34841..7191ab4434e5 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -66,6 +66,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
66 unsigned long ckih1, unsigned long ckih2); 66 unsigned long ckih1, unsigned long ckih2);
67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
68 unsigned long ckih1, unsigned long ckih2); 68 unsigned long ckih1, unsigned long ckih2);
69extern int mx25_clocks_init_dt(void);
69extern int mx27_clocks_init_dt(void); 70extern int mx27_clocks_init_dt(void);
70extern int mx31_clocks_init_dt(void); 71extern int mx31_clocks_init_dt(void);
71extern int mx51_clocks_init_dt(void); 72extern int mx51_clocks_init_dt(void);
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
new file mode 100644
index 000000000000..e17dfbc42192
--- /dev/null
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/irq.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/time.h>
17#include "common.h"
18#include "mx25.h"
19
20static void __init imx25_dt_init(void)
21{
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23}
24
25static void __init imx25_timer_init(void)
26{
27 mx25_clocks_init_dt();
28}
29
30static struct sys_timer imx25_timer = {
31 .init = imx25_timer_init,
32};
33
34static const char * const imx25_dt_board_compat[] __initconst = {
35 "fsl,imx25",
36 NULL
37};
38
39DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
40 .map_io = mx25_map_io,
41 .init_early = imx25_init_early,
42 .init_irq = mx25_init_irq,
43 .handle_irq = imx25_handle_irq,
44 .timer = &imx25_timer,
45 .init_machine = imx25_dt_init,
46 .dt_compat = imx25_dt_board_compat,
47 .restart = mxc_restart,
48MACHINE_END
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index 5f1510363ee7..2fdc9bf2fb5e 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,17 +17,25 @@
17 17
18#include "hardware.h" 18#include "hardware.h"
19 19
20#define IMX6Q_UART1_BASE_ADDR 0x02020000
21#define IMX6Q_UART2_BASE_ADDR 0x021e8000
22#define IMX6Q_UART3_BASE_ADDR 0x021ec000
23#define IMX6Q_UART4_BASE_ADDR 0x021f0000
24#define IMX6Q_UART5_BASE_ADDR 0x021f4000
25
26/*
27 * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
28 * of IMX6Q_UART##n##_BASE_ADDR.
29 */
30#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
31#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
32#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
33
20static struct map_desc imx_lluart_desc = { 34static struct map_desc imx_lluart_desc = {
21#ifdef CONFIG_DEBUG_IMX6Q_UART2 35#ifdef CONFIG_DEBUG_IMX6Q_UART
22 .virtual = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR), 36 .virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
23 .pfn = __phys_to_pfn(MX6Q_UART2_BASE_ADDR), 37 .pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
24 .length = MX6Q_UART2_SIZE, 38 .length = 0x4000,
25 .type = MT_DEVICE,
26#endif
27#ifdef CONFIG_DEBUG_IMX6Q_UART4
28 .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
29 .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
30 .length = MX6Q_UART4_SIZE,
31 .type = MT_DEVICE, 39 .type = MT_DEVICE,
32#endif 40#endif
33}; 41};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index cce33e433bd1..4eb1b3ac794c 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -38,6 +38,40 @@
38#include "cpuidle.h" 38#include "cpuidle.h"
39#include "hardware.h" 39#include "hardware.h"
40 40
41#define IMX6Q_ANALOG_DIGPROG 0x260
42
43static int imx6q_revision(void)
44{
45 struct device_node *np;
46 void __iomem *base;
47 static u32 rev;
48
49 if (!rev) {
50 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
51 if (!np)
52 return IMX_CHIP_REVISION_UNKNOWN;
53 base = of_iomap(np, 0);
54 if (!base) {
55 of_node_put(np);
56 return IMX_CHIP_REVISION_UNKNOWN;
57 }
58 rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
59 iounmap(base);
60 of_node_put(np);
61 }
62
63 switch (rev & 0xff) {
64 case 0:
65 return IMX_CHIP_REVISION_1_0;
66 case 1:
67 return IMX_CHIP_REVISION_1_1;
68 case 2:
69 return IMX_CHIP_REVISION_1_2;
70 default:
71 return IMX_CHIP_REVISION_UNKNOWN;
72 }
73}
74
41void imx6q_restart(char mode, const char *cmd) 75void imx6q_restart(char mode, const char *cmd)
42{ 76{
43 struct device_node *np; 77 struct device_node *np;
@@ -204,6 +238,7 @@ static void __init imx6q_timer_init(void)
204{ 238{
205 mx6q_clocks_init(); 239 mx6q_clocks_init();
206 twd_local_timer_of_register(); 240 twd_local_timer_of_register();
241 imx_print_silicon_rev("i.MX6Q", imx6q_revision());
207} 242}
208 243
209static struct sys_timer imx6q_timer = { 244static struct sys_timer imx6q_timer = {
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
index f7e7dbac8f4b..19d3f54db5af 100644
--- a/arch/arm/mach-imx/mx6q.h
+++ b/arch/arm/mach-imx/mx6q.h
@@ -27,9 +27,5 @@
27#define MX6Q_CCM_SIZE 0x4000 27#define MX6Q_CCM_SIZE 0x4000
28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29#define MX6Q_ANATOP_SIZE 0x1000 29#define MX6Q_ANATOP_SIZE 0x1000
30#define MX6Q_UART2_BASE_ADDR 0x021e8000
31#define MX6Q_UART2_SIZE 0x4000
32#define MX6Q_UART4_BASE_ADDR 0x021f0000
33#define MX6Q_UART4_SIZE 0x4000
34 30
35#endif /* __MACH_MX6Q_H__ */ 31#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index d018ad4bcc3c..503d7dd944ff 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -46,6 +46,11 @@ config MACH_GURUPLUG
46 46
47config ARCH_KIRKWOOD_DT 47config ARCH_KIRKWOOD_DT
48 bool "Marvell Kirkwood Flattened Device Tree" 48 bool "Marvell Kirkwood Flattened Device Tree"
49 select POWER_SUPPLY
50 select POWER_RESET
51 select POWER_RESET_GPIO
52 select REGULATOR
53 select REGULATOR_FIXED_VOLTAGE
49 select USE_OF 54 select USE_OF
50 help 55 help
51 Say 'Y' here if you want your kernel to support the 56 Say 'Y' here if you want your kernel to support the
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 43d16d6714b8..a1aa87f09180 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -17,51 +17,11 @@
17#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include "common.h" 19#include "common.h"
20#include "mpp.h"
21 20
22static struct mv643xx_eth_platform_data dnskw_ge00_data = { 21static struct mv643xx_eth_platform_data dnskw_ge00_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 22 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
24}; 23};
25 24
26static unsigned int dnskw_mpp_config[] __initdata = {
27 MPP13_UART1_TXD, /* Custom ... */
28 MPP14_UART1_RXD, /* ... Controller (DNS-320 only) */
29 MPP20_SATA1_ACTn, /* LED: White Right HDD */
30 MPP21_SATA0_ACTn, /* LED: White Left HDD */
31 MPP24_GPIO,
32 MPP25_GPIO,
33 MPP26_GPIO, /* LED: Power */
34 MPP27_GPIO, /* LED: Red Right HDD */
35 MPP28_GPIO, /* LED: Red Left HDD */
36 MPP29_GPIO, /* LED: Red USB (DNS-325 only) */
37 MPP30_GPIO,
38 MPP31_GPIO,
39 MPP32_GPIO,
40 MPP33_GPO,
41 MPP34_GPIO, /* Button: Front power */
42 MPP35_GPIO, /* LED: Red USB (DNS-320 only) */
43 MPP36_GPIO, /* Power: Turn off board */
44 MPP37_GPIO, /* Power: Turn back on after power failure */
45 MPP38_GPIO,
46 MPP39_GPIO, /* Power: SATA0 */
47 MPP40_GPIO, /* Power: SATA1 */
48 MPP41_GPIO, /* SATA0 present */
49 MPP42_GPIO, /* SATA1 present */
50 MPP43_GPIO, /* LED: White USB */
51 MPP44_GPIO, /* Fan: Tachometer Pin */
52 MPP45_GPIO, /* Fan: high speed */
53 MPP46_GPIO, /* Fan: low speed */
54 MPP47_GPIO, /* Button: Back unmount */
55 MPP48_GPIO, /* Button: Back reset */
56 MPP49_GPIO, /* Temp Alarm (DNS-325) Pin of U5 (DNS-320) */
57 0
58};
59
60static void dnskw_power_off(void)
61{
62 gpio_set_value(36, 1);
63}
64
65/* Register any GPIO for output and set the value */ 25/* Register any GPIO for output and set the value */
66static void __init dnskw_gpio_register(unsigned gpio, char *name, int def) 26static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
67{ 27{
@@ -76,22 +36,8 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
76 36
77void __init dnskw_init(void) 37void __init dnskw_init(void)
78{ 38{
79 kirkwood_mpp_conf(dnskw_mpp_config);
80
81 kirkwood_ehci_init();
82 kirkwood_ge00_init(&dnskw_ge00_data); 39 kirkwood_ge00_init(&dnskw_ge00_data);
83 40
84 /* Register power-off GPIO. */
85 if (gpio_request(36, "dnskw:power:off") == 0
86 && gpio_direction_output(36, 0) == 0)
87 pm_power_off = dnskw_power_off;
88 else
89 pr_err("dnskw: failed to configure power-off GPIO\n");
90
91 /* Ensure power is supplied to both HDDs */
92 dnskw_gpio_register(39, "dnskw:power:sata0", 1);
93 dnskw_gpio_register(40, "dnskw:power:sata1", 1);
94
95 /* Set NAS to turn back on after a power failure */ 41 /* Set NAS to turn back on after a power failure */
96 dnskw_gpio_register(37, "dnskw:power:recover", 1); 42 dnskw_gpio_register(37, "dnskw:power:recover", 1);
97} 43}
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
index 6912882b0aa9..d7196db33984 100644
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -17,32 +17,16 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/mv643xx_eth.h> 19#include <linux/mv643xx_eth.h>
20#include <linux/gpio.h>
21#include "common.h" 20#include "common.h"
22#include "mpp.h"
23 21
24static struct mv643xx_eth_platform_data dockstar_ge00_data = { 22static struct mv643xx_eth_platform_data dockstar_ge00_data = {
25 .phy_addr = MV643XX_ETH_PHY_ADDR(0), 23 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
26}; 24};
27 25
28static unsigned int dockstar_mpp_config[] __initdata = {
29 MPP29_GPIO, /* USB Power Enable */
30 MPP46_GPIO, /* LED green */
31 MPP47_GPIO, /* LED orange */
32 0
33};
34
35void __init dockstar_dt_init(void) 26void __init dockstar_dt_init(void)
36{ 27{
37 /* 28 /*
38 * Basic setup. Needs to be called early. 29 * Basic setup. Needs to be called early.
39 */ 30 */
40 kirkwood_mpp_conf(dockstar_mpp_config);
41
42 if (gpio_request(29, "USB Power Enable") != 0 ||
43 gpio_direction_output(29, 1) != 0)
44 pr_err("can't setup GPIO 29 (USB Power Enable)\n");
45 kirkwood_ehci_init();
46
47 kirkwood_ge00_init(&dockstar_ge00_data); 31 kirkwood_ge00_init(&dockstar_ge00_data);
48} 32}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 8a8ebe09e512..08248e24ffcd 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -17,7 +17,6 @@
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/platform_data/mmc-mvsdio.h> 18#include <linux/platform_data/mmc-mvsdio.h>
19#include "common.h" 19#include "common.h"
20#include "mpp.h"
21 20
22static struct mv643xx_eth_platform_data dreamplug_ge00_data = { 21static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(0), 22 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
@@ -31,25 +30,11 @@ static struct mvsdio_platform_data dreamplug_mvsdio_data = {
31 /* unfortunately the CD signal has not been connected */ 30 /* unfortunately the CD signal has not been connected */
32}; 31};
33 32
34static unsigned int dreamplug_mpp_config[] __initdata = {
35 MPP0_SPI_SCn,
36 MPP1_SPI_MOSI,
37 MPP2_SPI_SCK,
38 MPP3_SPI_MISO,
39 MPP47_GPIO, /* Bluetooth LED */
40 MPP48_GPIO, /* Wifi LED */
41 MPP49_GPIO, /* Wifi AP LED */
42 0
43};
44
45void __init dreamplug_init(void) 33void __init dreamplug_init(void)
46{ 34{
47 /* 35 /*
48 * Basic setup. Needs to be called early. 36 * Basic setup. Needs to be called early.
49 */ 37 */
50 kirkwood_mpp_conf(dreamplug_mpp_config);
51
52 kirkwood_ehci_init();
53 kirkwood_ge00_init(&dreamplug_ge00_data); 38 kirkwood_ge00_init(&dreamplug_ge00_data);
54 kirkwood_ge01_init(&dreamplug_ge01_data); 39 kirkwood_ge01_init(&dreamplug_ge01_data);
55 kirkwood_sdio_init(&dreamplug_mvsdio_data); 40 kirkwood_sdio_init(&dreamplug_mvsdio_data);
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 5dcd0d62aa42..9db979aec82e 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -19,40 +19,16 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/mv643xx_eth.h> 21#include <linux/mv643xx_eth.h>
22#include <linux/gpio.h>
23#include "common.h" 22#include "common.h"
24#include "mpp.h"
25 23
26static struct mv643xx_eth_platform_data goflexnet_ge00_data = { 24static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
27 .phy_addr = MV643XX_ETH_PHY_ADDR(0), 25 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
28}; 26};
29 27
30static unsigned int goflexnet_mpp_config[] __initdata = {
31 MPP29_GPIO, /* USB Power Enable */
32 MPP47_GPIO, /* LED Orange */
33 MPP46_GPIO, /* LED Green */
34 MPP45_GPIO, /* LED Left Capacity 3 */
35 MPP44_GPIO, /* LED Left Capacity 2 */
36 MPP43_GPIO, /* LED Left Capacity 1 */
37 MPP42_GPIO, /* LED Left Capacity 0 */
38 MPP41_GPIO, /* LED Right Capacity 3 */
39 MPP40_GPIO, /* LED Right Capacity 2 */
40 MPP39_GPIO, /* LED Right Capacity 1 */
41 MPP38_GPIO, /* LED Right Capacity 0 */
42 0
43};
44
45void __init goflexnet_init(void) 28void __init goflexnet_init(void)
46{ 29{
47 /* 30 /*
48 * Basic setup. Needs to be called early. 31 * Basic setup. Needs to be called early.
49 */ 32 */
50 kirkwood_mpp_conf(goflexnet_mpp_config);
51
52 if (gpio_request(29, "USB Power Enable") != 0 ||
53 gpio_direction_output(29, 1) != 0)
54 pr_err("can't setup GPIO 29 (USB Power Enable)\n");
55 kirkwood_ehci_init();
56
57 kirkwood_ge00_init(&goflexnet_ge00_data); 33 kirkwood_ge00_init(&goflexnet_ge00_data);
58} 34}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index 6d3a56421142..9f6f496380d8 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -14,52 +14,17 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/mv643xx_eth.h> 16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include <linux/input.h> 17#include <linux/input.h>
19#include "common.h" 18#include "common.h"
20#include "mpp.h"
21
22#define IB62X0_GPIO_POWER_OFF 24
23 19
24static struct mv643xx_eth_platform_data ib62x0_ge00_data = { 20static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
25 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 21 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
26}; 22};
27 23
28static unsigned int ib62x0_mpp_config[] __initdata = {
29 MPP0_NF_IO2,
30 MPP1_NF_IO3,
31 MPP2_NF_IO4,
32 MPP3_NF_IO5,
33 MPP4_NF_IO6,
34 MPP5_NF_IO7,
35 MPP18_NF_IO0,
36 MPP19_NF_IO1,
37 MPP22_GPIO, /* OS LED red */
38 MPP24_GPIO, /* Power off device */
39 MPP25_GPIO, /* OS LED green */
40 MPP27_GPIO, /* USB transfer LED */
41 MPP28_GPIO, /* Reset button */
42 MPP29_GPIO, /* USB Copy button */
43 0
44};
45
46static void ib62x0_power_off(void)
47{
48 gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
49}
50
51void __init ib62x0_init(void) 24void __init ib62x0_init(void)
52{ 25{
53 /* 26 /*
54 * Basic setup. Needs to be called early. 27 * Basic setup. Needs to be called early.
55 */ 28 */
56 kirkwood_mpp_conf(ib62x0_mpp_config);
57
58 kirkwood_ehci_init();
59 kirkwood_ge00_init(&ib62x0_ge00_data); 29 kirkwood_ge00_init(&ib62x0_ge00_data);
60 if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
61 gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
62 pm_power_off = ib62x0_power_off;
63 else
64 pr_err("board-ib62x0: failed to configure power-off GPIO\n");
65} 30}
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index 24f5aa7f698b..c8ebde4919e2 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -13,31 +13,13 @@
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/mv643xx_eth.h> 14#include <linux/mv643xx_eth.h>
15#include "common.h" 15#include "common.h"
16#include "mpp.h"
17 16
18static struct mv643xx_eth_platform_data iconnect_ge00_data = { 17static struct mv643xx_eth_platform_data iconnect_ge00_data = {
19 .phy_addr = MV643XX_ETH_PHY_ADDR(11), 18 .phy_addr = MV643XX_ETH_PHY_ADDR(11),
20}; 19};
21 20
22static unsigned int iconnect_mpp_config[] __initdata = {
23 MPP12_GPIO,
24 MPP35_GPIO,
25 MPP41_GPIO,
26 MPP42_GPIO,
27 MPP43_GPIO,
28 MPP44_GPIO,
29 MPP45_GPIO,
30 MPP46_GPIO,
31 MPP47_GPIO,
32 MPP48_GPIO,
33 0
34};
35
36void __init iconnect_init(void) 21void __init iconnect_init(void)
37{ 22{
38 kirkwood_mpp_conf(iconnect_mpp_config);
39
40 kirkwood_ehci_init();
41 kirkwood_ge00_init(&iconnect_ge00_data); 23 kirkwood_ge00_init(&iconnect_ge00_data);
42} 24}
43 25
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
index e4ed62c28f54..f655b2637b0e 100644
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -13,7 +13,6 @@
13#include <linux/mv643xx_eth.h> 13#include <linux/mv643xx_eth.h>
14#include <linux/ethtool.h> 14#include <linux/ethtool.h>
15#include "common.h" 15#include "common.h"
16#include "mpp.h"
17 16
18static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { 17static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
19 .phy_addr = MV643XX_ETH_PHY_NONE, 18 .phy_addr = MV643XX_ETH_PHY_NONE,
@@ -21,35 +20,10 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
21 .duplex = DUPLEX_FULL, 20 .duplex = DUPLEX_FULL,
22}; 21};
23 22
24static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
25 MPP12_GPIO, /* Reset Button */
26 MPP14_GPIO, /* Power Button */
27 MPP15_GPIO, /* Backup LED (blue) */
28 MPP16_GPIO, /* Power LED (white) */
29 MPP35_GPIO, /* OTB Button */
30 MPP36_GPIO, /* Rebuild LED (white) */
31 MPP37_GPIO, /* Health LED (red) */
32 MPP38_GPIO, /* SATA LED brightness control 1 */
33 MPP39_GPIO, /* SATA LED brightness control 2 */
34 MPP40_GPIO, /* Backup LED brightness control 1 */
35 MPP41_GPIO, /* Backup LED brightness control 2 */
36 MPP42_GPIO, /* Power LED brightness control 1 */
37 MPP43_GPIO, /* Power LED brightness control 2 */
38 MPP44_GPIO, /* Health LED brightness control 1 */
39 MPP45_GPIO, /* Health LED brightness control 2 */
40 MPP46_GPIO, /* Rebuild LED brightness control 1 */
41 MPP47_GPIO, /* Rebuild LED brightness control 2 */
42 0
43};
44
45void __init iomega_ix2_200_init(void) 23void __init iomega_ix2_200_init(void)
46{ 24{
47 /* 25 /*
48 * Basic setup. Needs to be called early. 26 * Basic setup. Needs to be called early.
49 */ 27 */
50 kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
51
52 kirkwood_ehci_init();
53
54 kirkwood_ge01_init(&iomega_ix2_200_ge00_data); 28 kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
55} 29}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
index f7d32834b757..44e4605ba0bf 100644
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -18,27 +18,15 @@
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/clk-private.h> 19#include <linux/clk-private.h>
20#include "common.h" 20#include "common.h"
21#include "mpp.h"
22 21
23static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = { 22static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(0), 23 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
25}; 24};
26 25
27static unsigned int km_kirkwood_mpp_config[] __initdata = {
28 MPP8_GPIO, /* I2C SDA */
29 MPP9_GPIO, /* I2C SCL */
30 0
31};
32
33void __init km_kirkwood_init(void) 26void __init km_kirkwood_init(void)
34{ 27{
35 struct clk *sata_clk; 28 struct clk *sata_clk;
36 /* 29 /*
37 * Basic setup. Needs to be called early.
38 */
39 kirkwood_mpp_conf(km_kirkwood_mpp_config);
40
41 /*
42 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing 30 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
43 * SATA bits (14-15) of the Clock Gating Control Register. Since these 31 * SATA bits (14-15) of the Clock Gating Control Register. Since these
44 * devices are also not present in this variant, their clocks get 32 * devices are also not present in this variant, their clocks get
@@ -52,6 +40,5 @@ void __init km_kirkwood_init(void)
52 if (!IS_ERR(sata_clk)) 40 if (!IS_ERR(sata_clk))
53 sata_clk->flags |= CLK_IGNORE_UNUSED; 41 sata_clk->flags |= CLK_IGNORE_UNUSED;
54 42
55 kirkwood_ehci_init();
56 kirkwood_ge00_init(&km_kirkwood_ge00_data); 43 kirkwood_ge00_init(&km_kirkwood_ge00_data);
57} 44}
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 7e18cad9b796..4ec8b7ae784a 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -15,9 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
18#include <linux/gpio.h>
19#include "common.h" 18#include "common.h"
20#include "mpp.h"
21 19
22static struct mv643xx_eth_platform_data lsxl_ge00_data = { 20static struct mv643xx_eth_platform_data lsxl_ge00_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(0), 21 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
@@ -27,23 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
27 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 25 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
28}; 26};
29 27
30static unsigned int lsxl_mpp_config[] __initdata = {
31 MPP10_GPO, /* HDD Power Enable */
32 MPP11_GPIO, /* USB Vbus Enable */
33 MPP18_GPO, /* FAN High Enable# */
34 MPP19_GPO, /* FAN Low Enable# */
35 MPP36_GPIO, /* Function Blue LED */
36 MPP37_GPIO, /* Alarm LED */
37 MPP38_GPIO, /* Info LED */
38 MPP39_GPIO, /* Power LED */
39 MPP40_GPIO, /* Fan Lock */
40 MPP41_GPIO, /* Function Button */
41 MPP42_GPIO, /* Power Switch */
42 MPP43_GPIO, /* Power Auto Switch */
43 MPP48_GPIO, /* Function Red LED */
44 0
45};
46
47/* 28/*
48 * On the LS-XHL/LS-CHLv2, the shutdown process is following: 29 * On the LS-XHL/LS-CHLv2, the shutdown process is following:
49 * - Userland monitors key events until the power switch goes to off position 30 * - Userland monitors key events until the power switch goes to off position
@@ -57,21 +38,12 @@ static void lsxl_power_off(void)
57 kirkwood_restart('h', NULL); 38 kirkwood_restart('h', NULL);
58} 39}
59 40
60#define LSXL_GPIO_HDD_POWER 10
61#define LSXL_GPIO_USB_POWER 11
62
63void __init lsxl_init(void) 41void __init lsxl_init(void)
64{ 42{
65 /* 43 /*
66 * Basic setup. Needs to be called early. 44 * Basic setup. Needs to be called early.
67 */ 45 */
68 kirkwood_mpp_conf(lsxl_mpp_config);
69
70 /* usb and sata power on */
71 gpio_set_value(LSXL_GPIO_USB_POWER, 1);
72 gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
73 46
74 kirkwood_ehci_init();
75 kirkwood_ge00_init(&lsxl_ge00_data); 47 kirkwood_ge00_init(&lsxl_ge00_data);
76 kirkwood_ge01_init(&lsxl_ge01_data); 48 kirkwood_ge01_init(&lsxl_ge01_data);
77 49
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index e78a227468e6..56bfe5a1605a 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -24,52 +24,16 @@ static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(2), 24 .phy_addr = MV643XX_ETH_PHY_ADDR(2),
25}; 25};
26 26
27static unsigned int mplcec4_mpp_config[] __initdata = {
28 MPP0_NF_IO2,
29 MPP1_NF_IO3,
30 MPP2_NF_IO4,
31 MPP3_NF_IO5,
32 MPP4_NF_IO6,
33 MPP5_NF_IO7,
34 MPP6_SYSRST_OUTn,
35 MPP7_GPO, /* Status LED Green High Active */
36 MPP10_UART0_TXD,
37 MPP11_UART0_RXD,
38 MPP12_SD_CLK,
39 MPP13_SD_CMD, /* Alt UART1_TXD */
40 MPP14_SD_D0, /* Alt UART1_RXD */
41 MPP15_SD_D1,
42 MPP16_SD_D2,
43 MPP17_SD_D3,
44 MPP18_NF_IO0,
45 MPP19_NF_IO1,
46 MPP28_GPIO, /* Input SYS_POR_DET (active High) */
47 MPP29_GPIO, /* Input SYS_RTC_INT (active High) */
48 MPP34_SATA1_ACTn,
49 MPP35_SATA0_ACTn,
50 MPP40_GPIO, /* LED User1 orange */
51 MPP41_GPIO, /* LED User1 green */
52 MPP44_GPIO, /* LED User0 orange */
53 MPP45_GPIO, /* LED User0 green */
54 MPP46_GPIO, /* Status LED Yellow High Active */
55 MPP47_GPIO, /* SD_CD# (in/IRQ)*/
56 0
57};
58
59
60static struct mvsdio_platform_data mplcec4_mvsdio_data = { 27static struct mvsdio_platform_data mplcec4_mvsdio_data = {
61 .gpio_card_detect = 47, /* MPP47 used as SD card detect */ 28 .gpio_card_detect = 47, /* MPP47 used as SD card detect */
62}; 29};
63 30
64 31
65
66void __init mplcec4_init(void) 32void __init mplcec4_init(void)
67{ 33{
68 /* 34 /*
69 * Basic setup. Needs to be called early. 35 * Basic setup. Needs to be called early.
70 */ 36 */
71 kirkwood_mpp_conf(mplcec4_mpp_config);
72 kirkwood_ehci_init();
73 kirkwood_ge00_init(&mplcec4_ge00_data); 37 kirkwood_ge00_init(&mplcec4_ge00_data);
74 kirkwood_ge01_init(&mplcec4_ge01_data); 38 kirkwood_ge01_init(&mplcec4_ge01_data);
75 kirkwood_sdio_init(&mplcec4_mvsdio_data); 39 kirkwood_sdio_init(&mplcec4_mvsdio_data);
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index 78596c4f76d2..8821720ab5a4 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -73,7 +73,6 @@ void __init ns2_init(void)
73 */ 73 */
74 kirkwood_mpp_conf(ns2_mpp_config); 74 kirkwood_mpp_conf(ns2_mpp_config);
75 75
76 kirkwood_ehci_init();
77 if (of_machine_is_compatible("lacie,netspace_lite_v2") || 76 if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
78 of_machine_is_compatible("lacie,netspace_mini_v2")) 77 of_machine_is_compatible("lacie,netspace_mini_v2"))
79 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); 78 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
index 027ce83f3fe5..f58d2e1a4042 100644
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ b/arch/arm/mach-kirkwood/board-nsa310.c
@@ -85,10 +85,6 @@ void __init nsa310_init(void)
85 85
86 nsa310_gpio_init(); 86 nsa310_gpio_init();
87 87
88 /* this can be removed once the mainline kirkwood.dtsi gets
89 * the ehci configuration by default */
90 kirkwood_ehci_init();
91
92 kirkwood_pcie_id(&dev, &rev); 88 kirkwood_pcie_id(&dev, &rev);
93 89
94 i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info)); 90 i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info));
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
index e807e8cfdd44..815fc6451d52 100644
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
@@ -55,8 +55,8 @@ static unsigned int openblocks_a6_mpp_config[] __initdata = {
55 MPP38_GPIO, /* INIT */ 55 MPP38_GPIO, /* INIT */
56 MPP39_GPIO, /* USB OC */ 56 MPP39_GPIO, /* USB OC */
57 MPP41_GPIO, /* LED: Red */ 57 MPP41_GPIO, /* LED: Red */
58 MPP42_GPIO, /* LED: Yellow */ 58 MPP42_GPIO, /* LED: Green */
59 MPP43_GPIO, /* LED: Green */ 59 MPP43_GPIO, /* LED: Yellow */
60 0, 60 0,
61}; 61};
62 62
@@ -66,6 +66,5 @@ void __init openblocks_a6_init(void)
66 * Basic setup. Needs to be called early. 66 * Basic setup. Needs to be called early.
67 */ 67 */
68 kirkwood_mpp_conf(openblocks_a6_mpp_config); 68 kirkwood_mpp_conf(openblocks_a6_mpp_config);
69 kirkwood_ehci_init();
70 kirkwood_ge00_init(&openblocks_ge00_data); 69 kirkwood_ge00_init(&openblocks_ge00_data);
71} 70}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index f3bfedae3a20..acb0187c7ee1 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -23,47 +23,21 @@
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <mach/kirkwood.h> 24#include <mach/kirkwood.h>
25#include "common.h" 25#include "common.h"
26#include "mpp.h"
27#include "tsx1x-common.h" 26#include "tsx1x-common.h"
28 27
29static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { 28static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
30 .phy_addr = MV643XX_ETH_PHY_ADDR(8), 29 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
31}; 30};
32 31
33static unsigned int qnap_ts219_mpp_config[] __initdata = {
34 MPP0_SPI_SCn,
35 MPP1_SPI_MOSI,
36 MPP2_SPI_SCK,
37 MPP3_SPI_MISO,
38 MPP4_SATA1_ACTn,
39 MPP5_SATA0_ACTn,
40 MPP8_TW0_SDA,
41 MPP9_TW0_SCK,
42 MPP10_UART0_TXD,
43 MPP11_UART0_RXD,
44 MPP13_UART1_TXD, /* PIC controller */
45 MPP14_UART1_RXD, /* PIC controller */
46 MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */
47 MPP16_GPIO, /* Reset button (on devices with 88F6281) */
48 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
49 MPP37_GPIO, /* Reset button (on devices with 88F6282) */
50 MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */
51 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
52 0
53};
54
55void __init qnap_dt_ts219_init(void) 32void __init qnap_dt_ts219_init(void)
56{ 33{
57 u32 dev, rev; 34 u32 dev, rev;
58 35
59 kirkwood_mpp_conf(qnap_ts219_mpp_config);
60
61 kirkwood_pcie_id(&dev, &rev); 36 kirkwood_pcie_id(&dev, &rev);
62 if (dev == MV88F6282_DEV_ID) 37 if (dev == MV88F6282_DEV_ID)
63 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); 38 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
64 39
65 kirkwood_ge00_init(&qnap_ts219_ge00_data); 40 kirkwood_ge00_init(&qnap_ts219_ge00_data);
66 kirkwood_ehci_init();
67 41
68 pm_power_off = qnap_tsx1x_power_off; 42 pm_power_off = qnap_tsx1x_power_off;
69} 43}
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
index e2ec9d891fe3..15e69fcde9f4 100644
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ b/arch/arm/mach-kirkwood/board-usi_topkick.c
@@ -76,7 +76,6 @@ void __init usi_topkick_init(void)
76 /* SATA0 power enable */ 76 /* SATA0 power enable */
77 gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1); 77 gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1);
78 78
79 kirkwood_ehci_init();
80 kirkwood_ge00_init(&topkick_ge00_data); 79 kirkwood_ge00_init(&topkick_ge00_data);
81 kirkwood_sdio_init(&topkick_mvsdio_data); 80 kirkwood_sdio_init(&topkick_mvsdio_data);
82} 81}
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 4748ec551a68..98070370d602 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -100,6 +100,25 @@ static struct fb_videomode apx4devkit_video_modes[] = {
100 }, 100 },
101}; 101};
102 102
103static struct fb_videomode apf28dev_video_modes[] = {
104 {
105 .name = "LW700",
106 .refresh = 60,
107 .xres = 800,
108 .yres = 480,
109 .pixclock = 30303, /* picosecond */
110 .left_margin = 96,
111 .right_margin = 96, /* at least 3 & 1 */
112 .upper_margin = 0x14,
113 .lower_margin = 0x15,
114 .hsync_len = 64,
115 .vsync_len = 4,
116 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
117 FB_SYNC_DATA_ENABLE_HIGH_ACT |
118 FB_SYNC_DOTCLK_FAILING_ACT,
119 },
120};
121
103static struct mxsfb_platform_data mxsfb_pdata __initdata; 122static struct mxsfb_platform_data mxsfb_pdata __initdata;
104 123
105/* 124/*
@@ -160,6 +179,7 @@ static struct sys_timer imx28_timer = {
160enum mac_oui { 179enum mac_oui {
161 OUI_FSL, 180 OUI_FSL,
162 OUI_DENX, 181 OUI_DENX,
182 OUI_CRYSTALFONTZ,
163}; 183};
164 184
165static void __init update_fec_mac_prop(enum mac_oui oui) 185static void __init update_fec_mac_prop(enum mac_oui oui)
@@ -175,8 +195,12 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
175 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); 195 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
176 if (!np) 196 if (!np)
177 return; 197 return;
198
178 from = np; 199 from = np;
179 200
201 if (of_get_property(np, "local-mac-address", NULL))
202 continue;
203
180 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); 204 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
181 if (!newmac) 205 if (!newmac)
182 return; 206 return;
@@ -205,6 +229,11 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
205 macaddr[1] = 0xe5; 229 macaddr[1] = 0xe5;
206 macaddr[2] = 0x4e; 230 macaddr[2] = 0x4e;
207 break; 231 break;
232 case OUI_CRYSTALFONTZ:
233 macaddr[0] = 0x58;
234 macaddr[1] = 0xb9;
235 macaddr[2] = 0xe1;
236 break;
208 } 237 }
209 val = ocotp[i]; 238 val = ocotp[i];
210 macaddr[3] = (val >> 16) & 0xff; 239 macaddr[3] = (val >> 16) & 0xff;
@@ -261,6 +290,11 @@ static void __init m28evk_init(void)
261 mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; 290 mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
262} 291}
263 292
293static void __init sc_sps1_init(void)
294{
295 enable_clk_enet_out();
296}
297
264static int apx4devkit_phy_fixup(struct phy_device *phy) 298static int apx4devkit_phy_fixup(struct phy_device *phy)
265{ 299{
266 phy->dev_flags |= MICREL_PHY_50MHZ_CLK; 300 phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
@@ -355,6 +389,22 @@ static void __init tx28_post_init(void)
355 pinctrl_put(pctl); 389 pinctrl_put(pctl);
356} 390}
357 391
392static void __init cfa10049_init(void)
393{
394 enable_clk_enet_out();
395 update_fec_mac_prop(OUI_CRYSTALFONTZ);
396}
397
398static void __init apf28_init(void)
399{
400 enable_clk_enet_out();
401
402 mxsfb_pdata.mode_list = apf28dev_video_modes;
403 mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
404 mxsfb_pdata.default_bpp = 16;
405 mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
406}
407
358static void __init mxs_machine_init(void) 408static void __init mxs_machine_init(void)
359{ 409{
360 if (of_machine_is_compatible("fsl,imx28-evk")) 410 if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -365,6 +415,12 @@ static void __init mxs_machine_init(void)
365 m28evk_init(); 415 m28evk_init();
366 else if (of_machine_is_compatible("bluegiga,apx4devkit")) 416 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
367 apx4devkit_init(); 417 apx4devkit_init();
418 else if (of_machine_is_compatible("crystalfontz,cfa10049"))
419 cfa10049_init();
420 else if (of_machine_is_compatible("armadeus,imx28-apf28"))
421 apf28_init();
422 else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
423 sc_sps1_init();
368 424
369 of_platform_populate(NULL, of_default_bus_match_table, 425 of_platform_populate(NULL, of_default_bus_match_table,
370 mxs_auxdata_lookup, NULL); 426 mxs_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 7c3792613392..856f4c796061 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -29,6 +29,7 @@
29#include <linux/of_irq.h> 29#include <linux/of_irq.h>
30 30
31#include <asm/mach/time.h> 31#include <asm/mach/time.h>
32#include <asm/sched_clock.h>
32#include <mach/mxs.h> 33#include <mach/mxs.h>
33#include <mach/common.h> 34#include <mach/common.h>
34 35
@@ -233,15 +234,22 @@ static struct clocksource clocksource_mxs = {
233 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 234 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
234}; 235};
235 236
237static u32 notrace mxs_read_sched_clock_v2(void)
238{
239 return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
240}
241
236static int __init mxs_clocksource_init(struct clk *timer_clk) 242static int __init mxs_clocksource_init(struct clk *timer_clk)
237{ 243{
238 unsigned int c = clk_get_rate(timer_clk); 244 unsigned int c = clk_get_rate(timer_clk);
239 245
240 if (timrot_is_v1()) 246 if (timrot_is_v1())
241 clocksource_register_hz(&clocksource_mxs, c); 247 clocksource_register_hz(&clocksource_mxs, c);
242 else 248 else {
243 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), 249 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
244 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); 250 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
251 setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
252 }
245 253
246 return 0; 254 return 0;
247} 255}
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 33631c9f1218..bde91a58e105 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -149,15 +149,6 @@ static struct platform_device snd_soc_mop500 = {
149 }, 149 },
150}; 150};
151 151
152/* Platform device for Ux500-PCM */
153static struct platform_device ux500_pcm = {
154 .name = "ux500-pcm",
155 .id = 0,
156 .dev = {
157 .platform_data = NULL,
158 },
159};
160
161struct msp_i2s_platform_data msp2_platform_data = { 152struct msp_i2s_platform_data msp2_platform_data = {
162 .id = MSP_I2S_2, 153 .id = MSP_I2S_2,
163 .msp_i2s_dma_rx = &msp2_dma_rx, 154 .msp_i2s_dma_rx = &msp2_dma_rx,
@@ -185,10 +176,3 @@ void mop500_audio_init(struct device *parent)
185 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, 176 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
186 &msp3_platform_data); 177 &msp3_platform_data);
187} 178}
188
189/* Due for removal once the MSP driver has been fully DT:ed. */
190void mop500_of_audio_init(struct device *parent)
191{
192 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
193 platform_device_register(&ux500_pcm);
194}
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
index 8c979770d872..564f57d5d8a7 100644
--- a/arch/arm/mach-ux500/board-mop500-stuib.c
+++ b/arch/arm/mach-ux500/board-mop500-stuib.c
@@ -162,18 +162,6 @@ static struct bu21013_platform_device tsc_plat_device = {
162 .y_flip = true, 162 .y_flip = true,
163}; 163};
164 164
165static struct bu21013_platform_device tsc_plat2_device = {
166 .cs_en = bu21013_gpio_board_init,
167 .cs_dis = bu21013_gpio_board_exit,
168 .irq_read_val = bu21013_read_pin_val,
169 .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
170 .touch_x_max = TOUCH_XMAX,
171 .touch_y_max = TOUCH_YMAX,
172 .ext_clk = false,
173 .x_flip = false,
174 .y_flip = true,
175};
176
177static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { 165static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
178 { 166 {
179 I2C_BOARD_INFO("bu21013_tp", 0x5C), 167 I2C_BOARD_INFO("bu21013_tp", 0x5C),
@@ -181,21 +169,17 @@ static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
181 }, 169 },
182 { 170 {
183 I2C_BOARD_INFO("bu21013_tp", 0x5D), 171 I2C_BOARD_INFO("bu21013_tp", 0x5D),
184 .platform_data = &tsc_plat2_device, 172 .platform_data = &tsc_plat_device,
185 }, 173 },
186 174
187}; 175};
188 176
189void __init mop500_stuib_init(void) 177void __init mop500_stuib_init(void)
190{ 178{
191 if (machine_is_hrefv60()) { 179 if (machine_is_hrefv60())
192 tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO; 180 tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
193 tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO; 181 else
194 } else {
195 tsc_plat_device.cs_pin = GPIO_BU21013_CS; 182 tsc_plat_device.cs_pin = GPIO_BU21013_CS;
196 tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
197
198 }
199 183
200 mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib, 184 mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
201 ARRAY_SIZE(mop500_i2c0_devices_stuib)); 185 ARRAY_SIZE(mop500_i2c0_devices_stuib));
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index e6ad161449da..5b70212c2536 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -33,8 +33,6 @@
33#include <linux/smsc911x.h> 33#include <linux/smsc911x.h>
34#include <linux/gpio_keys.h> 34#include <linux/gpio_keys.h>
35#include <linux/delay.h> 35#include <linux/delay.h>
36#include <linux/of.h>
37#include <linux/of_platform.h>
38#include <linux/leds.h> 36#include <linux/leds.h>
39#include <linux/pinctrl/consumer.h> 37#include <linux/pinctrl/consumer.h>
40#include <linux/platform_data/pinctrl-nomadik.h> 38#include <linux/platform_data/pinctrl-nomadik.h>
@@ -525,7 +523,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
525}; 523};
526#endif 524#endif
527 525
528static struct pl022_ssp_controller ssp0_plat = { 526struct pl022_ssp_controller ssp0_plat = {
529 .bus_id = 0, 527 .bus_id = 0,
530#ifdef CONFIG_STE_DMA40 528#ifdef CONFIG_STE_DMA40
531 .enable_dma = 1, 529 .enable_dma = 1,
@@ -602,7 +600,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
602}; 600};
603#endif 601#endif
604 602
605static struct amba_pl011_data uart0_plat = { 603struct amba_pl011_data uart0_plat = {
606#ifdef CONFIG_STE_DMA40 604#ifdef CONFIG_STE_DMA40
607 .dma_filter = stedma40_filter, 605 .dma_filter = stedma40_filter,
608 .dma_rx_param = &uart0_dma_cfg_rx, 606 .dma_rx_param = &uart0_dma_cfg_rx,
@@ -610,7 +608,7 @@ static struct amba_pl011_data uart0_plat = {
610#endif 608#endif
611}; 609};
612 610
613static struct amba_pl011_data uart1_plat = { 611struct amba_pl011_data uart1_plat = {
614#ifdef CONFIG_STE_DMA40 612#ifdef CONFIG_STE_DMA40
615 .dma_filter = stedma40_filter, 613 .dma_filter = stedma40_filter,
616 .dma_rx_param = &uart1_dma_cfg_rx, 614 .dma_rx_param = &uart1_dma_cfg_rx,
@@ -618,7 +616,7 @@ static struct amba_pl011_data uart1_plat = {
618#endif 616#endif
619}; 617};
620 618
621static struct amba_pl011_data uart2_plat = { 619struct amba_pl011_data uart2_plat = {
622#ifdef CONFIG_STE_DMA40 620#ifdef CONFIG_STE_DMA40
623 .dma_filter = stedma40_filter, 621 .dma_filter = stedma40_filter,
624 .dma_rx_param = &uart2_dma_cfg_rx, 622 .dma_rx_param = &uart2_dma_cfg_rx,
@@ -681,8 +679,6 @@ static void __init mop500_init_machine(void)
681 679
682 /* This board has full regulator constraints */ 680 /* This board has full regulator constraints */
683 regulator_has_full_constraints(); 681 regulator_has_full_constraints();
684
685 mop500_uib_init();
686} 682}
687 683
688static void __init snowball_init_machine(void) 684static void __init snowball_init_machine(void)
@@ -747,8 +743,6 @@ static void __init hrefv60_init_machine(void)
747 743
748 /* This board has full regulator constraints */ 744 /* This board has full regulator constraints */
749 regulator_has_full_constraints(); 745 regulator_has_full_constraints();
750
751 mop500_uib_init();
752} 746}
753 747
754MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 748MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -794,135 +788,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
794 .timer = &ux500_timer, 788 .timer = &ux500_timer,
795 .handle_irq = gic_handle_irq, 789 .handle_irq = gic_handle_irq,
796 .init_machine = snowball_init_machine, 790 .init_machine = snowball_init_machine,
797 .init_late = ux500_init_late, 791 .init_late = NULL,
798MACHINE_END
799
800#ifdef CONFIG_MACH_UX500_DT
801
802struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
803 /* Requires call-back bindings. */
804 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
805 /* Requires DMA and call-back bindings. */
806 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
807 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
808 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
809 /* Requires DMA bindings. */
810 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
811 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
812 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
813 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
814 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
815 /* Requires clock name bindings. */
816 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
817 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
818 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
819 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
820 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
821 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
822 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
823 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
824 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
825 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
826 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
827 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
828 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
829 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
830 /* Requires device name bindings. */
831 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
832 /* Requires clock name and DMA bindings. */
833 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
834 "ux500-msp-i2s.0", &msp0_platform_data),
835 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
836 "ux500-msp-i2s.1", &msp1_platform_data),
837 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
838 "ux500-msp-i2s.2", &msp2_platform_data),
839 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
840 "ux500-msp-i2s.3", &msp3_platform_data),
841 {},
842};
843
844static const struct of_device_id u8500_local_bus_nodes[] = {
845 /* only create devices below soc node */
846 { .compatible = "stericsson,db8500", },
847 { .compatible = "stericsson,db8500-prcmu", },
848 { .compatible = "simple-bus"},
849 { },
850};
851
852static void __init u8500_init_machine(void)
853{
854 struct device *parent = NULL;
855 int i2c0_devs;
856 int i;
857
858 /* Pinmaps must be in place before devices register */
859 if (of_machine_is_compatible("st-ericsson,mop500"))
860 mop500_pinmaps_init();
861 else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
862 snowball_pinmaps_init();
863 else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
864 hrefv60_pinmaps_init();
865
866 parent = u8500_of_init_devices();
867
868 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
869 mop500_platform_devs[i]->dev.parent = parent;
870
871 /* automatically probe child nodes of db8500 device */
872 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
873
874 if (of_machine_is_compatible("st-ericsson,mop500")) {
875 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
876
877 platform_add_devices(mop500_platform_devs,
878 ARRAY_SIZE(mop500_platform_devs));
879
880 mop500_sdi_init(parent);
881 mop500_audio_init(parent);
882 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
883 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
884 i2c_register_board_info(2, mop500_i2c2_devices,
885 ARRAY_SIZE(mop500_i2c2_devices));
886
887 mop500_uib_init();
888
889 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
890 mop500_of_audio_init(parent);
891 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
892 /*
893 * The HREFv60 board removed a GPIO expander and routed
894 * all these GPIO pins to the internal GPIO controller
895 * instead.
896 */
897 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
898 platform_add_devices(mop500_platform_devs,
899 ARRAY_SIZE(mop500_platform_devs));
900
901 mop500_uib_init();
902 }
903
904 /* This board has full regulator constraints */
905 regulator_has_full_constraints();
906}
907
908static const char * u8500_dt_board_compat[] = {
909 "calaosystems,snowball-a9500",
910 "st-ericsson,hrefv60+",
911 "st-ericsson,u8500",
912 "st-ericsson,mop500",
913 NULL,
914};
915
916
917DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
918 .smp = smp_ops(ux500_smp_ops),
919 .map_io = u8500_map_io,
920 .init_irq = ux500_init_irq,
921 /* we re-use nomadik timer here */
922 .timer = &ux500_timer,
923 .handle_irq = gic_handle_irq,
924 .init_machine = u8500_init_machine,
925 .init_late = ux500_init_late,
926 .dt_compat = u8500_dt_board_compat,
927MACHINE_END 792MACHINE_END
928#endif
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index aca39a68712a..eaa605f5d90d 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -89,6 +89,10 @@ extern struct msp_i2s_platform_data msp1_platform_data;
89extern struct msp_i2s_platform_data msp2_platform_data; 89extern struct msp_i2s_platform_data msp2_platform_data;
90extern struct msp_i2s_platform_data msp3_platform_data; 90extern struct msp_i2s_platform_data msp3_platform_data;
91extern struct arm_pmu_platdata db8500_pmu_platdata; 91extern struct arm_pmu_platdata db8500_pmu_platdata;
92extern struct amba_pl011_data uart0_plat;
93extern struct amba_pl011_data uart1_plat;
94extern struct amba_pl011_data uart2_plat;
95extern struct pl022_ssp_controller ssp0_plat;
92 96
93extern void mop500_sdi_init(struct device *parent); 97extern void mop500_sdi_init(struct device *parent);
94extern void snowball_sdi_init(struct device *parent); 98extern void snowball_sdi_init(struct device *parent);
@@ -100,14 +104,8 @@ void __init mop500_pinmaps_init(void);
100void __init snowball_pinmaps_init(void); 104void __init snowball_pinmaps_init(void);
101void __init hrefv60_pinmaps_init(void); 105void __init hrefv60_pinmaps_init(void);
102void mop500_audio_init(struct device *parent); 106void mop500_audio_init(struct device *parent);
103/* Due for removal once the MSP driver has been fully DT:ed. */
104void mop500_of_audio_init(struct device *parent);
105 107
106int __init mop500_uib_init(void); 108int __init mop500_uib_init(void);
107void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 109void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
108 unsigned n); 110 unsigned n);
109
110/* TODO: Once all pieces are DT:ed, remove completely. */
111struct device * __init u8500_of_init_devices(void);
112
113#endif 111#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 5c5ad70e48be..93442fcd9eb0 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -17,12 +17,16 @@
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/mfd/abx500/ab8500.h> 19#include <linux/mfd/abx500/ab8500.h>
20#include <linux/platform_data/usb-musb-ux500.h> 20#include <linux/mfd/dbx500-prcmu.h>
21#include <linux/platform_data/pinctrl-nomadik.h> 21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/regulator/machine.h>
22#include <linux/random.h> 24#include <linux/random.h>
23 25
24#include <asm/pmu.h> 26#include <asm/pmu.h>
25#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/mach/arch.h>
29#include <asm/hardware/gic.h>
26#include <mach/hardware.h> 30#include <mach/hardware.h>
27#include <mach/setup.h> 31#include <mach/setup.h>
28#include <mach/devices.h> 32#include <mach/devices.h>
@@ -30,6 +34,7 @@
30 34
31#include "devices-db8500.h" 35#include "devices-db8500.h"
32#include "ste-dma40-db8500.h" 36#include "ste-dma40-db8500.h"
37#include "board-mop500.h"
33 38
34/* minimum static i/o mapping required to boot U8500 platforms */ 39/* minimum static i/o mapping required to boot U8500 platforms */
35static struct map_desc u8500_uart_io_desc[] __initdata = { 40static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -227,12 +232,12 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
227 return parent; 232 return parent;
228} 233}
229 234
235#ifdef CONFIG_MACH_UX500_DT
236
230/* TODO: Once all pieces are DT:ed, remove completely. */ 237/* TODO: Once all pieces are DT:ed, remove completely. */
231struct device * __init u8500_of_init_devices(void) 238static struct device * __init u8500_of_init_devices(void)
232{ 239{
233 struct device *parent; 240 struct device *parent = db8500_soc_device_init();
234
235 parent = db8500_soc_device_init();
236 241
237 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 242 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
238 243
@@ -248,3 +253,95 @@ struct device * __init u8500_of_init_devices(void)
248 253
249 return parent; 254 return parent;
250} 255}
256
257static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
258 /* Requires call-back bindings. */
259 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
260 /* Requires DMA bindings. */
261 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
262 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
263 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
264 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
265 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
266 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
267 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
268 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
269 /* Requires clock name bindings. */
270 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
271 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
272 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
273 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
274 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
275 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
276 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
277 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
278 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
279 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
280 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
281 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
282 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
283 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
284 /* Requires device name bindings. */
285 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
286 /* Requires clock name and DMA bindings. */
287 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
288 "ux500-msp-i2s.0", &msp0_platform_data),
289 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
290 "ux500-msp-i2s.1", &msp1_platform_data),
291 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
292 "ux500-msp-i2s.2", &msp2_platform_data),
293 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
294 "ux500-msp-i2s.3", &msp3_platform_data),
295 {},
296};
297
298static const struct of_device_id u8500_local_bus_nodes[] = {
299 /* only create devices below soc node */
300 { .compatible = "stericsson,db8500", },
301 { .compatible = "stericsson,db8500-prcmu", },
302 { .compatible = "simple-bus"},
303 { },
304};
305
306static void __init u8500_init_machine(void)
307{
308 struct device *parent = NULL;
309
310 /* Pinmaps must be in place before devices register */
311 if (of_machine_is_compatible("st-ericsson,mop500"))
312 mop500_pinmaps_init();
313 else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
314 snowball_pinmaps_init();
315 else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
316 hrefv60_pinmaps_init();
317 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
318 /* TODO: Add pinmaps for ccu9540 board. */
319
320 /* TODO: Export SoC, USB, cpu-freq and DMA40 */
321 parent = u8500_of_init_devices();
322
323 /* automatically probe child nodes of db8500 device */
324 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
325}
326
327static const char * stericsson_dt_platform_compat[] = {
328 "st-ericsson,u8500",
329 "st-ericsson,u8540",
330 "st-ericsson,u9500",
331 "st-ericsson,u9540",
332 NULL,
333};
334
335DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
336 .smp = smp_ops(ux500_smp_ops),
337 .map_io = u8500_map_io,
338 .init_irq = ux500_init_irq,
339 /* we re-use nomadik timer here */
340 .timer = &ux500_timer,
341 .handle_irq = gic_handle_irq,
342 .init_machine = u8500_init_machine,
343 .init_late = NULL,
344 .dt_compat = stericsson_dt_platform_compat,
345MACHINE_END
346
347#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1f3fbc2bb776..721e7b4275f3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -26,6 +26,8 @@
26#include <mach/setup.h> 26#include <mach/setup.h>
27#include <mach/devices.h> 27#include <mach/devices.h>
28 28
29#include "board-mop500.h"
30
29void __iomem *_PRCMU_BASE; 31void __iomem *_PRCMU_BASE;
30 32
31/* 33/*
@@ -82,6 +84,7 @@ void __init ux500_init_irq(void)
82 84
83void __init ux500_init_late(void) 85void __init ux500_init_late(void)
84{ 86{
87 mop500_uib_init();
85} 88}
86 89
87static const char * __init ux500_get_machine(void) 90static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index ba8d14f78d4d..79bf5fb4dad3 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,12 +19,15 @@
19#include <linux/cpumask.h> 19#include <linux/cpumask.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/clk/zynq.h>
23#include <linux/of_address.h>
22#include <linux/of_irq.h> 24#include <linux/of_irq.h>
23#include <linux/of_platform.h> 25#include <linux/of_platform.h>
24#include <linux/of.h> 26#include <linux/of.h>
25 27
26#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30#include <asm/mach/time.h>
28#include <asm/mach-types.h> 31#include <asm/mach-types.h>
29#include <asm/page.h> 32#include <asm/page.h>
30#include <asm/hardware/gic.h> 33#include <asm/hardware/gic.h>
@@ -84,15 +87,36 @@ static struct map_desc io_desc[] __initdata = {
84 87
85#ifdef CONFIG_DEBUG_LL 88#ifdef CONFIG_DEBUG_LL
86 { 89 {
87 .virtual = UART0_VIRT, 90 .virtual = LL_UART_VADDR,
88 .pfn = __phys_to_pfn(UART0_PHYS), 91 .pfn = __phys_to_pfn(LL_UART_PADDR),
89 .length = UART0_SIZE, 92 .length = UART_SIZE,
90 .type = MT_DEVICE, 93 .type = MT_DEVICE,
91 }, 94 },
92#endif 95#endif
93 96
94}; 97};
95 98
99static void __init xilinx_zynq_timer_init(void)
100{
101 struct device_node *np;
102 void __iomem *slcr;
103
104 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
105 slcr = of_iomap(np, 0);
106 WARN_ON(!slcr);
107
108 xilinx_zynq_clocks_init(slcr);
109
110 xttcpss_timer_init();
111}
112
113/*
114 * Instantiate and initialize the system timer structure
115 */
116static struct sys_timer xttcpss_sys_timer = {
117 .init = xilinx_zynq_timer_init,
118};
119
96/** 120/**
97 * xilinx_map_io() - Create memory mappings needed for early I/O. 121 * xilinx_map_io() - Create memory mappings needed for early I/O.
98 */ 122 */
@@ -102,7 +126,8 @@ static void __init xilinx_map_io(void)
102} 126}
103 127
104static const char *xilinx_dt_match[] = { 128static const char *xilinx_dt_match[] = {
105 "xlnx,zynq-ep107", 129 "xlnx,zynq-zc702",
130 "xlnx,zynq-7000",
106 NULL 131 NULL
107}; 132};
108 133
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index a009644a1555..954b91c13c91 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
17#ifndef __MACH_ZYNQ_COMMON_H__ 17#ifndef __MACH_ZYNQ_COMMON_H__
18#define __MACH_ZYNQ_COMMON_H__ 18#define __MACH_ZYNQ_COMMON_H__
19 19
20#include <asm/mach/time.h> 20void __init xttcpss_timer_init(void);
21
22extern struct sys_timer xttcpss_sys_timer;
23 21
24#endif 22#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
index 1b8bf0ecbcb0..5ebbd8e6eeee 100644
--- a/arch/arm/mach-zynq/include/mach/zynq_soc.h
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -25,8 +25,9 @@
25 * address that is known to work. 25 * address that is known to work.
26 */ 26 */
27#define UART0_PHYS 0xE0000000 27#define UART0_PHYS 0xE0000000
28#define UART0_SIZE SZ_4K 28#define UART1_PHYS 0xE0001000
29#define UART0_VIRT 0xF0001000 29#define UART_SIZE SZ_4K
30#define UART_VIRT 0xF0001000
30 31
31#define TTC0_PHYS 0xF8001000 32#define TTC0_PHYS 0xF8001000
32#define TTC0_SIZE SZ_4K 33#define TTC0_SIZE SZ_4K
@@ -36,12 +37,17 @@
36#define SCU_PERIPH_SIZE SZ_8K 37#define SCU_PERIPH_SIZE SZ_8K
37#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) 38#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE)
38 39
40#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
41# define LL_UART_PADDR UART1_PHYS
42#else
43# define LL_UART_PADDR UART0_PHYS
44#endif
45
46#define LL_UART_VADDR UART_VIRT
47
39/* The following are intended for the devices that are mapped early */ 48/* The following are intended for the devices that are mapped early */
40 49
41#define TTC0_BASE IOMEM(TTC0_VIRT) 50#define TTC0_BASE IOMEM(TTC0_VIRT)
42#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) 51#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
43 52
44#define LL_UART_PADDR UART0_PHYS
45#define LL_UART_VADDR UART0_VIRT
46
47#endif 53#endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index c2c96cc7d6e7..9662306aa12f 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -23,32 +23,15 @@
23#include <linux/clocksource.h> 23#include <linux/clocksource.h>
24#include <linux/clockchips.h> 24#include <linux/clockchips.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/slab.h>
30#include <linux/clk-provider.h>
26 31
27#include <asm/mach/time.h>
28#include <mach/zynq_soc.h> 32#include <mach/zynq_soc.h>
29#include "common.h" 33#include "common.h"
30 34
31#define IRQ_TIMERCOUNTER0 42
32
33/*
34 * This driver configures the 2 16-bit count-up timers as follows:
35 *
36 * T1: Timer 1, clocksource for generic timekeeping
37 * T2: Timer 2, clockevent source for hrtimers
38 * T3: Timer 3, <unused>
39 *
40 * The input frequency to the timer module for emulation is 2.5MHz which is
41 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
42 * the timers are clocked at 78.125KHz (12.8 us resolution).
43 *
44 * The input frequency to the timer module in silicon will be 200MHz. With the
45 * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
46 */
47#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
48#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
49
50#define XTTCPSS_TIMER_BASE TTC0_BASE
51#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
52/* 35/*
53 * Timer Register Offset Definitions of Timer 1, Increment base address by 4 36 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
54 * and use same offsets for Timer 2 37 * and use same offsets for Timer 2
@@ -65,9 +48,14 @@
65 48
66#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 49#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
67 50
68/* Setup the timers to use pre-scaling */ 51/* Setup the timers to use pre-scaling, using a fixed value for now that will
69 52 * work across most input frequency, but it may need to be more dynamic
70#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) 53 */
54#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
55#define PRESCALE 2048 /* The exponent must match this */
56#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
57#define CLK_CNTRL_PRESCALE_EN 1
58#define CNT_CNTRL_RESET (1<<4)
71 59
72/** 60/**
73 * struct xttcpss_timer - This definition defines local timer structure 61 * struct xttcpss_timer - This definition defines local timer structure
@@ -75,11 +63,25 @@
75 * @base_addr: Base address of timer 63 * @base_addr: Base address of timer
76 **/ 64 **/
77struct xttcpss_timer { 65struct xttcpss_timer {
78 void __iomem *base_addr; 66 void __iomem *base_addr;
79}; 67};
80 68
81static struct xttcpss_timer timers[2]; 69struct xttcpss_timer_clocksource {
82static struct clock_event_device xttcpss_clockevent; 70 struct xttcpss_timer xttc;
71 struct clocksource cs;
72};
73
74#define to_xttcpss_timer_clksrc(x) \
75 container_of(x, struct xttcpss_timer_clocksource, cs)
76
77struct xttcpss_timer_clockevent {
78 struct xttcpss_timer xttc;
79 struct clock_event_device ce;
80 struct clk *clk;
81};
82
83#define to_xttcpss_timer_clkevent(x) \
84 container_of(x, struct xttcpss_timer_clockevent, ce)
83 85
84/** 86/**
85 * xttcpss_set_interval - Set the timer interval value 87 * xttcpss_set_interval - Set the timer interval value
@@ -101,7 +103,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
101 103
102 /* Reset the counter (0x10) so that it starts from 0, one-shot 104 /* Reset the counter (0x10) so that it starts from 0, one-shot
103 mode makes this needed for timing to be right. */ 105 mode makes this needed for timing to be right. */
104 ctrl_reg |= 0x10; 106 ctrl_reg |= CNT_CNTRL_RESET;
105 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; 107 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
106 __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); 108 __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
107} 109}
@@ -116,90 +118,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
116 **/ 118 **/
117static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) 119static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
118{ 120{
119 struct clock_event_device *evt = &xttcpss_clockevent; 121 struct xttcpss_timer_clockevent *xttce = dev_id;
120 struct xttcpss_timer *timer = dev_id; 122 struct xttcpss_timer *timer = &xttce->xttc;
121 123
122 /* Acknowledge the interrupt and call event handler */ 124 /* Acknowledge the interrupt and call event handler */
123 __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), 125 __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
124 timer->base_addr + XTTCPSS_ISR_OFFSET); 126 timer->base_addr + XTTCPSS_ISR_OFFSET);
125 127
126 evt->event_handler(evt); 128 xttce->ce.event_handler(&xttce->ce);
127 129
128 return IRQ_HANDLED; 130 return IRQ_HANDLED;
129} 131}
130 132
131static struct irqaction event_timer_irq = {
132 .name = "xttcpss clockevent",
133 .flags = IRQF_DISABLED | IRQF_TIMER,
134 .handler = xttcpss_clock_event_interrupt,
135};
136
137/** 133/**
138 * xttcpss_timer_hardware_init - Initialize the timer hardware 134 * __xttc_clocksource_read - Reads the timer counter register
139 *
140 * Initialize the hardware to start the clock source, get the clock
141 * event timer ready to use, and hook up the interrupt.
142 **/
143static void __init xttcpss_timer_hardware_init(void)
144{
145 /* Setup the clock source counter to be an incrementing counter
146 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
147 it by 32 also. Let it start running now.
148 */
149 timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
150
151 __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
152 XTTCPSS_IER_OFFSET);
153 __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
154 XTTCPSS_CLK_CNTRL_OFFSET);
155 __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
156 XTTCPSS_CNT_CNTRL_OFFSET);
157
158 /* Setup the clock event timer to be an interval timer which
159 * is prescaled by 32 using the interval interrupt. Leave it
160 * disabled for now.
161 */
162
163 timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
164
165 __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
166 XTTCPSS_CNT_CNTRL_OFFSET);
167 __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
168 XTTCPSS_CLK_CNTRL_OFFSET);
169 __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
170 XTTCPSS_IER_OFFSET);
171
172 /* Setup IRQ the clock event timer */
173 event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
174 setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
175}
176
177/**
178 * __raw_readl_cycles - Reads the timer counter register
179 * 135 *
180 * returns: Current timer counter register value 136 * returns: Current timer counter register value
181 **/ 137 **/
182static cycle_t __raw_readl_cycles(struct clocksource *cs) 138static cycle_t __xttc_clocksource_read(struct clocksource *cs)
183{ 139{
184 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; 140 struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
185 141
186 return (cycle_t)__raw_readl(timer->base_addr + 142 return (cycle_t)__raw_readl(timer->base_addr +
187 XTTCPSS_COUNT_VAL_OFFSET); 143 XTTCPSS_COUNT_VAL_OFFSET);
188} 144}
189 145
190
191/*
192 * Instantiate and initialize the clock source structure
193 */
194static struct clocksource clocksource_xttcpss = {
195 .name = "xttcpss_timer1",
196 .rating = 200, /* Reasonable clock source */
197 .read = __raw_readl_cycles,
198 .mask = CLOCKSOURCE_MASK(16),
199 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
200};
201
202
203/** 146/**
204 * xttcpss_set_next_event - Sets the time interval for next event 147 * xttcpss_set_next_event - Sets the time interval for next event
205 * 148 *
@@ -211,7 +154,8 @@ static struct clocksource clocksource_xttcpss = {
211static int xttcpss_set_next_event(unsigned long cycles, 154static int xttcpss_set_next_event(unsigned long cycles,
212 struct clock_event_device *evt) 155 struct clock_event_device *evt)
213{ 156{
214 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; 157 struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
158 struct xttcpss_timer *timer = &xttce->xttc;
215 159
216 xttcpss_set_interval(timer, cycles); 160 xttcpss_set_interval(timer, cycles);
217 return 0; 161 return 0;
@@ -226,12 +170,15 @@ static int xttcpss_set_next_event(unsigned long cycles,
226static void xttcpss_set_mode(enum clock_event_mode mode, 170static void xttcpss_set_mode(enum clock_event_mode mode,
227 struct clock_event_device *evt) 171 struct clock_event_device *evt)
228{ 172{
229 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; 173 struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
174 struct xttcpss_timer *timer = &xttce->xttc;
230 u32 ctrl_reg; 175 u32 ctrl_reg;
231 176
232 switch (mode) { 177 switch (mode) {
233 case CLOCK_EVT_MODE_PERIODIC: 178 case CLOCK_EVT_MODE_PERIODIC:
234 xttcpss_set_interval(timer, TIMER_RATE / HZ); 179 xttcpss_set_interval(timer,
180 DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
181 PRESCALE * HZ));
235 break; 182 break;
236 case CLOCK_EVT_MODE_ONESHOT: 183 case CLOCK_EVT_MODE_ONESHOT:
237 case CLOCK_EVT_MODE_UNUSED: 184 case CLOCK_EVT_MODE_UNUSED:
@@ -252,15 +199,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
252 } 199 }
253} 200}
254 201
255/* 202static void __init zynq_ttc_setup_clocksource(struct device_node *np,
256 * Instantiate and initialize the clock event structure 203 void __iomem *base)
257 */ 204{
258static struct clock_event_device xttcpss_clockevent = { 205 struct xttcpss_timer_clocksource *ttccs;
259 .name = "xttcpss_timer2", 206 struct clk *clk;
260 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 207 int err;
261 .set_next_event = xttcpss_set_next_event, 208 u32 reg;
262 .set_mode = xttcpss_set_mode, 209
263 .rating = 200, 210 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
211 if (WARN_ON(!ttccs))
212 return;
213
214 err = of_property_read_u32(np, "reg", &reg);
215 if (WARN_ON(err))
216 return;
217
218 clk = of_clk_get_by_name(np, "cpu_1x");
219 if (WARN_ON(IS_ERR(clk)))
220 return;
221
222 err = clk_prepare_enable(clk);
223 if (WARN_ON(err))
224 return;
225
226 ttccs->xttc.base_addr = base + reg * 4;
227
228 ttccs->cs.name = np->name;
229 ttccs->cs.rating = 200;
230 ttccs->cs.read = __xttc_clocksource_read;
231 ttccs->cs.mask = CLOCKSOURCE_MASK(16);
232 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
233
234 __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
235 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
236 ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
237 __raw_writel(CNT_CNTRL_RESET,
238 ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
239
240 err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
241 if (WARN_ON(err))
242 return;
243}
244
245static void __init zynq_ttc_setup_clockevent(struct device_node *np,
246 void __iomem *base)
247{
248 struct xttcpss_timer_clockevent *ttcce;
249 int err, irq;
250 u32 reg;
251
252 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
253 if (WARN_ON(!ttcce))
254 return;
255
256 err = of_property_read_u32(np, "reg", &reg);
257 if (WARN_ON(err))
258 return;
259
260 ttcce->xttc.base_addr = base + reg * 4;
261
262 ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
263 if (WARN_ON(IS_ERR(ttcce->clk)))
264 return;
265
266 err = clk_prepare_enable(ttcce->clk);
267 if (WARN_ON(err))
268 return;
269
270 irq = irq_of_parse_and_map(np, 0);
271 if (WARN_ON(!irq))
272 return;
273
274 ttcce->ce.name = np->name;
275 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
276 ttcce->ce.set_next_event = xttcpss_set_next_event;
277 ttcce->ce.set_mode = xttcpss_set_mode;
278 ttcce->ce.rating = 200;
279 ttcce->ce.irq = irq;
280
281 __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
282 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
283 ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
284 __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
285
286 err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
287 np->name, ttcce);
288 if (WARN_ON(err))
289 return;
290
291 clockevents_config_and_register(&ttcce->ce,
292 clk_get_rate(ttcce->clk) / PRESCALE,
293 1, 0xfffe);
294}
295
296static const __initconst struct of_device_id zynq_ttc_match[] = {
297 { .compatible = "xlnx,ttc-counter-clocksource",
298 .data = zynq_ttc_setup_clocksource, },
299 { .compatible = "xlnx,ttc-counter-clockevent",
300 .data = zynq_ttc_setup_clockevent, },
301 {}
264}; 302};
265 303
266/** 304/**
@@ -269,30 +307,27 @@ static struct clock_event_device xttcpss_clockevent = {
269 * Initializes the timer hardware and register the clock source and clock event 307 * Initializes the timer hardware and register the clock source and clock event
270 * timers with Linux kernal timer framework 308 * timers with Linux kernal timer framework
271 **/ 309 **/
272static void __init xttcpss_timer_init(void) 310void __init xttcpss_timer_init(void)
273{ 311{
274 xttcpss_timer_hardware_init(); 312 struct device_node *np;
275 clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); 313
276 314 for_each_compatible_node(np, NULL, "xlnx,ttc") {
277 /* Calculate the parameters to allow the clockevent to operate using 315 struct device_node *np_chld;
278 integer math 316 void __iomem *base;
279 */ 317
280 clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); 318 base = of_iomap(np, 0);
281 319 if (WARN_ON(!base))
282 xttcpss_clockevent.max_delta_ns = 320 return;
283 clockevent_delta2ns(0xfffe, &xttcpss_clockevent); 321
284 xttcpss_clockevent.min_delta_ns = 322 for_each_available_child_of_node(np, np_chld) {
285 clockevent_delta2ns(1, &xttcpss_clockevent); 323 int (*cb)(struct device_node *np, void __iomem *base);
286 324 const struct of_device_id *match;
287 /* Indicate that clock event is on 1st CPU as SMP boot needs it */ 325
288 326 match = of_match_node(zynq_ttc_match, np_chld);
289 xttcpss_clockevent.cpumask = cpumask_of(0); 327 if (match) {
290 clockevents_register_device(&xttcpss_clockevent); 328 cb = match->data;
329 cb(np_chld, base);
330 }
331 }
332 }
291} 333}
292
293/*
294 * Instantiate and initialize the system timer structure
295 */
296struct sys_timer xttcpss_sys_timer = {
297 .init = xttcpss_timer_init,
298};
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 1867944415ca..8db0b981ca64 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
41static int __init orion_add_irq_domain(struct device_node *np, 41static int __init orion_add_irq_domain(struct device_node *np,
42 struct device_node *interrupt_parent) 42 struct device_node *interrupt_parent)
43{ 43{
44 int i = 0, irq_gpio; 44 int i = 0;
45 void __iomem *base; 45 void __iomem *base;
46 46
47 do { 47 do {
@@ -54,10 +54,6 @@ static int __init orion_add_irq_domain(struct device_node *np,
54 54
55 irq_domain_add_legacy(np, i * 32, 0, 0, 55 irq_domain_add_legacy(np, i * 32, 0, 0,
56 &irq_domain_simple_ops, NULL); 56 &irq_domain_simple_ops, NULL);
57
58 irq_gpio = i * 32;
59 orion_gpio_of_init(irq_gpio);
60
61 return 0; 57 return 0;
62} 58}
63 59
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index a17d7b3e3725..bc50b20a8ffc 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -929,6 +929,7 @@ struct platform_device s5p_device_mfc_r = {
929 .coherent_dma_mask = DMA_BIT_MASK(32), 929 .coherent_dma_mask = DMA_BIT_MASK(32),
930 }, 930 },
931}; 931};
932
932#endif /* CONFIG_S5P_DEV_MFC */ 933#endif /* CONFIG_S5P_DEV_MFC */
933 934
934/* MIPI CSIS */ 935/* MIPI CSIS */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index a9b8096b8252..f53beba2b63d 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -132,8 +132,6 @@ extern struct platform_device exynos4_device_pcm1;
132extern struct platform_device exynos4_device_pcm2; 132extern struct platform_device exynos4_device_pcm2;
133extern struct platform_device exynos4_device_spdif; 133extern struct platform_device exynos4_device_spdif;
134 134
135extern struct platform_device exynos_device_drm;
136
137extern struct platform_device samsung_asoc_dma; 135extern struct platform_device samsung_asoc_dma;
138extern struct platform_device samsung_asoc_idma; 136extern struct platform_device samsung_asoc_idma;
139extern struct platform_device samsung_device_keypad; 137extern struct platform_device samsung_device_keypad;
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
index ac13227272f0..e6d7c42d68b6 100644
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -10,6 +10,14 @@
10#ifndef __PLAT_SAMSUNG_MFC_H 10#ifndef __PLAT_SAMSUNG_MFC_H
11#define __PLAT_SAMSUNG_MFC_H __FILE__ 11#define __PLAT_SAMSUNG_MFC_H __FILE__
12 12
13struct s5p_mfc_dt_meminfo {
14 unsigned long loff;
15 unsigned long lsize;
16 unsigned long roff;
17 unsigned long rsize;
18 char *compatible;
19};
20
13/** 21/**
14 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver 22 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
15 * @rbase: base address for MFC 'right' memory interface 23 * @rbase: base address for MFC 'right' memory interface
@@ -24,4 +32,7 @@
24void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, 32void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
25 phys_addr_t lbase, unsigned int lsize); 33 phys_addr_t lbase, unsigned int lsize);
26 34
35int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
36 int depth, void *data);
37
27#endif /* __PLAT_SAMSUNG_MFC_H */ 38#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index ad6089465e2a..5ec104b5408b 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -14,6 +14,8 @@
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/memblock.h> 15#include <linux/memblock.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/of_fdt.h>
18#include <linux/of.h>
17 19
18#include <mach/map.h> 20#include <mach/map.h>
19#include <plat/devs.h> 21#include <plat/devs.h>
@@ -69,3 +71,35 @@ static int __init s5p_mfc_memory_init(void)
69 return 0; 71 return 0;
70} 72}
71device_initcall(s5p_mfc_memory_init); 73device_initcall(s5p_mfc_memory_init);
74
75#ifdef CONFIG_OF
76int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
77 int depth, void *data)
78{
79 __be32 *prop;
80 unsigned long len;
81 struct s5p_mfc_dt_meminfo *mfc_mem = data;
82
83 if (!data)
84 return 0;
85
86 if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
87 return 0;
88
89 prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
90 if (!prop || (len != 2 * sizeof(unsigned long)))
91 return 0;
92
93 mfc_mem->loff = be32_to_cpu(prop[0]);
94 mfc_mem->lsize = be32_to_cpu(prop[1]);
95
96 prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
97 if (!prop || (len != 2 * sizeof(unsigned long)))
98 return 0;
99
100 mfc_mem->roff = be32_to_cpu(prop[0]);
101 mfc_mem->rsize = be32_to_cpu(prop[1]);
102
103 return 1;
104}
105#endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a96bda3d3b84..4e1ccb1e6614 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
20obj-$(CONFIG_ARCH_U8500) += ux500/ 20obj-$(CONFIG_ARCH_U8500) += ux500/
21obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 21obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
22obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o 22obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
23obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
23 24
24# Chip specific 25# Chip specific
25obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 26obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
new file mode 100644
index 000000000000..37a30514fd66
--- /dev/null
+++ b/drivers/clk/clk-zynq.c
@@ -0,0 +1,383 @@
1/*
2 * Copyright (c) 2012 National Instruments
3 *
4 * Josh Cartwright <josh.cartwright@ni.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#include <linux/io.h>
19#include <linux/of.h>
20#include <linux/slab.h>
21#include <linux/kernel.h>
22#include <linux/clk-provider.h>
23
24static void __iomem *slcr_base;
25
26struct zynq_pll_clk {
27 struct clk_hw hw;
28 void __iomem *pll_ctrl;
29 void __iomem *pll_cfg;
30};
31
32#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw)
33
34#define CTRL_PLL_FDIV(x) ((x) >> 12)
35
36static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
37 unsigned long parent_rate)
38{
39 struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
40 return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
41}
42
43static const struct clk_ops zynq_pll_clk_ops = {
44 .recalc_rate = zynq_pll_recalc_rate,
45};
46
47static void __init zynq_pll_clk_setup(struct device_node *np)
48{
49 struct clk_init_data init;
50 struct zynq_pll_clk *pll;
51 const char *parent_name;
52 struct clk *clk;
53 u32 regs[2];
54 int ret;
55
56 ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
57 if (WARN_ON(ret))
58 return;
59
60 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
61 if (WARN_ON(!pll))
62 return;
63
64 pll->pll_ctrl = slcr_base + regs[0];
65 pll->pll_cfg = slcr_base + regs[1];
66
67 of_property_read_string(np, "clock-output-names", &init.name);
68
69 init.ops = &zynq_pll_clk_ops;
70 parent_name = of_clk_get_parent_name(np, 0);
71 init.parent_names = &parent_name;
72 init.num_parents = 1;
73
74 pll->hw.init = &init;
75
76 clk = clk_register(NULL, &pll->hw);
77 if (WARN_ON(IS_ERR(clk)))
78 return;
79
80 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
81 if (WARN_ON(ret))
82 return;
83}
84
85struct zynq_periph_clk {
86 struct clk_hw hw;
87 struct clk_onecell_data onecell_data;
88 struct clk *gates[2];
89 void __iomem *clk_ctrl;
90 spinlock_t clkact_lock;
91};
92
93#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw)
94
95static const u8 periph_clk_parent_map[] = {
96 0, 0, 1, 2
97};
98#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
99#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
100
101static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
103{
104 struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
105 return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
106}
107
108static u8 zynq_periph_get_parent(struct clk_hw *hw)
109{
110 struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
111 return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
112}
113
114static const struct clk_ops zynq_periph_clk_ops = {
115 .recalc_rate = zynq_periph_recalc_rate,
116 .get_parent = zynq_periph_get_parent,
117};
118
119static void __init zynq_periph_clk_setup(struct device_node *np)
120{
121 struct zynq_periph_clk *periph;
122 const char *parent_names[3];
123 struct clk_init_data init;
124 int clk_num = 0, err;
125 const char *name;
126 struct clk *clk;
127 u32 reg;
128 int i;
129
130 err = of_property_read_u32(np, "reg", &reg);
131 if (WARN_ON(err))
132 return;
133
134 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
135 if (WARN_ON(!periph))
136 return;
137
138 periph->clk_ctrl = slcr_base + reg;
139 spin_lock_init(&periph->clkact_lock);
140
141 init.name = np->name;
142 init.ops = &zynq_periph_clk_ops;
143 for (i = 0; i < ARRAY_SIZE(parent_names); i++)
144 parent_names[i] = of_clk_get_parent_name(np, i);
145 init.parent_names = parent_names;
146 init.num_parents = ARRAY_SIZE(parent_names);
147
148 periph->hw.init = &init;
149
150 clk = clk_register(NULL, &periph->hw);
151 if (WARN_ON(IS_ERR(clk)))
152 return;
153
154 err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
155 if (WARN_ON(err))
156 return;
157
158 err = of_property_read_string_index(np, "clock-output-names", 0,
159 &name);
160 if (WARN_ON(err))
161 return;
162
163 periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
164 periph->clk_ctrl, 0, 0,
165 &periph->clkact_lock);
166 if (WARN_ON(IS_ERR(periph->gates[0])))
167 return;
168 clk_num++;
169
170 /* some periph clks have 2 downstream gates */
171 err = of_property_read_string_index(np, "clock-output-names", 1,
172 &name);
173 if (err != -ENODATA) {
174 periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
175 periph->clk_ctrl, 1, 0,
176 &periph->clkact_lock);
177 if (WARN_ON(IS_ERR(periph->gates[1])))
178 return;
179 clk_num++;
180 }
181
182 periph->onecell_data.clks = periph->gates;
183 periph->onecell_data.clk_num = clk_num;
184
185 err = of_clk_add_provider(np, of_clk_src_onecell_get,
186 &periph->onecell_data);
187 if (WARN_ON(err))
188 return;
189}
190
191/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
192 * derivative rates depend on CLK_621_TRUE
193 */
194
195struct zynq_cpu_clk {
196 struct clk_hw hw;
197 struct clk_onecell_data onecell_data;
198 struct clk *subclks[4];
199 void __iomem *clk_ctrl;
200 spinlock_t clkact_lock;
201};
202
203#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw)
204
205static const u8 zynq_cpu_clk_parent_map[] = {
206 1, 1, 2, 0
207};
208#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
209#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
210
211static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
212{
213 struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
214 return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
215}
216
217static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
218 unsigned long parent_rate)
219{
220 struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
221 return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
222}
223
224static const struct clk_ops zynq_cpu_clk_ops = {
225 .get_parent = zynq_cpu_clk_get_parent,
226 .recalc_rate = zynq_cpu_clk_recalc_rate,
227};
228
229struct zynq_cpu_subclk {
230 struct clk_hw hw;
231 void __iomem *clk_621;
232 enum {
233 CPU_SUBCLK_6X4X,
234 CPU_SUBCLK_3X2X,
235 CPU_SUBCLK_2X,
236 CPU_SUBCLK_1X,
237 } which;
238};
239
240#define CLK_621_TRUE(x) ((x) & 1)
241
242#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw);
243
244static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
245 unsigned long parent_rate)
246{
247 unsigned long uninitialized_var(rate);
248 struct zynq_cpu_subclk *subclk;
249 bool is_621;
250
251 subclk = to_zynq_cpu_subclk(hw)
252 is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
253
254 switch (subclk->which) {
255 case CPU_SUBCLK_6X4X:
256 rate = parent_rate;
257 break;
258 case CPU_SUBCLK_3X2X:
259 rate = parent_rate / 2;
260 break;
261 case CPU_SUBCLK_2X:
262 rate = parent_rate / (is_621 ? 3 : 2);
263 break;
264 case CPU_SUBCLK_1X:
265 rate = parent_rate / (is_621 ? 6 : 4);
266 break;
267 };
268
269 return rate;
270}
271
272static const struct clk_ops zynq_cpu_subclk_ops = {
273 .recalc_rate = zynq_cpu_subclk_recalc_rate,
274};
275
276static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
277 void __iomem *clk_621)
278{
279 struct zynq_cpu_subclk *subclk;
280 struct clk_init_data init;
281 struct clk *clk;
282 int err;
283
284 err = of_property_read_string_index(np, "clock-output-names",
285 which, &init.name);
286 if (WARN_ON(err))
287 goto err_read_output_name;
288
289 subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
290 if (!subclk)
291 goto err_subclk_alloc;
292
293 subclk->clk_621 = clk_621;
294 subclk->which = which;
295
296 init.ops = &zynq_cpu_subclk_ops;
297 init.parent_names = &np->name;
298 init.num_parents = 1;
299
300 subclk->hw.init = &init;
301
302 clk = clk_register(NULL, &subclk->hw);
303 if (WARN_ON(IS_ERR(clk)))
304 goto err_clk_register;
305
306 return clk;
307
308err_clk_register:
309 kfree(subclk);
310err_subclk_alloc:
311err_read_output_name:
312 return ERR_PTR(-EINVAL);
313}
314
315static void __init zynq_cpu_clk_setup(struct device_node *np)
316{
317 struct zynq_cpu_clk *cpuclk;
318 const char *parent_names[3];
319 struct clk_init_data init;
320 void __iomem *clk_621;
321 struct clk *clk;
322 u32 reg[2];
323 int err;
324 int i;
325
326 err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
327 if (WARN_ON(err))
328 return;
329
330 cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
331 if (WARN_ON(!cpuclk))
332 return;
333
334 cpuclk->clk_ctrl = slcr_base + reg[0];
335 clk_621 = slcr_base + reg[1];
336 spin_lock_init(&cpuclk->clkact_lock);
337
338 init.name = np->name;
339 init.ops = &zynq_cpu_clk_ops;
340 for (i = 0; i < ARRAY_SIZE(parent_names); i++)
341 parent_names[i] = of_clk_get_parent_name(np, i);
342 init.parent_names = parent_names;
343 init.num_parents = ARRAY_SIZE(parent_names);
344
345 cpuclk->hw.init = &init;
346
347 clk = clk_register(NULL, &cpuclk->hw);
348 if (WARN_ON(IS_ERR(clk)))
349 return;
350
351 err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
352 if (WARN_ON(err))
353 return;
354
355 for (i = 0; i < 4; i++) {
356 cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
357 if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
358 return;
359 }
360
361 cpuclk->onecell_data.clks = cpuclk->subclks;
362 cpuclk->onecell_data.clk_num = i;
363
364 err = of_clk_add_provider(np, of_clk_src_onecell_get,
365 &cpuclk->onecell_data);
366 if (WARN_ON(err))
367 return;
368}
369
370static const __initconst struct of_device_id zynq_clk_match[] = {
371 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
372 { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, },
373 { .compatible = "xlnx,zynq-periph-clock",
374 .data = zynq_periph_clk_setup, },
375 { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, },
376 {}
377};
378
379void __init xilinx_zynq_clocks_init(void __iomem *slcr)
380{
381 slcr_base = slcr;
382 of_clk_init(zynq_clk_match);
383}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 14a6c2913e49..a5cbeec6f6db 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -171,7 +171,7 @@ config GPIO_MSM_V2
171 171
172config GPIO_MVEBU 172config GPIO_MVEBU
173 def_bool y 173 def_bool y
174 depends on ARCH_MVEBU 174 depends on PLAT_ORION
175 select GPIO_GENERIC 175 select GPIO_GENERIC
176 select GENERIC_IRQ_CHIP 176 select GENERIC_IRQ_CHIP
177 177
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a006f0db15af..88f41e51565b 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2797,27 +2797,6 @@ static __init void exynos4_gpiolib_init(void)
2797 int group = 0; 2797 int group = 0;
2798 void __iomem *gpx_base; 2798 void __iomem *gpx_base;
2799 2799
2800#ifdef CONFIG_PINCTRL_SAMSUNG
2801 /*
2802 * This gpio driver includes support for device tree support and
2803 * there are platforms using it. In order to maintain
2804 * compatibility with those platforms, and to allow non-dt
2805 * Exynos4210 platforms to use this gpiolib support, a check
2806 * is added to find out if there is a active pin-controller
2807 * driver support available. If it is available, this gpiolib
2808 * support is ignored and the gpiolib support available in
2809 * pin-controller driver is used. This is a temporary check and
2810 * will go away when all of the Exynos4210 platforms have
2811 * switched to using device tree and the pin-ctrl driver.
2812 */
2813 struct device_node *pctrl_np;
2814 const char *pctrl_compat = "samsung,pinctrl-exynos4210";
2815 pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat);
2816 if (pctrl_np)
2817 if (of_device_is_available(pctrl_np))
2818 return;
2819#endif
2820
2821 /* gpio part1 */ 2800 /* gpio part1 */
2822 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K); 2801 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2823 if (gpio_base1 == NULL) { 2802 if (gpio_base1 == NULL) {
@@ -3032,6 +3011,28 @@ static __init int samsung_gpiolib_init(void)
3032 int i, nr_chips; 3011 int i, nr_chips;
3033 int group = 0; 3012 int group = 0;
3034 3013
3014#ifdef CONFIG_PINCTRL_SAMSUNG
3015 /*
3016 * This gpio driver includes support for device tree support and there
3017 * are platforms using it. In order to maintain compatibility with those
3018 * platforms, and to allow non-dt Exynos4210 platforms to use this
3019 * gpiolib support, a check is added to find out if there is a active
3020 * pin-controller driver support available. If it is available, this
3021 * gpiolib support is ignored and the gpiolib support available in
3022 * pin-controller driver is used. This is a temporary check and will go
3023 * away when all of the Exynos4210 platforms have switched to using
3024 * device tree and the pin-ctrl driver.
3025 */
3026 struct device_node *pctrl_np;
3027 static const struct of_device_id exynos_pinctrl_ids[] = {
3028 { .compatible = "samsung,pinctrl-exynos4210", },
3029 { .compatible = "samsung,pinctrl-exynos4x12", },
3030 };
3031 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3032 if (pctrl_np && of_device_is_available(pctrl_np))
3033 return -ENODEV;
3034#endif
3035
3035 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 3036 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3036 3037
3037 if (soc_is_s3c24xx()) { 3038 if (soc_is_s3c24xx()) {
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index ffe74b27d66d..40c9c3eecd94 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -22,22 +22,22 @@
22 22
23#include "pinctrl-mvebu.h" 23#include "pinctrl-mvebu.h"
24 24
25#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 25#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) 26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
28#define DOVE_AU0_AC97_SEL BIT(16) 28#define DOVE_AU0_AC97_SEL BIT(16)
29#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) 29#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
30#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 30#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
31#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) 31#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
32#define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 32#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)
33#define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 33#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)
34#define DOVE_TWSI_OPTION3_GPIO BIT(22) 34#define DOVE_TWSI_OPTION3_GPIO BIT(22)
35#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) 35#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
36#define DOVE_SSP_ON_AU1 BIT(0) 36#define DOVE_SSP_ON_AU1 BIT(0)
37#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 37#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
38#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 38#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)
39#define DOVE_NAND_GPIO_EN BIT(0) 39#define DOVE_NAND_GPIO_EN BIT(0)
40#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) 40#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
41#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 41#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
42#define DOVE_SPI_GPIO_SEL BIT(5) 42#define DOVE_SPI_GPIO_SEL BIT(5)
43#define DOVE_UART1_GPIO_SEL BIT(4) 43#define DOVE_UART1_GPIO_SEL BIT(4)
@@ -234,6 +234,14 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
234 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 234 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
235 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 235 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
236 236
237 /*
238 * clear all audio1 related bits before configure
239 */
240 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
241 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
242 sspc1 &= ~DOVE_SSP_ON_AU1;
243 mpp4 &= ~DOVE_AU1_GPIO_SEL;
244
237 if (config & BIT(0)) 245 if (config & BIT(0))
238 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 246 gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
239 if (config & BIT(1)) 247 if (config & BIT(1))
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index 9a74ef674a0e..fa6ce31c94d9 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -21,340 +21,341 @@
21 21
22#include "pinctrl-mvebu.h" 22#include "pinctrl-mvebu.h"
23 23
24#define V(f6180, f6190, f6192, f6281, f6282) \ 24#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
25 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ 25 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
26 (f6281 << 3) | (f6282 << 4)) 26 (f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
27 27
28enum kirkwood_variant { 28enum kirkwood_variant {
29 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0), 29 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0),
30 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0), 30 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0),
31 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0), 31 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0),
32 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0), 32 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0),
33 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1), 33 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0),
34 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1),
34}; 35};
35 36
36static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = { 37static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
37 MPP_MODE(0, 38 MPP_MODE(0,
38 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 39 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
39 MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1)), 40 MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1)),
40 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1))), 41 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))),
41 MPP_MODE(1, 42 MPP_MODE(1,
42 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 43 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
43 MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1)), 44 MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1)),
44 MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1))), 45 MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))),
45 MPP_MODE(2, 46 MPP_MODE(2,
46 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 47 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
47 MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1)), 48 MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1)),
48 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1))), 49 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))),
49 MPP_MODE(3, 50 MPP_MODE(3,
50 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 51 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
51 MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1)), 52 MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1)),
52 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1))), 53 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))),
53 MPP_MODE(4, 54 MPP_MODE(4,
54 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 55 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
55 MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1)), 56 MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1)),
56 MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1)), 57 MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
57 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), 58 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
58 MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1)), 59 MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0)),
59 MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0))), 60 MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0))),
60 MPP_MODE(5, 61 MPP_MODE(5,
61 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 62 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
62 MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1)), 63 MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1)),
63 MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1)), 64 MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
64 MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0)), 65 MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
65 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), 66 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
66 MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))), 67 MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
67 MPP_MODE(6, 68 MPP_MODE(6,
68 MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1)), 69 MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1, 1)),
69 MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1)), 70 MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1, 1)),
70 MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0))), 71 MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
71 MPP_MODE(7, 72 MPP_MODE(7,
72 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 73 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
73 MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0)), 74 MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1)),
74 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1)), 75 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)),
75 MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0)), 76 MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
76 MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))), 77 MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
77 MPP_MODE(8, 78 MPP_MODE(8,
78 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 79 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
79 MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1)), 80 MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1)),
80 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)), 81 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
81 MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1)), 82 MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1)),
82 MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1)), 83 MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0)),
83 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)), 84 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
84 MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0)), 85 MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
85 MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))), 86 MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
86 MPP_MODE(9, 87 MPP_MODE(9,
87 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 88 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
88 MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1)), 89 MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1)),
89 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)), 90 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
90 MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1)), 91 MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1)),
91 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)), 92 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
92 MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0)), 93 MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0)),
93 MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))), 94 MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
94 MPP_MODE(10, 95 MPP_MODE(10,
95 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 96 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
96 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1)), 97 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)),
97 MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1)), 98 MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
98 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), 99 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
99 MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0))), 100 MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
100 MPP_MODE(11, 101 MPP_MODE(11,
101 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 102 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
102 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1)), 103 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)),
103 MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1)), 104 MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
104 MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0)), 105 MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0)),
105 MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0)), 106 MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0)),
106 MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0)), 107 MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
107 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1))), 108 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0))),
108 MPP_MODE(12, 109 MPP_MODE(12,
109 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1)), 110 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0)),
110 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)), 111 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0)),
111 MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1)), 112 MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0)),
112 MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)), 113 MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0)),
113 MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1)), 114 MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0)),
114 MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1))), 115 MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
115 MPP_MODE(13, 116 MPP_MODE(13,
116 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 117 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
117 MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1)), 118 MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0)),
118 MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)), 119 MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1)),
119 MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1)), 120 MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0)),
120 MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))), 121 MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
121 MPP_MODE(14, 122 MPP_MODE(14,
122 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 123 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
123 MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1)), 124 MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0)),
124 MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)), 125 MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1)),
125 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1)), 126 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
126 MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)), 127 MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0)),
127 MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1)), 128 MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0)),
128 MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))), 129 MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
129 MPP_MODE(15, 130 MPP_MODE(15,
130 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 131 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
131 MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1)), 132 MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0)),
132 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)), 133 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
133 MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)), 134 MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0)),
134 MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1)), 135 MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
135 MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1))), 136 MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0))),
136 MPP_MODE(16, 137 MPP_MODE(16,
137 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 138 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
138 MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1)), 139 MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0)),
139 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)), 140 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
140 MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)), 141 MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0)),
141 MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1)), 142 MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
142 MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1)), 143 MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0)),
143 MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))), 144 MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
144 MPP_MODE(17, 145 MPP_MODE(17,
145 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 146 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
146 MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1)), 147 MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0)),
147 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1)), 148 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
148 MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1)), 149 MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0)),
149 MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1))), 150 MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
150 MPP_MODE(18, 151 MPP_MODE(18,
151 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 152 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
152 MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1)), 153 MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1)),
153 MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1))), 154 MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))),
154 MPP_MODE(19, 155 MPP_MODE(19,
155 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)), 156 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
156 MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1))), 157 MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))),
157 MPP_MODE(20, 158 MPP_MODE(20,
158 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 159 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
159 MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1)), 160 MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)),
160 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)), 161 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
161 MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1)), 162 MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)),
162 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)), 163 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)),
163 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)), 164 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
164 MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1)), 165 MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)),
165 MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0))), 166 MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0, 0))),
166 MPP_MODE(21, 167 MPP_MODE(21,
167 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 168 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
168 MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1)), 169 MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)),
169 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1)), 170 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)),
170 MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1)), 171 MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)),
171 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)), 172 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0, 0)),
172 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)), 173 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)),
173 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), 174 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
174 MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1))), 175 MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))),
175 MPP_MODE(22, 176 MPP_MODE(22,
176 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 177 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
177 MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1)), 178 MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)),
178 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1)), 179 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)),
179 MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1)), 180 MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)),
180 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)), 181 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0, 0)),
181 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1)), 182 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)),
182 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)), 183 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
183 MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1))), 184 MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))),
184 MPP_MODE(23, 185 MPP_MODE(23,
185 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 186 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
186 MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1)), 187 MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)),
187 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1)), 188 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)),
188 MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1)), 189 MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)),
189 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0)), 190 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0, 0)),
190 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1)), 191 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)),
191 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)), 192 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
192 MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1))), 193 MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))),
193 MPP_MODE(24, 194 MPP_MODE(24,
194 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 195 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
195 MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1)), 196 MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)),
196 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1)), 197 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)),
197 MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1)), 198 MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)),
198 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0)), 199 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0, 0)),
199 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1)), 200 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)),
200 MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1))), 201 MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))),
201 MPP_MODE(25, 202 MPP_MODE(25,
202 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 203 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
203 MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1)), 204 MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)),
204 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1)), 205 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)),
205 MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1)), 206 MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)),
206 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0)), 207 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0, 0)),
207 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1)), 208 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)),
208 MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1))), 209 MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))),
209 MPP_MODE(26, 210 MPP_MODE(26,
210 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 211 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
211 MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1)), 212 MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)),
212 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)), 213 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)),
213 MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1)), 214 MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)),
214 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0)), 215 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0, 0)),
215 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1)), 216 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)),
216 MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1))), 217 MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))),
217 MPP_MODE(27, 218 MPP_MODE(27,
218 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 219 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
219 MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1)), 220 MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)),
220 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)), 221 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)),
221 MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1)), 222 MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)),
222 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0)), 223 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0, 0)),
223 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1)), 224 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)),
224 MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1))), 225 MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))),
225 MPP_MODE(28, 226 MPP_MODE(28,
226 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 227 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
227 MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1)), 228 MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)),
228 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1)), 229 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)),
229 MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1)), 230 MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)),
230 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0)), 231 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0, 0)),
231 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)), 232 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)),
232 MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1))), 233 MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))),
233 MPP_MODE(29, 234 MPP_MODE(29,
234 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)), 235 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
235 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1)), 236 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)),
236 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1)), 237 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)),
237 MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1)), 238 MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)),
238 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)), 239 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0, 0)),
239 MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1))), 240 MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))),
240 MPP_MODE(30, 241 MPP_MODE(30,
241 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), 242 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
242 MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1)), 243 MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0)),
243 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1)), 244 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)),
244 MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1)), 245 MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0)),
245 MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1))), 246 MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0))),
246 MPP_MODE(31, 247 MPP_MODE(31,
247 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), 248 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
248 MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1)), 249 MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0)),
249 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1)), 250 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)),
250 MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1)), 251 MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0)),
251 MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1))), 252 MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0))),
252 MPP_MODE(32, 253 MPP_MODE(32,
253 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), 254 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
254 MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1)), 255 MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0)),
255 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1)), 256 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)),
256 MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1)), 257 MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0)),
257 MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1))), 258 MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0))),
258 MPP_MODE(33, 259 MPP_MODE(33,
259 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1)), 260 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)),
260 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1)), 261 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
261 MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1)), 262 MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)),
262 MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1))), 263 MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))),
263 MPP_MODE(34, 264 MPP_MODE(34,
264 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), 265 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
265 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1)), 266 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)),
266 MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1)), 267 MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0)),
267 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1)), 268 MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)),
268 MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1))), 269 MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))),
269 MPP_MODE(35, 270 MPP_MODE(35,
270 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)), 271 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
271 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)), 272 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
272 MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1)), 273 MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)),
273 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)), 274 MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
274 MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1)), 275 MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)),
275 MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1))), 276 MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1, 0))),
276 MPP_MODE(36, 277 MPP_MODE(36,
277 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 278 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
278 MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1)), 279 MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)),
279 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1)), 280 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)),
280 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)), 281 MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1, 0)),
281 MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1))), 282 MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
282 MPP_MODE(37, 283 MPP_MODE(37,
283 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 284 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
284 MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1)), 285 MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)),
285 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1)), 286 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)),
286 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)), 287 MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1, 0)),
287 MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1))), 288 MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
288 MPP_MODE(38, 289 MPP_MODE(38,
289 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 290 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
290 MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1)), 291 MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)),
291 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1)), 292 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)),
292 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1)), 293 MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1, 0)),
293 MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1))), 294 MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))),
294 MPP_MODE(39, 295 MPP_MODE(39,
295 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 296 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
296 MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1)), 297 MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)),
297 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1)), 298 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)),
298 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1)), 299 MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1, 0)),
299 MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1))), 300 MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))),
300 MPP_MODE(40, 301 MPP_MODE(40,
301 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 302 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
302 MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1)), 303 MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)),
303 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1)), 304 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)),
304 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1)), 305 MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1, 0)),
305 MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1))), 306 MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))),
306 MPP_MODE(41, 307 MPP_MODE(41,
307 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 308 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
308 MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1)), 309 MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)),
309 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)), 310 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)),
310 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1)), 311 MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1, 0)),
311 MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1))), 312 MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))),
312 MPP_MODE(42, 313 MPP_MODE(42,
313 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 314 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
314 MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1)), 315 MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)),
315 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)), 316 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)),
316 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1)), 317 MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1, 0)),
317 MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1))), 318 MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))),
318 MPP_MODE(43, 319 MPP_MODE(43,
319 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 320 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
320 MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1)), 321 MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)),
321 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1)), 322 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)),
322 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1)), 323 MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1, 0)),
323 MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1))), 324 MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))),
324 MPP_MODE(44, 325 MPP_MODE(44,
325 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 326 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
326 MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1)), 327 MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)),
327 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1)), 328 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)),
328 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)), 329 MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1, 0)),
329 MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1))), 330 MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))),
330 MPP_MODE(45, 331 MPP_MODE(45,
331 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 332 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
332 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1)), 333 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0)),
333 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1)), 334 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)),
334 MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1))), 335 MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0))),
335 MPP_MODE(46, 336 MPP_MODE(46,
336 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 337 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
337 MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1)), 338 MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0)),
338 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1)), 339 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)),
339 MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1))), 340 MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0))),
340 MPP_MODE(47, 341 MPP_MODE(47,
341 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 342 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
342 MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1)), 343 MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0)),
343 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1)), 344 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)),
344 MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))), 345 MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
345 MPP_MODE(48, 346 MPP_MODE(48,
346 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)), 347 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
347 MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1)), 348 MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0)),
348 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1)), 349 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)),
349 MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1))), 350 MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0))),
350 MPP_MODE(49, 351 MPP_MODE(49,
351 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)), 352 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1)),
352 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1)), 353 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0)),
353 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0)), 354 MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0)),
354 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1)), 355 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)),
355 MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0)), 356 MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0)),
356 MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1)), 357 MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0)),
357 MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1))), 358 MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))),
358}; 359};
359 360
360static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { 361static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
@@ -433,12 +434,23 @@ static struct mvebu_pinctrl_soc_info mv88f6282_info = {
433 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges), 434 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
434}; 435};
435 436
437static struct mvebu_pinctrl_soc_info mv98dx4122_info = {
438 .variant = VARIANT_MV98DX4122,
439 .controls = mv88f628x_mpp_controls,
440 .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
441 .modes = mv88f6xxx_mpp_modes,
442 .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
443 .gpioranges = mv88f628x_gpio_ranges,
444 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
445};
446
436static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = { 447static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
437 { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info }, 448 { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
438 { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info }, 449 { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
439 { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info }, 450 { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
440 { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info }, 451 { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
441 { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info }, 452 { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
453 { .compatible = "marvell,98dx4122-pinctrl", .data = &mv98dx4122_info },
442 { } 454 { }
443}; 455};
444 456
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 49a893972318..b1d956d81f0c 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -335,6 +335,9 @@ config AB8500_BATTERY_THERM_ON_BATCTRL
335 help 335 help
336 Say Y to enable battery temperature measurements using 336 Say Y to enable battery temperature measurements using
337 thermistor connected on BATCTRL ADC. 337 thermistor connected on BATCTRL ADC.
338
339source "drivers/power/reset/Kconfig"
340
338endif # POWER_SUPPLY 341endif # POWER_SUPPLY
339 342
340source "drivers/power/avs/Kconfig" 343source "drivers/power/avs/Kconfig"
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b949cf85590c..f1d99f4a0bc3 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o
49obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o 49obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o
50obj-$(CONFIG_POWER_AVS) += avs/ 50obj-$(CONFIG_POWER_AVS) += avs/
51obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o 51obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
52obj-$(CONFIG_POWER_RESET) += reset/
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
new file mode 100644
index 000000000000..6461b489fb09
--- /dev/null
+++ b/drivers/power/reset/Kconfig
@@ -0,0 +1,15 @@
1menuconfig POWER_RESET
2 bool "Board level reset or power off"
3 help
4 Provides a number of drivers which either reset a complete board
5 or shut it down, by manipulating the main power supply on the board.
6
7 Say Y here to enable board reset and power off
8
9config POWER_RESET_GPIO
10 bool "GPIO power-off driver"
11 depends on OF_GPIO && POWER_RESET
12 help
13 This driver supports turning off your board via a GPIO line.
14 If your board needs a GPIO high/low to power down, say Y and
15 create a binding in your devicetree.
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
new file mode 100644
index 000000000000..751488a4a0c5
--- /dev/null
+++ b/drivers/power/reset/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
diff --git a/drivers/power/reset/gpio-poweroff.c b/drivers/power/reset/gpio-poweroff.c
new file mode 100644
index 000000000000..0491e5335d02
--- /dev/null
+++ b/drivers/power/reset/gpio-poweroff.c
@@ -0,0 +1,129 @@
1/*
2 * Toggles a GPIO pin to power down a device
3 *
4 * Jamie Lentin <jm@lentin.co.uk>
5 * Andrew Lunn <andrew@lunn.ch>
6 *
7 * Copyright (C) 2012 Jamie Lentin
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/of_platform.h>
20#include <linux/of_gpio.h>
21#include <linux/module.h>
22
23/*
24 * Hold configuration here, cannot be more than one instance of the driver
25 * since pm_power_off itself is global.
26 */
27static int gpio_num = -1;
28static int gpio_active_low;
29
30static void gpio_poweroff_do_poweroff(void)
31{
32 BUG_ON(gpio_num == -1);
33
34 /* drive it active */
35 gpio_direction_output(gpio_num, !gpio_active_low);
36 mdelay(100);
37 /* rising edge or drive inactive */
38 gpio_set_value(gpio_num, gpio_active_low);
39 mdelay(100);
40 /* falling edge */
41 gpio_set_value(gpio_num, !gpio_active_low);
42
43 /* give it some time */
44 mdelay(3000);
45
46 WARN_ON(1);
47}
48
49static int __devinit gpio_poweroff_probe(struct platform_device *pdev)
50{
51 enum of_gpio_flags flags;
52 bool input = false;
53 int ret;
54
55 /* If a pm_power_off function has already been added, leave it alone */
56 if (pm_power_off != NULL) {
57 pr_err("%s: pm_power_off function already registered",
58 __func__);
59 return -EBUSY;
60 }
61
62 gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
63 if (gpio_num < 0) {
64 pr_err("%s: Could not get GPIO configuration: %d",
65 __func__, gpio_num);
66 return -ENODEV;
67 }
68 gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
69
70 if (of_get_property(pdev->dev.of_node, "input", NULL))
71 input = true;
72
73 ret = gpio_request(gpio_num, "poweroff-gpio");
74 if (ret) {
75 pr_err("%s: Could not get GPIO %d", __func__, gpio_num);
76 return ret;
77 }
78 if (input) {
79 if (gpio_direction_input(gpio_num)) {
80 pr_err("Could not set direction of GPIO %d to input",
81 gpio_num);
82 goto err;
83 }
84 } else {
85 if (gpio_direction_output(gpio_num, gpio_active_low)) {
86 pr_err("Could not set direction of GPIO %d", gpio_num);
87 goto err;
88 }
89 }
90
91 pm_power_off = &gpio_poweroff_do_poweroff;
92 return 0;
93
94err:
95 gpio_free(gpio_num);
96 return -ENODEV;
97}
98
99static int __devexit gpio_poweroff_remove(struct platform_device *pdev)
100{
101 if (gpio_num != -1)
102 gpio_free(gpio_num);
103 if (pm_power_off == &gpio_poweroff_do_poweroff)
104 pm_power_off = NULL;
105
106 return 0;
107}
108
109static const struct of_device_id of_gpio_poweroff_match[] = {
110 { .compatible = "gpio-poweroff", },
111 {},
112};
113
114static struct platform_driver gpio_poweroff_driver = {
115 .probe = gpio_poweroff_probe,
116 .remove = __devexit_p(gpio_poweroff_remove),
117 .driver = {
118 .name = "poweroff-gpio",
119 .owner = THIS_MODULE,
120 .of_match_table = of_gpio_poweroff_match,
121 },
122};
123
124module_platform_driver(gpio_poweroff_driver);
125
126MODULE_AUTHOR("Jamie Lentin <jm@lentin.co.uk>");
127MODULE_DESCRIPTION("GPIO poweroff driver");
128MODULE_LICENSE("GPL");
129MODULE_ALIAS("platform:poweroff-gpio");
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index f74794c93152..a7d1f5b4c4ed 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -14,6 +14,9 @@
14#include <linux/mbus.h> 14#include <linux/mbus.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/platform_data/usb-ehci-orion.h> 16#include <linux/platform_data/usb-ehci-orion.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
17 20
18#define rdl(off) __raw_readl(hcd->regs + (off)) 21#define rdl(off) __raw_readl(hcd->regs + (off))
19#define wrl(off, val) __raw_writel((val), hcd->regs + (off)) 22#define wrl(off, val) __raw_writel((val), hcd->regs + (off))
@@ -167,6 +170,8 @@ ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
167 } 170 }
168} 171}
169 172
173static u64 ehci_orion_dma_mask = DMA_BIT_MASK(32);
174
170static int ehci_orion_drv_probe(struct platform_device *pdev) 175static int ehci_orion_drv_probe(struct platform_device *pdev)
171{ 176{
172 struct orion_ehci_data *pd = pdev->dev.platform_data; 177 struct orion_ehci_data *pd = pdev->dev.platform_data;
@@ -177,13 +182,17 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
177 struct clk *clk; 182 struct clk *clk;
178 void __iomem *regs; 183 void __iomem *regs;
179 int irq, err; 184 int irq, err;
185 enum orion_ehci_phy_ver phy_version;
180 186
181 if (usb_disabled()) 187 if (usb_disabled())
182 return -ENODEV; 188 return -ENODEV;
183 189
184 pr_debug("Initializing Orion-SoC USB Host Controller\n"); 190 pr_debug("Initializing Orion-SoC USB Host Controller\n");
185 191
186 irq = platform_get_irq(pdev, 0); 192 if (pdev->dev.of_node)
193 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
194 else
195 irq = platform_get_irq(pdev, 0);
187 if (irq <= 0) { 196 if (irq <= 0) {
188 dev_err(&pdev->dev, 197 dev_err(&pdev->dev,
189 "Found HC with no IRQ. Check %s setup!\n", 198 "Found HC with no IRQ. Check %s setup!\n",
@@ -201,6 +210,14 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
201 goto err1; 210 goto err1;
202 } 211 }
203 212
213 /*
214 * Right now device-tree probed devices don't get dma_mask
215 * set. Since shared usb code relies on it, set it here for
216 * now. Once we have dma capability bindings this can go away.
217 */
218 if (!pdev->dev.dma_mask)
219 pdev->dev.dma_mask = &ehci_orion_dma_mask;
220
204 if (!request_mem_region(res->start, resource_size(res), 221 if (!request_mem_region(res->start, resource_size(res),
205 ehci_orion_hc_driver.description)) { 222 ehci_orion_hc_driver.description)) {
206 dev_dbg(&pdev->dev, "controller already in use\n"); 223 dev_dbg(&pdev->dev, "controller already in use\n");
@@ -248,7 +265,12 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
248 /* 265 /*
249 * setup Orion USB controller. 266 * setup Orion USB controller.
250 */ 267 */
251 switch (pd->phy_version) { 268 if (pdev->dev.of_node)
269 phy_version = EHCI_PHY_NA;
270 else
271 phy_version = pd->phy_version;
272
273 switch (phy_version) {
252 case EHCI_PHY_NA: /* dont change USB phy settings */ 274 case EHCI_PHY_NA: /* dont change USB phy settings */
253 break; 275 break;
254 case EHCI_PHY_ORION: 276 case EHCI_PHY_ORION:
@@ -303,9 +325,19 @@ static int __exit ehci_orion_drv_remove(struct platform_device *pdev)
303 325
304MODULE_ALIAS("platform:orion-ehci"); 326MODULE_ALIAS("platform:orion-ehci");
305 327
328static const struct of_device_id ehci_orion_dt_ids[] __devinitdata = {
329 { .compatible = "marvell,orion-ehci", },
330 {},
331};
332MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids);
333
306static struct platform_driver ehci_orion_driver = { 334static struct platform_driver ehci_orion_driver = {
307 .probe = ehci_orion_drv_probe, 335 .probe = ehci_orion_drv_probe,
308 .remove = __exit_p(ehci_orion_drv_remove), 336 .remove = __exit_p(ehci_orion_drv_remove),
309 .shutdown = usb_hcd_platform_shutdown, 337 .shutdown = usb_hcd_platform_shutdown,
310 .driver.name = "orion-ehci", 338 .driver = {
339 .name = "orion-ehci",
340 .owner = THIS_MODULE,
341 .of_match_table = of_match_ptr(ehci_orion_dt_ids),
342 },
311}; 343};
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 05e1be85fdee..dc42e44b6bc1 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -32,6 +32,7 @@
32#include <linux/timer.h> 32#include <linux/timer.h>
33#include <linux/bitops.h> 33#include <linux/bitops.h>
34#include <linux/uaccess.h> 34#include <linux/uaccess.h>
35#include <linux/of.h>
35 36
36#include "at91sam9_wdt.h" 37#include "at91sam9_wdt.h"
37 38
@@ -302,11 +303,21 @@ static int __exit at91wdt_remove(struct platform_device *pdev)
302 return res; 303 return res;
303} 304}
304 305
306#if defined(CONFIG_OF)
307static const struct of_device_id at91_wdt_dt_ids[] __initconst = {
308 { .compatible = "atmel,at91sam9260-wdt" },
309 { /* sentinel */ }
310};
311
312MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
313#endif
314
305static struct platform_driver at91wdt_driver = { 315static struct platform_driver at91wdt_driver = {
306 .remove = __exit_p(at91wdt_remove), 316 .remove = __exit_p(at91wdt_remove),
307 .driver = { 317 .driver = {
308 .name = "at91_wdt", 318 .name = "at91_wdt",
309 .owner = THIS_MODULE, 319 .owner = THIS_MODULE,
320 .of_match_table = of_match_ptr(at91_wdt_dt_ids),
310 }, 321 },
311}; 322};
312 323
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
new file mode 100644
index 000000000000..56be7cd9aa8b
--- /dev/null
+++ b/include/linux/clk/zynq.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (C) 2012 National Instruments
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __LINUX_CLK_ZYNQ_H_
20#define __LINUX_CLK_ZYNQ_H_
21
22void __init xilinx_zynq_clocks_init(void __iomem *slcr);
23
24#endif