Merge tag 'sunxi-clocks-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clocks changes for 4.1

The usual round of clock changes for the Allwinner SoCs.

There is nothing really standing out here, but a few changes and fixes, most
notably to allow the AHB clock to be parented to a PLL, instead of the CPU
clock to avoid any AHB rate change due to cpufreq.

4 files changed, 319 insertions, 103 deletions

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 60b44285250d..4fa11af3d378 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -20,6 +20,7 @@ Required properties:
         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
         "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
@@ -66,6 +67,8 @@ Required properties:
         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
         "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
         "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
+        "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
+        "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3a5292e3fcf8..058f273d6154 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-mod0.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
+obj-y += clk-usb.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
         clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 379324eb5486..7e1e2bd189b6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -482,6 +482,45 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
+ * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ */
+
+static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
+                                       u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u32 div;
+
+        /* divide only */
+        if (parent_rate < *freq)
+                *freq = parent_rate;
+
+        /*
+         * user manual says valid speed is 8k ~ 276M, but tests show it
+         * can work at speeds up to 300M, just after reparenting to pll6
+         */
+        if (*freq < 8000)
+                *freq = 8000;
+        if (*freq > 300000000)
+                *freq = 300000000;
+
+        div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
+
+        /* p = 0 ~ 3 */
+        if (div > 3)
+                div = 3;
+
+        *freq = parent_rate >> div;
+
+        /* we were called to round the frequency, we can now return */
+        if (p == NULL)
+                return;
+
+        *p = div;
+}
+
+/**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);
@@ -616,6 +655,11 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
         .n_start = 1,
 };
 
+static struct clk_factors_config sun5i_a13_ahb_config = {
+        .pshift = 4,
+        .pwidth = 2,
+};
+
 static struct clk_factors_config sun4i_apb1_config = {
         .mshift = 0,
         .mwidth = 5,
@@ -676,6 +720,13 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
         .name = "pll6x2",
 };
 
+static const struct factors_data sun5i_a13_ahb_data __initconst = {
+        .mux = 6,
+        .muxmask = BIT(1) | BIT(0),
+        .table = &sun5i_a13_ahb_config,
+        .getter = sun5i_a13_get_ahb_factors,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
         .mux = 24,
         .muxmask = BIT(1) | BIT(0),
@@ -838,59 +889,6 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
 
 
 /**
- * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
- */
-
-struct gates_reset_data {
-        void __iomem                    *reg;
-        spinlock_t                      *lock;
-        struct reset_controller_dev     rcdev;
-};
-
-static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
-                              unsigned long id)
-{
-        struct gates_reset_data *data = container_of(rcdev,
-                                                     struct gates_reset_data,
-                                                     rcdev);
-        unsigned long flags;
-        u32 reg;
-
-        spin_lock_irqsave(data->lock, flags);
-
-        reg = readl(data->reg);
-        writel(reg & ~BIT(id), data->reg);
-
-        spin_unlock_irqrestore(data->lock, flags);
-
-        return 0;
-}
-
-static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
-                                unsigned long id)
-{
-        struct gates_reset_data *data = container_of(rcdev,
-                                                     struct gates_reset_data,
-                                                     rcdev);
-        unsigned long flags;
-        u32 reg;
-
-        spin_lock_irqsave(data->lock, flags);
-
-        reg = readl(data->reg);
-        writel(reg | BIT(id), data->reg);
-
-        spin_unlock_irqrestore(data->lock, flags);
-
-        return 0;
-}
-
-static struct reset_control_ops sunxi_gates_reset_ops = {
-        .assert         = sunxi_gates_reset_assert,
-        .deassert       = sunxi_gates_reset_deassert,
-};
-
-/**
  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
  */
 
@@ -898,7 +896,6 @@ static struct reset_control_ops sunxi_gates_reset_ops = {
 
 struct gates_data {
         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
-        u32 reset_mask;