1 files changed, 3 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 60b44285250d..4fa11af3d378 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -20,6 +20,7 @@ Required properties:
         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
         "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
@@ -66,6 +67,8 @@ Required properties:
         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
         "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
         "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
+        "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
+        "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.