Merge branch 'pci/host-xgene' into next

* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: xgene: Add APM X-Gene PCIe driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile

7 files changed, 908 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt
new file mode 100644
index 000000000000..1070b068c7c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt
@@ -0,0 +1,57 @@
+* AppliedMicro X-Gene PCIe interface
+
+Required properties:
+- device_type: set to "pci"
+- compatible: should contain "apm,xgene-pcie" to identify the core.
+- reg: A list of physical base address and length for each set of controller
+       registers. Must contain an entry for each entry in the reg-names
+       property.
+- reg-names: Must include the following entries:
+  "csr": controller configuration registers.
+  "cfg": pcie configuration space registers.
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the outbound memory, I/O regions.
+- dma-ranges: ranges for the inbound memory regions.
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+        to define the mapping of the PCIe interface to interrupt
+        numbers.
+- clocks: from common clock binding: handle to pci clock.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if dma operations are coherent
+
+Example:
+
+SoC specific DT Entry:
+
+        pcie0: pcie@1f2b0000 {
+                status = "disabled";
+                device_type = "pci";
+                compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                        0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                reg-names = "csr", "cfg";
+                ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                          0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                              0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+                                 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+                                 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+                dma-coherent;
+                clocks = <&pcie0clk 0>;
+        };
+
+
+Board specific DT Entry:
+        &pcie0 {
+                status = "ok";
+        };
diff --git a/MAINTAINERS b/MAINTAINERS
index 07fd7e279700..fac7057ba67c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6868,6 +6868,14 @@ F:	include/linux/pci*
 F:      arch/x86/pci/
 F:      arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR APPLIEDMICRO XGENE
+M:      Tanmay Inamdar <tinamdar@apm.com>
+L:      linux-pci@vger.kernel.org
+L:      linux-arm-kernel@lists.infradead.org
+S:      Maintained
+F:      Documentation/devicetree/bindings/pci/xgene-pci.txt
+F:      drivers/pci/host/pci-xgene.c
+
 PCI DRIVER FOR IMX6
 M:      Richard Zhu <r65037@freescale.com>
 M:      Lucas Stach <l.stach@pengutronix.de>
diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
index b2f56229aa5e..f64900052f4e 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -25,6 +25,14 @@
         };
 };
 
+&pcie0clk {
+        status = "ok";
+};
+
+&pcie0 {
+        status = "ok";
+};
+
 &serial0 {
         status = "ok";
 };
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index c0aceef7f5b3..403197a0e621 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -269,6 +269,171 @@
                                 enable-mask = <0x2>;
                                 clock-output-names = "rtcclk";
                         };
+
+                        pcie0clk: pcie0clk@1f2bc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2bc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie0clk";
+                        };
+
+                        pcie1clk: pcie1clk@1f2cc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2cc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie1clk";
+                        };
+
+                        pcie2clk: pcie2clk@1f2dc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2dc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie2clk";
+                        };
+
+                        pcie3clk: pcie3clk@1f50c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f50c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie3clk";
+                        };
+
+                        pcie4clk: pcie4clk@1f51c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f51c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie4clk";
+                        };
+                };
+
+                pcie0: pcie@1f2b0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                                0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                                  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1