arm64: dts: Add APM X-Gene PCIe device tree nodes

Add the device tree nodes for APM X-Gene PCIe host controller and PCIe
clock interface.  Since X-Gene SOC supports maximum 5 ports, 5 dts nodes
are added.

Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

2 files changed, 173 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
index b2f56229aa5e..f64900052f4e 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -25,6 +25,14 @@
         };
 };
 
+&pcie0clk {
+        status = "ok";
+};
+
+&pcie0 {
+        status = "ok";
+};
+
 &serial0 {
         status = "ok";
 };
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index c0aceef7f5b3..403197a0e621 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -269,6 +269,171 @@
                                 enable-mask = <0x2>;
                                 clock-output-names = "rtcclk";
                         };
+
+                        pcie0clk: pcie0clk@1f2bc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2bc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie0clk";
+                        };
+
+                        pcie1clk: pcie1clk@1f2cc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2cc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie1clk";
+                        };
+
+                        pcie2clk: pcie2clk@1f2dc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2dc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie2clk";
+                        };
+
+                        pcie3clk: pcie3clk@1f50c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f50c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie3clk";
+                        };
+
+                        pcie4clk: pcie4clk@1f51c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f51c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie4clk";
+                        };
+                };
+
+                pcie0: pcie@1f2b0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                                0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                                  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie0clk 0>;
+                };
+
+                pcie1: pcie@1f2c0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
+                                0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
+                                  0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie1clk 0>;
+                };
+
+                pcie2: pcie@1f2d0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
+                                 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */
+                                  0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie2clk 0>;
+                };
+
+                pcie3: pcie@1f500000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
+                                0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */
+                                  0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie3clk 0>;
+                };
+
+                pcie4: pcie@1f510000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;