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authorBen Skeggs <bskeggs@redhat.com>2010-07-07 21:29:10 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-07-12 20:13:40 -0400
commitf56cb86f9abd229418f894a8ffedfb9ff465c181 (patch)
treeb29420af53d096e49ff573790c6161ed71599858
parent2107cce3056dccf37ae5cbfc95df348959b2c717 (diff)
drm/nouveau: add instmem flush() hook
This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h9
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c45
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c12
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c18
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fifo.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_instmem.c9
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fifo.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c5
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fifo.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c3
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c15
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c33
15 files changed, 39 insertions, 152 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index afebd32af203..e21eacc47290 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -269,8 +269,7 @@ struct nouveau_instmem_engine {
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*prepare_access)(struct drm_device *, bool write); 272 void (*flush)(struct drm_device *);
273 void (*finish_access)(struct drm_device *);
274}; 273};
275 274
276struct nouveau_mc_engine { 275struct nouveau_mc_engine {
@@ -1027,8 +1026,7 @@ extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1027extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1026extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1028extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1027extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1029extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1028extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1030extern void nv04_instmem_prepare_access(struct drm_device *, bool write); 1029extern void nv04_instmem_flush(struct drm_device *);
1031extern void nv04_instmem_finish_access(struct drm_device *);
1032 1030
1033/* nv50_instmem.c */ 1031/* nv50_instmem.c */
1034extern int nv50_instmem_init(struct drm_device *); 1032extern int nv50_instmem_init(struct drm_device *);
@@ -1040,8 +1038,7 @@ extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1040extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1038extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1041extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1039extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1042extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1040extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1043extern void nv50_instmem_prepare_access(struct drm_device *, bool write); 1041extern void nv50_instmem_flush(struct drm_device *);
1044extern void nv50_instmem_finish_access(struct drm_device *);
1045 1042
1046/* nv04_mc.c */ 1043/* nv04_mc.c */
1047extern int nv04_mc_init(struct drm_device *); 1044extern int nv04_mc_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 4b42bf218f61..5152c0a7e6f7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -143,7 +143,6 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
143 phys |= 0x30; 143 phys |= 0x30;
144 } 144 }
145 145
146 dev_priv->engine.instmem.prepare_access(dev, true);
147 while (size) { 146 while (size) {
148 unsigned offset_h = upper_32_bits(phys); 147 unsigned offset_h = upper_32_bits(phys);
149 unsigned offset_l = lower_32_bits(phys); 148 unsigned offset_l = lower_32_bits(phys);
@@ -175,7 +174,7 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
175 } 174 }
176 } 175 }
177 } 176 }
178 dev_priv->engine.instmem.finish_access(dev); 177 dev_priv->engine.instmem.flush(dev);
179 178
180 nv_wr32(dev, 0x100c80, 0x00050001); 179 nv_wr32(dev, 0x100c80, 0x00050001);
181 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 180 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
@@ -218,7 +217,6 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
218 virt -= dev_priv->vm_vram_base; 217 virt -= dev_priv->vm_vram_base;
219 pages = (size >> 16) << 1; 218 pages = (size >> 16) << 1;
220 219
221 dev_priv->engine.instmem.prepare_access(dev, true);
222 while (pages) { 220 while (pages) {
223 pgt = dev_priv->vm_vram_pt[virt >> 29]; 221 pgt = dev_priv->vm_vram_pt[virt >> 29];
224 pte = (virt & 0x1ffe0000ULL) >> 15; 222 pte = (virt & 0x1ffe0000ULL) >> 15;
@@ -232,7 +230,7 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
232 while (pte < end) 230 while (pte < end)
233 nv_wo32(dev, pgt, pte++, 0); 231 nv_wo32(dev, pgt, pte++, 0);
234 } 232 }
235 dev_priv->engine.instmem.finish_access(dev); 233 dev_priv->engine.instmem.flush(dev);
236 234
237 nv_wr32(dev, 0x100c80, 0x00050001); 235 nv_wr32(dev, 0x100c80, 0x00050001);
238 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 236 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 5624f37e4c75..7d86e05ac883 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -132,7 +132,6 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
132 } 132 }
133 } 133 }
134 134
135 instmem->prepare_access(dev, true);
136 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); 135 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
137 do { 136 do {
138 if (!nouveau_ramht_entry_valid(dev, ramht, co)) { 137 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
@@ -143,7 +142,7 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
143 nv_wo32(dev, ramht, (co + 4)/4, ctx); 142 nv_wo32(dev, ramht, (co + 4)/4, ctx);
144 143
145 list_add_tail(&ref->list, &chan->ramht_refs); 144 list_add_tail(&ref->list, &chan->ramht_refs);
146 instmem->finish_access(dev); 145 instmem->flush(dev);
147 return 0; 146 return 0;
148 } 147 }
149 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n", 148 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
@@ -153,7 +152,6 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
153 if (co >= dev_priv->ramht_size) 152 if (co >= dev_priv->ramht_size)
154 co = 0; 153 co = 0;
155 } while (co != ho); 154 } while (co != ho);
156 instmem->finish_access(dev);
157 155
158 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id); 156 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
159 return -ENOMEM; 157 return -ENOMEM;
@@ -173,7 +171,6 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
173 return; 171 return;
174 } 172 }
175 173
176 instmem->prepare_access(dev, true);
177 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); 174 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
178 do { 175 do {
179 if (nouveau_ramht_entry_valid(dev, ramht, co) && 176 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
@@ -186,7 +183,7 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
186 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000); 183 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
187 184
188 list_del(&ref->list); 185 list_del(&ref->list);
189 instmem->finish_access(dev); 186 instmem->flush(dev);
190 return; 187 return;
191 } 188 }
192 189
@@ -195,7 +192,6 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
195 co = 0; 192 co = 0;
196 } while (co != ho); 193 } while (co != ho);
197 list_del(&ref->list); 194 list_del(&ref->list);
198 instmem->finish_access(dev);
199 195
200 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n", 196 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
201 chan->id, ref->handle); 197 chan->id, ref->handle);
@@ -280,10 +276,9 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
280 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { 276 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
281 int i; 277 int i;
282