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authorStephane Eranian <eranian@google.com>2014-01-08 05:15:53 -0500
committerIngo Molnar <mingo@kernel.org>2014-01-12 04:16:08 -0500
commitf228c5b882602697a1adb50d61ff688b0df1eced (patch)
treee5ce02d0b6de20c8a1aa15e6d36ce8d28d39b9af
parentf3ae75de98c4bac145a87d830c156c96f9414022 (diff)
perf/x86/intel: Add Intel RAPL PP1 energy counter support
This patch adds support for the Intel RAPL energy counter PP1 (Power Plane 1). On client processors, it usually corresponds to the energy consumption of the builtin graphic card. That is why the sysfs event is called energy-gpu. New event: - name: power/energy-gpu/ - code: event=0x4 - unit: 2^-32 Joules On processors without graphics, this should count 0. The patch only enables this event on client processors. Reviewed-by: Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com> Signed-off-by: Stephane Eranian <eranian@google.com> Cc: ak@linux.intel.com Cc: acme@redhat.com Cc: jolsa@redhat.com Cc: zheng.z.yan@intel.com Cc: bp@alien8.de Cc: vincent.weaver@maine.edu Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1389176153-3128-3-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_rapl.c31
1 files changed, 24 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_rapl.c b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
index 0e3754e450d9..5ad35ad94d0f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_rapl.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
@@ -27,6 +27,10 @@
27 * event: rapl_energy_dram 27 * event: rapl_energy_dram
28 * perf code: 0x3 28 * perf code: 0x3
29 * 29 *
30 * dram counter: consumption of the builtin-gpu domain (client only)
31 * event: rapl_energy_gpu
32 * perf code: 0x4
33 *
30 * We manage those counters as free running (read-only). They may be 34 * We manage those counters as free running (read-only). They may be
31 * use simultaneously by other tools, such as turbostat. 35 * use simultaneously by other tools, such as turbostat.
32 * 36 *
@@ -55,10 +59,13 @@
55#define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */ 59#define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
56#define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */ 60#define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
57#define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */ 61#define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
62#define RAPL_IDX_PP1_NRG_STAT 3 /* DRAM */
63#define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
58 64
59/* Clients have PP0, PKG */ 65/* Clients have PP0, PKG */
60#define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ 66#define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
61 1<<RAPL_IDX_PKG_NRG_STAT) 67 1<<RAPL_IDX_PKG_NRG_STAT|\
68 1<<RAPL_IDX_PP1_NRG_STAT)
62 69
63/* Servers have PP0, PKG, RAM */ 70/* Servers have PP0, PKG, RAM */
64#define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\ 71#define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
@@ -315,6 +322,10 @@ static int rapl_pmu_event_init(struct perf_event *event)
315 bit = RAPL_IDX_RAM_NRG_STAT; 322 bit = RAPL_IDX_RAM_NRG_STAT;
316 msr = MSR_DRAM_ENERGY_STATUS; 323 msr = MSR_DRAM_ENERGY_STATUS;
317 break; 324 break;
325 case INTEL_RAPL_PP1:
326 bit = RAPL_IDX_PP1_NRG_STAT;
327 msr = MSR_PP1_ENERGY_STATUS;
328 break;
318 default: 329 default:
319 return -EINVAL; 330 return -EINVAL;
320 } 331 }
@@ -367,19 +378,22 @@ static struct attribute_group rapl_pmu_attr_group = {
367}; 378};
368 379
369EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); 380EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
370EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); 381EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
371EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); 382EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
383EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
372 384
373EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); 385EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
374EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); 386EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
375EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); 387EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
388EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
376 389
377/* 390/*
378 * we compute in 0.23 nJ increments regardless of MSR 391 * we compute in 0.23 nJ increments regardless of MSR
379 */ 392 */
380EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); 393EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
381EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); 394EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
382EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); 395EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
396EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
383 397
384static struct attribute *rapl_events_srv_attr[] = { 398static struct attribute *rapl_events_srv_attr[] = {
385 EVENT_PTR(rapl_cores), 399 EVENT_PTR(rapl_cores),
@@ -399,12 +413,15 @@ static struct attribute *rapl_events_srv_attr[] = {
399static struct attribute *rapl_events_cln_attr[] = { 413static struct attribute *rapl_events_cln_attr[] = {
400 EVENT_PTR(rapl_cores), 414 EVENT_PTR(rapl_cores),
401 EVENT_PTR(rapl_pkg), 415 EVENT_PTR(rapl_pkg),
416 EVENT_PTR(rapl_gpu),
402 417
403 EVENT_PTR(rapl_cores_unit), 418 EVENT_PTR(rapl_cores_unit),
404 EVENT_PTR(rapl_pkg_unit), 419 EVENT_PTR(rapl_pkg_unit),
420 EVENT_PTR(rapl_gpu_unit),
405 421
406 EVENT_PTR(rapl_cores_scale), 422 EVENT_PTR(rapl_cores_scale),
407 EVENT_PTR(rapl_pkg_scale), 423 EVENT_PTR(rapl_pkg_scale),
424 EVENT_PTR(rapl_gpu_scale),
408 NULL, 425 NULL,
409}; 426};
410 427