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authorOlof Johansson <olof@lixom.net>2012-09-16 21:25:15 -0400
committerOlof Johansson <olof@lixom.net>2012-09-16 21:25:15 -0400
commitea2abb670b712380adf0aa6945dc651711ac2b92 (patch)
tree4708bd5d9c6d30af1b90491abbfcd052f74a32f5
parent26a806c064b7be25fc7c255b5d83646cf4645a93 (diff)
parentb4350f40f73b75efdceae3d9e04266979acabd8c (diff)
Merge tag 'tegra-for-3.7-common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren: ARM: tegra: switch to the common clock framework This branch contains a few bug-fixes, followed by a conversion of Tegra's clock driver to the common clock framework, followed by various bug fixes found after the conversion. * tag 'tegra-for-3.7-common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: Tegra: Add smp_twd clock for Tegra20 ARM: tegra: cpu-tegra: explicitly manage re-parenting ARM: tegra: fix overflow in tegra20_pll_clk_round_rate() ARM: tegra: Fix data type for io address ARM: tegra: remove tegra_timer from tegra_list_clks ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30 ARM: tegra: Remove duplicate code ARM: tegra: Port tegra to generic clock framework ARM: tegra: Add clk_tegra structure and helper functions ARM: tegra: Rename tegra20 clock file ARM: tegra20: Separate out clk ops and clk data ARM: tegra30: Separate out clk ops and clk data ARM: tegra: fix U16 divider range check ARM: tegra: turn on UART A clock at boot
Diffstat
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-tegra/Makefile4
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c1
-rw-r--r--arch/arm/mach-tegra/clock.c570
-rw-r--r--arch/arm/mach-tegra/clock.h40
-rw-r--r--arch/arm/mach-tegra/common.c1
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c48
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h3
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1555
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h42
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c1142
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2484
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c2475
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h53
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1369
15 files changed, 5055 insertions, 4733 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 46ef5652da68..60355f1cc4b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -686,6 +686,7 @@ config ARCH_TEGRA
686 select NEED_MACH_IO_H if PCI 686 select NEED_MACH_IO_H if PCI
687 select ARCH_HAS_CPUFREQ 687 select ARCH_HAS_CPUFREQ
688 select USE_OF 688 select USE_OF
689 select COMMON_CLK
689 help 690 help
690 This enables support for NVIDIA Tegra based systems (Tegra APX, 691 This enables support for NVIDIA Tegra based systems (Tegra APX,
691 Tegra 6xx and Tegra 2 series). 692 Tegra 6xx and Tegra 2 series).
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303b9ac8..f07f99452a98 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,9 +12,11 @@ obj-y += powergate.o
12obj-y += apbio.o 12obj-y += apbio.o
13obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
14obj-$(CONFIG_CPU_IDLE) += sleep.o 14obj-$(CONFIG_CPU_IDLE) += sleep.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 20obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_SMP) += reset.o 21obj-$(CONFIG_SMP) += reset.o
20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 22obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index c0999633a9ab..b4e7cc14713c 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -71,6 +71,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
71 71
72static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 72static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
73 /* name parent rate enabled */ 73 /* name parent rate enabled */
74 { "uarta", "pll_p", 216000000, true },
74 { "uartd", "pll_p", 216000000, true }, 75 { "uartd", "pll_p", 216000000, true },
75 { "usbd", "clk_m", 12000000, false }, 76 { "usbd", "clk_m", 12000000, false },
76 { "usb2", "clk_m", 12000000, false }, 77 { "usb2", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c0819c..632133fc985b 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010 Google, Inc. 3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
4 * 5 *
5 * Author: 6 * Author:
6 * Colin Cross <ccross@google.com> 7 * Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/clkdev.h> 22#include <linux/clkdev.h>
22#include <linux/debugfs.h>
23#include <linux/delay.h>
24#include <linux/init.h> 23#include <linux/init.h>
25#include <linux/list.h> 24#include <linux/list.h>
26#include <linux/module.h> 25#include <linux/module.h>
@@ -36,321 +35,67 @@
36/* 35/*
37 * Locking: 36 * Locking:
38 * 37 *
39 * Each struct clk has a spinlock.
40 *
41 * To avoid AB-BA locking problems, locks must always be traversed from child
42 * clock to parent clock. For example, when enabling a clock, the clock's lock
43 * is taken, and then clk_enable is called on the parent, which take's the
44 * parent clock's lock. There is one exceptions to this ordering: When dumping
45 * the clock tree through debugfs. In this case, clk_lock_all is called,
46 * which attemps to iterate through the entire list of clocks and take every
47 * clock lock. If any call to spin_trylock fails, all locked clocks are
48 * unlocked, and the process is retried. When all the locks are held,
49 * the only clock operation that can be called is clk_get_rate_all_locked.
50 *
51 * Within a single clock, no clock operation can call another clock operation
52 * on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any
53 * clock operation can call any other clock operation on any of it's possible
54 * parents.
55 *
56 * An additional mutex, clock_list_lock, is used to protect the list of all 38 * An additional mutex, clock_list_lock, is used to protect the list of all
57 * clocks. 39 * clocks.
58 * 40 *
59 * The clock operations must lock internally to protect against
60 * read-modify-write on registers that are shared by multiple clocks
61 */ 41 */
62static DEFINE_MUTEX(clock_list_lock); 42static DEFINE_MUTEX(clock_list_lock);
63static LIST_HEAD(clocks); 43static LIST_HEAD(clocks);
64 44
65struct clk *tegra_get_clock_by_name(const char *name) 45void tegra_clk_add(struct clk *clk)
66{ 46{
67 struct clk *c; 47 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
68 struct clk *ret = NULL;
69 mutex_lock(&clock_list_lock);
70 list_for_each_entry(c, &clocks, node) {
71 if (strcmp(c->name, name) == 0) {
72 ret = c;
73 break;
74 }
75 }
76 mutex_unlock(&clock_list_lock);
77 return ret;
78}
79
80/* Must be called with c->spinlock held */
81static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
82{
83 u64 rate;
84
85 rate = clk_get_rate(p);
86
87 if (c->mul != 0 && c->div != 0) {
88 rate *= c->mul;
89 rate += c->div - 1; /* round up */
90 do_div(rate, c->div);
91 }
92
93 return rate;
94}
95
96/* Must be called with c->spinlock held */
97unsigned long clk_get_rate_locked(struct clk *c)
98{
99 unsigned long rate;
100
101 if (c->parent)
102 rate = clk_predict_rate_from_parent(c, c->parent);
103 else
104 rate = c->rate;
105
106 return rate;
107}
108
109unsigned long clk_get_rate(struct clk *c)
110{
111 unsigned long flags;
112 unsigned long rate;
113
114 spin_lock_irqsave(&c->spinlock, flags);
115
116 rate = clk_get_rate_locked(c);
117
118 spin_unlock_irqrestore(&c->spinlock, flags);
119
120 return rate;
121}
122EXPORT_SYMBOL(clk_get_rate);
123
124int clk_reparent(struct clk *c, struct clk *parent)
125{
126 c->parent = parent;
127 return 0;
128}
129
130void clk_init(struct clk *c)
131{
132 spin_lock_init(&c->spinlock);
133
134 if (c->ops && c->ops->init)
135 c->ops->init(c);
136
137 if (!c->ops || !c->ops->enable) {
138 c->refcnt++;
139 c->set = true;
140 if (c->parent)
141 c->state = c->parent->state;
142 else
143 c->state = ON;
144 }
145 48
146 mutex_lock(&clock_list_lock); 49 mutex_lock(&clock_list_lock);
147 list_add(&c->node, &clocks); 50 list_add(&c->node, &clocks);
148 mutex_unlock(&clock_list_lock); 51 mutex_unlock(&clock_list_lock);
149} 52}
150 53
151int clk_enable(struct clk *c) 54struct clk *tegra_get_clock_by_name(const char *name)
152{
153 int ret = 0;
154 unsigned long flags;
155
156 spin_lock_irqsave(&c->spinlock, flags);
157
158 if (c->refcnt == 0) {
159 if (c->parent) {
160 ret = clk_enable(c->parent);
161 if (ret)
162 goto out;
163 }
164
165 if (c->ops && c->ops->enable) {
166 ret = c->ops->enable(c);
167 if (ret) {
168 if (c->parent)
169 clk_disable(c->parent);
170 goto out;
171 }
172 c->state = ON;
173 c->set = true;
174 }
175 }
176 c->refcnt++;
177out:
178 spin_unlock_irqrestore(&c->spinlock, flags);
179 return ret;
180}
181EXPORT_SYMBOL(clk_enable);
182
183void clk_disable(struct clk *c)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&c->spinlock, flags);
188
189 if (c->refcnt == 0) {
190 WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
191 spin_unlock_irqrestore(&c->spinlock, flags);
192 return;
193 }
194 if (c->refcnt == 1) {
195 if (c->ops && c->ops->disable)
196 c->ops->disable(c);
197
198 if (c->parent)
199 clk_disable(c->parent);
200
201 c->state = OFF;
202 }
203 c->refcnt--;
204
205 spin_unlock_irqrestore(&c->spinlock, flags);
206}
207EXPORT_SYMBOL(clk_disable);
208
209int clk_set_parent(struct clk *c, struct clk *parent)
210{
211 int ret;
212 unsigned long flags;
213 unsigned long new_rate;
214 unsigned long old_rate;
215
216 spin_lock_irqsave(&c->spinlock, flags);
217
218 if (!c->ops || !c->ops->set_parent) {
219 ret = -ENOSYS;
220 goto out;
221 }
222
223 new_rate = clk_predict_rate_from_parent(c, parent);
224 old_rate = clk_get_rate_locked(c);
225
226 ret = c->ops->set_parent(c, parent);
227 if (ret)
228 goto out;
229
230out:
231 spin_unlock_irqrestore(&c->spinlock, flags);
232 return ret;
233}
234EXPORT_SYMBOL(clk_set_parent);
235
236struct clk *clk_get_parent(struct clk *c)
237{
238 return c->parent;
239}
240EXPORT_SYMBOL(clk_get_parent);
241
242int clk_set_rate_locked(struct clk *c, unsigned long rate)
243{
244 long new_rate;
245
246 if (!c->ops || !c->ops->set_rate)
247 return -ENOSYS;
248
249 if (rate > c->max_rate)
250 rate = c->max_rate;
251
252 if (c->ops && c->ops->round_rate) {
253 new_rate = c->ops->round_rate(c, rate);
254
255 if (new_rate < 0)
256 return new_rate;
257
258 rate = new_rate;
259 }
260
261 return c->ops->set_rate(c, rate);
262}
263
264int clk_set_rate(struct clk *c, unsigned long rate)
265{
266 int ret;
267 unsigned long flags;
268
269 spin_lock_irqsave(&c->spinlock, flags);
270
271 ret = clk_set_rate_locked(c, rate);
272
273 spin_unlock_irqrestore(&c->spinlock, flags);
274
275 return ret;
276}
277EXPORT_SYMBOL(clk_set_rate);
278
279
280/* Must be called with clocks lock and all indvidual clock locks held */
281unsigned long clk_get_rate_all_locked(struct clk *c)
282{ 55{
283 u64 rate; 56 struct clk_tegra *c;
284 int mul = 1; 57 struct clk *ret = NULL;
285 int div = 1; 58 mutex_lock(&clock_list_lock);
286 struct clk *p = c; 59 list_for_each_entry(c, &clocks, node) {
287 60 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
288 while (p) { 61 ret = c->hw.clk;
289 c = p; 62 break;
290 if (c->mul != 0 && c->div != 0) {
291 mul *= c->mul;
292 div *= c->div;
293 } 63 }
294 p = c->parent;
295 } 64 }
296 65 mutex_unlock(&clock_list_lock);
297 rate = c->rate;
298 rate *= mul;
299 do_div(rate, div);
300
301 return rate;
302}
303
304long clk_round_rate(struct clk *c, unsigned long rate)
305{
306 unsigned long flags;
307 long ret;
308
309 spin_lock_irqsave(&c->spinlock, flags);
310
311 if (!c->ops || !c->ops->round_rate) {
312 ret = -ENOSYS;
313 goto out;
314 }
315
316 if (rate > c->max_rate)
317 rate = c->max_rate;
318
319 ret = c->ops->round_rate(c, rate);
320
321out:
322 spin_unlock_irqrestore(&c->spinlock, flags);
323 return ret; 66 return ret;
324} 67}
325EXPORT_SYMBOL(clk_round_rate);
326 68
327static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) 69static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
328{ 70{
329 struct clk *c; 71 struct clk *c;
330 struct clk *p; 72 struct clk *p;
73 struct clk *parent;
331 74
332 int ret = 0; 75 int ret = 0;
333 76
334 c = tegra_get_clock_by_name(table->name); 77 c = tegra_get_clock_by_name(table->name);
335 78
336 if (!c) { 79 if (!c) {
337 pr_warning("Unable to initialize clock %s\n", 80 pr_warn("Unable to initialize clock %s\n",
338 table->name); 81 table->name);
339 return -ENODEV; 82 return -ENODEV;
340 } 83 }
341 84
85 parent = clk_get_parent(c);
86
342 if (table->parent) { 87 if (table->parent) {
343 p = tegra_get_clock_by_name(table->parent); 88 p = tegra_get_clock_by_name(table->parent);
344 if (!p) { 89 if (!p) {
345 pr_warning("Unable to find parent %s of clock %s\n", 90 pr_warn("Unable to find parent %s of clock %s\n",
346 table->parent, table->name); 91 table->parent, table->name);
347 return -ENODEV; 92 return -ENODEV;
348 } 93 }
349 94
350 if (c->parent != p) { 95 if (parent != p) {
351 ret = clk_set_parent(c, p); 96 ret = clk_set_parent(c, p);
352 if (ret) { 97 if (ret) {
353 pr_warning("Unable to set parent %s of clock %s: %d\n", 98 pr_warn("Unable to set parent %s of clock %s: %d\n",
354 table->parent, table->name, ret); 99 table->parent, table->name, ret);
355 return -EINVAL; 100 return -EINVAL;
356 } 101 }
@@ -360,16 +105,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
360 if (table->rate && table->rate != clk_get_rate(c)) { 105 if (table->rate && table->rate != clk_get_rate(c)) {
361 ret = clk_set_rate(c, table->rate); 106 ret = clk_set_rate(c, table->rate);
362 if (ret) { 107 if (ret) {
363 pr_warning("Unable to set clock %s to rate %lu: %d\n", 108 pr_warn("Unable to set clock %s to rate %lu: %d\n",
364 table->name, table->rate, ret); 109 table->name, table->rate, ret);
365 return -EINVAL; 110 return -EINVAL;
366 } 111 }
367 } 112 }
368 113
369 if (table->enabled) { 114 if (table->enabled) {
370 ret = clk_enable(c); 115 ret = clk_prepare_enable(c);
371 if (ret) { 116 if (ret) {
372 pr_warning("Unable to enable clock %s: %d\n", 117 pr_warn("Unable to enable clock %s: %d\n",
373 table->name, ret); 118 table->name, ret);
374 return -EINVAL; 119 return -EINVAL;
375 } 120 }
@@ -383,19 +128,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
383 for (; table->name; table++) 128 for (; table->name; table++)
384 tegra_clk_init_one_from_table(table); 129 tegra_clk_init_one_from_table(table);
385} 130}
386EXPORT_SYMBOL(tegra_clk_init_from_table);
387 131
388void tegra_periph_reset_deassert(struct clk *c) 132void tegra_periph_reset_deassert(struct clk *c)
389{ 133{
390 BUG_ON(!c->ops->reset); 134 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
391 c->ops->reset(c, false); 135 BUG_ON(!clk->reset);
136 clk->reset(__clk_get_hw(c), false);
392} 137}
393EXPORT_SYMBOL(tegra_periph_reset_deassert); 138EXPORT_SYMBOL(tegra_periph_reset_deassert);
394 139
395void tegra_periph_reset_assert(struct clk *c) 140void tegra_periph_reset_assert(struct clk *c)
396{ 141{
397 BUG_ON(!c->ops->reset); 142 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
398 c->ops->reset(c, true); 143 BUG_ON(!clk->reset);
144 clk->reset(__clk_get_hw(c), true);
399} 145}
400EXPORT_SYMBOL(tegra_periph_reset_assert); 146EXPORT_SYMBOL(tegra_periph_reset_assert);
401 147
@@ -405,268 +151,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
405int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 151int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
406{ 152{
407 int ret = 0; 153 int ret = 0;
408 unsigned long flags; 154 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
409 155
410 spin_lock_irqsave(&c->spinlock, flags); 156 if (!clk->clk_cfg_ex) {
411
412 if (!c->ops || !c->ops->clk_cfg_ex) {
413 ret = -ENOSYS; 157 ret = -ENOSYS;
414 goto out; 158 goto out;
415 } 159 }
416 ret = c->ops->clk_cfg_ex(c, p, setting); 160 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
417 161
418out: 162out:
419 spin_unlock_irqrestore(&c->spinlock, flags);
420
421 return ret; 163 return ret;
422} 164}
423
424#ifdef CONFIG_DEBUG_FS
425
426static int __clk_lock_all_spinlocks(void)
427{
428 struct clk *c;
429
430 list_for_each_entry(c, &clocks, node)
431 if (!spin_trylock(&c->spinlock))
432 goto unlock_spinlocks;
433
434 return 0;
435
436unlock_spinlocks:
437 list_for_each_entry_continue_reverse(c, &clocks, node)
438 spin_unlock(&c->spinlock);
439
440 return -EAGAIN;
441}
442
443static void __clk_unlock_all_spinlocks(void)
444{
445 struct clk *c;
446
447 list_for_each_entry_reverse(c, &clocks, node)
448 spin_unlock(&c->spinlock);
449}
450
451/*
452 * This function retries until it can take all locks, and may take
453 * an arbitrarily long time to complete.
454 * Must be called with irqs enabled, returns with irqs disabled
455 * Must be called with clock_list_lock held
456 */
457static void clk_lock_all(void)
458{
459 int ret;
460retry:
461 local_irq_disable();
462
463 ret = __clk_lock_all_spinlocks();
464 if (ret)
465 goto failed_spinlocks;
466
467 /* All locks taken successfully, return */
468 return;
469
470failed_spinlocks:
471 local_irq_enable();
472 yield();
473 goto retry;
474}
475
476/*
477 * Unlocks all clocks after a clk_lock_all
478 * Must be called with irqs disabled, returns with irqs enabled
479 * Must be called with clock_list_lock held
480 */
481static void clk_unlock_all(void)
482{
483 __clk_unlock_all_spinlocks();
484
485 local_irq_enable();
486}
487
488static struct dentry *clk_debugfs_root;
489
490
491static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
492{
493 struct clk *child;
494 const char *state = "uninit";
495 char div[8] = {0};
496
497 if (c->state == ON)
498 state = "on";
499 else if (c->state == OFF)
500 state = "off";
501
502 if (c->mul != 0 && c->div != 0) {
503 if (c->mul > c->div) {
504 int mul = c->mul / c->div;
505 int mul2 = (c->mul * 10 / c->div) % 10;
506 int mul3 = (c->mul * 10) % c->div;
507 if (mul2 == 0 && mul3 == 0)
508 snprintf(div, sizeof(div), "x%d", mul);
509 else if (mul3 == 0)
510 snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
511 else
512 snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
513 } else {
514 snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
515 (c->div % c->mul) ? ".5" : "");
516 }
517 }
518
519 seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
520 level * 3 + 1, "",
521 c->rate > c->max_rate ? '!' : ' ',
522 !c->set ? '*' : ' ',
523 30 - level * 3, c->name,
524 state, c->refcnt, div, clk_get_rate_all_locked(c));
525
526 list_for_each_entry(child, &clocks, node) {
527 if (child->parent != c)
528 continue;
529
530 clock_tree_show_one(s, child, level + 1);
531 }
532}
533
534static int clock_tree_show(struct seq_file *s, void *data)
535{
536 struct clk *c;
537 seq_printf(s, " clock state ref div rate\n");
538 seq_printf(s, "--------------------------------------------------------------\n");
539
540 mutex_lock(&clock_list_lock);
541
542 clk_lock_all();
543
544 list_for_each_entry(c, &clocks, node)
545 if (c->parent == NULL)
546 clock_tree_show_one(s, c, 0);
547
548 clk_unlock_all();
549
550 mutex_unlock(&clock_list_lock);
551 return 0;
552}
553
554static int clock_tree_open(struct inode *inode, struct file *file)
555{
556 return single_open(file, clock_tree_show, inode->i_private);
557}
558
559static const struct file_operations clock_tree_fops = {
560 .open = clock_tree_open,
561 .read = seq_read,
562 .llseek = seq_lseek,
563 .release = single_release,
564};
565
566static int possible_parents_show(struct seq_file *s, void *data)
567{
568 struct clk *c = s->private;
569 int i;
570
571 for (i = 0; c->inputs[i].input; i++) {
572 char *first = (i == 0) ? "" : " ";
573 seq_printf(s, "%s%s", first, c->inputs[i].input->name);
574 }
575 seq_printf(s, "\n");
576 return 0;
577}
578
579static int possible_parents_open(struct inode *inode, struct file *file)
580{
581 return single_open(file, possible_parents_show, inode->i_private);
582}
583
584static const struct file_operations possible_parents_fops = {
585 .open = possible_parents_open,
586 .read = seq_read,
587 .llseek = seq_lseek,
588 .release = single_release,
589};
590
591static int clk_debugfs_register_one(struct clk *c)
592{
593 struct dentry *d;
594
595 d = debugfs_create_dir(c->name, clk_debugfs_root);
596 if (!d)
597 return -ENOMEM;
598 c->dent = d;
599
600 d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
601 if (!d)
602 goto err_out;
603
604 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
605 if (!d)
606 goto err_out;
607
608 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
609 if (!d)
610 goto err_out;
611
612 if (c->inputs) {
613 d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
614 c, &possible_parents_fops);
615 if (!d)
616 goto err_out;
617 }
618
619 return 0;
620
621err_out:
622 debugfs_remove_recursive(c->dent);
623 return -ENOMEM;
624}
625
626static int clk_debugfs_register(struct clk *c)
627{
628 int err;
629 struct clk *pa = c->parent;
630
631 if (pa && !pa->dent) {
632 err = clk_debugfs_register(pa);
633 if (err)
634 return err;
635 }
636
637 if (!c->dent) {
638 err = clk_debugfs_register_one(c);
639 if (err)
640 return err;
641 }
642 return 0;
643}
644
645int __init tegra_clk_debugfs_init(void)
646{
647 struct clk *c;
648 struct dentry *d;
649 int err = -ENOMEM;
650
651 d = debugfs_create_dir("clock", NULL);
652 if (!d)
653 return -ENOMEM;
654 clk_debugfs_root = d;
655
656 d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
657 &clock_tree_fops);
658 if (!d)
659 goto err_out;
660
661 list_for_each_entry(c, &clocks, node) {
662 err = clk_debugfs_register(c);
663 if (err)
664 goto err_out;
665 }
666 return 0;
667err_out:
668 debugfs_remove_recursive(clk_debugfs_root);
669 return err;
670}
671
672#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc300657deba..2aa37f5c44c0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/include/mach/clock.h 2 * arch/arm/mach-tegra/include/mach/clock.h
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * Author: 7 * Author:
7 * Colin Cross <ccross@google.com> 8 * Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
20#ifndef __MACH_TEGRA_CLOCK_H 21#ifndef __MACH_TEGRA_CLOCK_H
21#define __MACH_TEGRA_CLOCK_H 22#define __MACH_TEGRA_CLOCK_H
22 23
24#include <linux/clk-provider.h>
23#include <linux/clkdev.h> 25#include <linux/clkdev.h>
24#include <linux/list.h> 26#include <linux/list.h>
25#include <linux/spinlock.h>
26 27
27#include <mach/clk.h> 28#include <mach/clk.h>
28 29
@@ -52,7 +53,8 @@
52#define ENABLE_ON_INIT (1 << 28) 53#define ENABLE_ON_INIT (1 << 28)
53#define PERIPH_ON_APB (1 << 29) 54#define PERIPH_ON_APB (1 << 29)
54 55
55struct clk; 56struct clk_tegra;
57#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
56 58
57struct clk_mux_sel { 59struct clk_mux_sel {
58 struct clk *input; 60 struct clk *input;
@@ -68,47 +70,29 @@ struct clk_pll_freq_table {
68 u8 cpcon; 70 u8 cpcon;
69}; 71};
70 72
71struct clk_ops {
72 void (*init)(struct clk *);
73 int (*enable)(struct clk *);
74 void (*disable)(struct clk *);
75 int (*set_parent)(struct clk *, struct clk *);
76 int (*set_rate)(struct clk *, unsigned long);
77 long (*round_rate)(struct clk *, unsigned long);
78 void (*reset)(struct clk *, bool);
79 int (*clk_cfg_ex)(struct clk *,
80 enum tegra_clk_ex_param, u32);
81};
82
83enum clk_state { 73enum clk_state {
84 UNINITIALIZED = 0, 74 UNINITIALIZED = 0,
85 ON, 75 ON,
86 OFF, 76 OFF,
87}; 77};
88 78
89struct clk { 79struct clk_tegra {
90 /* node for master clocks list */ 80 /* node for master clocks list */
91 struct list_head node; /* node for list of all clocks */ 81 struct list_head node; /* node for list of all clocks */
92 struct clk_lookup lookup; 82 struct clk_lookup lookup;
83 struct clk_hw hw;
93 84
94#ifdef CONFIG_DEBUG_FS
95 struct dentry *dent;
96#endif
97 bool set; 85 bool set;
98 struct clk_ops *ops; 86 unsigned long fixed_rate;
99 unsigned long rate;
100 unsigned long max_rate; 87 unsigned long max_rate;
101 unsigned long min_rate; 88 unsigned long min_rate;
102 u32 flags; 89 u32 flags;
103 const char *name; 90 const char *name;
104 91
105 u32 refcnt;
106 enum clk_state state; 92 enum clk_state state;
107 struct clk *parent;
108 u32 div; 93 u32 div;
109 u32 mul; 94 u32 mul;
110 95
111 const struct clk_mux_sel *inputs;
112 u32 reg; 96 u32 reg;
113 u32 reg_shift; 97 u32 reg_shift;
114 98
@@ -144,7 +128,8 @@ struct clk {
144 } shared_bus_user; 128 } shared_bus_user;
145 } u; 129 } u;
146 130
147 spinlock_t spinlock; 131 void (*reset)(struct clk_hw *, bool);
132 int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
148}; 133};
149 134
150struct clk_duplicate { 135struct clk_duplicate {
@@ -159,13 +144,10 @@ struct tegra_clk_init_table {
159 bool enabled; 144 bool enabled;
160}; 145};
161 146
147void tegra_clk_add(struct clk *c);
162void tegra2_init_clocks(void); 148void tegra2_init_clocks(void);
163void tegra30_init_clocks(void); 149void tegra30_init_clocks(void);
164void clk_init(struct clk *clk);
165struct clk *tegra_get_clock_by_name(const char *name); 150struct clk *tegra_get_clock_by_name(const char *name);
166int clk_reparent(struct clk *c, struct clk *parent);
167void tegra_clk_init_from_table(struct tegra_clk_init_table *table); 151void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
168unsigned long clk_get_rate_locked(struct clk *c);
169int clk_set_rate_locked(struct clk *c, unsigned long rate);
170 152
171#endif 153#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6bcc651..f3654f830991 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -152,6 +152,5 @@ void __init tegra30_init_early(void)
152 152
153void __init tegra_init_late(void) 153void __init tegra_init_late(void)
154{ 154{
155 tegra_clk_debugfs_init();
156 tegra_powergate_debugfs_init(); 155 tegra_powergate_debugfs_init();
157} 156}
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db1e2f1..627bf0f4262e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
49#define NUM_CPUS 2 49#define NUM_CPUS 2
50 50
51static struct clk *cpu_clk; 51static struct clk *cpu_clk;
52static struct clk *pll_x_clk;
53static struct clk *pll_p_clk;
52static struct clk *emc_clk; 54static struct clk *emc_clk;
53 55
54static unsigned long target_cpu_speed[NUM_CPUS]; 56static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
71 return rate; 73 return rate;
72} 74}
73 75
76static int tegra_cpu_clk_set_rate(unsigned long rate)
77{
78 int ret;
79
80 /*
81 * Take an extra reference to the main pll so it doesn't turn
82 * off when we move the cpu off of it
83 */
84 clk_prepare_enable(pll_x_clk);
85
86 ret = clk_set_parent(cpu_clk, pll_p_clk);
87 if (ret) {
88 pr_err("Failed to switch cpu to clock pll_p\n");
89 goto out;
90 }
91
92 if (rate == clk_get_rate(pll_p_clk))
93 goto out;
94
95 ret = clk_set_rate(pll_x_clk, rate);
96 if (ret) {
97 pr_err("Failed to change pll_x to %lu\n", rate);
98 goto out;
99 }
100
101 ret = clk_set_parent(cpu_clk, pll_x_clk);
102 if (ret) {
103 pr_err("Failed to switch cpu to clock pll_x\n");
104 goto out;
105 }
106
107out:
108 clk_disable_unprepare(pll_x_clk);
109 return ret;
110}
111
74static int tegra_update_cpu_speed(unsigned long rate) 112static int tegra_update_cpu_speed(unsigned long rate)
75{ 113{
76 int ret = 0; 114 int ret = 0;
@@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
101 freqs.old, freqs.new); 139 freqs.old, freqs.new);
102#endif 140#endif
103 141
104 ret = clk_set_rate(cpu_clk, freqs.new * 1000); 142 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
105 if (ret) { 143 if (ret) {
106 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n", 144 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
107 freqs.new); 145 freqs.new);
@@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
183 if (IS_ERR(cpu_clk)) 221 if (IS_ERR(cpu_clk))
184 return PTR_ERR(cpu_clk); 222 return PTR_ERR(cpu_clk);
185 223
224 pll_x_clk = clk_get_sys(NULL, "pll_x");
225 if (IS_ERR(pll_x_clk))
226 return PTR_ERR(pll_x_clk);
227
228 pll_p_clk = clk_get_sys(NULL, "pll_p");
229 if (IS_ERR(pll_p_clk))
230 return PTR_ERR(pll_p_clk);
231
186 emc_clk = clk_get_sys("cpu", "emc"); 232 emc_clk = clk_get_sys("cpu", "emc");
187 if (IS_ERR(emc_clk)) { 233 if (IS_ERR(emc_clk)) {
188 clk_put(cpu_clk); 234 clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403303a0..95f3a547c770 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
34void tegra_periph_reset_deassert(struct clk *c); 34void tegra_periph_reset_deassert(struct clk *c);
35void tegra_periph_reset_assert(struct clk *c); 35void tegra_periph_reset_assert(struct clk *c);
36 36
37#ifndef CONFIG_COMMON_CLK
37unsigned long clk_get_rate_all_locked(struct clk *c); 38unsigned long clk_get_rate_all_locked(struct clk *c);
39#endif
40
38void tegra2_sdmmc_tap_delay(struct clk *c, int delay); 41void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
39int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting); 42int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
40 43
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 000000000000..840ab262272a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1555 @@
1/*
2 * arch/arm/mach-tegra/tegra20_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clkdev.h>
28#include <linux/clk.h>
29
30#include <mach/iomap.h>
31#include <mach/suspend.h>
32
33#include "clock.h"
34#include "fuse.h"
35#include "tegra2_emc.h"
36
37#define RST_DEVICES 0x004
38#define RST_DEVICES_SET 0x300
39#define RST_DEVICES_CLR 0x304
40#define RST_DEVICES_NUM 3
41
42#define CLK_OUT_ENB 0x010
43#define CLK_OUT_ENB_SET 0x320
44#define CLK_OUT_ENB_CLR 0x324
45#define CLK_OUT_ENB_NUM 3
46
47#define CLK_MASK_ARM 0x44
48#define MISC_CLK_ENB 0x48
49
50#define OSC_CTRL 0x50
51#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
52#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
53#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
54#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
55#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
56#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
57
58#define OSC_FREQ_DET 0x58
59#define OSC_FREQ_DET_TRIG (1<<31)
60
61#define OSC_FREQ_DET_STATUS 0x5C
62#define OSC_FREQ_DET_BUSY (1<<31)
63#define OSC_FREQ_DET_CNT_MASK 0xFFFF
64
65#define PERIPH_CLK_SOURCE_I2S1 0x100
66#define PERIPH_CLK_SOURCE_EMC 0x19c
67#define PERIPH_CLK_SOURCE_OSC 0x1fc
68#define PERIPH_CLK_SOURCE_NUM \
69 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
70
71#define PERIPH_CLK_SOURCE_MASK (3<<30)
72#define PERIPH_CLK_SOURCE_SHIFT 30
73#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
74#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
75#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
76#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
77#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
78#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
79
80#define SDMMC_CLK_INT_FB_SEL (1 << 23)
81#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
82#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
83
84#define PLL_BASE 0x0
85#define PLL_BASE_BYPASS (1<<31)
86#define PLL_BASE_ENABLE (1<<30)
87#define PLL_BASE_REF_ENABLE (1<<29)
88#define PLL_BASE_OVERRIDE (1<<28)
89#define PLL_BASE_DIVP_MASK (0x7<<20)
90#define PLL_BASE_DIVP_SHIFT 20
91#define PLL_BASE_DIVN_MASK (0x3FF<<8)
92#define PLL_BASE_DIVN_SHIFT 8
93#define PLL_BASE_DIVM_MASK (0x1F)
94#define PLL_BASE_DIVM_SHIFT 0
95
96#define PLL_OUT_RATIO_MASK (0xFF<<8)
97#define PLL_OUT_RATIO_SHIFT 8
98#define PLL_OUT_OVERRIDE (1<<2)
99#define PLL_OUT_CLKEN (1<<1)
100#define PLL_OUT_RESET_DISABLE (1<<0)
101
102#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
103
104#define PLL_MISC_DCCON_SHIFT 20
105#define PLL_MISC_CPCON_SHIFT 8
106#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
107#define PLL_MISC_LFCON_SHIFT 4
108#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
109#define PLL_MISC_VCOCON_SHIFT 0
110#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
111
112#define PLLU_BASE_POST_DIV (1<<20)
113
114#define PLLD_MISC_CLKENABLE (1<<30)
115#define PLLD_MISC_DIV_RST (1<<23)
116#define PLLD_MISC_DCCON_SHIFT 12
117
118#define PLLE_MISC_READY (1 << 15)
119
120#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
121#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
122#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
123
124#define SUPER_CLK_MUX 0x00
125#define SUPER_STATE_SHIFT 28
126#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
127#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
128#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
131#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
132#define SUPER_SOURCE_MASK 0xF
133#define SUPER_FIQ_SOURCE_SHIFT 12
134#define SUPER_IRQ_SOURCE_SHIFT 8
135#define SUPER_RUN_SOURCE_SHIFT 4
136#define SUPER_IDLE_SOURCE_SHIFT 0
137
138#define SUPER_CLK_DIVIDER 0x04
139
140#define BUS_CLK_DISABLE (1<<3)
141#define BUS_CLK_DIV_MASK 0x3
142
143#define PMC_CTRL 0x0
144 #define PMC_CTRL_BLINK_ENB (1 << 7)
145
146#define PMC_DPD_PADS_ORIDE 0x1c
147 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
148
149#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
150#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
151#define PMC_BLINK_TIMER_ENB (1 << 15)
152#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
153#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
154
155static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
156static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
157
158/*
159 * Some clocks share a register with other clocks. Any clock op that
160 * non-atomically modifies a register used by another clock must lock
161 * clock_register_lock first.
162 */
163static DEFINE_SPINLOCK(clock_register_lock);
164
165/*
166 * Some peripheral clocks share an enable bit, so refcount the enable bits
167 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
168 */
169static int tegra_periph_clk_enable_refcount[3 * 32];
170
171#define clk_writel(value, reg) \
172 __raw_writel(value, reg_clk_base + (reg))
173#define clk_readl(reg) \
174 __raw_readl(reg_clk_base + (reg))
175#define pmc_writel(value, reg) \
176 __raw_writel(value, reg_pmc_base + (reg))
177#define pmc_readl(reg) \
178 __raw_readl(reg_pmc_base + (reg))
179
180static unsigned long clk_measure_input_freq(void)
181{
182 u32 clock_autodetect;
183 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
184 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
185 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
186 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
187 return 12000000;
188 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
189 return 13000000;
190 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
191 return 19200000;
192 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
193 return 26000000;
194 } else {
195 pr_err("%s: Unexpected clock autodetect value %d",
196 __func__, clock_autodetect);
197 BUG();
198 return 0;
199 }
200}
201
202static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
203{
204 s64 divider_u71 = parent_rate * 2;
205 divider_u71 += rate - 1;
206 do_div(divider_u71, rate);
207
208 if (divider_u71 - 2 < 0)
209 return 0;
210
211 if (divider_u71 - 2 > 255)
212 return -EINVAL;
213
214 return divider_u71 - 2;
215}
216
217static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
218{
219 s64 divider_u16;
220
221 divider_u16 = parent_rate;
222 divider_u16 += rate - 1;
223 do_div(divider_u16, rate);
224
225 if (divider_u16 - 1 < 0)
226 return 0;
227
228 if (divider_u16 - 1 > 0xFFFF)
229 return -EINVAL;
230
231 return divider_u16 - 1;
232}
233
234static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
235 unsigned long parent_rate)
236{
237 return to_clk_tegra(hw)->fixed_rate;
238}
239
240struct clk_ops tegra_clk_32k_ops = {
241 .recalc_rate = tegra_clk_fixed_recalc_rate,
242};
243
244/* clk_m functions */
245static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
246 unsigned long prate)
247{
248 if (!to_clk_tegra(hw)->fixed_rate)
249 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
250 return to_clk_tegra(hw)->fixed_rate;
251}
252
253static void tegra20_clk_m_init(struct clk_hw *hw)
254{
255 struct clk_tegra *c = to_clk_tegra(hw);
256 u32 osc_ctrl = clk_readl(OSC_CTRL);
257 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
258
259 switch (c->fixed_rate) {
260 case 12000000:
261 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
262 break;
263 case 13000000:
264 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
265 break;
266 case 19200000:
267 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
268 break;
269 case 26000000:
270 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
271 break;
272 default:
273 BUG();
274 }
275 clk_writel(auto_clock_control, OSC_CTRL);
276}
277
278struct clk_ops tegra_clk_m_ops = {
279 .init = tegra20_clk_m_init,
280 .recalc_rate = tegra20_clk_m_recalc_rate,
281};
282
283/* super clock functions */
284/* "super clocks" on tegra have two-stage muxes and a clock skipping
285 * super divider. We will ignore the clock skipping divider, since we
286 * can't lower the voltage when using the clock skip, but we can if we
287 * lower the PLL frequency.
288 */
289static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
290{
291 struct clk_tegra *c = to_clk_tegra(hw);
292 u32 val;
293
294 val = clk_readl(c->reg + SUPER_CLK_MUX);
295 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
296 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
297 c->state = ON;
298 return c->state;
299}
300
301static int tegra20_super_clk_enable(struct clk_hw *hw)
302{
303 struct clk_tegra *c = to_clk_tegra(hw);
304 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
305 return 0;
306}
307
308static void tegra20_super_clk_disable(struct clk_hw *hw)
309{
310 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
311
312 /* oops - don't disable the CPU clock! */
313 BUG();
314}
315
316static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
317{
318 struct clk_tegra *c = to_clk_tegra(hw);
319 int val = clk_readl(c->reg + SUPER_CLK_MUX);
320 int source;
321 int shift;
322
323 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
324 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
325 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
326 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
327 source = (val >> shift) & SUPER_SOURCE_MASK;
328 return source;
329}
330
331static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
332{
333 struct clk_tegra *c = to_clk_tegra(hw);
334 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
335 int shift;
336
337 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
338 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
339 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
340 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
341 val &= ~(SUPER_SOURCE_MASK << shift);
342 val |= index << shift;
343
344 clk_writel(val, c->reg);
345
346 return 0;
347}
348
349/* FIX ME: Need to switch parents to change the source PLL rate */
350static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
351 unsigned long prate)
352{
353 return prate;
354}
355
356static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
357 unsigned long *prate)
358{
359 return *prate;
360}
361
362static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
363 unsigned long parent_rate)
364{
365 return 0;
366}
367
368struct clk_ops tegra_super_ops = {
369 .is_enabled = tegra20_super_clk_is_enabled,
370 .enable = tegra20_super_clk_enable,
371 .disable = tegra20_super_clk_disable,
372 .set_parent = tegra20_super_clk_set_parent,
373 .get_parent = tegra20_super_clk_get_parent,
374 .set_rate = tegra20_super_clk_set_rate,
375 .round_rate = tegra20_super_clk_round_rate,
376 .recalc_rate = tegra20_super_clk_recalc_rate,
377};
378
379static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
380 unsigned long parent_rate)
381{
382 struct clk_tegra *c = to_clk_tegra(hw);
383 u64 rate = parent_rate;
384
385 if (c->mul != 0 && c->div != 0) {
386 rate *= c->mul;
387 rate += c->div - 1; /* round up */
388 do_div(rate, c->div);
389 }
390
391 return rate;
392}
393
394struct clk_ops tegra_twd_ops = {
395 .recalc_rate = tegra20_twd_clk_recalc_rate,
396};
397
398static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
399{
400 return 0;
401}
402
403struct clk_ops tegra_cop_ops = {
404 .get_parent = tegra20_cop_clk_get_parent,
405};
406
407/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
408 * reset the COP block (i.e. AVP) */
409void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
410{
411 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
412
413 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
414 clk_writel(1 << 1, reg);
415}
416
417/* bus clock functions */
418static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
419{
420 struct clk_tegra *c = to_clk_tegra(hw);
421 u32 val = clk_readl(c->reg);
422
423 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
424 return c->state;
425}
426
427static int tegra20_bus_clk_enable(struct clk_hw *hw)
428{
429 struct clk_tegra *c = to_clk_tegra(hw);
430 unsigned long flags;
431 u32 val;
432
433 spin_lock_irqsave(&clock_register_lock, flags);
434
435 val = clk_readl(c->reg);
436 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
437 clk_writel(val, c->reg);
438
439 spin_unlock_irqrestore(&clock_register_lock, flags);
440
441 return 0;
442}
443
444static void tegra20_bus_clk_disable(struct clk_hw *hw)
445{
446 struct clk_tegra *c = to_clk_tegra(hw);
447 unsigned long flags;
448 u32 val;
449
450 spin_lock_irqsave(&clock_register_lock, flags);
451
452 val = clk_readl(c->reg);
453 val |= BUS_CLK_DISABLE << c->reg_shift;
454 clk_writel(val, c->reg);
455
456 spin_unlock_irqrestore(&clock_register_lock, flags);
457}
458
459static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
460 unsigned long prate)
461{
462 struct clk_tegra *c = to_clk_tegra(hw);
463 u32 val = clk_readl(c->reg);
464 u64 rate = prate;
465
466 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
467 c->mul = 1;
468
469 if (c->mul != 0 && c->div != 0) {
470 rate *= c->mul;
471 rate += c->div - 1; /* round up */
472 do_div(rate, c->div);
473 }
474 return rate;
475}
476
477static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
478 unsigned long parent_rate)
479{
480 struct clk_tegra *c = to_clk_tegra(hw);
481 int ret = -EINVAL;
482 unsigned long flags;
483 u32 val;
484 int i;
485
486 spin_lock_irqsave(&clock_register_lock, flags);
487
488 val = clk_readl(c->reg);
489 for (i = 1; i <= 4; i++) {
490 if (rate == parent_rate / i) {
491 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
492 val |= (i - 1) << c->reg_shift;
493 clk_writel(val, c->reg);
494 c->div = i;
495 c->mul = 1;
496 ret = 0;
497 break;
498 }
499 }
500
501 spin_unlock_irqrestore(&clock_register_lock, flags);
502
503 return ret;
504}
505
506static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
507 unsigned long *prate)
508{
509 unsigned long parent_rate = *prate;
510 s64 divider;
511
512 if (rate >= parent_rate)
513 return rate;
514
515 divider = parent_rate;
516 divider += rate - 1;
517 do_div(divider, rate);
518
519 if (divider < 0)
520 return divider;
521
522 if (divider > 4)
523 divider = 4;
524 do_div(parent_rate, divider);
525
526 return parent_rate;
527}
528
529struct clk_ops tegra_bus_ops = {
530 .is_enabled = tegra20_bus_clk_is_enabled,
531 .enable = tegra20_bus_clk_enable,
532 .disable = tegra20_bus_clk_disable,
533 .set_rate = tegra20_bus_clk_set_rate,
534 .round_rate = tegra20_bus_clk_round_rate,
535 .recalc_rate = tegra20_bus_clk_recalc_rate,
536};
537
538/* Blink output functions */
539static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
540{
541 struct clk_tegra *c = to_clk_tegra(hw);
542 u32 val;
543
544 val = pmc_readl(PMC_CTRL);
545 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
546 return c->state;
547}
548
549static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
550 unsigned long prate)
551{
552 struct clk_tegra *c = to_clk_tegra(hw);
553 u64 rate = prate;
554 u32 val;
555
556 c->mul = 1;
557 val = pmc_readl(c->reg);
558
559 if (val & PMC_BLINK_TIMER_ENB) {
560 unsigned int on_off;
561
562 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
563 PMC_BLINK_TIMER_DATA_ON_MASK;
564 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
565 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
566 on_off += val;
567 /* each tick in the blink timer is 4 32KHz clocks */
568 c->div = on_off * 4;
569 } else {
570 c->div = 1;
571 }
572
573 if (c->mul != 0 && c->div != 0) {
574 rate *= c->mul;
575 rate += c->div - 1; /* round up */
576 do_div(rate, c->div);
577 }
578 return rate;
579}
580
581static int tegra20_blink_clk_enable(struct clk_hw *hw)
582{
583 u32 val;
584
585 val = pmc_readl(PMC_DPD_PADS_ORIDE);
586 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
587
588 val = pmc_readl(PMC_CTRL);
589 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
590
591 return 0;
592}
593
594static void tegra20_blink_clk_disable(struct clk_hw *hw)
595{
596 u32 val;
597
598 val = pmc_readl(PMC_CTRL);
599 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
600
601 val = pmc_readl(PMC_DPD_PADS_ORIDE);
602 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
603}
604
605static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
606 unsigned long parent_rate)
607{
608 struct clk_tegra *c = to_clk_tegra(hw);
609
610 if (rate >= parent_rate) {
611 c->div = 1;
612 pmc_writel(0, c->reg);
613 } else {
614 unsigned int on_off;
615 u32 val;
616
617 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
618 c->div = on_off * 8;
619
620 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
621 PMC_BLINK_TIMER_DATA_ON_SHIFT;
622 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
623 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
624 val |= on_off;
625 val |= PMC_BLINK_TIMER_ENB;
626 pmc_writel(val, c->reg);
627 }
628
629 return 0;
630}
631
632static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
633 unsigned long *prate)
634{
635 int div;
636 int mul;
637 long round_rate = *prate;
638
639 mul = 1;
640
641 if (rate >= *prate) {
642 div = 1;
643 } else {
644 div = DIV_ROUND_UP(*prate / 8, rate);
645 div *= 8;
646 }
647
648 round_rate *= mul;
649 round_rate += div - 1;
650 do_div(round_rate, div);
651
652 return round_rate;
653}
654
655struct clk_ops tegra_blink_clk_ops = {
656 .is_enabled = tegra20_blink_clk_is_enabled,
657 .enable = tegra20_blink_clk_enable,
658 .disable = tegra20_blink_clk_disable,
659 .set_rate = tegra20_blink_clk_set_rate,
660 .round_rate = tegra20_blink_clk_round_rate,
661 .recalc_rate = tegra20_blink_clk_recalc_rate,
662};
663
664/* PLL Functions */
665static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
666{
667 udelay(c->u.pll.lock_delay);
668 return 0;
669}
670
671static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
672{
673 struct clk_tegra *c = to_clk_tegra(hw);
674 u32 val = clk_readl(c->reg + PLL_BASE);
675
676 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
677 return c->state;
678}
679
680static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
681 unsigned long prate)
682{
683 struct clk_tegra *c = to_clk_tegra(hw);
684 u32 val = clk_readl(c->reg + PLL_BASE);
685 u64 rate = prate;
686
687 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
688 const struct clk_pll_freq_table *sel;
689 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
690 if (sel->input_rate == prate &&
691 sel->output_rate == c->u.pll.fixed_rate) {
692 c->mul = sel->n;
693 c->div = sel->m * sel->p;
694 break;
695 }
696 }
697 pr_err("Clock %s has unknown fixed frequency\n",
698 __clk_get_name(hw->clk));
699 BUG();
700 } else if (val & PLL_BASE_BYPASS) {
701 c->mul = 1;
702 c->div = 1;
703 } else {
704 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
705 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
706 if (c->flags & PLLU)
707 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
708 else
709 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
710 }
711
712 if (c->mul != 0 && c->div != 0) {
713 rate *= c->mul;
714 rate += c->div - 1; /* round up */
715 do_div(rate, c->div);
716 }
717 return rate;
718}
719
720static int tegra20_pll_clk_enable(struct clk_hw *hw)
721{
722 struct clk_tegra *c = to_clk_tegra(hw);
723 u32 val;
724 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
725
726 val = clk_readl(c->reg + PLL_BASE);
727 val &= ~PLL_BASE_BYPASS;
728 val |= PLL_BASE_ENABLE;
729 clk_writel(val, c->reg + PLL_BASE);
730
731 tegra20_pll_clk_wait_for_lock(c);
732
733 return 0;
734}
735
736static void tegra20_pll_clk_disable(struct clk_hw *hw)
737{
738 struct clk_tegra *c = to_clk_tegra(hw);
739 u32 val;
740 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
741
742 val = clk_readl(c->reg);
743 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
744 clk_writel(val, c->reg);
745}
746
747static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
748 unsigned long parent_rate)
749{
750 struct clk_tegra *c = to_clk_tegra(hw);
751 unsigned long input_rate = parent_rate;
752 const struct clk_pll_freq_table *sel;
753 u32 val;
754
755 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
756
757 if (c->flags & PLL_FIXED) {
758 int ret = 0;
759 if (rate != c->u.pll.fixed_rate) {
760 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
761 __func__, __clk_get_name(hw->clk),
762 c->u.pll.fixed_rate, rate);
763 ret = -EINVAL;
764 }
765 return ret;
766 }
767
768 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
769 if (sel->input_rate == input_rate && sel->output_rate == rate) {
770 c->mul = sel->n;
771 c->div = sel->m * sel->p;
772
773 val = clk_readl(c->reg + PLL_BASE);
774 if (c->flags & PLL_FIXED)
775 val |= PLL_BASE_OVERRIDE;
776 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
777 PLL_BASE_DIVM_MASK);
778 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
779 (sel->n << PLL_BASE_DIVN_SHIFT);
780 BUG_ON(sel->p < 1 || sel->p > 2);
781 if (c->flags & PLLU) {
782 if (sel->p == 1)
783 val |= PLLU_BASE_POST_DIV;
784 } else {
785 if (sel->p == 2)
786 val |= 1 << PLL_BASE_DIVP_SHIFT;
787 }
788 clk_writel(val, c->reg + PLL_BASE);
789
790 if (c->flags & PLL_HAS_CPCON) {
791 val = clk_readl(c->reg + PLL_MISC(c));
792 val &= ~PLL_MISC_CPCON_MASK;
793 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
794 clk_writel(val, c->reg + PLL_MISC(c));
795 }
796
797 if (c->state == ON)
798 tegra20_pll_clk_enable(hw);
799 return 0;
800 }
801 }
802 return -EINVAL;
803}
804
805static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
806 unsigned long *prate)
807{
808 struct clk_tegra *c = to_clk_tegra(hw);
809 const struct clk_pll_freq_table *sel;
810 unsigned long input_rate = *prate;
811 u64 output_rate = *prate;
812 int mul;
813 int div;
814
815 if (c->flags & PLL_FIXED)
816 return c->u.pll.fixed_rate;
817
818 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
819 if (sel->input_rate == input_rate && sel->output_rate == rate) {
820 mul = sel->n;
821 div = sel->m * sel->p;
822 break;
823 }
824
825 if (sel->input_rate == 0)
826 return -EINVAL;
827
828 output_rate *= mul;
829 output_rate += div - 1; /* round up */
830 do_div(output_rate, div);
831
832 return output_rate;
833}
834
835struct clk_ops tegra_pll_ops = {
836 .is_enabled = tegra20_pll_clk_is_enabled,
837 .enable = tegra20_pll_clk_enable,
838 .disable = tegra20_pll_clk_disable,
839 .set_rate = tegra20_pll_clk_set_rate,
840 .recalc_rate = tegra20_pll_clk_recalc_rate,
841 .round_rate = tegra20_pll_clk_round_rate,
842};
843
844static void tegra20_pllx_clk_init(struct clk_hw *hw)
845{
846 struct clk_tegra *c = to_clk_tegra(hw);
847
848 if (tegra_sku_id == 7)
849 c->max_rate = 750000000;
850}
851
852struct clk_ops tegra_pllx_ops = {
853 .init = tegra20_pllx_clk_init,
854 .is_enabled = tegra20_pll_clk_is_enabled,
855 .enable = tegra20_pll_clk_enable,
856 .disable = tegra20_pll_clk_disable,
857 .set_rate = tegra20_pll_clk_set_rate,
858 .recalc_rate = tegra20_pll_clk_recalc_rate,
859 .round_rate = tegra20_pll_clk_round_rate,
860};
861
862static int tegra20_plle_clk_enable(struct clk_hw *hw)
863{
864 struct clk_tegra *c = to_clk_tegra(hw);
865 u32 val;
866
867 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
868
869 mdelay(1);
870
871 val = clk_readl(c->reg + PLL_BASE);
872 if (!(val & PLLE_MISC_READY))
873 return -EBUSY;
874
875 val = clk_readl(c->reg + PLL_BASE);
876 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
877 clk_writel(val, c->reg + PLL_BASE);
878
879 return 0;
880}
881
882struct clk_ops tegra_plle_ops = {
883 .is_enabled = tegra20_pll_clk_is_enabled,
884 .enable = tegra20_plle_clk_enable,
885 .set_rate = tegra20_pll_clk_set_rate,
886 .recalc_rate = tegra20_pll_clk_recalc_rate,
887 .round_rate = tegra20_pll_clk_round_rate,
888};
889
890/* Clock divider ops */
891static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
892{
893 struct clk_tegra *c = to_clk_tegra(hw);
894 u32 val = clk_readl(c->reg);
895
896 val >>= c->reg_shift;
897 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
898 if (!(val & PLL_OUT_RESET_DISABLE))
899 c->state = OFF;
900 return c->state;
901}
902
903static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
904 unsigned long prate)
905{
906 struct clk_tegra *c = to_clk_tegra(hw);
907 u64 rate = prate;
908 u32 val = clk_readl(c->reg);
909 u32 divu71;
910
911 val >>= c->reg_shift;
912
913 if (c->flags & DIV_U71) {
914 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
915 c->div = (divu71 + 2);
916 c->mul = 2;
917 } else if (c->flags & DIV_2) {
918 c->div = 2;
919 c->mul = 1;
920 } else {
921 c->div = 1;
922 c->mul = 1;
923 }
924
925 rate *= c->mul;
926 rate += c->div - 1; /* round up */
927 do_div(rate, c->div);
928
929 return rate;
930}
931
932static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
933{
934 struct clk_tegra *c = to_clk_tegra(hw);
935 unsigned long flags;
936 u32 new_val;
937 u32 val;
938
939 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
940
941 if (c->flags & DIV_U71) {
942 spin_lock_irqsave(&clock_register_lock, flags);
943 val = clk_readl(c->reg);
944 new_val = val >> c->reg_shift;
945 new_val &= 0xFFFF;
946
947 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
948
949 val &= ~(0xFFFF << c->reg_shift);
950 val |= new_val << c->reg_shift;
951 clk_writel(val, c->reg);
952 spin_unlock_irqrestore(&clock_register_lock, flags);
953 return 0;
954 } else if (c->flags & DIV_2) {
955 BUG_ON(!(c->flags & PLLD));
956 spin_lock_irqsave(&clock_register_lock, flags);
957 val = clk_readl(c->reg);
958 val &= ~PLLD_MISC_DIV_RST;
959 clk_writel(val, c->reg);
960 spin_unlock_irqrestore(&clock_register_lock, flags);
961 return 0;
962 }
963 return -EINVAL;
964}
965
966static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
967{
968 struct clk_tegra *c = to_clk_tegra(hw);
969 unsigned long flags;
970 u32 new_val;
971 u32 val;
972
973 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
974
975 if (c->flags & DIV_U71) {
976 spin_lock_irqsave(&clock_register_lock, flags);
977 val = clk_readl(c->reg);
978 new_val = val >> c->reg_shift;
979 new_val &= 0xFFFF;
980
981 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
982
983 val &= ~(0xFFFF << c->reg_shift);
984 val |= new_val << c->reg_shift;
985 clk_writel(val, c->reg);
986 spin_unlock_irqrestore(&clock_register_lock, flags);
987 } else if (c->flags & DIV_2) {
988 BUG_ON(!(c->flags & PLLD));
989 spin_lock_irqsave(&clock_register_lock, flags);
990 val = clk_readl(c->reg);
991 val |= PLLD_MISC_DIV_RST;
992 clk_writel(val, c->reg);
993 spin_unlock_irqrestore(&clock_register_lock, flags);
994 }
995}
996
997static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
998 unsigned long parent_rate)
999{
1000 struct clk_tegra *c = to_clk_tegra(hw);
1001 unsigned long flags;
1002 int divider_u71;
1003 u32 new_val;
1004 u32 val;
1005
1006 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1007
1008 if (c->flags & DIV_U71) {
1009 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1010 if (divider_u71 >= 0) {
1011 spin_lock_irqsave(&clock_register_lock, flags);
1012 val = clk_readl(c->reg);
1013 new_val = val >> c->reg_shift;
1014 new_val &= 0xFFFF;
1015 if (c->flags & DIV_U71_FIXED)
1016 new_val |= PLL_OUT_OVERRIDE;
1017 new_val &= ~PLL_OUT_RATIO_MASK;
1018 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1019
1020 val &= ~(0xFFFF << c->reg_shift);
1021 val |= new_val << c->reg_shift;
1022 clk_writel(val, c->reg);
1023 c->div = divider_u71 + 2;
1024 c->mul = 2;
1025 spin_unlock_irqrestore(&clock_register_lock, flags);
1026 return 0;
1027 }
1028 } else if (c->flags & DIV_2) {
1029 if (parent_rate == rate * 2)
1030 return 0;
1031 }
1032 return -EINVAL;
1033}
1034
1035static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1036 unsigned long *prate)
1037{
1038 struct clk_tegra *c = to_clk_tegra(hw);
1039 unsigned long parent_rate = *prate;
1040 int divider;
1041
1042 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1043
1044 if (c->flags & DIV_U71) {
1045 divider = clk_div71_get_divider(parent_rate, rate);
1046 if (divider < 0)
1047 return divider;
1048 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1049 } else if (c->flags & DIV_2) {
1050 return DIV_ROUND_UP(parent_rate, 2);
1051 }
1052 return -EINVAL;
1053}
1054
1055struct clk_ops tegra_pll_div_ops = {
1056 .is_enabled = tegra20_pll_div_clk_is_enabled,
1057 .enable = tegra20_pll_div_clk_enable,
1058 .disable = tegra20_pll_div_clk_disable,
1059 .set_rate = tegra20_pll_div_clk_set_rate,
1060 .round_rate = tegra20_pll_div_clk_round_rate,
1061 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
1062};
1063
1064/* Periph clk ops */
1065
1066static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
1067{
1068 struct clk_tegra *c = to_clk_tegra(hw);
1069
1070 c->state = ON;
1071
1072 if (!c->u.periph.clk_num)
1073 goto out;
1074
1075 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1076 PERIPH_CLK_TO_ENB_BIT(c)))
1077 c->state = OFF;
1078
1079 if (!(c->flags & PERIPH_NO_RESET))
1080 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1081 PERIPH_CLK_TO_ENB_BIT(c))
1082 c->state = OFF;
1083
1084out:
1085 return c->state;
1086}
1087
1088static int tegra20_periph_clk_enable(struct clk_hw *hw)
1089{
1090 struct clk_tegra *c = to_clk_tegra(hw);
1091 unsigned long flags;
1092 u32 val;
1093
1094 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1095
1096 if (!c->u.periph.clk_num)
1097 return 0;
1098
1099 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1100 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1101 return 0;
1102
1103 spin_lock_irqsave(&clock_register_lock, flags);
1104
1105 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1106 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1107 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1108 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1109 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1110 if (c->flags & PERIPH_EMC_ENB) {
1111 /* The EMC peripheral clock has 2 extra enable bits */
1112 /* FIXME: Do they need to be disabled? */
1113 val = clk_readl(c->reg);
1114 val |= 0x3 << 24;
1115 clk_writel(val, c->reg);
1116 }
1117
1118 spin_unlock_irqrestore(&clock_register_lock, flags);
1119
1120 return 0;
1121}
1122
1123static void tegra20_periph_clk_disable(struct clk_hw *hw)
1124{
1125 struct clk_tegra *c = to_clk_tegra(hw);
1126 unsigned long flags;
1127
1128 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1129
1130 if (!c->u.periph.clk_num)
1131 return;
1132
1133 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1134
1135 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1136 return;
1137
1138 spin_lock_irqsave(&clock_register_lock, flags);
1139
1140 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1141 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1142
1143 spin_unlock_irqrestore(&clock_register_lock, flags);
1144}
1145
1146void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1147{
1148 struct clk_tegra *c = to_clk_tegra(hw);
1149 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1150
1151 pr_debug("%s %s on clock %s\n", __func__,
1152 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1153
1154 BUG_ON(!c->u.periph.clk_num);
1155
1156 if (!(c->flags & PERIPH_NO_RESET))
1157 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1158 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1159}
1160
1161static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1162{
1163 struct clk_tegra *c = to_clk_tegra(hw);
1164 u32 val;
1165 u32 mask;
1166 u32 shift;
1167
1168 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1169
1170 if (c->flags & MUX_PWM) {
1171 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1172 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1173 } else {
1174 shift = PERIPH_CLK_SOURCE_SHIFT;
1175 mask = PERIPH_CLK_SOURCE_MASK;
1176 }
1177
1178 val = clk_readl(c->reg);
1179 val &= ~mask;
1180 val |= (index) << shift;
1181
1182 clk_writel(val, c->reg);
1183
1184 return 0;
1185}
1186
1187static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1188{
1189 struct clk_tegra *c = to_clk_tegra(hw);
1190 u32 val = clk_readl(c->reg);
1191 u32 mask;
1192 u32 shift;
1193
1194 if (c->flags & MUX_PWM) {
1195 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1196 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1197 } else {
1198 shift = PERIPH_CLK_SOURCE_SHIFT;
1199 mask = PERIPH_CLK_SOURCE_MASK;
1200 }
1201
1202 if (c->flags & MUX)
1203 return (val & mask) >> shift;
1204 else
1205 return 0;
1206}
1207
1208static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1209 unsigned long prate)
1210{
1211 struct clk_tegra *c = to_clk_tegra(hw);
1212 unsigned long rate = prate;
1213 u32 val = clk_readl(c->reg);
1214
1215 if (c->flags & DIV_U71) {
1216 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1217 c->div = divu71 + 2;
1218 c->mul = 2;
1219 } else if (c->flags & DIV_U16) {
1220 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1221 c->div = divu16 + 1;
1222 c->mul = 1;
1223 } else {
1224 c->div = 1;
1225 c->mul = 1;
1226 return rate;
1227 }
1228
1229 if (c->mul != 0 && c->div != 0) {
1230 rate *= c->mul;
1231 rate += c->div - 1; /* round up */
1232 do_div(rate, c->div);
1233 }
1234
1235 return rate;
1236}
1237
1238static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1239 unsigned long parent_rate)
1240{
1241 struct clk_tegra *c = to_clk_tegra(hw);
1242 u32 val;
1243 int divider;
1244
1245 val = clk_readl(c->reg);
1246
1247 if (c->flags & DIV_U71) {
1248 divider = clk_div71_get_divider(parent_rate, rate);
1249
1250 if (divider >= 0) {
1251 val = clk_readl(c->reg);
1252 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1253 val |= divider;
1254 clk_writel(val, c->reg);
1255 c->div = divider + 2;
1256 c->mul = 2;
1257 return 0;
1258 }
1259 } else if (c->flags & DIV_U16) {
1260 divider = clk_div16_get_divider(parent_rate, rate);
1261 if (divider >= 0) {
1262 val = clk_readl(c->reg);
1263 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1264 val |= divider;
1265 clk_writel(val, c->reg);
1266 c->div = divider + 1;
1267 c->mul = 1;
1268 return 0;
1269 }
1270 } else if (parent_rate <= rate) {
1271 c->div = 1;
1272 c->mul = 1;
1273 return 0;
1274 }
1275
1276 return -EINVAL;
1277}
1278
1279static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1280 unsigned long rate, unsigned long *prate)
1281{
1282 struct clk_tegra *c = to_clk_tegra(hw);
1283 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1284 int divider;
1285
1286 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1287
1288 if (prate)
1289 parent_rate = *prate;
1290
1291 if (c->flags & DIV_U71) {
1292 divider = clk_div71_get_divider(parent_rate, rate);
1293 if (divider < 0)
1294 return divider;
1295
1296 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1297 } else if (c->flags & DIV_U16) {
1298 divider = clk_div16_get_divider(parent_rate, rate);
1299 if (divider < 0)
1300 return divider;
1301 return DIV_ROUND_UP(parent_rate, divider + 1);
1302 }
1303 return -EINVAL;
1304}
1305
1306struct clk_ops tegra_periph_clk_ops = {
1307 .is_enabled = tegra20_periph_clk_is_enabled,
1308 .enable = tegra20_periph_clk_enable,
1309 .disable = tegra20_periph_clk_disable,
1310 .set_parent = tegra20_periph_clk_set_parent,
1311 .get_parent = tegra20_periph_clk_get_parent,
1312 .set_rate = tegra20_periph_clk_set_rate,
1313 .round_rate = tegra20_periph_clk_round_rate,
1314 .recalc_rate = tegra20_periph_clk_recalc_rate,
1315};
1316
1317/* External memory controller clock ops */
1318static void tegra20_emc_clk_init(struct clk_hw *hw)
1319{
1320 struct clk_tegra *c = to_clk_tegra(hw);
1321 c->max_rate = __clk_get_rate(hw->clk);
1322}
1323
1324static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1325 unsigned long *prate)
1326{
1327 struct clk_tegra *c = to_clk_tegra(hw);
1328 long emc_rate;
1329 long clk_rate;
1330
1331 /*
1332 * The slowest entry in the EMC clock table that is at least as
1333 * fast as rate.
1334 */
1335 emc_rate = tegra_emc_round_rate(rate);
1336 if (emc_rate < 0)
1337 return c->max_rate;
1338
1339 /*
1340 * The fastest rate the PLL will generate that is at most the
1341 * requested rate.
1342 */
1343 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1344
1345 /*
1346 * If this fails, and emc_rate > clk_rate, it's because the maximum
1347 * rate in the EMC tables is larger than the maximum rate of the EMC
1348 * clock. The EMC clock's max rate is the rate it was running when the
1349 * kernel booted. Such a mismatch is probably due to using the wrong
1350 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1351 */
1352 WARN_ONCE(emc_rate != clk_rate,
1353 "emc_rate %ld != clk_rate %ld",
1354 emc_rate, clk_rate);
1355
1356 return emc_rate;
1357}
1358
1359static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1360 unsigned long parent_rate)
1361{
1362 int ret;
1363
1364 /*
1365 * The Tegra2 memory controller has an interlock with the clock
1366 * block that allows memory shadowed registers to be updated,
1367 * and then transfer them to the main registers at the same
1368 * time as the clock update without glitches.
1369 */
1370 ret = tegra_emc_set_rate(rate);
1371 if (ret < 0)
1372 return ret;
1373
1374 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1375 udelay(1);
1376
1377 return ret;
1378}
1379
1380struct clk_ops tegra_emc_clk_ops = {
1381 .init = tegra20_emc_clk_init,
1382 .is_enabled = tegra20_periph_clk_is_enabled,
1383 .enable = tegra20_periph_clk_enable,
1384 .disable = tegra20_periph_clk_disable,
1385 .set_parent = tegra20_periph_clk_set_parent,
1386 .get_parent = tegra20_periph_clk_get_parent,
1387 .set_rate = tegra20_emc_clk_set_rate,
1388 .round_rate = tegra20_emc_clk_round_rate,
1389 .recalc_rate = tegra20_periph_clk_recalc_rate,
1390};
1391
1392/* Clock doubler ops */
1393static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1394{
1395 struct clk_tegra *c = to_clk_tegra(hw);
1396
1397 c->state = ON;
1398
1399 if (!c->u.periph.clk_num)
1400 goto out;
1401
1402 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1403 PERIPH_CLK_TO_ENB_BIT(c)))
1404 c->state = OFF;
1405
1406out:
1407 return c->state;
1408};
1409
1410static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1411 unsigned long prate)
1412{
1413 struct clk_tegra *c = to_clk_tegra(hw);
1414 u64 rate = prate;
1415
1416 c->mul = 2;
1417 c->div = 1;
1418
1419 rate *= c->mul;
1420 rate += c->div - 1; /* round up */
1421 do_div(rate, c->div);
1422
1423 return rate;
1424}
1425
1426static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1427 unsigned long *prate)
1428{
1429 unsigned long output_rate = *prate;
1430
1431 do_div(output_rate, 2);
1432 return output_rate;
1433}
1434
1435static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1436 unsigned long parent_rate)
1437{
1438 if (rate != 2 * parent_rate)
1439 return -EINVAL;
1440 return 0;
1441}
1442
1443struct clk_ops tegra_clk_double_ops = {
1444 .is_enabled = tegra20_clk_double_is_enabled,
1445 .enable = tegra20_periph_clk_enable,
1446 .disable = tegra20_periph_clk_disable,
1447 .set_rate = tegra20_clk_double_set_rate,
1448 .recalc_rate = tegra20_clk_double_recalc_rate,
1449 .round_rate = tegra20_clk_double_round_rate,
1450};
1451
1452/* Audio sync clock ops */
1453static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1454{
1455 struct clk_tegra *c = to_clk_tegra(hw);
1456 u32 val = clk_readl(c->reg);
1457
1458 c->state = (val & (1<<4)) ? OFF : ON;
1459 return c->state;
1460}
1461
1462static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1463{
1464 struct clk_tegra *c = to_clk_tegra(hw);
1465
1466 clk_writel(0, c->reg);
1467 return 0;
1468}
1469
1470static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1471{
1472 struct clk_tegra *c = to_clk_tegra(hw);
1473 clk_writel(1, c->reg);
1474}
1475
1476static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1477{
1478 struct clk_tegra *c = to_clk_tegra(hw);
1479 u32 val = clk_readl(c->reg);
1480 int source;
1481
1482 source = val & 0xf;
1483 return source;
1484}
1485
1486static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1487{
1488 struct clk_tegra *c = to_clk_tegra(hw);
1489 u32 val;
1490
1491 val = clk_readl(c->reg);
1492 val &= ~0xf;
1493 val |= index;
1494
1495 clk_writel(val, c->reg);
1496
1497 return 0;
1498}
1499
1500struct clk_ops tegra_audio_sync_clk_ops = {
1501 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1502 .enable = tegra20_audio_sync_clk_enable,
1503 .disable = tegra20_audio_sync_clk_disable,
1504 .set_parent = tegra20_audio_sync_clk_set_parent,
1505 .get_parent = tegra20_audio_sync_clk_get_parent,
1506};
1507
1508/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1509
1510static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1511{
1512 struct clk_tegra *c = to_clk_tegra(hw);
1513 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1514 * currently done in the pinmux code. */
1515 c->state = ON;
1516
1517 BUG_ON(!c->u.periph.clk_num);
1518
1519 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1520 PERIPH_CLK_TO_ENB_BIT(c)))
1521 c->state = OFF;
1522 return c->state;
1523}
1524
1525static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1526{
1527 struct clk_tegra *c = to_clk_tegra(hw);
1528 BUG_ON(!c->u.periph.clk_num);
1529
1530 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1531 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1532 return 0;
1533}
1534
1535static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1536{
1537 struct clk_tegra *c = to_clk_tegra(hw);
1538 BUG_ON(!c->u.periph.clk_num);
1539
1540 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1541 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1542}
1543
1544static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1545 unsigned long prate)
1546{
1547 return to_clk_tegra(hw)->fixed_rate;
1548}
1549
1550struct clk_ops tegra_cdev_clk_ops = {
1551 .is_enabled = tegra20_cdev_clk_is_enabled,
1552 .enable = tegra20_cdev_clk_enable,
1553 .disable = tegra20_cdev_clk_disable,
1554 .recalc_rate = tegra20_cdev_recalc_rate,
1555};
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..8bfd31bcc490
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H
19
20extern struct clk_ops tegra_clk_32k_ops;
21extern struct clk_ops tegra_pll_ops;
22extern struct clk_ops tegra_clk_m_ops;
23extern struct clk_ops tegra_pll_div_ops;
24extern struct clk_ops tegra_pllx_ops;
25extern struct clk_ops tegra_plle_ops;
26extern struct clk_ops tegra_clk_double_ops;
27extern struct clk_ops tegra_cdev_clk_ops;
28extern struct clk_ops tegra_audio_sync_clk_ops;
29extern struct clk_ops tegra_super_ops;
30extern struct clk_ops tegra_cpu_ops;
31extern struct clk_ops tegra_twd_ops;
32extern struct clk_ops tegra_cop_ops;
33extern struct clk_ops tegra_bus_ops;
34extern struct clk_ops tegra_blink_clk_ops;
35extern struct clk_ops tegra_emc_clk_ops;
36extern struct clk_ops tegra_periph_clk_ops;
37extern struct clk_ops tegra_clk_shared_bus_ops;
38
39void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
40void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
41
42#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..1a35c003fba8
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1142 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29
30#include <mach/iomap.h>
31#include <mach/suspend.h>
32
33#include "clock.h"
34#include "fuse.h"
35#include "tegra2_emc.h"
36#include "tegra20_clocks.h"
37
38/* Clock definitions */
39
40#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
41 _parent_names, _parents, _parent) \
42 static struct clk tegra_##_name = { \
43 .hw = &tegra_##_name##_hw.hw, \
44 .name = #_name, \
45 .rate = _rate, \
46 .ops = _ops, \
47 .flags = _flags, \
48 .parent_names = _parent_names, \
49 .parents = _parents, \
50 .num_parents = ARRAY_SIZE(_parent_names), \
51 .parent = _parent, \
52 };
53
54static struct clk tegra_clk_32k;
55static struct clk_tegra tegra_clk_32k_hw = {
56 .hw = {
57 .clk = &tegra_clk_32k,
58 },
59 .fixed_rate = 32768,
60};
61
62static struct clk tegra_clk_32k = {
63 .name = "clk_32k",
64 .rate = 32768,
65 .ops = &tegra_clk_32k_ops,
66 .hw = &tegra_clk_32k_hw.hw,
67 .flags = CLK_IS_ROOT,
68};
69
70static struct clk tegra_clk_m;
71static struct clk_tegra tegra_clk_m_hw = {
72 .hw = {
73 .clk = &tegra_clk_m,
74 },
75 .flags = ENABLE_ON_INIT,
76 .reg = 0x1fc,
77 .reg_shift = 28,
78 .max_rate = 26000000,
79 .fixed_rate = 0,
80};
81
82static struct clk tegra_clk_m = {
83 .name = "clk_m",
84 .ops = &tegra_clk_m_ops,
85 .hw = &tegra_clk_m_hw.hw,
86 .flags = CLK_IS_ROOT,
87};
88
89#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
90 _input_max, _cf_min, _cf_max, _vco_min, \
91 _vco_max, _freq_table, _lock_delay, _ops, \
92 _fixed_rate, _parent) \
93 static const char *tegra_##_name##_parent_names[] = { \
94 #_parent, \
95 }; \
96 static struct clk *tegra_##_name##_parents[] = { \
97 &tegra_##_parent, \
98 }; \
99 static struct clk tegra_##_name; \
100 static struct clk_tegra tegra_##_name##_hw = { \
101 .hw = { \
102 .clk = &tegra_##_name, \
103 }, \
104 .flags = _flags, \
105 .reg = _reg, \
106 .max_rate = _max_rate, \
107 .u.pll = { \
108 .input_min = _input_min, \
109 .input_max = _input_max, \
110 .cf_min = _cf_min, \
111 .cf_max = _cf_max, \
112 .vco_min = _vco_min, \
113 .vco_max = _vco_max, \
114 .freq_table = _freq_table, \
115 .lock_delay = _lock_delay, \
116 .fixed_rate = _fixed_rate, \
117 }, \
118 }; \
119 static struct clk tegra_##_name = { \
120 .name = #_name, \
121 .ops = &_ops, \
122 .hw = &tegra_##_name##_hw.hw, \
123 .parent = &tegra_##_parent, \
124 .parent_names = tegra_##_name##_parent_names, \
125 .parents = tegra_##_name##_parents, \
126 .num_parents = 1, \
127 };
128
129#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
130 _max_rate, _ops, _parent, _clk_flags) \
131 static const char *tegra_##_name##_parent_names[] = { \
132 #_parent, \
133 }; \
134 static struct clk *tegra_##_name##_parents[] = { \
135 &tegra_##_parent, \
136 }; \
137 static struct clk tegra_##_name; \
138 static struct clk_tegra tegra_##_name##_hw = { \
139 .hw = { \
140 .clk = &tegra_##_name, \
141 }, \
142 .flags = _flags, \
143 .reg = _reg, \
144 .max_rate = _max_rate, \
145 .reg_shift = _reg_shift, \
146 }; \
147 static struct clk tegra_##_name = { \
148 .name = #_name, \
149 .ops = &tegra_pll_div_ops, \
150 .hw = &tegra_##_name##_hw.hw, \
151 .parent = &tegra_##_parent, \
152 .parent_names = tegra_##_name##_parent_names, \
153 .parents = tegra_##_name##_parents, \
154 .num_parents = 1, \
155 .flags = _clk_flags, \
156 };
157
158
159static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
160 {32768, 12000000, 366, 1, 1, 0},
161 {32768, 13000000, 397, 1, 1, 0},
162 {32768, 19200000, 586, 1, 1, 0},
163 {32768, 26000000, 793, 1, 1, 0},
164 {0, 0, 0, 0, 0, 0},
165};
166
167DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
168 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
169 tegra_pll_ops, 0, clk_32k);
170
171static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
172 { 12000000, 600000000, 600, 12, 1, 8 },
173 { 13000000, 600000000, 600, 13, 1, 8 },
174 { 19200000, 600000000, 500, 16, 1, 6 },
175 { 26000000, 600000000, 600, 26, 1, 8 },
176 { 0, 0, 0, 0, 0, 0 },
177};
178
179DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
180 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
181 tegra_pll_ops, 0, clk_m);
182
183DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
184 tegra_pll_div_ops, pll_c, 0);
185
186static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
187 { 12000000, 666000000, 666, 12, 1, 8},
188 { 13000000, 666000000, 666, 13, 1, 8},
189 { 19200000, 666000000, 555, 16, 1, 8},
190 { 26000000, 666000000, 666, 26, 1, 8},
191 { 12000000, 600000000, 600, 12, 1, 8},
192 { 13000000, 600000000, 600, 13, 1, 8},
193 { 19200000, 600000000, 375, 12, 1, 6},
194 { 26000000, 600000000, 600, 26, 1, 8},
195 { 0, 0, 0, 0, 0, 0 },
196};
197
198DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
199 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
200 tegra_pll_ops, 0, clk_m);
201
202DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
203 tegra_pll_div_ops, pll_m, 0);
204
205static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
206 { 12000000, 216000000, 432, 12, 2, 8},
207 { 13000000, 216000000, 432, 13, 2, 8},
208 { 19200000, 216000000, 90, 4, 2, 1},
209 { 26000000, 216000000, 432, 26, 2, 8},
210 { 12000000, 432000000, 432, 12, 1, 8},
211 { 13000000, 432000000, 432, 13, 1, 8},
212 { 19200000, 432000000, 90, 4, 1, 1},
213 { 26000000, 432000000, 432, 26, 1, 8},
214 { 0, 0, 0, 0, 0, 0 },
215};
216
217
218DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
219 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
220 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
221
222DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
223 432000000, tegra_pll_div_ops, pll_p, 0);
224DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
225 432000000, tegra_pll_div_ops, pll_p, 0);
226DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
227 432000000, tegra_pll_div_ops, pll_p, 0);
228DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
229 432000000, tegra_pll_div_ops, pll_p, 0);
230
231static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
232 { 28800000, 56448000, 49, 25, 1, 1},
233 { 28800000, 73728000, 64, 25, 1, 1},
234 { 28800000, 24000000, 5, 6, 1, 1},
235 { 0, 0, 0, 0, 0, 0 },
236};
237
238DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
239 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
240 tegra_pll_ops, 0, pll_p_out1);
241
242DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
243 tegra_pll_div_ops, pll_a, 0);
244
245static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
246 { 12000000, 216000000, 216, 12, 1, 4},
247 { 13000000, 216000000, 216, 13, 1, 4},
248 { 19200000, 216000000, 135, 12, 1, 3},
249 { 26000000, 216000000, 216, 26, 1, 4},
250
251 { 12000000, 594000000, 594, 12, 1, 8},
252 { 13000000, 594000000, 594, 13, 1, 8},
253 { 19200000, 594000000, 495, 16, 1, 8},
254 { 26000000, 594000000, 594, 26, 1, 8},
255
256 { 12000000, 1000000000, 1000, 12, 1, 12},
257 { 13000000, 1000000000, 1000, 13, 1, 12},
258 { 19200000, 1000000000, 625, 12, 1, 8},
259 { 26000000, 1000000000, 1000, 26, 1, 12},
260
261 { 0, 0, 0, 0, 0, 0 },
262};
263
264DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
265 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
266 1000, tegra_pll_ops, 0, clk_m);
267
268DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
269 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
270
271static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
272 { 12000000, 480000000, 960, 12, 2, 0},
273 { 13000000, 480000000, 960, 13, 2, 0},
274 { 19200000, 480000000, 200, 4, 2, 0},
275 { 26000000, 480000000, 960, 26, 2, 0},
276 { 0, 0, 0, 0, 0, 0 },
277};
278
279DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
280 48000000, 960000000, tegra_pll_u_freq_table, 1000,
281 tegra_pll_ops, 0, clk_m);
282
283static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
284 /* 1 GHz */
285 { 12000000, 1000000000, 1000, 12, 1, 12},
286 { 13000000, 1000000000, 1000, 13, 1, 12},
287 { 19200000, 1000000000, 625, 12, 1, 8},
288 { 26000000, 1000000000, 1000, 26, 1, 12},
289
290 /* 912 MHz */
291 { 12000000, 912000000, 912, 12, 1, 12},
292 { 13000000, 912000000, 912, 13, 1, 12},
293 { 19200000, 912000000, 760, 16, 1, 8},
294 { 26000000, 912000000, 912, 26, 1, 12},
295
296 /* 816 MHz */
297 { 12000000, 816000000, 816, 12, 1, 12},
298 { 13000000, 816000000, 816, 13, 1, 12},
299 { 19200000, 816000000, 680, 16, 1, 8},
300 { 26000000, 816000000, 816, 26, 1, 12},
301
302 /* 760 MHz */
303 { 12000000, 760000000, 760, 12, 1, 12},
304 { 13000000, 760000000, 760, 13, 1, 12},
305 { 19200000, 760000000, 950, 24, 1, 8},
306 { 26000000, 760000000, 760, 26, 1, 12},
307
308 /* 750 MHz */
309 { 12000000, 750000000, 750, 12, 1, 12},
310 { 13000000, 750000000, 750, 13, 1, 12},
311 { 19200000, 750000000, 625, 16, 1, 8},
312 { 26000000, 750000000, 750, 26, 1, 12},
313
314 /* 608 MHz */
315 { 12000000, 608000000, 608, 12, 1, 12},
316 { 13000000, 608000000, 608, 13, 1, 12},
317 { 19200000, 608000000, 380, 12, 1, 8},
318 { 26000000, 608000000, 608, 26, 1, 12},
319
320 /* 456 MHz */
321 { 12000000, 456000000, 456, 12, 1, 12},
322 { 13000000, 456000000, 456, 13, 1, 12},
323 { 19200000, 456000000, 380, 16, 1, 8},
324 { 26000000, 456000000, 456, 26, 1, 12},
325
326 /* 312 MHz */
327 { 12000000, 312000000, 312, 12, 1, 12},
328 { 13000000, 312000000, 312, 13, 1, 12},
329 { 19200000, 312000000, 260, 16, 1, 8},
330 { 26000000, 312000000, 312, 26, 1, 12},
331
332 { 0, 0, 0, 0, 0, 0 },
333};
334
335DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
336 31000000, 1000000, 6000000, 20000000, 1200000000,
337 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
338
339static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
340 { 12000000, 100000000, 200, 24, 1, 0 },
341 { 0, 0, 0, 0, 0, 0 },
342};
343
344DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
345 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
346
347static const char *tegra_common_parent_names[] = {
348 "clk_m",
349};
350
351static struct clk *tegra_common_parents[] = {
352 &tegra_clk_m,
353};
354
355static struct clk tegra_clk_d;
356static struct clk_tegra tegra_clk_d_hw = {
357 .hw = {
358 .clk = &tegra_clk_d,
359 },
360 .flags = PERIPH_NO_RESET,
361 .reg = 0x34,
362 .reg_shift = 12,
363 .max_rate = 52000000,
364 .u.periph = {
365 .clk_num = 90,
366 },
367};
368
369static struct clk tegra_clk_d = {
370 .name = "clk_d",
371 .hw = &tegra_clk_d_hw.hw,
372 .ops = &tegra_clk_double_ops,
373 .parent = &tegra_clk_m,
374 .parent_names = tegra_common_parent_names,
375 .parents = tegra_common_parents,
376 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
377};
378
379static struct clk tegra_cdev1;
380static struct clk_tegra tegra_cdev1_hw = {
381 .hw = {
382 .clk = &tegra_cdev1,
383 },
384 .fixed_rate = 26000000,
385 .u.periph = {
386 .clk_num = 94,
387 },
388};
389static struct clk tegra_cdev1 = {
390 .name = "cdev1",
391 .hw = &tegra_cdev1_hw.hw,
392 .ops = &tegra_cdev_clk_ops,
393 .flags = CLK_IS_ROOT,
394};
395
396/* dap_mclk2, belongs to the cdev2 pingroup. */
397static struct clk tegra_cdev2;
398static struct clk_tegra tegra_cdev2_hw = {
399 .hw = {
400 .clk = &tegra_cdev2,
401 },
402 .fixed_rate = 26000000,
403 .u.periph = {
404 .clk_num = 93,
405 },
406};
407static struct clk tegra_cdev2 = {
408 .name = "cdev2",
409 .hw = &tegra_cdev2_hw.hw,
410 .ops = &tegra_cdev_clk_ops,
411 .flags = CLK_IS_ROOT,
412};
413
414/* initialized before peripheral clocks */
415static struct clk_mux_sel mux_audio_sync_clk[8+1];
416static const struct audio_sources {
417 const char *name;
418 int value;
419} mux_audio_sync_clk_sources[] = {
420 { .name = "spdif_in", .value = 0 },
421 { .name = "i2s1", .value = 1 },
422 { .name = "i2s2", .value = 2 },
423 { .name = "pll_a_out0", .value = 4 },
424#if 0 /* FIXME: not implemented */
425 { .name = "ac97", .value = 3 },
426 { .name = "ext_audio_clk2", .value = 5 },
427 { .name = "ext_audio_clk1", .value = 6 },
428 { .name = "ext_vimclk", .value = 7 },
429#endif
430 { NULL, 0 }
431};
432
433static const char *audio_parent_names[] = {
434 "spdif_in",
435 "i2s1",
436 "i2s2",
437 "dummy",
438 "pll_a_out0",
439 "dummy",
440 "dummy",
441 "dummy",
442};
443
444static struct clk *audio_parents[] = {
445 NULL,
446 NULL,
447 NULL,
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453};
454
455static struct clk tegra_audio;
456static struct clk_tegra tegra_audio_hw = {
457 .hw = {
458 .clk = &tegra_audio,
459 },
460 .reg = 0x38,
461 .max_rate = 73728000,
462};
463DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
464 audio_parents, NULL);
465
466static const char *audio_2x_parent_names[] = {
467 "audio",
468};
469
470static struct clk *audio_2x_parents[] = {
471 &tegra_audio,
472};
473
474static struct clk tegra_audio_2x;
475static struct clk_tegra tegra_audio_2x_hw = {
476 .hw = {
477 .clk = &tegra_audio_2x,
478 },
479 .flags = PERIPH_NO_RESET,
480 .max_rate = 48000000,
481 .reg = 0x34,
482 .reg_shift = 8,
483 .u.periph = {
484 .clk_num = 89,
485 },
486};
487DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
488 audio_2x_parents, &tegra_audio);
489
490static struct clk_lookup tegra_audio_clk_lookups[] = {
491 { .con_id = "audio", .clk = &tegra_audio },
492 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
493};
494
495/* This is called after peripheral clocks are initialized, as the
496 * audio_sync clock depends on some of the peripheral clocks.
497 */
498
499static void init_audio_sync_clock_mux(void)
500{
501 int i;
502 struct clk_mux_sel *sel = mux_audio_sync_clk;
503 const struct audio_sources *src = mux_audio_sync_clk_sources;
504 struct clk_lookup *lookup;
505
506 for (i = 0; src->name; i++, sel++, src++) {
507 sel->input = tegra_get_clock_by_name(src->name);
508 if (!sel->input)
509 pr_err("%s: could not find clk %s\n", __func__,
510 src->name);
511 audio_parents[src->value] = sel->input;
512 sel->value = src->value;
513 }
514
515 lookup = tegra_audio_clk_lookups;
516 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
517 struct clk *c = lookup->clk;
518 struct clk_tegra *clk = to_clk_tegra(c->hw);
519 __clk_init(NULL, c);
520 INIT_LIST_HEAD(&clk->shared_bus_list);
521 clk->lookup.con_id = lookup->con_id;
522 clk->lookup.clk = c;
523 clkdev_add(&clk->lookup);
524 tegra_clk_add(c);
525 }
526}
527
528static const char *mux_cclk[] = {
529 "clk_m",
530 "pll_c",
531 "clk_32k",
532 "pll_m",
533 "pll_p",
534 "pll_p_out4",
535 "pll_p_out3",
536 "clk_d",
537 "pll_x",
538};
539
540
541static struct clk *mux_cclk_p[] = {
542 &tegra_clk_m,
543 &tegra_pll_c,
544 &tegra_clk_32k,
545 &tegra_pll_m,
546 &tegra_pll_p,
547 &tegra_pll_p_out4,
548 &tegra_pll_p_out3,
549 &tegra_clk_d,
550 &tegra_pll_x,
551};
552
553static const char *mux_sclk[] = {
554 "clk_m",
555 "pll_c_out1",
556 "pll_p_out4",
557 "pllp_p_out3",
558 "pll_p_out2",
559 "clk_d",
560 "clk_32k",
561 "pll_m_out1",
562};
563
564static struct clk *mux_sclk_p[] = {
565 &tegra_clk_m,
566 &tegra_pll_c_out1,
567 &tegra_pll_p_out4,
568 &tegra_pll_p_out3,
569 &tegra_pll_p_out2,
570 &tegra_clk_d,
571 &tegra_clk_32k,
572 &tegra_pll_m_out1,
573};
574
575static struct clk tegra_cclk;
576static struct clk_tegra tegra_cclk_hw = {
577 .hw = {
578 .clk = &tegra_cclk,
579 },
580 .reg = 0x20,
581 .max_rate = 1000000000,
582};
583DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
584 mux_cclk_p, NULL);
585
586static const char *mux_twd[] = {
587 "cclk",
588};
589
590static struct clk *mux_twd_p[] = {
591 &tegra_cclk,
592};
593
594static struct clk tegra_clk_twd;
595static struct clk_tegra tegra_clk_twd_hw = {
596 .hw = {
597 .clk = &tegra_clk_twd,
598 },
599 .max_rate = 1000000000,
600 .mul = 1,
601 .div = 4,
602};
603
604static struct clk tegra_clk_twd = {
605 .name = "twd",
606 .ops = &tegra_twd_ops,
607 .hw = &tegra_clk_twd_hw.hw,
608 .parent = &tegra_cclk,
609 .parent_names = mux_twd,
610 .parents = mux_twd_p,
611 .num_parents = ARRAY_SIZE(mux_twd),
612};
613
614static struct clk tegra_sclk;
615static struct clk_tegra tegra_sclk_hw = {
616 .hw = {
617 .clk = &tegra_sclk,
618 },
619 .reg = 0x28,
620 .max_rate = 240000000,
621 .min_rate = 120000000,
622};
623DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
624 mux_sclk_p, NULL);
625
626static const char *tegra_cop_parent_names[] = {
627 "tegra_sclk",
628};
629
630static struct clk *tegra_cop_parents[] = {
631 &tegra_sclk,
632};
633
634static struct clk tegra_cop;
635static struct clk_tegra tegra_cop_hw = {
636 .hw = {
637 .clk = &tegra_cop,
638 },
639 .max_rate = 240000000,
640 .reset = &tegra2_cop_clk_reset,
641};
642DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
643 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
644
645static const char *tegra_hclk_parent_names[] = {
646 "tegra_sclk",
647};
648
649static struct clk *tegra_hclk_parents[] = {
650 &tegra_sclk,
651};
652
653static struct clk tegra_hclk;
654static struct clk_tegra tegra_hclk_hw = {
655 .hw = {
656 .clk = &tegra_hclk,
657 },
658 .flags = DIV_BUS,
659 .reg = 0x30,
660 .reg_shift = 4,
661 .max_rate = 240000000,
662};
663DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
664 tegra_hclk_parents, &tegra_sclk);
665
666static const char *tegra_pclk_parent_names[] = {
667 "tegra_hclk",
668};
669
670static struct clk *tegra_pclk_parents[] = {
671 &tegra_hclk,
672};
673
674static struct clk tegra_pclk;
675static struct clk_tegra tegra_pclk_hw = {
676 .hw = {
677 .clk = &tegra_pclk,
678 },
679 .flags = DIV_BUS,
680 .reg = 0x30,
681 .reg_shift = 0,
682 .max_rate = 120000000,
683};
684DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
685 tegra_pclk_parents, &tegra_hclk);
686
687static const char *tegra_blink_parent_names[] = {
688 "clk_32k",
689};
690
691static struct clk *tegra_blink_parents[] = {
692 &tegra_clk_32k,
693};
694
695static struct clk tegra_blink;
696static struct clk_tegra tegra_blink_hw = {
697 .hw = {
698 .clk = &tegra_blink,
699 },
700 .reg = 0x40,
701 .max_rate = 32768,
702};
703DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
704 tegra_blink_parents, &tegra_clk_32k);
705
706static const char *mux_pllm_pllc_pllp_plla[] = {
707 "pll_m",
708 "pll_c",
709 "pll_p",
710 "pll_a_out0",
711};
712
713static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
714 &tegra_pll_m,
715 &tegra_pll_c,
716 &tegra_pll_p,
717 &tegra_pll_a_out0,
718};
719
720static const char *mux_pllm_pllc_pllp_clkm[] = {
721 "pll_m",
722 "pll_c",
723 "pll_p",
724 "clk_m",
725};
726
727static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
728 &tegra_pll_m,
729 &tegra_pll_c,
730 &tegra_pll_p,
731 &tegra_clk_m,
732};
733
734static const char *mux_pllp_pllc_pllm_clkm[] = {
735 "pll_p",
736 "pll_c",
737 "pll_m",
738 "clk_m",
739};
740
741static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
742 &tegra_pll_p,
743 &tegra_pll_c,
744 &tegra_pll_m,
745 &tegra_clk_m,
746};
747
748static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
749 "pll_a_out0",
750 "audio_2x",
751 "pll_p",
752 "clk_m",
753};
754
755static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
756 &tegra_pll_a_out0,
757 &tegra_audio_2x,
758 &tegra_pll_p,
759 &tegra_clk_m,
760};
761
762static const char *mux_pllp_plld_pllc_clkm[] = {
763 "pllp",
764 "pll_d_out0",
765 "pll_c",
766 "clk_m",
767};
768
769static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
770 &tegra_pll_p,
771 &tegra_pll_d_out0,
772 &tegra_pll_c,
773 &tegra_clk_m,
774};
775
776static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
777 "pll_p",
778 "pll_c",
779 "audio",
780 "clk_m",
781 "clk_32k",
782};
783
784static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
785 &tegra_pll_p,
786 &tegra_pll_c,
787 &tegra_audio,
788 &tegra_clk_m,
789 &tegra_clk_32k,
790};
791
792static const char *mux_pllp_pllc_pllm[] = {
793 "pll_p",
794 "pll_c",
795 "pll_m"
796};
797
798static struct clk *mux_pllp_pllc_pllm_p[] = {
799 &tegra_pll_p,
800 &tegra_pll_c,
801 &tegra_pll_m,
802};
803
804static const char *mux_clk_m[] = {
805 "clk_m",
806};
807
808static struct clk *mux_clk_m_p[] = {
809 &tegra_clk_m,
810};
811
812static const char *mux_pllp_out3[] = {
813 "pll_p_out3",
814};
815
816static struct clk *mux_pllp_out3_p[] = {
817 &tegra_pll_p_out3,
818};
819
820static const char *mux_plld[] = {
821 "pll_d",
822};
823
824static struct clk *mux_plld_p[] = {
825 &tegra_pll_d,
826};
827
828static const char *mux_clk_32k[] = {
829 "clk_32k",
830};
831
832static struct clk *mux_clk_32k_p[] = {
833 &tegra_clk_32k,
834};
835
836static const char *mux_pclk[] = {
837 "pclk",
838};
839
840static struct clk *mux_pclk_p[] = {
841 &tegra_pclk,
842};
843
844static struct clk tegra_emc;
845static struct clk_tegra tegra_emc_hw = {
846 .hw = {
847 .clk = &tegra_emc,
848 },
849 .reg = 0x19c,
850 .max_rate = 800000000,
851 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
852 .reset = &tegra2_periph_clk_reset,
853 .u.periph = {
854 .clk_num = 57,
855 },
856};
857DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
858 mux_pllm_pllc_pllp_clkm_p, NULL);
859
860#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
861 _max, _inputs, _flags) \
862 static struct clk tegra_##_name; \
863 static struct clk_tegra tegra_##_name##_hw = { \
864 .hw = { \
865 .clk = &tegra_##_name, \
866 }, \
867 .lookup = { \
868 .dev_id = _dev, \
869 .con_id = _con, \
870 }, \
871 .reg = _reg, \
872 .flags = _flags, \
873 .max_rate = _max, \
874 .u.periph = { \
875 .clk_num = _clk_num, \
876 }, \
877 .reset = tegra2_periph_clk_reset, \
878 }; \
879 static struct clk tegra_##_name = { \
880 .name = #_name, \
881 .ops = &tegra_periph_clk_ops, \
882 .hw = &tegra_##_name##_hw.hw, \
883 .parent_names = _inputs, \
884 .parents = _inputs##_p, \
885 .num_parents = ARRAY_SIZE(_inputs), \
886 };
887
888PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
889PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
890PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
891PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
892PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
893PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
894PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
895PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
896PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
897PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
898PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
899PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
904PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
905PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
906PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
907PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
909PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
911PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
912PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
913PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
914PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
915/* FIXME: what is la? */
916PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
917PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
918PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
919PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
920PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
921PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
922PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
923PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
925PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
926PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
927PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
928PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
933PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
934PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
936PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
937PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
938PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
940PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
941PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
944PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
945PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
946PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
947PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
949PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
950PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
951PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
952PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
953PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
954PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
955PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
956
957static struct clk *tegra_list_clks[] = {
958 &tegra_apbdma,
959 &tegra_rtc,
960 &tegra_i2s1,
961 &tegra_i2s2,
962 &tegra_spdif_out,
963 &tegra_spdif_in,
964 &tegra_pwm,
965 &tegra_spi,
966 &tegra_xio,
967 &tegra_twc,
968 &tegra_sbc1,
969 &tegra_sbc2,
970 &tegra_sbc3,
971 &tegra_sbc4,
972 &tegra_ide,
973 &tegra_ndflash,
974 &tegra_vfir,
975 &tegra_sdmmc1,
976 &tegra_sdmmc2,
977 &tegra_sdmmc3,
978 &tegra_sdmmc4,
979 &tegra_vcp,
980 &tegra_bsea,
981 &tegra_bsev,
982 &tegra_vde,
983 &tegra_csite,
984 &tegra_la,
985 &tegra_owr,
986 &tegra_nor,
987 &tegra_mipi,
988 &tegra_i2c1,
989 &tegra_i2c2,
990 &tegra_i2c3,
991 &tegra_dvc,
992 &tegra_i2c1_i2c,
993 &tegra_i2c2_i2c,
994 &tegra_i2c3_i2c,
995 &tegra_dvc_i2c,
996 &tegra_uarta,
997 &tegra_uartb,
998 &tegra_uartc,
999 &tegra_uartd,
1000 &tegra_uarte,
1001 &tegra_3d,
1002 &tegra_2d,
1003 &tegra_vi,
1004 &tegra_vi_sensor,
1005 &tegra_epp,
1006 &tegra_mpe,
1007 &tegra_host1x,
1008 &tegra_cve,
1009 &tegra_tvo,
1010 &tegra_hdmi,
1011 &tegra_tvdac,
1012 &tegra_disp1,
1013 &tegra_disp2,
1014 &tegra_usbd,
1015 &tegra_usb2,
1016 &tegra_usb3,
1017 &tegra_dsi,
1018 &tegra_csi,
1019 &tegra_isp,
1020 &tegra_csus,
1021 &tegra_pex,
1022 &tegra_afi,
1023 &tegra_pcie_xclk,
1024};
1025
1026#define CLK_DUPLICATE(_name, _dev, _con) \
1027 { \
1028 .name = _name, \
1029 .lookup = { \
1030 .dev_id = _dev, \
1031 .con_id = _con, \
1032 }, \
1033 }
1034
1035/* Some clocks may be used by different drivers depending on the board
1036 * configuration. List those here to register them twice in the clock lookup
1037 * table under two names.
1038 */
1039static struct clk_duplicate tegra_clk_duplicates[] = {
1040 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1041 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1042 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1043 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1044 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1045 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1046 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1047 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1048 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1049 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1050 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1051 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1052 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1053 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1054 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1055 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1056 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1057 CLK_DUPLICATE("cclk", NULL, "cpu"),
1058 CLK_DUPLICATE("twd", "smp_twd", NULL),
1059};
1060
1061#define CLK(dev, con, ck) \
1062 { \
1063 .dev_id = dev, \
1064 .con_id = con, \
1065 .clk = ck, \
1066 }
1067
1068static struct clk *tegra_ptr_clks[] = {
1069 &tegra_clk_32k,
1070 &tegra_pll_s,
1071 &tegra_clk_m,
1072 &tegra_pll_m,
1073 &tegra_pll_m_out1,
1074 &tegra_pll_c,
1075 &tegra_pll_c_out1,
1076 &tegra_pll_p,
1077 &tegra_pll_p_out1,
1078 &tegra_pll_p_out2,
1079 &tegra_pll_p_out3,
1080 &tegra_pll_p_out4,
1081 &tegra_pll_a,
1082 &tegra_pll_a_out0,
1083 &tegra_pll_d,
1084 &tegra_pll_d_out0,
1085 &tegra_pll_u,
1086 &tegra_pll_x,
1087 &tegra_pll_e,
1088 &tegra_cclk,
1089 &tegra_clk_twd,
1090 &tegra_sclk,
1091 &tegra_hclk,
1092 &tegra_pclk,
1093 &tegra_clk_d,
1094 &tegra_cdev1,
1095 &tegra_cdev2,
1096 &tegra_blink,
1097 &tegra_cop,
1098 &tegra_emc,
1099};
1100
1101static void tegra2_init_one_clock(struct clk *c)
1102{
1103 struct clk_tegra *clk = to_clk_tegra(c->hw);
1104 int ret;
1105
1106 ret = __clk_init(NULL, c);
1107 if (ret)
1108 pr_err("clk init failed %s\n", __clk_get_name(c));
1109
1110 INIT_LIST_HEAD(&clk->shared_bus_list);
1111 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1112 clk->lookup.con_id = c->name;
1113 clk->lookup.clk = c;
1114 clkdev_add(&clk->lookup);
1115 tegra_clk_add(c);
1116}
1117
1118void __init tegra2_init_clocks(void)
1119{
1120 int i;
1121 struct clk *c;
1122
1123 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1124 tegra2_init_one_clock(tegra_ptr_clks[i]);
1125
1126 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1127 tegra2_init_one_clock(tegra_list_clks[i]);
1128
1129 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1130 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1131 if (!c) {
1132 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1133 tegra_clk_duplicates[i].name);
1134 continue;
1135 }
1136
1137 tegra_clk_duplicates[i].lookup.clk = c;
1138 clkdev_add(&tegra_clk_duplicates[i].lookup);
1139 }
1140
1141 init_audio_sync_clock_mux();
1142}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844b2061..000000000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/spinlock.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/clkdev.h>
27#include <linux/clk.h>
28
29#include <mach/iomap.h>
30#include <mach/suspend.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra2_emc.h"
35
36#define RST_DEVICES 0x004
37#define RST_DEVICES_SET 0x300
38#define RST_DEVICES_CLR 0x304
39#define RST_DEVICES_NUM 3
40
41#define CLK_OUT_ENB 0x010
42#define CLK_OUT_ENB_SET 0x320
43#define CLK_OUT_ENB_CLR 0x324
44#define CLK_OUT_ENB_NUM 3
45
46#define CLK_MASK_ARM 0x44
47#define MISC_CLK_ENB 0x48
48
49#define OSC_CTRL 0x50
50#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57#define OSC_FREQ_DET 0x58
58#define OSC_FREQ_DET_TRIG (1<<31)
59
60#define OSC_FREQ_DET_STATUS 0x5C
61#define OSC_FREQ_DET_BUSY (1<<31)
62#define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64#define PERIPH_CLK_SOURCE_I2S1 0x100
65#define PERIPH_CLK_SOURCE_EMC 0x19c
66#define PERIPH_CLK_SOURCE_OSC 0x1fc
67#define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
77#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78
79#define SDMMC_CLK_INT_FB_SEL (1 << 23)
80#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
81#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82
83#define PLL_BASE 0x0
84#define PLL_BASE_BYPASS (1<<31)
85#define PLL_BASE_ENABLE (1<<30)
86#define PLL_BASE_REF_ENABLE (1<<29)
87#define PLL_BASE_OVERRIDE (1<<28)
88#define PLL_BASE_DIVP_MASK (0x7<<20)
89#define PLL_BASE_DIVP_SHIFT 20
90#define PLL_BASE_DIVN_MASK (0x3FF<<8)
91#define PLL_BASE_DIVN_SHIFT 8
92#define PLL_BASE_DIVM_MASK (0x1F)
93#define PLL_BASE_DIVM_SHIFT 0
94
95#define PLL_OUT_RATIO_MASK (0xFF<<8)
96#define PLL_OUT_RATIO_SHIFT 8
97#define PLL_OUT_OVERRIDE (1<<2)
98#define PLL_OUT_CLKEN (1<<1)
99#define PLL_OUT_RESET_DISABLE (1<<0)
100
101#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102
103#define PLL_MISC_DCCON_SHIFT 20
104#define PLL_MISC_CPCON_SHIFT 8
105#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
106#define PLL_MISC_LFCON_SHIFT 4
107#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
108#define PLL_MISC_VCOCON_SHIFT 0
109#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
110
111#define PLLU_BASE_POST_DIV (1<<20)
112
113#define PLLD_MISC_CLKENABLE (1<<30)
114#define PLLD_MISC_DIV_RST (1<<23)
115#define PLLD_MISC_DCCON_SHIFT 12
116
117#define PLLE_MISC_READY (1 << 15)
118
119#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
120#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
121#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
122
123#define SUPER_CLK_MUX 0x00
124#define SUPER_STATE_SHIFT 28
125#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
126#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
127#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
128#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
131#define SUPER_SOURCE_MASK 0xF
132#define SUPER_FIQ_SOURCE_SHIFT 12
133#define SUPER_IRQ_SOURCE_SHIFT 8
134#define SUPER_RUN_SOURCE_SHIFT 4
135#define SUPER_IDLE_SOURCE_SHIFT 0
136
137#define SUPER_CLK_DIVIDER 0x04
138
139#define BUS_CLK_DISABLE (1<<3)
140#define BUS_CLK_DIV_MASK 0x3
141
142#define PMC_CTRL 0x0
143 #define PMC_CTRL_BLINK_ENB (1 << 7)
144
145#define PMC_DPD_PADS_ORIDE 0x1c
146 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
147
148#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
149#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
150#define PMC_BLINK_TIMER_ENB (1 << 15)
151#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
152#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
153
154static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
155static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156
157/*
158 * Some clocks share a register with other clocks. Any clock op that
159 * non-atomically modifies a register used by another clock must lock
160 * clock_register_lock first.
161 */
162static DEFINE_SPINLOCK(clock_register_lock);
163
164/*
165 * Some peripheral clocks share an enable bit, so refcount the enable bits
166 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
167 */
168static int tegra_periph_clk_enable_refcount[3 * 32];
169
170#define clk_writel(value, reg) \
171 __raw_writel(value, reg_clk_base + (reg))
172#define clk_readl(reg) \
173 __raw_readl(reg_clk_base + (reg))
174#define pmc_writel(value, reg) \
175 __raw_writel(value, reg_pmc_base + (reg))
176#define pmc_readl(reg) \
177 __raw_readl(reg_pmc_base + (reg))
178
179static unsigned long clk_measure_input_freq(void)
180{
181 u32 clock_autodetect;
182 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
183 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
184 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
185 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
186 return 12000000;
187 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
188 return 13000000;
189 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
190 return 19200000;
191 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
192 return 26000000;
193 } else {
194 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
195 BUG();
196 return 0;
197 }
198}
199
200static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
201{
202 s64 divider_u71 = parent_rate * 2;
203 divider_u71 += rate - 1;
204 do_div(divider_u71, rate);
205
206 if (divider_u71 - 2 < 0)
207 return 0;
208
209 if (divider_u71 - 2 > 255)
210 return -EINVAL;
211
212 return divider_u71 - 2;
213}
214
215static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
216{
217 s64 divider_u16;
218
219 divider_u16 = parent_rate;
220 divider_u16 += rate - 1;
221 do_div(divider_u16, rate);
222
223 if (divider_u16 - 1 < 0)
224 return 0;
225
226 if (divider_u16 - 1 > 255)
227 return -EINVAL;
228
229 return divider_u16 - 1;
230}
231
232/* clk_m functions */
233static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
234{
235 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
236
237 c->rate = clk_measure_input_freq();
238 switch (c->rate) {
239 case 12000000:
240 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
241 break;
242 case 13000000:
243 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
244 break;
245 case 19200000:
246 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
247 break;
248 case 26000000:
249 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
250 break;
251 default:
252 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
253 BUG();
254 }
255 clk_writel(auto_clock_control, OSC_CTRL);
256 return c->rate;
257}
258
259static void tegra2_clk_m_init(struct clk *c)
260{
261 pr_debug("%s on clock %s\n", __func__, c->name);
262 tegra2_clk_m_autodetect_rate(c);
263}
264
265static int tegra2_clk_m_enable(struct clk *c)
266{
267 pr_debug("%s on clock %s\n", __func__, c->name);
268 return 0;
269}
270
271static void tegra2_clk_m_disable(struct clk *c)
272{
273 pr_debug("%s on clock %s\n", __func__, c->name);
274 BUG();
275}
276
277static struct clk_ops tegra_clk_m_ops = {
278 .init = tegra2_clk_m_init,
279 .enable = tegra2_clk_m_enable,
280 .disable = tegra2_clk_m_disable,
281};
282
283/* super clock functions */
284/* "super clocks" on tegra have two-stage muxes and a clock skipping
285 * super divider. We will ignore the clock skipping divider, since we
286 * can't lower the voltage when using the clock skip, but we can if we
287 * lower the PLL frequency.
288 */
289static void tegra2_super_clk_init(struct clk *c)
290{
291 u32 val;
292 int source;
293 int shift;
294 const struct clk_mux_sel *sel;
295 val = clk_readl(c->reg + SUPER_CLK_MUX);
296 c->state = ON;
297 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
298 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
299 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
300 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
301 source = (val >> shift) & SUPER_SOURCE_MASK;
302 for (sel = c->inputs; sel->input != NULL; sel++) {
303 if (sel->value == source)
304 break;
305 }
306 BUG_ON(sel->input == NULL);
307 c->parent = sel->input;
308}
309
310static int tegra2_super_clk_enable(struct clk *c)
311{
312 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
313 return 0;
314}
315
316static void tegra2_super_clk_disable(struct clk *c)
317{
318 pr_debug("%s on clock %s\n", __func__, c->name);
319
320 /* oops - don't disable the CPU clock! */
321 BUG();
322}
323
324static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
325{
326 u32 val;
327 const struct clk_mux_sel *sel;
328 int shift;
329
330 val = clk_readl(c->reg + SUPER_CLK_MUX);
331 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
332 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
333 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
334 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
335 for (sel = c->inputs; sel->input != NULL; sel++) {
336 if (sel->input == p) {
337 val &= ~(SUPER_SOURCE_MASK << shift);
338 val |= sel->value << shift;
339
340 if (c->refcnt)
341 clk_enable(p);
342
343 clk_writel(val, c->reg);
344
345 if (c->refcnt && c->parent)
346 clk_disable(c->parent);
347
348 clk_reparent(c, p);
349 return 0;
350 }
351 }
352 return -EINVAL;
353}
354
355/*
356 * Super clocks have "clock skippers" instead of dividers. Dividing using
357 * a clock skipper does not allow the voltage to be scaled down, so instead
358 * adjust the rate of the parent clock. This requires that the parent of a
359 * super clock have no other children, otherwise the rate will change
360 * underneath the other children.
361 */
362static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
363{
364 return clk_set_rate(c->parent, rate);
365}
366
367static struct clk_ops tegra_super_ops = {
368 .init = tegra2_super_clk_init,
369 .enable = tegra2_super_clk_enable,
370 .disable = tegra2_super_clk_disable,
371 .set_parent = tegra2_super_clk_set_parent,
372 .set_rate = tegra2_super_clk_set_rate,
373};
374
375/* virtual cpu clock functions */
376/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
377 To change the frequency of these clocks, the parent pll may need to be
378 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
379 and then the clock moved back to the pll. To hide this sequence, a virtual
380 clock handles it.
381 */
382static void tegra2_cpu_clk_init(struct clk *c)
383{
384}
385
386static int tegra2_cpu_clk_enable(struct clk *c)
387{
388 return 0;
389}
390
391static void tegra2_cpu_clk_disable(struct clk *c)
392{
393 pr_debug("%s on clock %s\n", __func__, c->name);
394
395 /* oops - don't disable the CPU clock! */
396 BUG();
397}
398
399static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
400{
401 int ret;
402 /*
403 * Take an extra reference to the main pll so it doesn't turn
404 * off when we move the cpu off of it
405 */
406 clk_enable(c->u.cpu.main);
407
408 ret = clk_set_parent(c->parent, c->u.cpu.backup);
409 if (ret) {
410 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
411 goto out;
412 }
413
414 if (rate == clk_get_rate(c->u.cpu.backup))
415 goto out;
416
417 ret = clk_set_rate(c->u.cpu.main, rate);
418 if (ret) {
419 pr_err("Failed to change cpu pll to %lu\n", rate);
420 goto out;
421 }
422
423 ret = clk_set_parent(c->parent, c->u.cpu.main);
424 if (ret) {
425 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
426 goto out;
427 }
428
429out:
430 clk_disable(c->u.cpu.main);
431 return ret;
432}
433
434static struct clk_ops tegra_cpu_ops = {
435 .init = tegra2_cpu_clk_init,
436 .enable = tegra2_cpu_clk_enable,
437 .disable = tegra2_cpu_clk_disable,
438 .set_rate = tegra2_cpu_clk_set_rate,
439};
440
441/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
442 * reset the COP block (i.e. AVP) */
443static void tegra2_cop_clk_reset(struct clk *c, bool assert)
444{
445 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
446
447 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
448 clk_writel(1 << 1, reg);
449}
450
451static struct clk_ops tegra_cop_ops = {
452 .reset = tegra2_cop_clk_reset,
453};
454
455/* bus clock functions */
456static void tegra2_bus_clk_init(struct clk *c)
457{
458 u32 val = clk_readl(c->reg);
459 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
460 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
461 c->mul = 1;
462}
463
464static int tegra2_bus_clk_enable(struct clk *c)
465{
466 u32 val;
467 unsigned long flags;
468
469 spin_lock_irqsave(&clock_register_lock, flags);
470
471 val = clk_readl(c->reg);
472 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
473 clk_writel(val, c->reg);
474
475 spin_unlock_irqrestore(&clock_register_lock, flags);
476
477 return 0;
478}
479
480static void tegra2_bus_clk_disable(struct clk *c)
481{
482 u32 val;
483 unsigned long flags;
484
485 spin_lock_irqsave(&clock_register_lock, flags);
486
487 val = clk_readl(c->reg);
488 val |= BUS_CLK_DISABLE << c->reg_shift;
489 clk_writel(val, c->reg);
490
491 spin_unlock_irqrestore(&clock_register_lock, flags);
492}
493
494static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
495{
496 u32 val;
497 unsigned long parent_rate = clk_get_rate(c->parent);
498 unsigned long flags;
499 int ret = -EINVAL;
500 int i;
501
502 spin_lock_irqsave(&clock_register_lock, flags);
503
504 val = clk_readl(c->reg);
505 for (i = 1; i <= 4; i++) {
506 if (rate == parent_rate / i) {
507 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
508 val |= (i - 1) << c->reg_shift;
509 clk_writel(val, c->reg);
510 c->div = i;
511 c->mul = 1;
512 ret = 0;
513 break;
514 }
515 }
516
517 spin_unlock_irqrestore(&clock_register_lock, flags);
518
519 return ret;
520}
521
522static struct clk_ops tegra_bus_ops = {
523 .init = tegra2_bus_clk_init,
524 .enable = tegra2_bus_clk_enable,
525 .disable = tegra2_bus_clk_disable,
526 .set_rate = tegra2_bus_clk_set_rate,
527};
528
529/* Blink output functions */
530
531static void tegra2_blink_clk_init(struct clk *c)
532{
533 u32 val;
534
535 val = pmc_readl(PMC_CTRL);
536 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
537 c->mul = 1;
538 val = pmc_readl(c->reg);
539
540 if (val & PMC_BLINK_TIMER_ENB) {
541 unsigned int on_off;
542
543 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
544 PMC_BLINK_TIMER_DATA_ON_MASK;
545 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
546 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
547 on_off += val;
548 /* each tick in the blink timer is 4 32KHz clocks */
549 c->div = on_off * 4;
550 } else {
551 c->div = 1;
552 }
553}
554
555static int tegra2_blink_clk_enable(struct clk *c)
556{
557 u32 val;
558
559 val = pmc_readl(PMC_DPD_PADS_ORIDE);
560 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
561
562 val = pmc_readl(PMC_CTRL);
563 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
564
565 return 0;
566}
567
568static void tegra2_blink_clk_disable(struct clk *c)
569{
570 u32 val;
571
572 val = pmc_readl(PMC_CTRL);
573 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
574
575 val = pmc_readl(PMC_DPD_PADS_ORIDE);
576 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
577}
578
579static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
580{
581 unsigned long parent_rate = clk_get_rate(c->parent);
582 if (rate >= parent_rate) {
583 c->div = 1;
584 pmc_writel(0, c->reg);
585 } else {
586 unsigned int on_off;
587 u32 val;
588
589 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
590 c->div = on_off * 8;
591
592 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
593 PMC_BLINK_TIMER_DATA_ON_SHIFT;
594 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
595 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
596 val |= on_off;
597 val |= PMC_BLINK_TIMER_ENB;
598 pmc_writel(val, c->reg);
599 }
600
601 return 0;
602}
603
604static struct clk_ops tegra_blink_clk_ops = {
605 .init = &tegra2_blink_clk_init,
606 .enable = &tegra2_blink_clk_enable,
607 .disable = &tegra2_blink_clk_disable,
608 .set_rate = &tegra2_blink_clk_set_rate,
609};
610
611/* PLL Functions */
612static int tegra2_pll_clk_wait_for_lock(struct clk *c)
613{
614 udelay(c->u.pll.lock_delay);
615
616 return 0;
617}
618
619static void tegra2_pll_clk_init(struct clk *c)
620{
621 u32 val = clk_readl(c->reg + PLL_BASE);
622
623 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
624
625 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
626 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
627 c->mul = 1;
628 c->div = 1;
629 } else if (val & PLL_BASE_BYPASS) {
630 c->mul = 1;
631 c->div = 1;
632 } else {
633 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
634 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
635 if (c->flags & PLLU)
636 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
637 else
638 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
639 }
640}
641
642static int tegra2_pll_clk_enable(struct clk *c)
643{
644 u32 val;
645 pr_debug("%s on clock %s\n", __func__, c->name);
646
647 val = clk_readl(c->reg + PLL_BASE);
648 val &= ~PLL_BASE_BYPASS;
649 val |= PLL_BASE_ENABLE;
650 clk_writel(val, c->reg + PLL_BASE);
651
652 tegra2_pll_clk_wait_for_lock(c);
653
654 return 0;
655}
656
657static void tegra2_pll_clk_disable(struct clk *c)
658{
659 u32 val;
660 pr_debug("%s on clock %s\n", __func__, c->name);
661
662 val = clk_readl(c->reg);
663 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
664 clk_writel(val, c->reg);
665}
666
667static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
668{
669 u32 val;
670 unsigned long input_rate;
671 const struct clk_pll_freq_table *sel;
672
673 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
674
675 input_rate = clk_get_rate(c->parent);
676 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
677 if (sel->input_rate == input_rate && sel->output_rate == rate) {
678 c->mul = sel->n;
679 c->div = sel->m * sel->p;
680
681 val = clk_readl(c->reg + PLL_BASE);
682 if (c->flags & PLL_FIXED)
683 val |= PLL_BASE_OVERRIDE;
684 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
685 PLL_BASE_DIVM_MASK);
686 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
687 (sel->n << PLL_BASE_DIVN_SHIFT);
688 BUG_ON(sel->p < 1 || sel->p > 2);
689 if (c->flags & PLLU) {
690 if (sel->p == 1)
691 val |= PLLU_BASE_POST_DIV;
692 } else {
693 if (sel->p == 2)
694 val |= 1 << PLL_BASE_DIVP_SHIFT;
695 }
696 clk_writel(val, c->reg + PLL_BASE);
697
698 if (c->flags & PLL_HAS_CPCON) {
699 val = clk_readl(c->reg + PLL_MISC(c));
700 val &= ~PLL_MISC_CPCON_MASK;
701 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
702 clk_writel(val, c->reg + PLL_MISC(c));
703 }
704
705 if (c->state == ON)
706 tegra2_pll_clk_enable(c);
707
708 return 0;
709 }
710 }
711 return -EINVAL;
712}
713
714static struct clk_ops tegra_pll_ops = {
715 .init = tegra2_pll_clk_init,
716 .enable = tegra2_pll_clk_enable,
717 .disable = tegra2_pll_clk_disable,
718 .set_rate = tegra2_pll_clk_set_rate,
719};
720
721static void tegra2_pllx_clk_init(struct clk *c)
722{
723 tegra2_pll_clk_init(c);
724
725 if (tegra_sku_id == 7)
726 c->max_rate = 750000000;
727}
728
729static struct clk_ops tegra_pllx_ops = {
730 .init = tegra2_pllx_clk_init,
731 .enable = tegra2_pll_clk_enable,
732 .disable = tegra2_pll_clk_disable,
733 .set_rate = tegra2_pll_clk_set_rate,
734};
735
736static int tegra2_plle_clk_enable(struct clk *c)
737{
738 u32 val;
739
740 pr_debug("%s on clock %s\n", __func__, c->name);
741
742 mdelay(1);
743
744 val = clk_readl(c->reg + PLL_BASE);
745 if (!(val & PLLE_MISC_READY))
746 return -EBUSY;
747
748 val = clk_readl(c->reg + PLL_BASE);
749 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
750 clk_writel(val, c->reg + PLL_BASE);
751
752 return 0;
753}
754
755static struct clk_ops tegra_plle_ops = {
756 .init = tegra2_pll_clk_init,
757 .enable = tegra2_plle_clk_enable,
758 .set_rate = tegra2_pll_clk_set_rate,
759};
760
761/* Clock divider ops */
762static void tegra2_pll_div_clk_init(struct clk *c)
763{
764 u32 val = clk_readl(c->reg);
765 u32 divu71;
766 val >>= c->reg_shift;
767 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
768 if (!(val & PLL_OUT_RESET_DISABLE))
769 c->state = OFF;
770
771 if (c->flags & DIV_U71) {
772 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
773 c->div = (divu71 + 2);
774 c->mul = 2;
775 } else if (c->flags & DIV_2) {
776 c->div = 2;
777 c->mul = 1;
778 } else {
779 c->div = 1;
780 c->mul = 1;
781 }
782}
783
784static int tegra2_pll_div_clk_enable(struct clk *c)
785{
786 u32 val;
787 u32 new_val;
788 unsigned long flags;
789
790 pr_debug("%s: %s\n", __func__, c->name);
791 if (c->flags & DIV_U71) {
792 spin_lock_irqsave(&clock_register_lock, flags);
793 val = clk_readl(c->reg);
794 new_val = val >> c->reg_shift;
795 new_val &= 0xFFFF;
796
797 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
798
799 val &= ~(0xFFFF << c->reg_shift);
800 val |= new_val << c->reg_shift;
801 clk_writel(val, c->reg);
802 spin_unlock_irqrestore(&clock_register_lock, flags);
803 return 0;
804 } else if (c->flags & DIV_2) {
805 BUG_ON(!(c->flags & PLLD));
806 spin_lock_irqsave(&clock_register_lock, flags);
807 val = clk_readl(c->reg);
808 val &= ~PLLD_MISC_DIV_RST;
809 clk_writel(val, c->reg);
810 spin_unlock_irqrestore(&clock_register_lock, flags);
811 return 0;
812 }
813 return -EINVAL;
814}
815
816static void tegra2_pll_div_clk_disable(struct clk *c)
817{
818 u32 val;
819 u32 new_val;
820 unsigned long flags;
821
822 pr_debug("%s: %s\n", __func__, c->name);
823 if (c->flags & DIV_U71) {
824 spin_lock_irqsave(&clock_register_lock, flags);
825 val = clk_readl(c->reg);
826 new_val = val >> c->reg_shift;
827 new_val &= 0xFFFF;
828
829 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
830
831 val &= ~(0xFFFF << c->reg_shift);
832 val |= new_val << c->reg_shift;
833 clk_writel(val, c->reg);
834 spin_unlock_irqrestore(&clock_register_lock, flags);
835 } else if (c->flags & DIV_2) {
836 BUG_ON(!(c->flags & PLLD));
837 spin_lock_irqsave(&clock_register_lock, flags);
838 val = clk_readl(c->reg);
839 val |= PLLD_MISC_DIV_RST;
840 clk_writel(val, c->reg);
841 spin_unlock_irqrestore(&clock_register_lock, flags);
842 }
843}
844
845static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
846{
847 u32 val;
848 u32 new_val;
849 int divider_u71;
850 unsigned long parent_rate = clk_get_rate(c->parent);
851 unsigned long flags;
852
853 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
854 if (c->flags & DIV_U71) {
855 divider_u71 = clk_div71_get_divider(parent_rate, rate);
856 if (divider_u71 >= 0) {
857 spin_lock_irqsave(&clock_register_lock, flags);
858 val = clk_readl(c->reg);
859 new_val = val >> c->reg_shift;
860 new_val &= 0xFFFF;
861 if (c->flags & DIV_U71_FIXED)
862 new_val |= PLL_OUT_OVERRIDE;
863 new_val &= ~PLL_OUT_RATIO_MASK;
864 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
865
866 val &= ~(0xFFFF << c->reg_shift);
867 val |= new_val << c->reg_shift;
868 clk_writel(val, c->reg);
869 c->div = divider_u71 + 2;
870 c->mul = 2;
871 spin_unlock_irqrestore(&clock_register_lock, flags);
872 return 0;
873 }
874 } else if (c->flags & DIV_2) {
875 if (parent_rate == rate * 2)
876 return 0;
877 }
878 return -EINVAL;
879}
880
881static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
882{
883 int divider;
884 unsigned long parent_rate = clk_get_rate(c->parent);
885 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
886
887 if (c->flags & DIV_U71) {
888 divider = clk_div71_get_divider(parent_rate, rate);
889 if (divider < 0)
890 return divider;
891 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
892 } else if (c->flags & DIV_2) {
893 return DIV_ROUND_UP(parent_rate, 2);
894 }
895 return -EINVAL;
896}
897
898static struct clk_ops tegra_pll_div_ops = {
899 .init = tegra2_pll_div_clk_init,
900 .enable = tegra2_pll_div_clk_enable,
901 .disable = tegra2_pll_div_clk_disable,
902 .set_rate = tegra2_pll_div_clk_set_rate,
903 .round_rate = tegra2_pll_div_clk_round_rate,
904};
905
906/* Periph clk ops */
907
908static void tegra2_periph_clk_init(struct clk *c)
909{
910 u32 val = clk_readl(c->reg);
911 const struct clk_mux_sel *mux = NULL;
912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
924 if (c->flags & MUX) {
925 for (sel = c->inputs; sel->input != NULL; sel++) {
926 if ((val & mask) >> shift == sel->value)
927 mux = sel;
928 }
929 BUG_ON(!mux);
930
931 c->parent = mux->input;
932 } else {
933 c->parent = c->inputs[0].input;
934 }
935
936 if (c->flags & DIV_U71) {
937 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
938 c->div = divu71 + 2;
939 c->mul = 2;
940 } else if (c->flags & DIV_U16) {
941 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
942 c->div = divu16 + 1;
943 c->mul = 1;
944 } else {
945 c->div = 1;
946 c->mul = 1;
947 }
948
949 c->state = ON;
950
951 if (!c->u.periph.clk_num)
952 return;
953
954 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
955 PERIPH_CLK_TO_ENB_BIT(c)))
956 c->state = OFF;
957
958 if (!(c->flags & PERIPH_NO_RESET))
959 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
960 PERIPH_CLK_TO_ENB_BIT(c))
961 c->state = OFF;
962}
963
964static int tegra2_periph_clk_enable(struct clk *c)
965{
966 u32 val;
967 unsigned long flags;
968 int refcount;
969 pr_debug("%s on clock %s\n", __func__, c->name);
970
971 if (!c->u.periph.clk_num)
972 return 0;
973
974 spin_lock_irqsave(&clock_register_lock, flags);
975
976 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
977
978 if (refcount > 1)
979 goto out;
980
981 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
982 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
983 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
984 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
985 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
986 if (c->flags & PERIPH_EMC_ENB) {
987 /* The EMC peripheral clock has 2 extra enable bits */
988 /* FIXME: Do they need to be disabled? */
989 val = clk_readl(c->reg);
990 val |= 0x3 << 24;
991 clk_writel(val, c->reg);
992 }
993
994out:
995 spin_unlock_irqrestore(&clock_register_lock, flags);
996
997 return 0;
998}
999
1000static void tegra2_periph_clk_disable(struct clk *c)
1001{
1002 unsigned long flags;
1003
1004 pr_debug("%s on clock %s\n", __func__, c->name);
1005
1006 if (!c->u.periph.clk_num)
1007 return;
1008
1009 spin_lock_irqsave(&clock_register_lock, flags);
1010
1011 if (c->refcnt)
1012 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1013
1014 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1015 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1016 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1017
1018 spin_unlock_irqrestore(&clock_register_lock, flags);
1019}
1020
1021static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1022{
1023 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1024
1025 pr_debug("%s %s on clock %s\n", __func__,
1026 assert ? "assert" : "deassert", c->name);
1027
1028 BUG_ON(!c->u.periph.clk_num);
1029
1030 if (!(c->flags & PERIPH_NO_RESET))
1031 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1032 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1033}
1034
1035static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1036{
1037 u32 val;
1038 const struct clk_mux_sel *sel;
1039 u32 mask, shift;
1040
1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1042
1043 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1045 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1046 } else {
1047 shift = PERIPH_CLK_SOURCE_SHIFT;
1048 mask = PERIPH_CLK_SOURCE_MASK;
1049 }
1050
1051 for (sel = c->inputs; sel->input != NULL; sel++) {
1052 if (sel->input == p) {
1053 val = clk_readl(c->reg);
1054 val &= ~mask;
1055 val |= (sel->value) << shift;
1056
1057 if (c->refcnt)
1058 clk_enable(p);
1059
1060 clk_writel(val, c->reg);
1061
1062 if (c->refcnt && c->parent)
1063 clk_disable(c->parent);
1064
1065 clk_reparent(c, p);
1066 return 0;
1067 }
1068 }
1069
1070 return -EINVAL;
1071}
1072
1073static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1074{
1075 u32 val;
1076 int divider;
1077 unsigned long parent_rate = clk_get_rate(c->parent);
1078
1079 if (c->flags & DIV_U71) {
1080 divider = clk_div71_get_divider(parent_rate, rate);
1081 if (divider >= 0) {
1082 val = clk_readl(c->reg);
1083 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1084 val |= divider;
1085 clk_writel(val, c->reg);
1086 c->div = divider + 2;
1087 c->mul = 2;
1088 return 0;
1089 }
1090 } else if (c->flags & DIV_U16) {
1091 divider = clk_div16_get_divider(parent_rate, rate);
1092 if (divider >= 0) {
1093 val = clk_readl(c->reg);
1094 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1095 val |= divider;
1096 clk_writel(val, c->reg);
1097 c->div = divider + 1;
1098 c->mul = 1;
1099 return 0;
1100 }
1101 } else if (parent_rate <= rate) {
1102 c->div = 1;
1103 c->mul = 1;
1104 return 0;
1105 }
1106 return -EINVAL;
1107}
1108
1109static long tegra2_periph_clk_round_rate(struct clk *c,
1110 unsigned long rate)
1111{
1112 int divider;
1113 unsigned long parent_rate = clk_get_rate(c->parent);
1114 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1115
1116 if (c->flags & DIV_U71) {
1117 divider = clk_div71_get_divider(parent_rate, rate);
1118 if (divider < 0)
1119 return divider;
1120
1121 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1122 } else if (c->flags & DIV_U16) {
1123 divider = clk_div16_get_divider(parent_rate, rate);
1124 if (divider < 0)
1125 return divider;
1126 return DIV_ROUND_UP(parent_rate, divider + 1);
1127 }
1128 return -EINVAL;
1129}
1130
1131static struct clk_ops tegra_periph_clk_ops = {
1132 .init = &tegra2_periph_clk_init,
1133 .enable = &tegra2_periph_clk_enable,
1134 .disable = &tegra2_periph_clk_disable,
1135 .set_parent = &tegra2_periph_clk_set_parent,
1136 .set_rate = &tegra2_periph_clk_set_rate,
1137 .round_rate = &tegra2_periph_clk_round_rate,
1138 .reset = &tegra2_periph_clk_reset,
1139};
1140
1141/* The SDMMC controllers have extra bits in the clock source register that
1142 * adjust the delay between the clock and data to compenstate for delays
1143 * on the PCB. */
1144void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1145{
1146 u32 reg;
1147 unsigned long flags;
1148
1149 spin_lock_irqsave(&c->spinlock, flags);
1150
1151 delay = clamp(delay, 0, 15);
1152 reg = clk_readl(c->reg);
1153 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1154 reg |= SDMMC_CLK_INT_FB_SEL;
1155 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1156 clk_writel(reg, c->reg);
1157
1158 spin_unlock_irqrestore(&c->spinlock, flags);
1159}
1160
1161/* External memory controller clock ops */
1162static void tegra2_emc_clk_init(struct clk *c)
1163{
1164 tegra2_periph_clk_init(c);
1165 c->max_rate = clk_get_rate_locked(c);
1166}
1167
1168static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1169{
1170 long emc_rate;
1171 long clk_rate;
1172
1173 /*
1174 * The slowest entry in the EMC clock table that is at least as
1175 * fast as rate.
1176 */
1177 emc_rate = tegra_emc_round_rate(rate);
1178 if (emc_rate < 0)
1179 return c->max_rate;
1180
1181 /*
1182 * The fastest rate the PLL will generate that is at most the
1183 * requested rate.
1184 */
1185 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
1186
1187 /*
1188 * If this fails, and emc_rate > clk_rate, it's because the maximum
1189 * rate in the EMC tables is larger than the maximum rate of the EMC
1190 * clock. The EMC clock's max rate is the rate it was running when the
1191 * kernel booted. Such a mismatch is probably due to using the wrong
1192 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1193 */
1194 WARN_ONCE(emc_rate != clk_rate,
1195 "emc_rate %ld != clk_rate %ld",
1196 emc_rate, clk_rate);
1197
1198 return emc_rate;
1199}
1200
1201static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1202{
1203 int ret;
1204 /*
1205 * The Tegra2 memory controller has an interlock with the clock
1206 * block that allows memory shadowed registers to be updated,
1207 * and then transfer them to the main registers at the same
1208 * time as the clock update without glitches.
1209 */
1210 ret = tegra_emc_set_rate(rate);
1211 if (ret < 0)
1212 return ret;
1213
1214 ret = tegra2_periph_clk_set_rate(c, rate);
1215 udelay(1);
1216
1217 return ret;
1218}
1219
1220static struct clk_ops tegra_emc_clk_ops = {
1221 .init = &tegra2_emc_clk_init,
1222 .enable = &tegra2_periph_clk_enable,
1223 .disable = &tegra2_periph_clk_disable,
1224 .set_parent = &tegra2_periph_clk_set_parent,
1225 .set_rate = &tegra2_emc_clk_set_rate,
1226 .round_rate = &tegra2_emc_clk_round_rate,
1227 .reset = &tegra2_periph_clk_reset,
1228};
1229
1230/* Clock doubler ops */
1231static void tegra2_clk_double_init(struct clk *c)
1232{
1233 c->mul = 2;
1234 c->div = 1;
1235 c->state = ON;
1236
1237 if (!c->u.periph.clk_num)
1238 return;
1239
1240 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1241 PERIPH_CLK_TO_ENB_BIT(c)))
1242 c->state = OFF;
1243};
1244
1245static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1246{
1247 if (rate != 2 * clk_get_rate(c->parent))
1248 return -EINVAL;
1249 c->mul = 2;
1250 c->div = 1;
1251 return 0;
1252}
1253
1254static struct clk_ops tegra_clk_double_ops = {
1255 .init = &tegra2_clk_double_init,
1256 .enable = &tegra2_periph_clk_enable,
1257 .disable = &tegra2_periph_clk_disable,
1258 .set_rate = &tegra2_clk_double_set_rate,
1259};
1260
1261/* Audio sync clock ops */
1262static void tegra2_audio_sync_clk_init(struct clk *c)
1263{
1264 int source;
1265 const struct clk_mux_sel *sel;
1266 u32 val = clk_readl(c->reg);
1267 c->state = (val & (1<<4)) ? OFF : ON;
1268 source = val & 0xf;
1269 for (sel = c->inputs; sel->input != NULL; sel++)
1270 if (sel->value == source)
1271 break;
1272 BUG_ON(sel->input == NULL);
1273 c->parent = sel->input;
1274}
1275
1276static int tegra2_audio_sync_clk_enable(struct clk *c)
1277{
1278 clk_writel(0, c->reg);
1279 return 0;
1280}
1281
1282static void tegra2_audio_sync_clk_disable(struct clk *c)
1283{
1284 clk_writel(1, c->reg);
1285}
1286
1287static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1288{
1289 u32 val;
1290 const struct clk_mux_sel *sel;
1291 for (sel = c->inputs; sel->input != NULL; sel++) {
1292 if (sel->input == p) {
1293 val = clk_readl(c->reg);
1294 val &= ~0xf;
1295 val |= sel->value;
1296
1297 if (c->refcnt)
1298 clk_enable(p);
1299
1300 clk_writel(val, c->reg);
1301
1302 if (c->refcnt && c->parent)
1303 clk_disable(c->parent);
1304
1305 clk_reparent(c, p);
1306 return 0;
1307 }
1308 }
1309
1310 return -EINVAL;
1311}
1312
1313static struct clk_ops tegra_audio_sync_clk_ops = {
1314 .init = tegra2_audio_sync_clk_init,
1315 .enable = tegra2_audio_sync_clk_enable,
1316 .disable = tegra2_audio_sync_clk_disable,
1317 .set_parent = tegra2_audio_sync_clk_set_parent,
1318};
1319
1320/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1321
1322static void tegra2_cdev_clk_init(struct clk *c)
1323{
1324 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1325 * currently done in the pinmux code. */
1326 c->state = ON;
1327
1328 BUG_ON(!c->u.periph.clk_num);
1329
1330 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1331 PERIPH_CLK_TO_ENB_BIT(c)))
1332 c->state = OFF;
1333}
1334
1335static int tegra2_cdev_clk_enable(struct clk *c)
1336{
1337 BUG_ON(!c->u.periph.clk_num);
1338
1339 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1340 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1341 return 0;
1342}
1343
1344static void tegra2_cdev_clk_disable(struct clk *c)
1345{
1346 BUG_ON(!c->u.periph.clk_num);
1347
1348 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1350}
1351
1352static struct clk_ops tegra_cdev_clk_ops = {
1353 .init = &tegra2_cdev_clk_init,
1354 .enable = &tegra2_cdev_clk_enable,
1355 .disable = &tegra2_cdev_clk_disable,
1356};
1357
1358/* shared bus ops */
1359/*
1360 * Some clocks may have multiple downstream users that need to request a
1361 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1362 * clock to each user. The frequency of the bus is set to the highest
1363 * enabled shared_bus_user clock, with a minimum value set by the
1364 * shared bus.
1365 */
1366static int tegra_clk_shared_bus_update(struct clk *bus)
1367{
1368 struct clk *c;
1369 unsigned long rate = bus->min_rate;
1370
1371 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1372 if (c->u.shared_bus_user.enabled)
1373 rate = max(c->u.shared_bus_user.rate, rate);
1374
1375 if (rate == clk_get_rate_locked(bus))
1376 return 0;
1377
1378 return clk_set_rate_locked(bus, rate);
1379};
1380
1381static void tegra_clk_shared_bus_init(struct clk *c)
1382{
1383 unsigned long flags;
1384
1385 c->max_rate = c->parent->max_rate;
1386 c->u.shared_bus_user.rate = c->parent->max_rate;
1387 c->state = OFF;
1388 c->set = true;
1389
1390 spin_lock_irqsave(&c->parent->spinlock, flags);
1391
1392 list_add_tail(&c->u.shared_bus_user.node,
1393 &c->parent->shared_bus_list);
1394
1395 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1396}
1397
1398static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1399{
1400 unsigned long flags;
1401 int ret;
1402 long new_rate = rate;
1403
1404 new_rate = clk_round_rate(c->parent, new_rate);
1405 if (new_rate < 0)
1406 return new_rate;
1407
1408 spin_lock_irqsave(&c->parent->spinlock, flags);
1409
1410 c->u.shared_bus_user.rate = new_rate;
1411 ret = tegra_clk_shared_bus_update(c->parent);
1412
1413 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1414
1415 return ret;
1416}
1417
1418static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1419{
1420 return clk_round_rate(c->parent, rate);
1421}
1422
1423static int tegra_clk_shared_bus_enable(struct clk *c)
1424{
1425 unsigned long flags;
1426 int ret;
1427
1428 spin_lock_irqsave(&c->parent->spinlock, flags);
1429
1430 c->u.shared_bus_user.enabled = true;
1431 ret = tegra_clk_shared_bus_update(c->parent);
1432
1433 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1434
1435 return ret;
1436}
1437
1438static void tegra_clk_shared_bus_disable(struct clk *c)
1439{
1440 unsigned long flags;
1441 int ret;
1442
1443 spin_lock_irqsave(&c->parent->spinlock, flags);
1444
1445 c->u.shared_bus_user.enabled = false;
1446 ret = tegra_clk_shared_bus_update(c->parent);
1447 WARN_ON_ONCE(ret);
1448
1449 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1450}
1451
1452static struct clk_ops tegra_clk_shared_bus_ops = {
1453 .init = tegra_clk_shared_bus_init,
1454 .enable = tegra_clk_shared_bus_enable,
1455 .disable = tegra_clk_shared_bus_disable,
1456 .set_rate = tegra_clk_shared_bus_set_rate,
1457 .round_rate = tegra_clk_shared_bus_round_rate,
1458};
1459
1460
1461/* Clock definitions */
1462static struct clk tegra_clk_32k = {
1463 .name = "clk_32k",
1464 .rate = 32768,
1465 .ops = NULL,
1466 .max_rate = 32768,
1467};
1468
1469static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1470 {32768, 12000000, 366, 1, 1, 0},
1471 {32768, 13000000, 397, 1, 1, 0},
1472 {32768, 19200000, 586, 1, 1, 0},
1473 {32768, 26000000, 793, 1, 1, 0},
1474 {0, 0, 0, 0, 0, 0},
1475};
1476
1477static struct clk tegra_pll_s = {
1478 .name = "pll_s",
1479 .flags = PLL_ALT_MISC_REG,
1480 .ops = &tegra_pll_ops,
1481 .parent = &tegra_clk_32k,
1482 .max_rate = 26000000,
1483 .reg = 0xf0,
1484 .u.pll = {
1485 .input_min = 32768,
1486 .input_max = 32768,
1487 .cf_min = 0, /* FIXME */
1488 .cf_max = 0, /* FIXME */
1489 .vco_min = 12000000,
1490 .vco_max = 26000000,
1491 .freq_table = tegra_pll_s_freq_table,
1492 .lock_delay = 300,
1493 },
1494};
1495
1496static struct clk_mux_sel tegra_clk_m_sel[] = {
1497 { .input = &tegra_clk_32k, .value = 0},
1498 { .input = &tegra_pll_s, .value = 1},
1499 { NULL , 0},
1500};
1501
1502static struct clk tegra_clk_m = {
1503 .name = "clk_m",
1504 .flags = ENABLE_ON_INIT,
1505 .ops = &tegra_clk_m_ops,
1506 .inputs = tegra_clk_m_sel,
1507 .reg = 0x1fc,
1508 .reg_shift = 28,
1509 .max_rate = 26000000,
1510};
1511
1512static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1513 { 12000000, 600000000, 600, 12, 1, 8 },
1514 { 13000000, 600000000, 600, 13, 1, 8 },
1515 { 19200000, 600000000, 500, 16, 1, 6 },
1516 { 26000000, 600000000, 600, 26, 1, 8 },
1517 { 0, 0, 0, 0, 0, 0 },
1518};
1519
1520static struct clk tegra_pll_c = {
1521 .name = "pll_c",
1522 .flags = PLL_HAS_CPCON,
1523 .ops = &tegra_pll_ops,
1524 .reg = 0x80,
1525 .parent = &tegra_clk_m,
1526 .max_rate = 600000000,
1527 .u.pll = {
1528 .input_min = 2000000,
1529 .input_max = 31000000,
1530 .cf_min = 1000000,
1531 .cf_max = 6000000,
1532 .vco_min = 20000000,
1533 .vco_max = 1400000000,
1534 .freq_table = tegra_pll_c_freq_table,
1535 .lock_delay = 300,
1536 },
1537};
1538
1539static struct clk tegra_pll_c_out1 = {
1540 .name = "pll_c_out1",
1541 .ops = &tegra_pll_div_ops,
1542 .flags = DIV_U71,
1543 .parent = &tegra_pll_c,
1544 .reg = 0x84,
1545 .reg_shift = 0,
1546 .max_rate = 600000000,
1547};
1548
1549static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1550 { 12000000, 666000000, 666, 12, 1, 8},
1551 { 13000000, 666000000, 666, 13, 1, 8},
1552 { 19200000, 666000000, 555, 16, 1, 8},
1553 { 26000000, 666000000, 666, 26, 1, 8},
1554 { 12000000, 600000000, 600, 12, 1, 8},
1555 { 13000000, 600000000, 600, 13, 1, 8},
1556 { 19200000, 600000000, 375, 12, 1, 6},
1557 { 26000000, 600000000, 600, 26, 1, 8},
1558 { 0, 0, 0, 0, 0, 0 },
1559};
1560
1561static struct clk tegra_pll_m = {
1562 .name = "pll_m",
1563 .flags = PLL_HAS_CPCON,
1564 .ops = &tegra_pll_ops,
1565 .reg = 0x90,
1566 .parent = &tegra_clk_m,
1567 .max_rate = 800000000,
1568 .u.pll = {
1569 .input_min = 2000000,
1570 .input_max = 31000000,
1571 .cf_min = 1000000,
1572 .cf_max = 6000000,
1573 .vco_min = 20000000,
1574 .vco_max = 1200000000,
1575 .freq_table = tegra_pll_m_freq_table,
1576 .lock_delay = 300,
1577 },
1578};
1579
1580static struct clk tegra_pll_m_out1 = {
1581 .name = "pll_m_out1",
1582 .ops = &tegra_pll_div_ops,
1583 .flags = DIV_U71,
1584 .parent = &tegra_pll_m,
1585 .reg = 0x94,
1586 .reg_shift = 0,
1587 .max_rate = 600000000,
1588};
1589
1590static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1591 { 12000000, 216000000, 432, 12, 2, 8},
1592 { 13000000, 216000000, 432, 13, 2, 8},
1593 { 19200000, 216000000, 90, 4, 2, 1},
1594 { 26000000, 216000000, 432, 26, 2, 8},
1595 { 12000000, 432000000, 432, 12, 1, 8},
1596 { 13000000, 432000000, 432, 13, 1, 8},
1597 { 19200000, 432000000, 90, 4, 1, 1},
1598 { 26000000, 432000000, 432, 26, 1, 8},
1599 { 0, 0, 0, 0, 0, 0 },
1600};
1601
1602static struct clk tegra_pll_p = {
1603 .name = "pll_p",
1604 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1605 .ops = &tegra_pll_ops,
1606 .reg = 0xa0,
1607 .parent = &tegra_clk_m,
1608 .max_rate = 432000000,
1609 .u.pll = {
1610 .input_min = 2000000,
1611 .input_max = 31000000,
1612 .cf_min = 1000000,
1613 .cf_max = 6000000,
1614 .vco_min = 20000000,
1615 .vco_max = 1400000000,
1616 .freq_table = tegra_pll_p_freq_table,
1617 .lock_delay = 300,
1618 },
1619};
1620
1621static struct clk tegra_pll_p_out1 = {
1622 .name = "pll_p_out1",
1623 .ops = &tegra_pll_div_ops,
1624 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1625 .parent = &tegra_pll_p,
1626 .reg = 0xa4,
1627 .reg_shift = 0,
1628 .max_rate = 432000000,
1629};
1630
1631static struct clk tegra_pll_p_out2 = {
1632 .name = "pll_p_out2",
1633 .ops = &tegra_pll_div_ops,
1634 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1635 .parent = &tegra_pll_p,
1636 .reg = 0xa4,
1637 .reg_shift = 16,
1638 .max_rate = 432000000,
1639};
1640
1641static struct clk tegra_pll_p_out3 = {
1642 .name = "pll_p_out3",
1643 .ops = &tegra_pll_div_ops,
1644 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1645 .parent = &tegra_pll_p,
1646 .reg = 0xa8,
1647 .reg_shift = 0,
1648 .max_rate = 432000000,
1649};
1650
1651static struct clk tegra_pll_p_out4 = {
1652 .name = "pll_p_out4",
1653 .ops = &tegra_pll_div_ops,
1654 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1655 .parent = &tegra_pll_p,
1656 .reg = 0xa8,
1657 .reg_shift = 16,
1658 .max_rate = 432000000,
1659};
1660
1661static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1662 { 28800000, 56448000, 49, 25, 1, 1},
1663 { 28800000, 73728000, 64, 25, 1, 1},
1664 { 28800000, 24000000, 5, 6, 1, 1},
1665 { 0, 0, 0, 0, 0, 0 },
1666};
1667
1668static struct clk tegra_pll_a = {
1669 .name = "pll_a",
1670 .flags = PLL_HAS_CPCON,
1671 .ops = &tegra_pll_ops,
1672 .reg = 0xb0,
1673 .parent = &tegra_pll_p_out1,
1674 .max_rate = 73728000,
1675 .u.pll = {
1676 .input_min = 2000000,
1677 .input_max = 31000000,
1678 .cf_min = 1000000,
1679 .cf_max = 6000000,
1680 .vco_min = 20000000,
1681 .vco_max = 1400000000,
1682 .freq_table = tegra_pll_a_freq_table,
1683 .lock_delay = 300,
1684 },
1685};
1686
1687static struct clk tegra_pll_a_out0 = {
1688 .name = "pll_a_out0",
1689 .ops = &tegra_pll_div_ops,
1690 .flags = DIV_U71,
1691 .parent = &tegra_pll_a,
1692 .reg = 0xb4,
1693 .reg_shift = 0,
1694 .max_rate = 73728000,
1695};
1696
1697static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1698 { 12000000, 216000000, 216, 12, 1, 4},
1699 { 13000000, 216000000, 216, 13, 1, 4},
1700 { 19200000, 216000000, 135, 12, 1, 3},
1701 { 26000000, 216000000, 216, 26, 1, 4},
1702
1703 { 12000000, 594000000, 594, 12, 1, 8},
1704 { 13000000, 594000000, 594, 13, 1, 8},
1705 { 19200000, 594000000, 495, 16, 1, 8},
1706 { 26000000, 594000000, 594, 26, 1, 8},
1707
1708 { 12000000, 1000000000, 1000, 12, 1, 12},
1709 { 13000000, 1000000000, 1000, 13, 1, 12},
1710 { 19200000, 1000000000, 625, 12, 1, 8},
1711 { 26000000, 1000000000, 1000, 26, 1, 12},
1712
1713 { 0, 0, 0, 0, 0, 0 },
1714};
1715
1716static struct clk tegra_pll_d = {
1717 .name = "pll_d",
1718 .flags = PLL_HAS_CPCON | PLLD,
1719 .ops = &tegra_pll_ops,
1720 .reg = 0xd0,
1721 .parent = &tegra_clk_m,
1722 .max_rate = 1000000000,
1723 .u.pll = {
1724 .input_min = 2000000,
1725 .input_max = 40000000,
1726 .cf_min = 1000000,
1727 .cf_max = 6000000,
1728 .vco_min = 40000000,
1729 .vco_max = 1000000000,
1730 .freq_table = tegra_pll_d_freq_table,
1731 .lock_delay = 1000,
1732 },
1733};
1734
1735static struct clk tegra_pll_d_out0 = {
1736 .name = "pll_d_out0",
1737 .ops = &tegra_pll_div_ops,
1738 .flags = DIV_2 | PLLD,
1739 .parent = &tegra_pll_d,
1740 .max_rate = 500000000,
1741};
1742
1743static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1744 { 12000000, 480000000, 960, 12, 2, 0},
1745 { 13000000, 480000000, 960, 13, 2, 0},
1746 { 19200000, 480000000, 200, 4, 2, 0},
1747 { 26000000, 480000000, 960, 26, 2, 0},
1748 { 0, 0, 0, 0, 0, 0 },
1749};
1750
1751static struct clk tegra_pll_u = {
1752 .name = "pll_u",
1753 .flags = PLLU,
1754 .ops = &tegra_pll_ops,
1755 .reg = 0xc0,
1756 .parent = &tegra_clk_m,
1757 .max_rate = 480000000,
1758 .u.pll = {
1759 .input_min = 2000000,
1760 .input_max = 40000000,
1761 .cf_min = 1000000,
1762 .cf_max = 6000000,
1763 .vco_min = 480000000,
1764 .vco_max = 960000000,
1765 .freq_table = tegra_pll_u_freq_table,
1766 .lock_delay = 1000,
1767 },
1768};
1769
1770static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1771 /* 1 GHz */
1772 { 12000000, 1000000000, 1000, 12, 1, 12},
1773 { 13000000, 1000000000, 1000, 13, 1, 12},
1774 { 19200000, 1000000000, 625, 12, 1, 8},
1775 { 26000000, 1000000000, 1000, 26, 1, 12},
1776
1777 /* 912 MHz */
1778 { 12000000, 912000000, 912, 12, 1, 12},
1779 { 13000000, 912000000, 912, 13, 1, 12},
1780 { 19200000, 912000000, 760, 16, 1, 8},
1781 { 26000000, 912000000, 912, 26, 1, 12},
1782
1783 /* 816 MHz */
1784 { 12000000, 816000000, 816, 12, 1, 12},
1785 { 13000000, 816000000, 816, 13, 1, 12},
1786 { 19200000, 816000000, 680, 16, 1, 8},
1787 { 26000000, 816000000, 816, 26, 1, 12},
1788
1789 /* 760 MHz */
1790 { 12000000, 760000000, 760, 12, 1, 12},
1791 { 13000000, 760000000, 760, 13, 1, 12},
1792 { 19200000, 760000000, 950, 24, 1, 8},
1793 { 26000000, 760000000, 760, 26, 1, 12},
1794
1795 /* 750 MHz */
1796 { 12000000, 750000000, 750, 12, 1, 12},
1797 { 13000000, 750000000, 750, 13, 1, 12},
1798 { 19200000, 750000000, 625, 16, 1, 8},
1799 { 26000000, 750000000, 750, 26, 1, 12},
1800
1801 /* 608 MHz */
1802 { 12000000, 608000000, 608, 12, 1, 12},
1803 { 13000000, 608000000, 608, 13, 1, 12},
1804 { 19200000, 608000000, 380, 12, 1, 8},
1805 { 26000000, 608000000, 608, 26, 1, 12},
1806
1807 /* 456 MHz */
1808 { 12000000, 456000000, 456, 12, 1, 12},
1809 { 13000000, 456000000, 456, 13, 1, 12},
1810 { 19200000, 456000000, 380, 16, 1, 8},
1811 { 26000000, 456000000, 456, 26, 1, 12},
1812
1813 /* 312 MHz */
1814 { 12000000, 312000000, 312, 12, 1, 12},
1815 { 13000000, 312000000, 312, 13, 1, 12},
1816 { 19200000, 312000000, 260, 16, 1, 8},
1817 { 26000000, 312000000, 312, 26, 1, 12},
1818
1819 { 0, 0, 0, 0, 0, 0 },
1820};
1821
1822static struct clk tegra_pll_x = {
1823 .name = "pll_x",
1824 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1825 .ops = &tegra_pllx_ops,
1826 .reg = 0xe0,
1827 .parent = &tegra_clk_m,
1828 .max_rate = 1000000000,
1829 .u.pll = {
1830 .input_min = 2000000,
1831 .input_max = 31000000,
1832 .cf_min = 1000000,
1833 .cf_max = 6000000,
1834 .vco_min = 20000000,
1835 .vco_max = 1200000000,
1836 .freq_table = tegra_pll_x_freq_table,
1837 .lock_delay = 300,
1838 },
1839};
1840
1841static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1842 { 12000000, 100000000, 200, 24, 1, 0 },
1843 { 0, 0, 0, 0, 0, 0 },
1844};
1845
1846static struct clk tegra_pll_e = {
1847 .name = "pll_e",
1848 .flags = PLL_ALT_MISC_REG,
1849 .ops = &tegra_plle_ops,
1850 .parent = &tegra_clk_m,
1851 .reg = 0xe8,
1852 .max_rate = 100000000,
1853 .u.pll = {
1854 .input_min = 12000000,
1855 .input_max = 12000000,
1856 .freq_table = tegra_pll_e_freq_table,
1857 },
1858};
1859
1860static struct clk tegra_clk_d = {
1861 .name = "clk_d",
1862 .flags = PERIPH_NO_RESET,
1863 .ops = &tegra_clk_double_ops,
1864 .reg = 0x34,
1865 .reg_shift = 12,
1866 .parent = &tegra_clk_m,
1867 .max_rate = 52000000,
1868 .u.periph = {
1869 .clk_num = 90,
1870 },
1871};
1872
1873/* dap_mclk1, belongs to the cdev1 pingroup. */
1874static struct clk tegra_clk_cdev1 = {
1875 .name = "cdev1",
1876 .ops = &tegra_cdev_clk_ops,
1877 .rate = 26000000,
1878 .max_rate = 26000000,
1879 .u.periph = {
1880 .clk_num = 94,
1881 },
1882};
1883
1884/* dap_mclk2, belongs to the cdev2 pingroup. */
1885static struct clk tegra_clk_cdev2 = {
1886 .name = "cdev2",
1887 .ops = &tegra_cdev_clk_ops,
1888 .rate = 26000000,
1889 .max_rate = 26000000,
1890 .u.periph = {
1891 .clk_num = 93,
1892 },
1893};
1894
1895/* initialized before peripheral clocks */
1896static struct clk_mux_sel mux_audio_sync_clk[8+1];
1897static const struct audio_sources {
1898 const char *name;
1899 int value;
1900} mux_audio_sync_clk_sources[] = {
1901 { .name = "spdif_in", .value = 0 },
1902 { .name = "i2s1", .value = 1 },
1903 { .name = "i2s2", .value = 2 },
1904 { .name = "pll_a_out0", .value = 4 },
1905#if 0 /* FIXME: not implemented */
1906 { .name = "ac97", .value = 3 },
1907 { .name = "ext_audio_clk2", .value = 5 },
1908 { .name = "ext_audio_clk1", .value = 6 },
1909 { .name = "ext_vimclk", .value = 7 },
1910#endif
1911 { NULL, 0 }
1912};
1913
1914static struct clk tegra_clk_audio = {
1915 .name = "audio",
1916 .inputs = mux_audio_sync_clk,
1917 .reg = 0x38,
1918 .max_rate = 73728000,
1919 .ops = &tegra_audio_sync_clk_ops
1920};
1921
1922static struct clk tegra_clk_audio_2x = {
1923 .name = "audio_2x",
1924 .flags = PERIPH_NO_RESET,
1925 .max_rate = 48000000,
1926 .ops = &tegra_clk_double_ops,
1927 .reg = 0x34,
1928 .reg_shift = 8,
1929 .parent = &tegra_clk_audio,
1930 .u.periph = {
1931 .clk_num = 89,
1932 },
1933};
1934
1935static struct clk_lookup tegra_audio_clk_lookups[] = {
1936 { .con_id = "audio", .clk = &tegra_clk_audio },
1937 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1938};
1939
1940/* This is called after peripheral clocks are initialized, as the
1941 * audio_sync clock depends on some of the peripheral clocks.
1942 */
1943
1944static void init_audio_sync_clock_mux(void)
1945{
1946 int i;
1947 struct clk_mux_sel *sel = mux_audio_sync_clk;
1948 const struct audio_sources *src = mux_audio_sync_clk_sources;
1949 struct clk_lookup *lookup;
1950
1951 for (i = 0; src->name; i++, sel++, src++) {
1952 sel->input = tegra_get_clock_by_name(src->name);
1953 if (!sel->input)
1954 pr_err("%s: could not find clk %s\n", __func__,
1955 src->name);
1956 sel->value = src->value;
1957 }
1958
1959 lookup = tegra_audio_clk_lookups;
1960 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1961 clk_init(lookup->clk);
1962 clkdev_add(lookup);
1963 }
1964}
1965
1966static struct clk_mux_sel mux_cclk[] = {
1967 { .input = &tegra_clk_m, .value = 0},
1968 { .input = &tegra_pll_c, .value = 1},
1969 { .input = &tegra_clk_32k, .value = 2},
1970 { .input = &tegra_pll_m, .value = 3},
1971 { .input = &tegra_pll_p, .value = 4},
1972 { .input = &tegra_pll_p_out4, .value = 5},
1973 { .input = &tegra_pll_p_out3, .value = 6},
1974 { .input = &tegra_clk_d, .value = 7},
1975 { .input = &tegra_pll_x, .value = 8},
1976 { NULL, 0},
1977};
1978
1979static struct clk_mux_sel mux_sclk[] = {
1980 { .input = &tegra_clk_m, .value = 0},
1981 { .input = &tegra_pll_c_out1, .value = 1},
1982 { .input = &tegra_pll_p_out4, .value = 2},
1983 { .input = &tegra_pll_p_out3, .value = 3},
1984 { .input = &tegra_pll_p_out2, .value = 4},
1985 { .input = &tegra_clk_d, .value = 5},
1986 { .input = &tegra_clk_32k, .value = 6},
1987 { .input = &tegra_pll_m_out1, .value = 7},
1988 { NULL, 0},
1989};
1990
1991static struct clk tegra_clk_cclk = {
1992 .name = "cclk",
1993 .inputs = mux_cclk,
1994 .reg = 0x20,
1995 .ops = &tegra_super_ops,
1996 .max_rate = 1000000000,
1997};
1998
1999static struct clk tegra_clk_sclk = {
2000 .name = "sclk",
2001 .inputs = mux_sclk,
2002 .reg = 0x28,
2003 .ops = &tegra_super_ops,
2004 .max_rate = 240000000,
2005 .min_rate = 120000000,
2006};
2007
2008static struct clk tegra_clk_virtual_cpu = {
2009 .name = "cpu",
2010 .parent = &tegra_clk_cclk,
2011 .ops = &tegra_cpu_ops,
2012 .max_rate = 1000000000,
2013 .u.cpu = {
2014 .main = &tegra_pll_x,
2015 .backup = &tegra_pll_p,
2016 },
2017};
2018
2019static struct clk tegra_clk_cop = {
2020 .name = "cop",
2021 .parent = &tegra_clk_sclk,
2022 .ops = &tegra_cop_ops,
2023 .max_rate = 240000000,
2024};
2025
2026static struct clk tegra_clk_hclk = {
2027 .name = "hclk",
2028 .flags = DIV_BUS,
2029 .parent = &tegra_clk_sclk,
2030 .reg = 0x30,
2031 .reg_shift = 4,
2032 .ops = &tegra_bus_ops,
2033 .max_rate = 240000000,
2034};
2035
2036static struct clk tegra_clk_pclk = {
2037 .name = "pclk",
2038 .flags = DIV_BUS,
2039 .parent = &tegra_clk_hclk,
2040 .reg = 0x30,
2041 .reg_shift = 0,
2042 .ops = &tegra_bus_ops,
2043 .max_rate = 120000000,
2044};
2045
2046static struct clk tegra_clk_blink = {
2047 .name = "blink",
2048 .parent = &tegra_clk_32k,
2049 .reg = 0x40,
2050 .ops = &tegra_blink_clk_ops,
2051 .max_rate = 32768,
2052};
2053
2054static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2055 { .input = &tegra_pll_m, .value = 0},
2056 { .input = &tegra_pll_c, .value = 1},
2057 { .input = &tegra_pll_p, .value = 2},
2058 { .input = &tegra_pll_a_out0, .value = 3},
2059 { NULL, 0},
2060};
2061
2062static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2063 { .input = &tegra_pll_m, .value = 0},
2064 { .input = &tegra_pll_c, .value = 1},
2065 { .input = &tegra_pll_p, .value = 2},
2066 { .input = &tegra_clk_m, .value = 3},
2067 { NULL, 0},
2068};
2069
2070static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2071 { .input = &tegra_pll_p, .value = 0},
2072 { .input = &tegra_pll_c, .value = 1},
2073 { .input = &tegra_pll_m, .value = 2},
2074 { .input = &tegra_clk_m, .value = 3},
2075 { NULL, 0},
2076};
2077
2078static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2079 {.input = &tegra_pll_a_out0, .value = 0},
2080 {.input = &tegra_clk_audio_2x, .value = 1},
2081 {.input = &tegra_pll_p, .value = 2},
2082 {.input = &tegra_clk_m, .value = 3},
2083 { NULL, 0},
2084};
2085
2086static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2087 {.input = &tegra_pll_p, .value = 0},
2088 {.input = &tegra_pll_d_out0, .value = 1},
2089 {.input = &tegra_pll_c, .value = 2},
2090 {.input = &tegra_clk_m, .value = 3},
2091 { NULL, 0},
2092};
2093
2094static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2095 {.input = &tegra_pll_p, .value = 0},
2096 {.input = &tegra_pll_c, .value = 1},
2097 {.input = &tegra_clk_audio, .value = 2},
2098 {.input = &tegra_clk_m, .value = 3},
2099 {.input = &tegra_clk_32k, .value = 4},
2100 { NULL, 0},
2101};
2102
2103static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2104 {.input = &tegra_pll_p, .value = 0},
2105 {.input = &tegra_pll_c, .value = 1},
2106 {.input = &tegra_pll_m, .value = 2},
2107 { NULL, 0},
2108};
2109
2110static struct clk_mux_sel mux_clk_m[] = {
2111 { .input = &tegra_clk_m, .value = 0},
2112 { NULL, 0},
2113};
2114
2115static struct clk_mux_sel mux_pllp_out3[] = {
2116 { .input = &tegra_pll_p_out3, .value = 0},
2117 { NULL, 0},
2118};
2119
2120static struct clk_mux_sel mux_plld[] = {
2121 { .input = &tegra_pll_d, .value = 0},
2122 { NULL, 0},
2123};
2124
2125static struct clk_mux_sel mux_clk_32k[] = {
2126 { .input = &tegra_clk_32k, .value = 0},
2127 { NULL, 0},
2128};
2129
2130static struct clk_mux_sel mux_pclk[] = {
2131 { .input = &tegra_clk_pclk, .value = 0},
2132 { NULL, 0},
2133};
2134
2135static struct clk tegra_clk_emc = {
2136 .name = "emc",
2137 .ops = &tegra_emc_clk_ops,
2138 .reg = 0x19c,
2139 .max_rate = 800000000,
2140 .inputs = mux_pllm_pllc_pllp_clkm,
2141 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2142 .u.periph = {
2143 .clk_num = 57,
2144 },
2145};
2146
2147#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2148 { \
2149 .name = _name, \
2150 .lookup = { \
2151 .dev_id = _dev, \
2152 .con_id = _con, \
2153 }, \
2154 .ops = &tegra_periph_clk_ops, \
2155 .reg = _reg, \
2156 .inputs = _inputs, \
2157 .flags = _flags, \
2158 .max_rate = _max, \
2159 .u.periph = { \
2160 .clk_num = _clk_num, \
2161 }, \
2162 }
2163
2164#define SHARED_CLK(_name, _dev, _con, _parent) \
2165 { \
2166 .name = _name, \
2167 .lookup = { \
2168 .dev_id = _dev, \
2169 .con_id = _con, \
2170 }, \
2171 .ops = &tegra_clk_shared_bus_ops, \
2172 .parent = _parent, \
2173 }
2174
2175static struct clk tegra_list_clks[] = {
2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2187 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2188 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2189 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2190 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2191 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2192 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2193 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2194 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2195 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2196 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2197 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2198 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2199 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2200 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2201 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2202 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2203 /* FIXME: what is la? */
2204 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2205 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2206 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2207 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2208 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2209 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2210 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2211 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2212 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2224 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2225 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2226 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2227 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2228 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2229 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2230 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2231 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2232 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2233 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2234 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2235 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2236 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2237 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2238 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2239 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2240 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2241 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2242 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2243 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2244
2245 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2246 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2247 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2248 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2249 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2250 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2251 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2252 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2253 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2254 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2255 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2256};
2257
2258#define CLK_DUPLICATE(_name, _dev, _con) \
2259 { \
2260 .name = _name, \
2261 .lookup = { \
2262 .dev_id = _dev, \
2263 .con_id = _con, \
2264 }, \
2265 }
2266
2267/* Some clocks may be used by different drivers depending on the board
2268 * configuration. List those here to register them twice in the clock lookup
2269 * table under two names.
2270 */
2271static struct clk_duplicate tegra_clk_duplicates[] = {
2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2285 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2286 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2287 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2288 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2289};
2290
2291#define CLK(dev, con, ck) \
2292 { \
2293 .dev_id = dev, \
2294 .con_id = con, \
2295 .clk = ck, \
2296 }
2297
2298static struct clk *tegra_ptr_clks[] = {
2299 &tegra_clk_32k,
2300 &tegra_pll_s,
2301 &tegra_clk_m,
2302 &tegra_pll_m,
2303 &tegra_pll_m_out1,
2304 &tegra_pll_c,
2305 &tegra_pll_c_out1,
2306 &tegra_pll_p,
2307 &tegra_pll_p_out1,
2308 &tegra_pll_p_out2,
2309 &tegra_pll_p_out3,
2310 &tegra_pll_p_out4,
2311 &tegra_pll_a,
2312 &tegra_pll_a_out0,
2313 &tegra_pll_d,
2314 &tegra_pll_d_out0,
2315 &tegra_pll_u,
2316 &tegra_pll_x,
2317 &tegra_pll_e,
2318 &tegra_clk_cclk,
2319 &tegra_clk_sclk,
2320 &tegra_clk_hclk,
2321 &tegra_clk_pclk,
2322 &tegra_clk_d,
2323 &tegra_clk_cdev1,
2324 &tegra_clk_cdev2,
2325 &tegra_clk_virtual_cpu,
2326 &tegra_clk_blink,
2327 &tegra_clk_cop,
2328 &tegra_clk_emc,
2329};
2330
2331static void tegra2_init_one_clock(struct clk *c)
2332{
2333 clk_init(c);
2334 INIT_LIST_HEAD(&c->shared_bus_list);
2335 if (!c->lookup.dev_id && !c->lookup.con_id)
2336 c->lookup.con_id = c->name;
2337 c->lookup.clk = c;
2338 clkdev_add(&c->lookup);
2339}
2340
2341void __init tegra2_init_clocks(void)
2342{
2343 int i;
2344 struct clk *c;
2345
2346 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2347 tegra2_init_one_clock(tegra_ptr_clks[i]);
2348
2349 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2350 tegra2_init_one_clock(&tegra_list_clks[i]);
2351
2352 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2353 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2354 if (!c) {
2355 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2356 tegra_clk_duplicates[i].name);
2357 continue;
2358 }
2359
2360 tegra_clk_duplicates[i].lookup.clk = c;
2361 clkdev_add(&tegra_clk_duplicates[i].lookup);
2362 }
2363
2364 init_audio_sync_clock_mux();
2365}
2366
2367#ifdef CONFIG_PM
2368static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2369 PERIPH_CLK_SOURCE_NUM + 22];
2370
2371void tegra_clk_suspend(void)
2372{
2373 unsigned long off, i;
2374 u32 *ctx = clk_rst_suspend;
2375
2376 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2377 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2378 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2379 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2380 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2381 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2382 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2383 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2384 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2385 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2386 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2387
2388 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2389 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2390 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2391
2392 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2393 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2394
2395 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2396 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2397 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2398
2399 *ctx++ = clk_readl(tegra_clk_audio.reg);
2400
2401 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2402 off += 4) {
2403 if (off == PERIPH_CLK_SOURCE_EMC)
2404 continue;
2405 *ctx++ = clk_readl(off);
2406 }
2407
2408 off = RST_DEVICES;
2409 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2410 *ctx++ = clk_readl(off);
2411
2412 off = CLK_OUT_ENB;
2413 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2414 *ctx++ = clk_readl(off);
2415
2416 *ctx++ = clk_readl(MISC_CLK_ENB);
2417 *ctx++ = clk_readl(CLK_MASK_ARM);
2418
2419 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2420}
2421
2422void tegra_clk_resume(void)
2423{
2424 unsigned long off, i;
2425 const u32 *ctx = clk_rst_suspend;
2426 u32 val;
2427
2428 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2429 val |= *ctx++;
2430 clk_writel(val, OSC_CTRL);
2431
2432 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2433 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2434 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2435 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2436 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2437 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2438 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2439 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2440 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2441 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2442 udelay(1000);
2443
2444 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2445 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2446 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2447
2448 clk_writel(*ctx++, tegra_clk_cclk.reg);
2449 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2450
2451 clk_writel(*ctx++, tegra_clk_sclk.reg);
2452 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2453 clk_writel(*ctx++, tegra_clk_pclk.reg);
2454
2455 clk_writel(*ctx++, tegra_clk_audio.reg);
2456
2457 /* enable all clocks before configuring clock sources */
2458 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2459 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2460 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2461 wmb();
2462
2463 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2464 off += 4) {
2465 if (off == PERIPH_CLK_SOURCE_EMC)
2466 continue;
2467 clk_writel(*ctx++, off);
2468 }
2469 wmb();
2470
2471 off = RST_DEVICES;
2472 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2473 clk_writel(*ctx++, off);
2474 wmb();
2475
2476 off = CLK_OUT_ENB;
2477 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2478 clk_writel(*ctx++, off);
2479 wmb();
2480
2481 clk_writel(*ctx++, MISC_CLK_ENB);
2482 clk_writel(*ctx++, CLK_MASK_ARM);
2483}
2484#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..63615dadfbb2 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c 2 * arch/arm/mach-tegra/tegra30_clocks.c
3 * 3 *
4 * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -365,30 +365,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
365static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; 365static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
366 366
367#define clk_writel(value, reg) \ 367#define clk_writel(value, reg) \
368 __raw_writel(value, (u32)reg_clk_base + (reg)) 368 __raw_writel(value, reg_clk_base + (reg))
369#define clk_readl(reg) \ 369#define clk_readl(reg) \
370 __raw_readl((u32)reg_clk_base + (reg)) 370 __raw_readl(reg_clk_base + (reg))
371#define pmc_writel(value, reg) \ 371#define pmc_writel(value, reg) \
372 __raw_writel(value, (u32)reg_pmc_base + (reg)) 372 __raw_writel(value, reg_pmc_base + (reg))
373#define pmc_readl(reg) \ 373#define pmc_readl(reg) \
374 __raw_readl((u32)reg_pmc_base + (reg)) 374 __raw_readl(reg_pmc_base + (reg))
375#define chipid_readl() \ 375#define chipid_readl() \
376 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) 376 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
377 377
378#define clk_writel_delay(value, reg) \ 378#define clk_writel_delay(value, reg) \
379 do { \ 379 do { \
380 __raw_writel((value), (u32)reg_clk_base + (reg)); \ 380 __raw_writel((value), reg_clk_base + (reg)); \
381 udelay(2); \ 381 udelay(2); \
382 } while (0) 382 } while (0)
383 383
384 384static inline int clk_set_div(struct clk_tegra *c, u32 n)
385static inline int clk_set_div(struct clk *c, u32 n)
386{ 385{
387 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); 386 struct clk *clk = c->hw.clk;
387
388 return clk_set_rate(clk,
389 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
388} 390}
389 391
390static inline u32 periph_clk_to_reg( 392static inline u32 periph_clk_to_reg(
391 struct clk *c, u32 reg_L, u32 reg_V, int offs) 393 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
392{ 394{
393 u32 reg = c->u.periph.clk_num / 32; 395 u32 reg = c->u.periph.clk_num / 32;
394 BUG_ON(reg >= RST_DEVICES_NUM); 396 BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +472,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
470 return divider_u16 - 1; 472 return divider_u16 - 1;
471} 473}
472 474
475static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
476 unsigned long parent_rate)
477{
478 return to_clk_tegra(hw)->fixed_rate;
479}
480
481struct clk_ops tegra30_clk_32k_ops = {
482 .recalc_rate = tegra30_clk_fixed_recalc_rate,
483};
484
473/* clk_m functions */ 485/* clk_m functions */
474static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c) 486static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
487 unsigned long parent_rate)
488{
489 if (!to_clk_tegra(hw)->fixed_rate)
490 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
491 return to_clk_tegra(hw)->fixed_rate;
492}
493
494static void tegra30_clk_m_init(struct clk_hw *hw)
475{ 495{
476 u32 osc_ctrl = clk_readl(OSC_CTRL); 496 u32 osc_ctrl = clk_readl(OSC_CTRL);
477 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; 497 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
478 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 498 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
479 499
480 c->rate = clk_measure_input_freq(); 500 switch (to_clk_tegra(hw)->fixed_rate) {
481 switch (c->rate) {
482 case 12000000: 501 case 12000000:
483 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; 502 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
484 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 503 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +527,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
508 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 527 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
509 break; 528 break;
510 default: 529 default:
511 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); 530 pr_err("%s: Unexpected clock rate %ld", __func__,
531 to_clk_tegra(hw)->fixed_rate);
512 BUG(); 532 BUG();
513 } 533 }
514 clk_writel(auto_clock_control, OSC_CTRL); 534 clk_writel(auto_clock_control, OSC_CTRL);
515 return c->rate;
516} 535}
517 536
518static void tegra30_clk_m_init(struct clk *c) 537struct clk_ops tegra30_clk_m_ops = {
519{ 538 .init = tegra30_clk_m_init,
520 pr_debug("%s on clock %s\n", __func__, c->name); 539 .recalc_rate = tegra30_clk_m_recalc_rate,
521 tegra30_clk_m_autodetect_rate(c); 540};
522}
523 541
524static int tegra30_clk_m_enable(struct clk *c) 542static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
543 unsigned long parent_rate)
525{ 544{
526 pr_debug("%s on clock %s\n", __func__, c->name); 545 struct clk_tegra *c = to_clk_tegra(hw);
527 return 0; 546 u64 rate = parent_rate;
528}
529 547
530static void tegra30_clk_m_disable(struct clk *c) 548 if (c->mul != 0 && c->div != 0) {
531{ 549 rate *= c->mul;
532 pr_debug("%s on clock %s\n", __func__, c->name); 550 rate += c->div - 1; /* round up */
533 WARN(1, "Attempting to disable main SoC clock\n"); 551 do_div(rate, c->div);
534} 552 }
535 553
536static struct clk_ops tegra_clk_m_ops = { 554 return rate;
537 .init = tegra30_clk_m_init, 555}
538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable,
540};
541 556
542static struct clk_ops tegra_clk_m_div_ops = { 557struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable, 558 .recalc_rate = tegra30_clk_m_div_recalc_rate,
544}; 559};
545 560
546/* PLL reference divider functions */ 561/* PLL reference divider functions */
547static void tegra30_pll_ref_init(struct clk *c) 562static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
563 unsigned long parent_rate)
548{ 564{
565 struct clk_tegra *c = to_clk_tegra(hw);
566 unsigned long rate = parent_rate;
549 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; 567 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
550 pr_debug("%s on clock %s\n", __func__, c->name);
551 568
552 switch (pll_ref_div) { 569 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1: 570 case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +581,18 @@ static void tegra30_pll_ref_init(struct clk *c)
564 BUG(); 581 BUG();
565 } 582 }
566 c->mul = 1; 583 c->mul = 1;
567 c->state = ON; 584
585 if (c->mul != 0 && c->div != 0) {
586 rate *= c->mul;
587 rate += c->div - 1; /* round up */
588 do_div(rate, c->div);
589 }
590
591 return rate;
568} 592}
569 593
570static struct clk_ops tegra_pll_ref_ops = { 594struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init, 595 .recalc_rate = tegra30_pll_ref_recalc_rate,
572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable,
574}; 596};
575 597
576/* super clock functions */ 598/* super clock functions */
@@ -581,56 +603,50 @@ static struct clk_ops tegra_pll_ref_ops = {
581 * only when its parent is a fixed rate PLL, since we can't change PLL rate 603 * only when its parent is a fixed rate PLL, since we can't change PLL rate
582 * in this case. 604 * in this case.
583 */ 605 */
584static void tegra30_super_clk_init(struct clk *c) 606static void tegra30_super_clk_init(struct clk_hw *hw)
585{ 607{
586 u32 val; 608 struct clk_tegra *c = to_clk_tegra(hw);
587 int source; 609 struct clk_tegra *p =
588 int shift; 610 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
589 const struct clk_mux_sel *sel;
590 val = clk_readl(c->reg + SUPER_CLK_MUX);
591 c->state = ON;
592 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
593 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
594 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
595 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
596 source = (val >> shift) & SUPER_SOURCE_MASK;
597 if (c->flags & DIV_2)
598 source |= val & SUPER_LP_DIV2_BYPASS;
599 for (sel = c->inputs; sel->input != NULL; sel++) {
600 if (sel->value == source)
601 break;
602 }
603 BUG_ON(sel->input == NULL);
604 c->parent = sel->input;
605 611
612 c->state = ON;
606 if (c->flags & DIV_U71) { 613 if (c->flags & DIV_U71) {
607 /* Init safe 7.1 divider value (does not affect PLLX path) */ 614 /* Init safe 7.1 divider value (does not affect PLLX path) */
608 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, 615 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
609 c->reg + SUPER_CLK_DIVIDER); 616 c->reg + SUPER_CLK_DIVIDER);
610 c->mul = 2; 617 c->mul = 2;
611 c->div = 2; 618 c->div = 2;
612 if (!(c->parent->flags & PLLX)) 619 if (!(p->flags & PLLX))
613 c->div += SUPER_CLOCK_DIV_U71_MIN; 620 c->div += SUPER_CLOCK_DIV_U71_MIN;
614 } else 621 } else
615 clk_writel(0, c->reg + SUPER_CLK_DIVIDER); 622 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
616} 623}
617 624
618static int tegra30_super_clk_enable(struct clk *c) 625static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
619{ 626{
620 return 0; 627 struct clk_tegra *c = to_clk_tegra(hw);
621} 628 u32 val;
629 int source;
630 int shift;
622 631
623static void tegra30_super_clk_disable(struct clk *c) 632 val = clk_readl(c->reg + SUPER_CLK_MUX);
624{ 633 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
625 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and 634 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
626 geared up g-mode super clock - mode switch may request to disable 635 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
627 either of them; accept request with no affect on h/w */ 636 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
637 source = (val >> shift) & SUPER_SOURCE_MASK;
638 if (c->flags & DIV_2)
639 source |= val & SUPER_LP_DIV2_BYPASS;
640
641 return source;
628} 642}
629 643
630static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p) 644static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
631{ 645{
646 struct clk_tegra *c = to_clk_tegra(hw);
647 struct clk_tegra *p =
648 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
632 u32 val; 649 u32 val;
633 const struct clk_mux_sel *sel;
634 int shift; 650 int shift;
635 651
636 val = clk_readl(c->reg + SUPER_CLK_MUX); 652 val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +654,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
638 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 654 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
639 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 655 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
640 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 656 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
641 for (sel = c->inputs; sel->input != NULL; sel++) {
642 if (sel->input == p) {
643 /* For LP mode super-clock switch between PLLX direct
644 and divided-by-2 outputs is allowed only when other
645 than PLLX clock source is current parent */
646 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
648 if (c->parent->flags & PLLX)
649 return -EINVAL;
650 val ^= SUPER_LP_DIV2_BYPASS;
651 clk_writel_delay(val, c->reg);
652 }
653 val &= ~(SUPER_SOURCE_MASK << shift);
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
655
656 /* 7.1 divider for CPU super-clock does not affect
657 PLLX path */
658 if (c->flags & DIV_U71) {
659 u32 div = 0;
660 if (!(p->flags & PLLX)) {
661 div = clk_readl(c->reg +
662 SUPER_CLK_DIVIDER);
663 div &= SUPER_CLOCK_DIV_U71_MASK;
664 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
665 }
666 c->div = div + 2;
667 c->mul = 2;
668 }
669 657
670 if (c->refcnt) 658 /* For LP mode super-clock switch between PLLX direct
671 clk_enable(p); 659 and divided-by-2 outputs is allowed only when other
672 660 than PLLX clock source is current parent */
673 clk_writel_delay(val, c->reg); 661 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
674 662 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
675 if (c->refcnt && c->parent) 663 if (p->flags & PLLX)
676 clk_disable(c->parent); 664 return -EINVAL;
665 val ^= SUPER_LP_DIV2_BYPASS;
666 clk_writel_delay(val, c->reg);
667 }
668 val &= ~(SUPER_SOURCE_MASK << shift);
669 val |= (index & SUPER_SOURCE_MASK) << shift;
677 670
678 clk_reparent(c, p); 671 /* 7.1 divider for CPU super-clock does not affect
679 return 0; 672 PLLX path */
673 if (c->flags & DIV_U71) {
674 u32 div = 0;
675 if (!(p->flags & PLLX)) {
676 div = clk_readl(c->reg +
677 SUPER_CLK_DIVIDER);
678 div &= SUPER_CLOCK_DIV_U71_MASK;
679 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
680 } 680 }
681 c->div = div + 2;
682 c->mul = 2;
681 } 683 }
682 return -EINVAL; 684 clk_writel_delay(val, c->reg);
685
686 return 0;
683} 687}
684 688
685/* 689/*
@@ -691,10 +695,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
691 * rate of this PLL can't be changed, and it has many other children. In 695 * rate of this PLL can't be changed, and it has many other children. In
692 * this case use 7.1 fractional divider to adjust the super clock rate. 696 * this case use 7.1 fractional divider to adjust the super clock rate.
693 */ 697 */
694static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate) 698static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
699 unsigned long parent_rate)
695{ 700{
696 if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { 701 struct clk_tegra *c = to_clk_tegra(hw);
697 int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, 702 struct clk *parent = __clk_get_parent(hw->clk);
703 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
704
705 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
706 int div = clk_div71_get_divider(parent_rate,
698 rate, c->flags, ROUND_DIVIDER_DOWN); 707 rate, c->flags, ROUND_DIVIDER_DOWN);
699 div = max(div, SUPER_CLOCK_DIV_U71_MIN); 708 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
700 709
@@ -704,55 +713,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
704 c->mul = 2; 713 c->mul = 2;
705 return 0; 714 return 0;
706 } 715 }
707 return clk_set_rate(c->parent, rate); 716 return 0;
717}
718
719static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
720 unsigned long parent_rate)
721{
722 struct clk_tegra *c = to_clk_tegra(hw);
723 u64 rate = parent_rate;
724
725 if (c->mul != 0 && c->div != 0) {
726 rate *= c->mul;
727 rate += c->div - 1; /* round up */
728 do_div(rate, c->div);
729 }
730
731 return rate;
732}
733
734static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
735 unsigned long *prate)
736{
737 struct clk_tegra *c = to_clk_tegra(hw);
738 struct clk *parent = __clk_get_parent(hw->clk);
739 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
740 int mul = 2;
741 int div;
742
743 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
744 div = clk_div71_get_divider(*prate,
745 rate, c->flags, ROUND_DIVIDER_DOWN);
746 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
747 rate = *prate * mul;
748 rate += div - 1; /* round up */
749 do_div(rate, c->div);
750
751 return rate;
752 }
753 return *prate;
708} 754}
709 755
710static struct clk_ops tegra_super_ops = { 756struct clk_ops tegra30_super_ops = {
711 .init = tegra30_super_clk_init, 757 .init = tegra30_super_clk_init,
712 .enable = tegra30_super_clk_enable, 758 .set_parent = tegra30_super_clk_set_parent,
713 .disable = tegra30_super_clk_disable, 759 .get_parent = tegra30_super_clk_get_parent,
714 .set_parent = tegra30_super_clk_set_parent, 760 .recalc_rate = tegra30_super_clk_recalc_rate,
715 .set_rate = tegra30_super_clk_set_rate, 761 .round_rate = tegra30_super_clk_round_rate,
762 .set_rate = tegra30_super_clk_set_rate,
716}; 763};
717 764
718static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate) 765static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
766 unsigned long parent_rate)
719{ 767{
720 /* The input value 'rate' is the clock rate of the CPU complex. */ 768 struct clk_tegra *c = to_clk_tegra(hw);
721 c->rate = (rate * c->mul) / c->div; 769 u64 rate = parent_rate;
722 return 0; 770
771 if (c->mul != 0 && c->div != 0) {
772 rate *= c->mul;
773 rate += c->div - 1; /* round up */
774 do_div(rate, c->div);
775 }
776
777 return rate;
723} 778}
724 779
725static struct clk_ops tegra30_twd_ops = { 780struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate, 781 .recalc_rate = tegra30_twd_clk_recalc_rate,
727}; 782};
728 783
729/* Blink output functions */ 784/* Blink output functions */
730 785static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
731static void tegra30_blink_clk_init(struct clk *c)
732{ 786{
787 struct clk_tegra *c = to_clk_tegra(hw);
733 u32 val; 788 u32 val;
734 789
735 val = pmc_readl(PMC_CTRL); 790 val = pmc_readl(PMC_CTRL);
736 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; 791 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
737 c->mul = 1; 792 return c->state;
738 val = pmc_readl(c->reg);
739
740 if (val & PMC_BLINK_TIMER_ENB) {
741 unsigned int on_off;
742
743 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
744 PMC_BLINK_TIMER_DATA_ON_MASK;
745 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
746 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
747 on_off += val;
748 /* each tick in the blink timer is 4 32KHz clocks */
749 c->div = on_off * 4;
750 } else {
751 c->div = 1;
752 }
753} 793}
754 794
755static int tegra30_blink_clk_enable(struct clk *c) 795static int tegra30_blink_clk_enable(struct clk_hw *hw)
756{ 796{
757 u32 val; 797 u32 val;
758 798
@@ -765,7 +805,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
765 return 0; 805 return 0;
766} 806}
767 807
768static void tegra30_blink_clk_disable(struct clk *c) 808static void tegra30_blink_clk_disable(struct clk_hw *hw)
769{ 809{
770 u32 val; 810 u32 val;
771 811
@@ -776,9 +816,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
776 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); 816 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
777} 817}
778 818
779static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate) 819static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
820 unsigned long parent_rate)
780{ 821{
781 unsigned long parent_rate = clk_get_rate(c->parent); 822 struct clk_tegra *c = to_clk_tegra(hw);
823
782 if (rate >= parent_rate) { 824 if (rate >= parent_rate) {
783 c->div = 1; 825 c->div = 1;
784 pmc_writel(0, c->reg); 826 pmc_writel(0, c->reg);
@@ -801,41 +843,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
801 return 0; 843 return 0;
802} 844}
803 845
804static struct clk_ops tegra_blink_clk_ops = { 846static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
805 .init = &tegra30_blink_clk_init, 847 unsigned long parent_rate)
806 .enable = &tegra30_blink_clk_enable, 848{
807 .disable = &tegra30_blink_clk_disable, 849 struct clk_tegra *c = to_clk_tegra(hw);
808 .set_rate = &tegra30_blink_clk_set_rate, 850 u64 rate = parent_rate;
809}; 851 u32 val;
852 u32 mul;
853 u32 div;
854 u32 on_off;
810 855
811/* PLL Functions */ 856 mul = 1;
812static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, 857 val = pmc_readl(c->reg);
813 u32 lock_bit) 858
859 if (val & PMC_BLINK_TIMER_ENB) {
860 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
861 PMC_BLINK_TIMER_DATA_ON_MASK;
862 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
863 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
864 on_off += val;
865 /* each tick in the blink timer is 4 32KHz clocks */
866 div = on_off * 4;
867 } else {
868 div = 1;
869 }
870
871 if (mul != 0 && div != 0) {
872 rate *= mul;
873 rate += div - 1; /* round up */
874 do_div(rate, div);
875 }
876 return rate;
877}
878
879static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
880 unsigned long *prate)
814{ 881{
815#if USE_PLL_LOCK_BITS 882 int div;
816 int i; 883 int mul;
817 for (i = 0; i < c->u.pll.lock_delay; i++) { 884 long round_rate = *prate;
818 if (clk_readl(lock_reg) & lock_bit) { 885
819 udelay(PLL_POST_LOCK_DELAY); 886 mul = 1;
820 return 0; 887
821 } 888 if (rate >= *prate) {
822 udelay(2); /* timeout = 2 * lock time */ 889 div = 1;
890 } else {
891 div = DIV_ROUND_UP(*prate / 8, rate);
892 div *= 8;
823 } 893 }
824 pr_err("Timed out waiting for lock bit on pll %s", c->name);
825 return -1;
826#endif
827 udelay(c->u.pll.lock_delay);
828 894
829 return 0; 895 round_rate *= mul;
896 round_rate += div - 1;
897 do_div(round_rate, div);
898
899 return round_rate;
830} 900}
831 901
902struct clk_ops tegra30_blink_clk_ops = {
903 .is_enabled = tegra30_blink_clk_is_enabled,
904 .enable = tegra30_blink_clk_enable,
905 .disable = tegra30_blink_clk_disable,
906 .recalc_rate = tegra30_blink_clk_recalc_rate,
907 .round_rate = tegra30_blink_clk_round_rate,
908 .set_rate = tegra30_blink_clk_set_rate,
909};
832 910
833static void tegra30_utmi_param_configure(struct clk *c) 911static void tegra30_utmi_param_configure(struct clk_hw *hw)
834{ 912{
913 unsigned long main_rate =
914 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
835 u32 reg; 915 u32 reg;
836 int i; 916 int i;
837 unsigned long main_rate =
838 clk_get_rate(c->parent->parent);
839 917
840 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 918 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
841 if (main_rate == utmi_parameters[i].osc_frequency) 919 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +964,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
886 clk_writel(reg, UTMIP_PLL_CFG1); 964 clk_writel(reg, UTMIP_PLL_CFG1);
887} 965}
888 966
889static void tegra30_pll_clk_init(struct clk *c) 967/* PLL Functions */
968static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
969 u32 lock_bit)
970{
971 int ret = 0;
972
973#if USE_PLL_LOCK_BITS
974 int i;
975 for (i = 0; i < c->u.pll.lock_delay; i++) {
976 if (clk_readl(lock_reg) & lock_bit) {
977 udelay(PLL_POST_LOCK_DELAY);
978 return 0;
979 }
980 udelay(2); /* timeout = 2 * lock time */
981 }
982 pr_err("Timed out waiting for lock bit on pll %s",
983 __clk_get_name(hw->clk));
984 ret = -1;
985#else
986 udelay(c->u.pll.lock_delay);
987#endif
988 return ret;
989}
990
991static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
890{ 992{
993 struct clk_tegra *c = to_clk_tegra(hw);
891 u32 val = clk_readl(c->reg + PLL_BASE); 994 u32 val = clk_readl(c->reg + PLL_BASE);
892 995
893 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; 996 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
997 return c->state;
998}
894 999
895 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { 1000static void tegra30_pll_clk_init(struct clk_hw *hw)
896 const struct clk_pll_freq_table *sel; 1001{
897 unsigned long input_rate = clk_get_rate(c->parent); 1002 struct clk_tegra *c = to_clk_tegra(hw);
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
899 if (sel->input_rate == input_rate &&
900 sel->output_rate == c->u.pll.fixed_rate) {
901 c->mul = sel->n;
902 c->div = sel->m * sel->p;
903 return;
904 }
905 }
906 pr_err("Clock %s has unknown fixed frequency\n", c->name);
907 BUG();
908 } else if (val & PLL_BASE_BYPASS) {
909 c->mul = 1;
910 c->div = 1;
911 } else {
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
913 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
914 if (c->flags & PLLU)
915 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
916 else
917 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
918 PLL_BASE_DIVP_SHIFT));
919 if (c->flags & PLL_FIXED) {
920 unsigned long rate = clk_get_rate_locked(c);
921 BUG_ON(rate != c->u.pll.fixed_rate);
922 }
923 }
924 1003
925 if (c->flags & PLLU) 1004 if (c->flags & PLLU)
926 tegra30_utmi_param_configure(c); 1005 tegra30_utmi_param_configure(hw);
927} 1006}
928 1007
929static int tegra30_pll_clk_enable(struct clk *c) 1008static int tegra30_pll_clk_enable(struct clk_hw *hw)
930{ 1009{
1010 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val; 1011 u32 val;
932 pr_debug("%s on clock %s\n", __func__, c->name); 1012 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
933 1013
934#if USE_PLL_LOCK_BITS 1014#if USE_PLL_LOCK_BITS
935 val = clk_readl(c->reg + PLL_MISC(c)); 1015 val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1032,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
952 return 0; 1032 return 0;
953} 1033}
954 1034
955static void tegra30_pll_clk_disable(struct clk *c) 1035static void tegra30_pll_clk_disable(struct clk_hw *hw)
956{ 1036{
1037 struct clk_tegra *c = to_clk_tegra(hw);
957 u32 val; 1038 u32 val;
958 pr_debug("%s on clock %s\n", __func__, c->name); 1039 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
959 1040
960 val = clk_readl(c->reg); 1041 val = clk_readl(c->reg);
961 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1042 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1049,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
968 } 1049 }
969} 1050}
970 1051
971static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate) 1052static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1053 unsigned long parent_rate)
972{ 1054{
1055 struct clk_tegra *c = to_clk_tegra(hw);
973 u32 val, p_div, old_base; 1056 u32 val, p_div, old_base;
974 unsigned long input_rate; 1057 unsigned long input_rate;
975 const struct clk_pll_freq_table *sel; 1058 const struct clk_pll_freq_table *sel;
976 struct clk_pll_freq_table cfg; 1059 struct clk_pll_freq_table cfg;
977 1060
978 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
979
980 if (c->flags & PLL_FIXED) { 1061 if (c->flags & PLL_FIXED) {
981 int ret = 0; 1062 int ret = 0;
982 if (rate != c->u.pll.fixed_rate) { 1063 if (rate != c->u.pll.fixed_rate) {
983 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 1064 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
984 __func__, c->name, c->u.pll.fixed_rate, rate); 1065 __func__, __clk_get_name(hw->clk),
1066 c->u.pll.fixed_rate, rate);
985 ret = -EINVAL; 1067 ret = -EINVAL;
986 } 1068 }
987 return ret; 1069 return ret;
988 } 1070 }
989 1071
990 if (c->flags & PLLM) { 1072 if (c->flags & PLLM) {
991 if (rate != clk_get_rate_locked(c)) { 1073 if (rate != __clk_get_rate(hw->clk)) {
992 pr_err("%s: Can not change memory %s rate in flight\n", 1074 pr_err("%s: Can not change memory %s rate in flight\n",
993 __func__, c->name); 1075 __func__, __clk_get_name(hw->clk));
994 return -EINVAL; 1076 return -EINVAL;
995 } 1077 }
996 return 0;
997 } 1078 }
998 1079
999 p_div = 0; 1080 p_div = 0;
1000 input_rate = clk_get_rate(c->parent); 1081 input_rate = parent_rate;
1001 1082
1002 /* Check if the target rate is tabulated */ 1083 /* Check if the target rate is tabulated */
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1084 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1136,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1055 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || 1136 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1056 (cfg.output_rate > c->u.pll.vco_max)) { 1137 (cfg.output_rate > c->u.pll.vco_max)) {
1057 pr_err("%s: Failed to set %s out-of-table rate %lu\n", 1138 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1058 __func__, c->name, rate); 1139 __func__, __clk_get_name(hw->clk), rate);
1059 return -EINVAL; 1140 return -EINVAL;
1060 } 1141 }
1061 p_div <<= PLL_BASE_DIVP_SHIFT; 1142 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1154,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1073 return 0; 1154 return 0;
1074 1155
1075 if (c->state == ON) { 1156 if (c->state == ON) {
1076 tegra30_pll_clk_disable(c); 1157 tegra30_pll_clk_disable(hw);
1077 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1158 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1078 } 1159 }
1079 clk_writel(val, c->reg + PLL_BASE); 1160 clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1176,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1095 } 1176 }
1096 1177
1097 if (c->state == ON) 1178 if (c->state == ON)
1098 tegra30_pll_clk_enable(c); 1179 tegra30_pll_clk_enable(hw);
1180
1181 c->u.pll.fixed_rate = rate;
1099 1182
1100 return 0; 1183 return 0;
1101} 1184}
1102 1185
1103static struct clk_ops tegra_pll_ops = { 1186static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1104 .init = tegra30_pll_clk_init, 1187 unsigned long *prate)
1105 .enable = tegra30_pll_clk_enable, 1188{
1106 .disable = tegra30_pll_clk_disable, 1189 struct clk_tegra *c = to_clk_tegra(hw);
1107 .set_rate = tegra30_pll_clk_set_rate, 1190 unsigned long input_rate = *prate;
1191 unsigned long output_rate = *prate;
1192 const struct clk_pll_freq_table *sel;
1193 struct clk_pll_freq_table cfg;
1194 int mul;
1195 int div;
1196 u32 p_div;
1197 u32 val;
1198
1199 if (c->flags & PLL_FIXED)
1200 return c->u.pll.fixed_rate;
1201
1202 if (c->flags & PLLM)
1203 return __clk_get_rate(hw->clk);
1204
1205 p_div = 0;
1206 /* Check if the target rate is tabulated */
1207 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1208 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1209 if (c->flags & PLLU) {
1210 BUG_ON(sel->p < 1 || sel->p > 2);
1211 if (sel->p == 1)
1212 p_div = PLLU_BASE_POST_DIV;
1213 } else {
1214 BUG_ON(sel->p < 1);
1215 for (val = sel->p; val > 1; val >>= 1)
1216 p_div++;
1217 p_div <<= PLL_BASE_DIVP_SHIFT;
1218 }
1219 break;
1220 }
1221 }
1222
1223 if (sel->input_rate == 0) {
1224 unsigned long cfreq;
1225 BUG_ON(c->flags & PLLU);
1226 sel = &cfg;
1227
1228 switch (input_rate) {
1229 case 12000000:
1230 case 26000000:
1231 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1232 break;
1233 case 13000000:
1234 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1235 break;
1236 case 16800000:
1237 case 19200000:
1238 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1239 break;
1240 default:
1241 pr_err("%s: Unexpected reference rate %lu\n",
1242 __func__, input_rate);
1243 BUG();
1244 }
1245
1246 /* Raise VCO to guarantee 0.5% accuracy */
1247 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1248 cfg.output_rate <<= 1)
1249 p_div++;
1250
1251 cfg.p = 0x1 << p_div;
1252 cfg.m = input_rate / cfreq;
1253 cfg.n = cfg.output_rate / cfreq;
1254 }
1255
1256 mul = sel->n;
1257 div = sel->m * sel->p;
1258
1259 output_rate *= mul;
1260 output_rate += div - 1; /* round up */
1261 do_div(output_rate, div);
1262
1263 return output_rate;
1264}
1265
1266static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1267 unsigned long parent_rate)
1268{
1269 struct clk_tegra *c = to_clk_tegra(hw);
1270 u64 rate = parent_rate;
1271 u32 val = clk_readl(c->reg + PLL_BASE);
1272
1273 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1274 const struct clk_pll_freq_table *sel;
1275 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1276 if (sel->input_rate == parent_rate &&
1277 sel->output_rate == c->u.pll.fixed_rate) {
1278 c->mul = sel->n;
1279 c->div = sel->m * sel->p;
1280 break;
1281 }
1282 }
1283 pr_err("Clock %s has unknown fixed frequency\n",
1284 __clk_get_name(hw->clk));
1285 BUG();
1286 } else if (val & PLL_BASE_BYPASS) {
1287 c->mul = 1;
1288 c->div = 1;
1289 } else {
1290 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1291 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1292 if (c->flags & PLLU)
1293 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1294 else
1295 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1296 PLL_BASE_DIVP_SHIFT));
1297 }
1298
1299 if (c->mul != 0 && c->div != 0) {
1300 rate *= c->mul;
1301 rate += c->div - 1; /* round up */
1302 do_div(rate, c->div);
1303 }
1304
1305 return rate;
1306}
1307
1308struct clk_ops tegra30_pll_ops = {
1309 .is_enabled = tegra30_pll_clk_is_enabled,
1310 .init = tegra30_pll_clk_init,
1311 .enable = tegra30_pll_clk_enable,
1312 .disable = tegra30_pll_clk_disable,
1313 .recalc_rate = tegra30_pll_recalc_rate,
1314 .round_rate = tegra30_pll_round_rate,
1315 .set_rate = tegra30_pll_clk_set_rate,
1108}; 1316};
1109 1317
1110static int 1318int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1111tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1319 enum tegra_clk_ex_param p, u32 setting)
1112{ 1320{
1321 struct clk_tegra *c = to_clk_tegra(hw);
1113 u32 val, mask, reg; 1322 u32 val, mask, reg;
1114 1323
1115 switch (p) { 1324 switch (p) {
@@ -1141,41 +1350,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1141 return 0; 1350 return 0;
1142} 1351}
1143 1352
1144static struct clk_ops tegra_plld_ops = { 1353static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1145 .init = tegra30_pll_clk_init,
1146 .enable = tegra30_pll_clk_enable,
1147 .disable = tegra30_pll_clk_disable,
1148 .set_rate = tegra30_pll_clk_set_rate,
1149 .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
1150};
1151
1152static void tegra30_plle_clk_init(struct clk *c)
1153{ 1354{
1355 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val; 1356 u32 val;
1155 1357
1156 val = clk_readl(PLLE_AUX);
1157 c->parent = (val & PLLE_AUX_PLLP_SEL) ?
1158 tegra_get_clock_by_name("pll_p") :
1159 tegra_get_clock_by_name("pll_ref");
1160
1161 val = clk_readl(c->reg + PLL_BASE); 1358 val = clk_readl(c->reg + PLL_BASE);
1162 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; 1359 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1163 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; 1360 return c->state;
1164 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1165 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1166} 1361}
1167 1362
1168static void tegra30_plle_clk_disable(struct clk *c) 1363static void tegra30_plle_clk_disable(struct clk_hw *hw)
1169{ 1364{
1365 struct clk_tegra *c = to_clk_tegra(hw);
1170 u32 val; 1366 u32 val;
1171 pr_debug("%s on clock %s\n", __func__, c->name);
1172 1367
1173 val = clk_readl(c->reg + PLL_BASE); 1368 val = clk_readl(c->reg + PLL_BASE);
1174 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); 1369 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1175 clk_writel(val, c->reg + PLL_BASE); 1370 clk_writel(val, c->reg + PLL_BASE);
1176} 1371}
1177 1372
1178static void tegra30_plle_training(struct clk *c) 1373static void tegra30_plle_training(struct clk_tegra *c)
1179{ 1374{
1180 u32 val; 1375 u32 val;
1181 1376
@@ -1198,12 +1393,15 @@ static void tegra30_plle_training(struct clk *c)
1198 } while (!(val & PLLE_MISC_READY)); 1393 } while (!(val & PLLE_MISC_READY));
1199} 1394}
1200 1395
1201static int tegra30_plle_configure(struct clk *c, bool force_training) 1396static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1202{ 1397{
1203 u32 val; 1398 struct clk_tegra *c = to_clk_tegra(hw);
1399 struct clk *parent = __clk_get_parent(hw->clk);
1204 const struct clk_pll_freq_table *sel; 1400 const struct clk_pll_freq_table *sel;
1401 u32 val;
1402
1205 unsigned long rate = c->u.pll.fixed_rate; 1403 unsigned long rate = c->u.pll.fixed_rate;
1206 unsigned long input_rate = clk_get_rate(c->parent); 1404 unsigned long input_rate = __clk_get_rate(parent);
1207 1405
1208 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1406 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1209 if (sel->input_rate == input_rate && sel->output_rate == rate) 1407 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1412,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1214 return -ENOSYS; 1412 return -ENOSYS;
1215 1413
1216 /* disable PLLE, clear setup fiels */ 1414 /* disable PLLE, clear setup fiels */
1217 tegra30_plle_clk_disable(c); 1415 tegra30_plle_clk_disable(hw);
1218 1416
1219 val = clk_readl(c->reg + PLL_MISC(c)); 1417 val = clk_readl(c->reg + PLL_MISC(c));
1220 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 1418 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1450,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1252 return 0; 1450 return 0;
1253} 1451}
1254 1452
1255static int tegra30_plle_clk_enable(struct clk *c) 1453static int tegra30_plle_clk_enable(struct clk_hw *hw)
1256{ 1454{
1257 pr_debug("%s on clock %s\n", __func__, c->name); 1455 struct clk_tegra *c = to_clk_tegra(hw);
1258 return tegra30_plle_configure(c, !c->set); 1456
1457 return tegra30_plle_configure(hw, !c->set);
1259} 1458}
1260 1459
1261static struct clk_ops tegra_plle_ops = { 1460static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1262 .init = tegra30_plle_clk_init, 1461 unsigned long parent_rate)
1263 .enable = tegra30_plle_clk_enable, 1462{
1264 .disable = tegra30_plle_clk_disable, 1463 struct clk_tegra *c = to_clk_tegra(hw);
1464 unsigned long rate = parent_rate;
1465 u32 val;
1466
1467 val = clk_readl(c->reg + PLL_BASE);
1468 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1469 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1470 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1471
1472 if (c->mul != 0 && c->div != 0) {
1473 rate *= c->mul;
1474 rate += c->div - 1; /* round up */
1475 do_div(rate, c->div);
1476 }
1477 return rate;
1478}
1479
1480struct clk_ops tegra30_plle_ops = {
1481 .is_enabled = tegra30_plle_clk_is_enabled,
1482 .enable = tegra30_plle_clk_enable,
1483 .disable = tegra30_plle_clk_disable,
1484 .recalc_rate = tegra30_plle_clk_recalc_rate,
1265}; 1485};
1266 1486
1267/* Clock divider ops */ 1487/* Clock divider ops */
1268static void tegra30_pll_div_clk_init(struct clk *c) 1488static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1269{ 1489{
1490 struct clk_tegra *c = to_clk_tegra(hw);
1491
1270 if (c->flags & DIV_U71) { 1492 if (c->flags & DIV_U71) {
1271 u32 divu71;
1272 u32 val = clk_readl(c->reg); 1493 u32 val = clk_readl(c->reg);
1273 val >>= c->reg_shift; 1494 val >>= c->reg_shift;
1274 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; 1495 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1275 if (!(val & PLL_OUT_RESET_DISABLE)) 1496 if (!(val & PLL_OUT_RESET_DISABLE))
1276 c->state = OFF; 1497 c->state = OFF;
1277
1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1279 c->div = (divu71 + 2);
1280 c->mul = 2;
1281 } else if (c->flags & DIV_2) {
1282 c->state = ON;
1283 if (c->flags & (PLLD | PLLX)) {
1284 c->div = 2;
1285 c->mul = 1;
1286 } else
1287 BUG();
1288 } else { 1498 } else {
1289 c->state = ON; 1499 c->state = ON;
1290 c->div = 1;
1291 c->mul = 1;
1292 } 1500 }
1501 return c->state;
1293} 1502}
1294 1503
1295static int tegra30_pll_div_clk_enable(struct clk *c) 1504static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1296{ 1505{
1506 struct clk_tegra *c = to_clk_tegra(hw);
1297 u32 val; 1507 u32 val;
1298 u32 new_val; 1508 u32 new_val;
1299 1509
1300 pr_debug("%s: %s\n", __func__, c->name); 1510 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1301 if (c->flags & DIV_U71) { 1511 if (c->flags & DIV_U71) {
1302 val = clk_readl(c->reg); 1512 val = clk_readl(c->reg);
1303 new_val = val >> c->reg_shift; 1513 new_val = val >> c->reg_shift;
@@ -1315,12 +1525,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
1315 return -EINVAL; 1525 return -EINVAL;
1316} 1526}
1317 1527
1318static void tegra30_pll_div_clk_disable(struct clk *c) 1528static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1319{ 1529{
1530 struct clk_tegra *c = to_clk_tegra(hw);
1320 u32 val; 1531 u32 val;
1321 u32 new_val; 1532 u32 new_val;
1322 1533
1323 pr_debug("%s: %s\n", __func__, c->name); 1534 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1324 if (c->flags & DIV_U71) { 1535 if (c->flags & DIV_U71) {
1325 val = clk_readl(c->reg); 1536 val = clk_readl(c->reg);
1326 new_val = val >> c->reg_shift; 1537 new_val = val >> c->reg_shift;
@@ -1334,14 +1545,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
1334 } 1545 }
1335} 1546}
1336 1547
1337static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate) 1548static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1549 unsigned long parent_rate)
1338{ 1550{
1551 struct clk_tegra *c = to_clk_tegra(hw);
1339 u32 val; 1552 u32 val;
1340 u32 new_val; 1553 u32 new_val;
1341 int divider_u71; 1554 int divider_u71;
1342 unsigned long parent_rate = clk_get_rate(c->parent);
1343 1555
1344 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1345 if (c->flags & DIV_U71) { 1556 if (c->flags & DIV_U71) {
1346 divider_u71 = clk_div71_get_divider( 1557 divider_u71 = clk_div71_get_divider(
1347 parent_rate, rate, c->flags, ROUND_DIVIDER_UP); 1558 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1570,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
1359 clk_writel_delay(val, c->reg); 1570 clk_writel_delay(val, c->reg);
1360 c->div = divider_u71 + 2; 1571 c->div = divider_u71 + 2;
1361 c->mul = 2; 1572 c->mul = 2;
1573 c->fixed_rate = rate;
1362 return 0; 1574 return 0;
1363 } 1575 }
1364 } else if (c->flags & DIV_2) 1576 } else if (c->flags & DIV_2) {
1365 return clk_set_rate(c->parent, rate * 2); 1577 c->fixed_rate = rate;
1578 return 0;
1579 }
1366 1580
1367 return -EINVAL; 1581 return -EINVAL;
1368} 1582}
1369 1583
1370static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate) 1584static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1585 unsigned long parent_rate)
1586{
1587 struct clk_tegra *c = to_clk_tegra(hw);
1588 u64 rate = parent_rate;
1589
1590 if (c->flags & DIV_U71) {
1591 u32 divu71;
1592 u32 val = clk_readl(c->reg);
1593 val >>= c->reg_shift;
1594
1595 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1596 c->div = (divu71 + 2);
1597 c->mul = 2;
1598 } else if (c->flags & DIV_2) {
1599 if (c->flags & (PLLD | PLLX)) {
1600 c->div = 2;
1601 c->mul = 1;
1602 } else
1603 BUG();
1604 } else {
1605 c->div = 1;
1606 c->mul = 1;
1607 }
1608 if (c->mul != 0 && c->div != 0) {
1609 rate *= c->mul;
1610 rate += c->div - 1; /* round up */
1611 do_div(rate, c->div);
1612 }
1613
1614 return rate;
1615}
1616
1617static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1618 unsigned long rate, unsigned long *prate)
1371{ 1619{
1620 struct clk_tegra *c = to_clk_tegra(hw);
1621 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1372 int divider; 1622 int divider;
1373 unsigned long parent_rate = clk_get_rate(c->parent); 1623
1374 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1624 if (prate)
1625 parent_rate = *prate;
1375 1626
1376 if (c->flags & DIV_U71) { 1627 if (c->flags & DIV_U71) {
1377 divider = clk_div71_get_divider( 1628 divider = clk_div71_get_divider(
@@ -1379,23 +1630,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1379 if (divider < 0) 1630 if (divider < 0)
1380 return divider; 1631 return divider;
1381 return DIV_ROUND_UP(parent_rate * 2, divider + 2); 1632 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1382 } else if (c->flags & DIV_2) 1633 } else if (c->flags & DIV_2) {
1383 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ 1634 *prate = rate * 2;
1384 return rate; 1635 return rate;
1636 }
1385 1637
1386 return -EINVAL; 1638 return -EINVAL;
1387} 1639}
1388 1640
1389static struct clk_ops tegra_pll_div_ops = { 1641struct clk_ops tegra30_pll_div_ops = {
1390 .init = tegra30_pll_div_clk_init, 1642 .is_enabled = tegra30_pll_div_clk_is_enabled,
1391 .enable = tegra30_pll_div_clk_enable, 1643 .enable = tegra30_pll_div_clk_enable,
1392 .disable = tegra30_pll_div_clk_disable, 1644 .disable = tegra30_pll_div_clk_disable,
1393 .set_rate = tegra30_pll_div_clk_set_rate, 1645 .set_rate = tegra30_pll_div_clk_set_rate,
1394 .round_rate = tegra30_pll_div_clk_round_rate, 1646 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1647 .round_rate = tegra30_pll_div_clk_round_rate,
1395}; 1648};
1396 1649
1397/* Periph clk ops */ 1650/* Periph clk ops */
1398static inline u32 periph_clk_source_mask(struct clk *c) 1651static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1399{ 1652{
1400 if (c->flags & MUX8) 1653 if (c->flags & MUX8)
1401 return 7 << 29; 1654 return 7 << 29;
@@ -1409,7 +1662,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
1409 return 3 << 30; 1662 return 3 << 30;
1410} 1663}
1411 1664
1412static inline u32 periph_clk_source_shift(struct clk *c) 1665static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1413{ 1666{
1414 if (c->flags & MUX8) 1667 if (c->flags & MUX8)
1415 return 29; 1668 return 29;
@@ -1423,47 +1676,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
1423 return 30; 1676 return 30;
1424} 1677}
1425 1678
1426static void tegra30_periph_clk_init(struct clk *c) 1679static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1427{ 1680{
1428 u32 val = clk_readl(c->reg); 1681 struct clk_tegra *c = to_clk_tegra(hw);
1429 const struct clk_mux_sel *mux = 0;
1430 const struct clk_mux_sel *sel;
1431 if (c->flags & MUX) {
1432 for (sel = c->inputs; sel->input != NULL; sel++) {
1433 if (((val & periph_clk_source_mask(c)) >>
1434 periph_clk_source_shift(c)) == sel->value)
1435 mux = sel;
1436 }
1437 BUG_ON(!mux);
1438
1439 c->parent = mux->input;
1440 } else {
1441 c->parent = c->inputs[0].input;
1442 }
1443
1444 if (c->flags & DIV_U71) {
1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1446 if ((c->flags & DIV_U71_UART) &&
1447 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1448 divu71 = 0;
1449 }
1450 if (c->flags & DIV_U71_IDLE) {
1451 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1452 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1453 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1454 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1455 clk_writel(val, c->reg);
1456 }
1457 c->div = divu71 + 2;
1458 c->mul = 2;
1459 } else if (c->flags & DIV_U16) {
1460 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1461 c->div = divu16 + 1;
1462 c->mul = 1;
1463 } else {
1464 c->div = 1;
1465 c->mul = 1;
1466 }
1467 1682
1468 c->state = ON; 1683 c->state = ON;
1469 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 1684 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1686,12 @@ static void tegra30_periph_clk_init(struct clk *c)
1471 if (!(c->flags & PERIPH_NO_RESET)) 1686 if (!(c->flags & PERIPH_NO_RESET))
1472 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) 1687 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1473 c->state = OFF; 1688 c->state = OFF;
1689 return c->state;
1474} 1690}
1475 1691
1476static int tegra30_periph_clk_enable(struct clk *c) 1692static int tegra30_periph_clk_enable(struct clk_hw *hw)
1477{ 1693{
1478 pr_debug("%s on clock %s\n", __func__, c->name); 1694 struct clk_tegra *c = to_clk_tegra(hw);
1479 1695
1480 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; 1696 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1481 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) 1697 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1710,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
1494 return 0; 1710 return 0;
1495} 1711}
1496 1712
1497static void tegra30_periph_clk_disable(struct clk *c) 1713static void tegra30_periph_clk_disable(struct clk_hw *hw)
1498{ 1714{
1715 struct clk_tegra *c = to_clk_tegra(hw);
1499 unsigned long val; 1716 unsigned long val;
1500 pr_debug("%s on clock %s\n", __func__, c->name);
1501 1717
1502 if (c->refcnt) 1718 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1503 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1504 1719
1505 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { 1720 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1506 /* If peripheral is in the APB bus then read the APB bus to 1721 return;
1507 * flush the write operation in apb bus. This will avoid the
1508 * peripheral access after disabling clock*/
1509 if (c->flags & PERIPH_ON_APB)
1510 val = chipid_readl();
1511 1722
1512 clk_writel_delay( 1723 /* If peripheral is in the APB bus then read the APB bus to
1513 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); 1724 * flush the write operation in apb bus. This will avoid the
1514 } 1725 * peripheral access after disabling clock*/
1726 if (c->flags & PERIPH_ON_APB)
1727 val = chipid_readl();
1728
1729 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1515} 1730}
1516 1731
1517static void tegra30_periph_clk_reset(struct clk *c, bool assert) 1732void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1518{ 1733{
1734 struct clk_tegra *c = to_clk_tegra(hw);
1519 unsigned long val; 1735 unsigned long val;
1520 pr_debug("%s %s on clock %s\n", __func__,
1521 assert ? "assert" : "deassert", c->name);
1522 1736
1523 if (!(c->flags & PERIPH_NO_RESET)) { 1737 if (!(c->flags & PERIPH_NO_RESET)) {
1524 if (assert) { 1738 if (assert) {
@@ -1537,42 +1751,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
1537 } 1751 }
1538} 1752}
1539 1753
1540static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p) 1754static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1541{ 1755{
1756 struct clk_tegra *c = to_clk_tegra(hw);
1542 u32 val; 1757 u32 val;
1543 const struct clk_mux_sel *sel;
1544 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1545 1758
1546 if (!(c->flags & MUX)) 1759 if (!(c->flags & MUX))
1547 return (p == c->parent) ? 0 : (-EINVAL); 1760 return (index == 0) ? 0 : (-EINVAL);
1548 1761
1549 for (sel = c->inputs; sel->input != NULL; sel++) { 1762 val = clk_readl(c->reg);
1550 if (sel->input == p) { 1763 val &= ~periph_clk_source_mask(c);
1551 val = clk_readl(c->reg); 1764 val |= (index << periph_clk_source_shift(c));
1552 val &= ~periph_clk_source_mask(c); 1765 clk_writel_delay(val, c->reg);
1553 val |= (sel->value << periph_clk_source_shift(c)); 1766 return 0;
1554 1767}
1555 if (c->refcnt)
1556 clk_enable(p);
1557
1558 clk_writel_delay(val, c->reg);
1559 1768
1560 if (c->refcnt && c->parent) 1769static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1561 clk_disable(c->parent); 1770{
1771 struct clk_tegra *c = to_clk_tegra(hw);
1772 u32 val = clk_readl(c->reg);
1773 int source = (val & periph_clk_source_mask(c)) >>
1774 periph_clk_source_shift(c);
1562 1775
1563 clk_reparent(c, p); 1776 if (!(c->flags & MUX))
1564 return 0; 1777 return 0;
1565 }
1566 }
1567 1778
1568 return -EINVAL; 1779 return source;
1569} 1780}
1570 1781
1571static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate) 1782static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1783 unsigned long parent_rate)
1572{ 1784{
1785 struct clk_tegra *c = to_clk_tegra(hw);
1573 u32 val; 1786 u32 val;
1574 int divider; 1787 int divider;
1575 unsigned long parent_rate = clk_get_rate(c->parent);
1576 1788
1577 if (c->flags & DIV_U71) { 1789 if (c->flags & DIV_U71) {
1578 divider = clk_div71_get_divider( 1790 divider = clk_div71_get_divider(
@@ -1611,12 +1823,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
1611 return -EINVAL; 1823 return -EINVAL;
1612} 1824}
1613 1825
1614static long tegra30_periph_clk_round_rate(struct clk *c, 1826static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1615 unsigned long rate) 1827 unsigned long *prate)
1616{ 1828{
1829 struct clk_tegra *c = to_clk_tegra(hw);
1830 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1617 int divider; 1831 int divider;
1618 unsigned long parent_rate = clk_get_rate(c->parent); 1832
1619 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1833 if (prate)
1834 parent_rate = *prate;
1620 1835
1621 if (c->flags & DIV_U71) { 1836 if (c->flags & DIV_U71) {
1622 divider = clk_div71_get_divider( 1837 divider = clk_div71_get_divider(
@@ -1634,21 +1849,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
1634 return -EINVAL; 1849 return -EINVAL;
1635} 1850}
1636 1851
1637static struct clk_ops tegra_periph_clk_ops = { 1852static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1638 .init = &tegra30_periph_clk_init, 1853 unsigned long parent_rate)
1854{
1855 struct clk_tegra *c = to_clk_tegra(hw);
1856 u64 rate = parent_rate;
1857 u32 val = clk_readl(c->reg);
1858
1859 if (c->flags & DIV_U71) {
1860 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1861 if ((c->flags & DIV_U71_UART) &&
1862 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1863 divu71 = 0;
1864 }
1865 if (c->flags & DIV_U71_IDLE) {
1866 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1867 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1868 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1869 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1870 clk_writel(val, c->reg);
1871 }
1872 c->div = divu71 + 2;
1873 c->mul = 2;
1874 } else if (c->flags & DIV_U16) {
1875 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1876 c->div = divu16 + 1;
1877 c->mul = 1;
1878 } else {
1879 c->div = 1;
1880 c->mul = 1;
1881 }
1882
1883 if (c->mul != 0 && c->div != 0) {
1884 rate *= c->mul;
1885 rate += c->div - 1; /* round up */
1886 do_div(rate, c->div);
1887 }
1888 return rate;
1889}
1890
1891struct clk_ops tegra30_periph_clk_ops = {
1892 .is_enabled = tegra30_periph_clk_is_enabled,
1893 .enable = tegra30_periph_clk_enable,
1894 .disable = tegra30_periph_clk_disable,
1895 .set_parent = tegra30_periph_clk_set_parent,
1896 .get_parent = tegra30_periph_clk_get_parent,
1897 .set_rate = tegra30_periph_clk_set_rate,
1898 .round_rate = tegra30_periph_clk_round_rate,
1899 .recalc_rate = tegra30_periph_clk_recalc_rate,
1900};
1901
1902static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
1903{
1904 struct clk *d = clk_get_sys(NULL, "pll_d");
1905 /* The DSIB parent selection bit is in PLLD base
1906 register - can not do direct r-m-w, must be
1907 protected by PLLD lock */
1908 tegra_clk_cfg_ex(
1909 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
1910
1911 return 0;
1912}
1913
1914struct clk_ops tegra30_dsib_clk_ops = {
1915 .is_enabled = tegra30_periph_clk_is_enabled,
1639 .enable = &tegra30_periph_clk_enable, 1916 .enable = &tegra30_periph_clk_enable,
1640 .disable = &tegra30_periph_clk_disable, 1917 .disable = &tegra30_periph_clk_disable,
1641 .set_parent = &tegra30_periph_clk_set_parent, 1918 .set_parent = &tegra30_dsib_clk_set_parent,
1919 .get_parent = &tegra30_periph_clk_get_parent,
1642 .set_rate = &tegra30_periph_clk_set_rate, 1920 .set_rate = &tegra30_periph_clk_set_rate,
1643 .round_rate = &tegra30_periph_clk_round_rate, 1921 .round_rate = &tegra30_periph_clk_round_rate,
1644 .reset = &tegra30_periph_clk_reset, 1922 .recalc_rate = &tegra30_periph_clk_recalc_rate,
1645}; 1923};
1646 1924
1647
1648/* Periph extended clock configuration ops */ 1925/* Periph extended clock configuration ops */
1649static int 1926int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
1650tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1927 enum tegra_clk_ex_param p, u32 setting)
1651{ 1928{
1929 struct clk_tegra *c = to_clk_tegra(hw);
1930
1652 if (p == TEGRA_CLK_VI_INP_SEL) { 1931 if (p == TEGRA_CLK_VI_INP_SEL) {
1653 u32 val = clk_readl(c->reg); 1932 u32 val = clk_readl(c->reg);
1654 val &= ~PERIPH_CLK_VI_SEL_EX_MASK; 1933 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1939,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1660 return -EINVAL; 1939 return -EINVAL;
1661} 1940}
1662 1941
1663static struct clk_ops tegra_vi_clk_ops = { 1942int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
1664 .init = &tegra30_periph_clk_init, 1943 enum tegra_clk_ex_param p, u32 setting)
1665 .enable = &tegra30_periph_clk_enable,
1666 .disable = &tegra30_periph_clk_disable,
1667 .set_parent = &tegra30_periph_clk_set_parent,
1668 .set_rate = &tegra30_periph_clk_set_rate,
1669 .round_rate = &tegra30_periph_clk_round_rate,
1670 .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
1671 .reset = &tegra30_periph_clk_reset,
1672};
1673
1674static int
1675tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1676{ 1944{
1945 struct clk_tegra *c = to_clk_tegra(hw);
1946
1677 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { 1947 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
1678 u32 val = clk_readl(c->reg); 1948 u32 val = clk_readl(c->reg);
1679 if (setting) 1949 if (setting)
@@ -1686,21 +1956,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1686 return -EINVAL; 1956 return -EINVAL;
1687} 1957}
1688 1958
1689static struct clk_ops tegra_nand_clk_ops = { 1959int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
1690 .init = &tegra30_periph_clk_init, 1960 enum tegra_clk_ex_param p, u32 setting)
1691 .enable = &tegra30_periph_clk_enable,
1692 .disable = &tegra30_periph_clk_disable,
1693 .set_parent = &tegra30_periph_clk_set_parent,
1694 .set_rate = &tegra30_periph_clk_set_rate,
1695 .round_rate = &tegra30_periph_clk_round_rate,
1696 .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
1697 .reset = &tegra30_periph_clk_reset,
1698};
1699
1700
1701static int
1702tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1703{ 1961{
1962 struct clk_tegra *c = to_clk_tegra(hw);
1963
1704 if (p == TEGRA_CLK_DTV_INVERT) { 1964 if (p == TEGRA_CLK_DTV_INVERT) {
1705 u32 val = clk_readl(c->reg); 1965 u32 val = clk_readl(c->reg);
1706 if (setting) 1966 if (setting)
@@ -1713,91 +1973,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1713 return -EINVAL; 1973 return -EINVAL;
1714} 1974}
1715 1975
1716static struct clk_ops tegra_dtv_clk_ops = {
1717 .init = &tegra30_periph_clk_init,
1718 .enable = &tegra30_periph_clk_enable,
1719 .disable = &tegra30_periph_clk_disable,
1720 .set_parent = &tegra30_periph_clk_set_parent,
1721 .set_rate = &tegra30_periph_clk_set_rate,
1722 .round_rate = &tegra30_periph_clk_round_rate,
1723 .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
1724 .reset = &tegra30_periph_clk_reset,
1725};
1726
1727static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1728{
1729 const struct clk_mux_sel *sel;
1730 struct clk *d = tegra_get_clock_by_name("pll_d");
1731
1732 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1733
1734 for (sel = c->inputs; sel->input != NULL; sel++) {
1735 if (sel->input == p) {
1736 if (c->refcnt)
1737 clk_enable(p);
1738
1739 /* The DSIB parent selection bit is in PLLD base
1740 register - can not do direct r-m-w, must be
1741 protected by PLLD lock */
1742 tegra_clk_cfg_ex(
1743 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
1744
1745 if (c->refcnt && c->parent)
1746 clk_disable(c->parent);
1747
1748 clk_reparent(c, p);
1749 return 0;
1750 }
1751 }
1752
1753 return -EINVAL;
1754}
1755
1756static struct clk_ops tegra_dsib_clk_ops = {
1757 .init = &tegra30_periph_clk_init,
1758 .enable = &tegra30_periph_clk_enable,
1759 .disable = &tegra30_periph_clk_disable,
1760 .set_parent = &tegra30_dsib_clk_set_parent,
1761 .set_rate = &tegra30_periph_clk_set_rate,
1762 .round_rate = &tegra30_periph_clk_round_rate,
1763 .reset = &tegra30_periph_clk_reset,
1764};
1765
1766/* pciex clock support only reset function */
1767static struct clk_ops tegra_pciex_clk_ops = {
1768 .reset = tegra30_periph_clk_reset,
1769};
1770
1771/* Output clock ops */ 1976/* Output clock ops */
1772 1977
1773static DEFINE_SPINLOCK(clk_out_lock); 1978static DEFINE_SPINLOCK(clk_out_lock);
1774 1979
1775static void tegra30_clk_out_init(struct clk *c) 1980static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
1776{ 1981{
1777 const struct clk_mux_sel *mux = 0; 1982 struct clk_tegra *c = to_clk_tegra(hw);
1778 const struct clk_mux_sel *sel;
1779 u32 val = pmc_readl(c->reg); 1983 u32 val = pmc_readl(c->reg);
1780 1984
1781 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; 1985 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
1782 c->mul = 1; 1986 c->mul = 1;
1783 c->div = 1; 1987 c->div = 1;
1784 1988 return c->state;
1785 for (sel = c->inputs; sel->input != NULL; sel++) {
1786 if (((val & periph_clk_source_mask(c)) >>
1787 periph_clk_source_shift(c)) == sel->value)
1788 mux = sel;
1789 }
1790 BUG_ON(!mux);
1791 c->parent = mux->input;
1792} 1989}
1793 1990
1794static int tegra30_clk_out_enable(struct clk *c) 1991static int tegra30_clk_out_enable(struct clk_hw *hw)
1795{ 1992{
1993 struct clk_tegra *c = to_clk_tegra(hw);
1796 u32 val; 1994 u32 val;
1797 unsigned long flags; 1995 unsigned long flags;
1798 1996
1799 pr_debug("%s on clock %s\n", __func__, c->name);
1800
1801 spin_lock_irqsave(&clk_out_lock, flags); 1997 spin_lock_irqsave(&clk_out_lock, flags);
1802 val = pmc_readl(c->reg); 1998 val = pmc_readl(c->reg);
1803 val |= (0x1 << c->u.periph.clk_num); 1999 val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2003,12 @@ static int tegra30_clk_out_enable(struct clk *c)
1807 return 0; 2003 return 0;
1808} 2004}
1809 2005
1810static void tegra30_clk_out_disable(struct clk *c) 2006static void tegra30_clk_out_disable(struct clk_hw *hw)
1811{ 2007{
2008 struct clk_tegra *c = to_clk_tegra(hw);
1812 u32 val; 2009 u32 val;
1813 unsigned long flags; 2010 unsigned long flags;
1814 2011
1815 pr_debug("%s on clock %s\n", __func__, c->name);
1816
1817 spin_lock_irqsave(&clk_out_lock, flags); 2012 spin_lock_irqsave(&clk_out_lock, flags);
1818 val = pmc_readl(c->reg); 2013 val = pmc_readl(c->reg);
1819 val &= ~(0x1 << c->u.periph.clk_num); 2014 val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2016,59 @@ static void tegra30_clk_out_disable(struct clk *c)
1821 spin_unlock_irqrestore(&clk_out_lock, flags); 2016 spin_unlock_irqrestore(&clk_out_lock, flags);
1822} 2017}
1823 2018
1824static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p) 2019static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
1825{ 2020{
2021 struct clk_tegra *c = to_clk_tegra(hw);
1826 u32 val; 2022 u32 val;
1827 unsigned long flags; 2023 unsigned long flags;
1828 const struct clk_mux_sel *sel;
1829 2024
1830 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 2025 spin_lock_irqsave(&clk_out_lock, flags);
1831 2026 val = pmc_readl(c->reg);
1832 for (sel = c->inputs; sel->input != NULL; sel++) { 2027 val &= ~periph_clk_source_mask(c);
1833 if (sel->input == p) { 2028 val |= (index << periph_clk_source_shift(c));
1834 if (c->refcnt) 2029 pmc_writel(val, c->reg);
1835 clk_enable(p); 2030 spin_unlock_irqrestore(&clk_out_lock, flags);
1836 2031
1837 spin_lock_irqsave(&clk_out_lock, flags); 2032 return 0;
1838 val = pmc_readl(c->reg); 2033}
1839 val &= ~periph_clk_source_mask(c);
1840 val |= (sel->value << periph_clk_source_shift(c));
1841 pmc_writel(val, c->reg);
1842 spin_unlock_irqrestore(&clk_out_lock, flags);
1843 2034
1844 if (c->refcnt && c->parent) 2035static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
1845 clk_disable(c->parent); 2036{
2037 struct clk_tegra *c = to_clk_tegra(hw);
2038 u32 val = pmc_readl(c->reg);
2039 int source;
1846 2040
1847 clk_reparent(c, p); 2041 source = (val & periph_clk_source_mask(c)) >>
1848 return 0; 2042 periph_clk_source_shift(c);
1849 } 2043 return source;
1850 }
1851 return -EINVAL;
1852} 2044}
1853 2045
1854static struct clk_ops tegra_clk_out_ops = { 2046struct clk_ops tegra_clk_out_ops = {
1855 .init = &tegra30_clk_out_init, 2047 .is_enabled = tegra30_clk_out_is_enabled,
1856 .enable = &tegra30_clk_out_enable, 2048 .enable = tegra30_clk_out_enable,
1857 .disable = &tegra30_clk_out_disable, 2049 .disable = tegra30_clk_out_disable,
1858 .set_parent = &tegra30_clk_out_set_parent, 2050 .set_parent = tegra30_clk_out_set_parent,
2051 .get_parent = tegra30_clk_out_get_parent,
2052 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1859}; 2053};
1860 2054
1861
1862/* Clock doubler ops */ 2055/* Clock doubler ops */
1863static void tegra30_clk_double_init(struct clk *c) 2056static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
1864{ 2057{
1865 u32 val = clk_readl(c->reg); 2058 struct clk_tegra *c = to_clk_tegra(hw);
1866 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; 2059
1867 c->div = 1;
1868 c->state = ON; 2060 c->state = ON;
1869 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 2061 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1870 c->state = OFF; 2062 c->state = OFF;
2063 return c->state;
1871}; 2064};
1872 2065
1873static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate) 2066static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2067 unsigned long parent_rate)
1874{ 2068{
2069 struct clk_tegra *c = to_clk_tegra(hw);
1875 u32 val; 2070 u32 val;
1876 unsigned long parent_rate = clk_get_rate(c->parent); 2071
1877 if (rate == parent_rate) { 2072 if (rate == parent_rate) {
1878 val = clk_readl(c->reg) | (0x1 << c->reg_shift); 2073 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
1879 clk_writel(val, c->reg); 2074 clk_writel(val, c->reg);
@@ -1890,1215 +2085,139 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1890 return -EINVAL; 2085 return -EINVAL;
1891} 2086}
1892 2087
1893static struct clk_ops tegra_clk_double_ops = { 2088static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
1894 .init = &tegra30_clk_double_init, 2089 unsigned long parent_rate)
1895 .enable = &tegra30_periph_clk_enable, 2090{
1896 .disable = &tegra30_periph_clk_disable, 2091 struct clk_tegra *c = to_clk_tegra(hw);
1897 .set_rate = &tegra30_clk_double_set_rate, 2092 u64 rate = parent_rate;
1898};
1899 2093
1900/* Audio sync clock ops */ 2094 u32 val = clk_readl(c->reg);
1901static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate) 2095 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2096 c->div = 1;
2097
2098 if (c->mul != 0 && c->div != 0) {
2099 rate *= c->mul;
2100 rate += c->div - 1; /* round up */
2101 do_div(rate, c->div);
2102 }
2103
2104 return rate;
2105}
2106
2107static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2108 unsigned long *prate)
1902{ 2109{
1903 c->rate = rate; 2110 unsigned long output_rate = *prate;
1904 return 0; 2111
2112 do_div(output_rate, 2);
2113 return output_rate;
1905} 2114}
1906 2115
1907static struct clk_ops tegra_sync_source_ops = { 2116struct clk_ops tegra30_clk_double_ops = {
1908 .set_rate = &tegra30_sync_source_set_rate, 2117 .is_enabled = tegra30_clk_double_is_enabled,
2118 .enable = tegra30_periph_clk_enable,
2119 .disable = tegra30_periph_clk_disable,
2120 .recalc_rate = tegra30_clk_double_recalc_rate,
2121 .round_rate = tegra30_clk_double_round_rate,
2122 .set_rate = tegra30_clk_double_set_rate,
1909}; 2123};
1910 2124
1911static void tegra30_audio_sync_clk_init(struct clk *c) 2125/* Audio sync clock ops */
2126struct clk_ops tegra_sync_source_ops = {
2127 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2128};
2129
2130static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
1912{ 2131{
1913 int source; 2132 struct clk_tegra *c = to_clk_tegra(hw);
1914 const struct clk_mux_sel *sel;
1915 u32 val = clk_readl(c->reg); 2133 u32 val = clk_readl(c->reg);
1916 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; 2134 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
1917 source = val & AUDIO_SYNC_SOURCE_MASK; 2135 return c->state;
1918 for (sel = c->inputs; sel->input != NULL; sel++)
1919 if (sel->value == source)
1920 break;
1921 BUG_ON(sel->input == NULL);
1922 c->parent = sel->input;
1923} 2136}
1924 2137
1925static int tegra30_audio_sync_clk_enable(struct clk *c) 2138static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
1926{ 2139{
2140 struct clk_tegra *c = to_clk_tegra(hw);
1927 u32 val = clk_readl(c->reg); 2141 u32 val = clk_readl(c->reg);
1928 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); 2142 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
1929 return 0; 2143 return 0;
1930} 2144}
1931 2145
1932static void tegra30_audio_sync_clk_disable(struct clk *c) 2146static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
1933{ 2147{
2148 struct clk_tegra *c = to_clk_tegra(hw);
1934 u32 val = clk_readl(c->reg); 2149 u32 val = clk_readl(c->reg);
1935 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); 2150 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
1936} 2151}
1937 2152
1938static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p) 2153static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1939{ 2154{
2155 struct clk_tegra *c = to_clk_tegra(hw);
1940 u32 val; 2156 u32 val;
1941 const struct clk_mux_sel *sel;
1942 for (sel = c->inputs; sel->input != NULL; sel++) {
1943 if (sel->input == p) {
1944 val = clk_readl(c->reg);
1945 val &= ~AUDIO_SYNC_SOURCE_MASK;
1946 val |= sel->value;
1947
1948 if (c->refcnt)
1949 clk_enable(p);
1950 2157
1951 clk_writel(val, c->reg); 2158 val = clk_readl(c->reg);
2159 val &= ~AUDIO_SYNC_SOURCE_MASK;
2160 val |= index;
1952 2161
1953 if (c->refcnt && c->parent) 2162 clk_writel(val, c->reg);
1954 clk_disable(c->parent); 2163 return 0;
2164}
1955 2165
1956 clk_reparent(c, p); 2166static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
1957 return 0; 2167{
1958 } 2168 struct clk_tegra *c = to_clk_tegra(hw);
1959 } 2169 u32 val = clk_readl(c->reg);
2170 int source;
1960 2171
1961 return -EINVAL; 2172 source = val & AUDIO_SYNC_SOURCE_MASK;
2173 return source;
1962} 2174}
1963 2175
1964static struct clk_ops tegra_audio_sync_clk_ops = { 2176struct clk_ops tegra30_audio_sync_clk_ops = {
1965 .init = tegra30_audio_sync_clk_init, 2177 .is_enabled = tegra30_audio_sync_clk_is_enabled,
1966 .enable = tegra30_audio_sync_clk_enable, 2178 .enable = tegra30_audio_sync_clk_enable,
1967 .disable = tegra30_audio_sync_clk_disable, 2179 .disable = tegra30_audio_sync_clk_disable,
1968 .set_parent = tegra30_audio_sync_clk_set_parent, 2180 .set_parent = tegra30_audio_sync_clk_set_parent,
2181 .get_parent = tegra30_audio_sync_clk_get_parent,
2182 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1969}; 2183};
1970 2184
1971/* cml0 (pcie), and cml1 (sata) clock ops */ 2185/* cml0 (pcie), and cml1 (sata) clock ops */
1972static void tegra30_cml_clk_init(struct clk *c) 2186static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
1973{ 2187{
2188 struct clk_tegra *c = to_clk_tegra(hw);
1974 u32 val = clk_readl(c->reg); 2189 u32 val = clk_readl(c->reg);
1975 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; 2190 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2191 return c->state;
1976} 2192}
1977 2193
1978static int tegra30_cml_clk_enable(struct clk *c) 2194static int tegra30_cml_clk_enable(struct clk_hw *hw)
1979{ 2195{
2196 struct clk_tegra *c = to_clk_tegra(hw);
2197
1980 u32 val = clk_readl(c->reg); 2198 u32 val = clk_readl(c->reg);
1981 val |= (0x1 << c->u.periph.clk_num); 2199 val |= (0x1 << c->u.periph.clk_num);
1982 clk_writel(val, c->reg); 2200 clk_writel(val, c->reg);
2201
1983 return 0; 2202 return 0;
1984} 2203}
1985 2204
1986static void tegra30_cml_clk_disable(struct clk *c) 2205static void tegra30_cml_clk_disable(struct clk_hw *hw)
1987{ 2206{
2207 struct clk_tegra *c = to_clk_tegra(hw);
2208
1988 u32 val = clk_readl(c->reg); 2209 u32 val = clk_readl(c->reg);
1989 val &= ~(0x1 << c->u.periph.clk_num); 2210 val &= ~(0x1 << c->u.periph.clk_num);
1990 clk_writel(val, c->reg); 2211 clk_writel(val, c->reg);
1991} 2212}
1992 2213
1993static struct clk_ops tegra_cml_clk_ops = { 2214struct clk_ops tegra_cml_clk_ops = {
1994 .init = &tegra30_cml_clk_init, 2215 .is_enabled = tegra30_cml_clk_is_enabled,
1995 .enable = &tegra30_cml_clk_enable, 2216 .enable = tegra30_cml_clk_enable,
1996 .disable = &tegra30_cml_clk_disable, 2217 .disable = tegra30_cml_clk_disable,
1997}; 2218 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1998
1999/* Clock definitions */
2000static struct clk tegra_clk_32k = {
2001 .name = "clk_32k",
2002 .rate = 32768,
2003 .ops = NULL,
2004 .max_rate = 32768,
2005};
2006
2007static struct clk tegra_clk_m = {
2008 .name = "clk_m",
2009 .flags = ENABLE_ON_INIT,
2010 .ops = &tegra_clk_m_ops,
2011 .reg = 0x1fc,
2012 .reg_shift = 28,
2013 .max_rate = 48000000,
2014};
2015
2016static struct clk tegra_clk_m_div2 = {
2017 .name = "clk_m_div2",
2018 .ops = &tegra_clk_m_div_ops,
2019 .parent = &tegra_clk_m,
2020 .mul = 1,
2021 .div = 2,
2022 .state = ON,
2023 .max_rate = 24000000,
2024};
2025
2026static struct clk tegra_clk_m_div4 = {
2027 .name = "clk_m_div4",
2028 .ops = &tegra_clk_m_div_ops,
2029 .parent = &tegra_clk_m,
2030 .mul = 1,
2031 .div = 4,
2032 .state = ON,
2033 .max_rate = 12000000,
2034};
2035
2036static struct clk tegra_pll_ref = {
2037 .name = "pll_ref",
2038 .flags = ENABLE_ON_INIT,
2039 .ops = &tegra_pll_ref_ops,
2040 .parent = &tegra_clk_m,
2041 .max_rate = 26000000,
2042};
2043
2044static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
2045 { 12000000, 1040000000, 520, 6, 1, 8},
2046 { 13000000, 1040000000, 480, 6, 1, 8},
2047 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
2048 { 19200000, 1040000000, 325, 6, 1, 6},
2049 { 26000000, 1040000000, 520, 13, 1, 8},
2050
2051 { 12000000, 832000000, 416, 6, 1, 8},
2052 { 13000000, 832000000, 832, 13, 1, 8},
2053 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
2054 { 19200000, 832000000, 260, 6, 1, 8},
2055 { 26000000, 832000000, 416, 13, 1, 8},
2056
2057 { 12000000, 624000000, 624, 12, 1, 8},
2058 { 13000000, 624000000, 624, 13, 1, 8},
2059 { 16800000, 600000000, 520, 14, 1, 8},
2060 { 19200000, 624000000, 520, 16, 1, 8},
2061 { 26000000, 624000000, 624, 26, 1, 8},
2062
2063 { 12000000, 600000000, 600, 12, 1, 8},
2064 { 13000000, 600000000, 600, 13, 1, 8},
2065 { 16800000, 600000000, 500, 14, 1, 8},
2066 { 19200000, 600000000, 375, 12, 1, 6},
2067 { 26000000, 600000000, 600, 26, 1, 8},
2068
2069 { 12000000, 520000000, 520, 12, 1, 8},
2070 { 13000000, 520000000, 520, 13, 1, 8},
2071 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
2072 { 19200000, 520000000, 325, 12, 1, 6},
2073 { 26000000, 520000000, 520, 26, 1, 8},
2074
2075 { 12000000, 416000000, 416, 12, 1, 8},
2076 { 13000000, 416000000, 416, 13, 1, 8},
2077 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
2078 { 19200000, 416000000, 260, 12, 1, 6},
2079 { 26000000, 416000000, 416, 26, 1, 8},
2080 { 0, 0, 0, 0, 0, 0 },
2081};
2082
2083static struct clk tegra_pll_c = {
2084 .name = "pll_c",
2085 .flags = PLL_HAS_CPCON,
2086 .ops = &tegra_pll_ops,
2087 .reg = 0x80,
2088 .parent = &tegra_pll_ref,
2089 .max_rate = 1400000000,
2090 .u.pll = {
2091 .input_min = 2000000,
2092 .input_max = 31000000,
2093 .cf_min = 1000000,
2094 .cf_max = 6000000,
2095 .vco_min = 20000000,
2096 .vco_max = 1400000000,
2097 .freq_table = tegra_pll_c_freq_table,
2098 .lock_delay = 300,
2099 },
2100};
2101
2102static struct clk tegra_pll_c_out1 = {
2103 .name = "pll_c_out1",
2104 .ops = &tegra_pll_div_ops,
2105 .flags = DIV_U71,
2106 .parent = &tegra_pll_c,
2107 .reg = 0x84,
2108 .reg_shift = 0,
2109 .max_rate = 700000000,
2110};
2111
2112static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
2113 { 12000000, 666000000, 666, 12, 1, 8},
2114 { 13000000, 666000000, 666, 13, 1, 8},
2115 { 16800000, 666000000, 555, 14, 1, 8},
2116 { 19200000, 666000000, 555, 16, 1, 8},
2117 { 26000000, 666000000, 666, 26, 1, 8},
2118 { 12000000, 600000000, 600, 12, 1, 8},
2119 { 13000000, 600000000, 600, 13, 1, 8},
2120 { 16800000, 600000000, 500, 14, 1, 8},
2121 { 19200000, 600000000, 375, 12, 1, 6},
2122 { 26000000, 600000000, 600, 26, 1, 8},
2123 { 0, 0, 0, 0, 0, 0 },
2124};
2125
2126static struct clk tegra_pll_m = {
2127 .name = "pll_m",
2128 .flags = PLL_HAS_CPCON | PLLM,
2129 .ops = &tegra_pll_ops,
2130 .reg = 0x90,
2131 .parent = &tegra_pll_ref,
2132 .max_rate = 800000000,
2133 .u.pll = {
2134 .input_min = 2000000,
2135 .input_max = 31000000,
2136 .cf_min = 1000000,
2137 .cf_max = 6000000,
2138 .vco_min = 20000000,
2139 .vco_max = 1200000000,
2140 .freq_table = tegra_pll_m_freq_table,
2141 .lock_delay = 300,
2142 },
2143};
2144
2145static struct clk tegra_pll_m_out1 = {
2146 .name = "pll_m_out1",
2147 .ops = &tegra_pll_div_ops,
2148 .flags = DIV_U71,
2149 .parent = &tegra_pll_m,
2150 .reg = 0x94,
2151 .reg_shift = 0,
2152 .max_rate = 600000000,
2153};
2154
2155static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
2156 { 12000000, 216000000, 432, 12, 2, 8},
2157 { 13000000, 216000000, 432, 13, 2, 8},
2158 { 16800000, 216000000, 360, 14, 2, 8},
2159 { 19200000, 216000000, 360, 16, 2, 8},
2160 { 26000000, 216000000, 432, 26, 2, 8},
2161 { 0, 0, 0, 0, 0, 0 },
2162};
2163
2164static struct clk tegra_pll_p = {
2165 .name = "pll_p",
2166 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
2167 .ops = &tegra_pll_ops,
2168 .reg = 0xa0,
2169 .parent = &tegra_pll_ref,
2170 .max_rate = 432000000,
2171 .u.pll = {
2172 .input_min = 2000000,
2173 .input_max = 31000000,
2174 .cf_min = 1000000,
2175 .cf_max = 6000000,
2176 .vco_min = 20000000,
2177 .vco_max = 1400000000,
2178 .freq_table = tegra_pll_p_freq_table,
2179 .lock_delay = 300,
2180 .fixed_rate = 408000000,
2181 },
2182};
2183
2184static struct clk tegra_pll_p_out1 = {
2185 .name = "pll_p_out1",
2186 .ops = &tegra_pll_div_ops,
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2188 .parent = &tegra_pll_p,
2189 .reg = 0xa4,
2190 .reg_shift = 0,
2191 .max_rate = 432000000,
2192};
2193
2194static struct clk tegra_pll_p_out2 = {
2195 .name = "pll_p_out2",
2196 .ops = &tegra_pll_div_ops,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2198 .parent = &tegra_pll_p,
2199 .reg = 0xa4,
2200 .reg_shift = 16,
2201 .max_rate = 432000000,
2202};
2203
2204static struct clk tegra_pll_p_out3 = {
2205 .name = "pll_p_out3",
2206 .ops = &tegra_pll_div_ops,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2208 .parent = &tegra_pll_p,
2209 .reg = 0xa8,
2210 .reg_shift = 0,
2211 .max_rate = 432000000,
2212};
2213
2214static struct clk tegra_pll_p_out4 = {
2215 .name = "pll_p_out4",
2216 .ops = &tegra_pll_div_ops,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2218 .parent = &tegra_pll_p,
2219 .reg = 0xa8,
2220 .reg_shift = 16,
2221 .max_rate = 432000000,
2222};
2223
2224static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
2225 { 9600000, 564480000, 294, 5, 1, 4},
2226 { 9600000, 552960000, 288, 5, 1, 4},
2227 { 9600000, 24000000, 5, 2, 1, 1},
2228
2229 { 28800000, 56448000, 49, 25, 1, 1},
2230 { 28800000, 73728000, 64, 25, 1, 1},
2231 { 28800000, 24000000, 5, 6, 1, 1},
2232 { 0, 0, 0, 0, 0, 0 },
2233};
2234
2235static struct clk tegra_pll_a = {
2236 .name = "pll_a",
2237 .flags = PLL_HAS_CPCON,
2238 .ops = &tegra_pll_ops,
2239 .reg = 0xb0,
2240 .parent = &tegra_pll_p_out1,
2241 .max_rate = 700000000,
2242 .u.pll = {
2243 .input_min = 2000000,
2244 .input_max = 31000000,
2245 .cf_min = 1000000,
2246 .cf_max = 6000000,
2247 .vco_min = 20000000,
2248 .vco_max = 1400000000,
2249 .freq_table = tegra_pll_a_freq_table,
2250 .lock_delay = 300,
2251 },
2252};
2253
2254static struct clk tegra_pll_a_out0 = {
2255 .name = "pll_a_out0",
2256 .ops = &tegra_pll_div_ops,
2257 .flags = DIV_U71,
2258 .parent = &tegra_pll_a,
2259 .reg = 0xb4,
2260 .reg_shift = 0,
2261 .max_rate = 100000000,
2262};
2263
2264static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
2265 { 12000000, 216000000, 216, 12, 1, 4},
2266 { 13000000, 216000000, 216, 13, 1, 4},
2267 { 16800000, 216000000, 180, 14, 1, 4},
2268 { 19200000, 216000000, 180, 16, 1, 4},
2269 { 26000000, 216000000, 216, 26, 1, 4},
2270
2271 { 12000000, 594000000, 594, 12, 1, 8},
2272 { 13000000, 594000000, 594, 13, 1, 8},
2273 { 16800000, 594000000, 495, 14, 1, 8},
2274 { 19200000, 594000000, 495, 16, 1, 8},
2275 { 26000000, 594000000, 594, 26, 1, 8},
2276
2277 { 12000000, 1000000000, 1000, 12, 1, 12},
2278 { 13000000, 1000000000, 1000, 13, 1, 12},
2279 { 19200000, 1000000000, 625, 12, 1, 8},
2280 { 26000000, 1000000000, 1000, 26, 1, 12},
2281
2282 { 0, 0, 0, 0, 0, 0 },
2283};
2284
2285static struct clk tegra_pll_d = {
2286 .name = "pll_d",
2287 .flags = PLL_HAS_CPCON | PLLD,
2288 .ops = &tegra_plld_ops,
2289 .reg = 0xd0,
2290 .parent = &tegra_pll_ref,
2291 .max_rate = 1000000000,
2292 .u.pll = {
2293 .input_min = 2000000,
2294 .input_max = 40000000,
2295 .cf_min = 1000000,
2296 .cf_max = 6000000,
2297 .vco_min = 40000000,
2298 .vco_max = 1000000000,
2299 .freq_table = tegra_pll_d_freq_table,
2300 .lock_delay = 1000,
2301 },
2302};
2303
2304static struct clk tegra_pll_d_out0 = {
2305 .name = "pll_d_out0",
2306 .ops = &tegra_pll_div_ops,
2307 .flags = DIV_2 | PLLD,
2308 .parent = &tegra_pll_d,
2309 .max_rate = 500000000,
2310};
2311
2312static struct clk tegra_pll_d2 = {
2313 .name = "pll_d2",
2314 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
2315 .ops = &tegra_plld_ops,
2316 .reg = 0x4b8,
2317 .parent = &tegra_pll_ref,
2318 .max_rate = 1000000000,
2319 .u.pll = {
2320 .input_min = 2000000,
2321 .input_max = 40000000,
2322 .cf_min = 1000000,
2323 .cf_max = 6000000,
2324 .vco_min = 40000000,
2325 .vco_max = 1000000000,
2326 .freq_table = tegra_pll_d_freq_table,
2327 .lock_delay = 1000,
2328 },
2329};
2330
2331static struct clk tegra_pll_d2_out0 = {
2332 .name = "pll_d2_out0",
2333 .ops = &tegra_pll_div_ops,
2334 .flags = DIV_2 | PLLD,
2335 .parent = &tegra_pll_d2,
2336 .max_rate = 500000000,
2337};
2338
2339static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
2340 { 12000000, 480000000, 960, 12, 2, 12},
2341 { 13000000, 480000000, 960, 13, 2, 12},
2342 { 16800000, 480000000, 400, 7, 2, 5},
2343 { 19200000, 480000000, 200, 4, 2, 3},
2344 { 26000000, 480000000, 960, 26, 2, 12},
2345 { 0, 0, 0, 0, 0, 0 },
2346};
2347
2348static struct clk tegra_pll_u = {
2349 .name = "pll_u",
2350 .flags = PLL_HAS_CPCON | PLLU,
2351 .ops = &tegra_pll_ops,
2352 .reg = 0xc0,
2353 .parent = &tegra_pll_ref,
2354 .max_rate = 480000000,
2355 .u.pll = {
2356 .input_min = 2000000,
2357 .input_max = 40000000,
2358 .cf_min = 1000000,
2359 .cf_max = 6000000,
2360 .vco_min = 480000000,
2361 .vco_max = 960000000,
2362 .freq_table = tegra_pll_u_freq_table,
2363 .lock_delay = 1000,
2364 },
2365};
2366
2367static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
2368 /* 1.7 GHz */
2369 { 12000000, 1700000000, 850, 6, 1, 8},
2370 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
2371 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
2372 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
2373 { 26000000, 1700000000, 850, 13, 1, 8},
2374
2375 /* 1.6 GHz */
2376 { 12000000, 1600000000, 800, 6, 1, 8},
2377 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
2378 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
2379 { 19200000, 1600000000, 500, 6, 1, 8},
2380 { 26000000, 1600000000, 800, 13, 1, 8},
2381
2382 /* 1.5 GHz */
2383 { 12000000, 1500000000, 750, 6, 1, 8},
2384 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
2385 { 16800000, 1500000000, 625, 7, 1, 8},
2386 { 19200000, 1500000000, 625, 8, 1, 8},
2387 { 26000000, 1500000000, 750, 13, 1, 8},
2388
2389 /* 1.4 GHz */
2390 { 12000000, 1400000000, 700, 6, 1, 8},
2391 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
2392 { 16800000, 1400000000, 1000, 12, 1, 8},
2393 { 19200000, 1400000000, 875, 12, 1, 8},
2394 { 26000000, 1400000000, 700, 13, 1, 8},
2395
2396 /* 1.3 GHz */
2397 { 12000000, 1300000000, 975, 9, 1, 8},
2398 { 13000000, 1300000000, 1000, 10, 1, 8},
2399 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
2400 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
2401 { 26000000, 1300000000, 650, 13, 1, 8},
2402
2403 /* 1.2 GHz */
2404 { 12000000, 1200000000, 1000, 10, 1, 8},
2405 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
2406 { 16800000, 1200000000, 1000, 14, 1, 8},
2407 { 19200000, 1200000000, 1000, 16, 1, 8},
2408 { 26000000, 1200000000, 600, 13, 1, 8},
2409
2410 /* 1.1 GHz */
2411 { 12000000, 1100000000, 825, 9, 1, 8},
2412 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
2413 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
2414 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
2415 { 26000000, 1100000000, 550, 13, 1, 8},
2416
2417 /* 1 GHz */
2418 { 12000000, 1000000000, 1000, 12, 1, 8},
2419 { 13000000, 1000000000, 1000, 13, 1, 8},
2420 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
2421 { 19200000, 1000000000, 625, 12, 1, 8},
2422 { 26000000, 1000000000, 1000, 26, 1, 8},
2423
2424 { 0, 0, 0, 0, 0, 0 },
2425};
2426
2427static struct clk tegra_pll_x = {
2428 .name = "pll_x",
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2430 .ops = &tegra_pll_ops,
2431 .reg = 0xe0,
2432 .parent = &tegra_pll_ref,
2433 .max_rate = 1700000000,
2434 .u.pll = {
2435 .input_min = 2000000,
2436 .input_max = 31000000,
2437 .cf_min = 1000000,
2438 .cf_max = 6000000,
2439 .vco_min = 20000000,
2440 .vco_max = 1700000000,
2441 .freq_table = tegra_pll_x_freq_table,
2442 .lock_delay = 300,
2443 },
2444};
2445
2446static struct clk tegra_pll_x_out0 = {
2447 .name = "pll_x_out0",
2448 .ops = &tegra_pll_div_ops,
2449 .flags = DIV_2 | PLLX,
2450 .parent = &tegra_pll_x,
2451 .max_rate = 850000000,
2452};
2453
2454
2455static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2456 /* PLLE special case: use cpcon field to store cml divider value */
2457 { 12000000, 100000000, 150, 1, 18, 11},
2458 { 216000000, 100000000, 200, 18, 24, 13},
2459 { 0, 0, 0, 0, 0, 0 },
2460};
2461
2462static struct clk tegra_pll_e = {
2463 .name = "pll_e",
2464 .flags = PLL_ALT_MISC_REG,
2465 .ops = &tegra_plle_ops,
2466 .reg = 0xe8,
2467 .max_rate = 100000000,
2468 .u.pll = {
2469 .input_min = 12000000,
2470 .input_max = 216000000,
2471 .cf_min = 12000000,
2472 .cf_max = 12000000,
2473 .vco_min = 1200000000,
2474 .vco_max = 2400000000U,
2475 .freq_table = tegra_pll_e_freq_table,
2476 .lock_delay = 300,
2477 .fixed_rate = 100000000,
2478 },
2479};
2480
2481static struct clk tegra_cml0_clk = {
2482 .name = "cml0",
2483 .parent = &tegra_pll_e,
2484 .ops = &tegra_cml_clk_ops,
2485 .reg = PLLE_AUX,
2486 .max_rate = 100000000,
2487 .u.periph = {
2488 .clk_num = 0,
2489 },
2490};
2491
2492static struct clk tegra_cml1_clk = {
2493 .name = "cml1",
2494 .parent = &tegra_pll_e,
2495 .ops = &tegra_cml_clk_ops,
2496 .reg = PLLE_AUX,
2497 .max_rate = 100000000,
2498 .u.periph = {
2499 .clk_num = 1,
2500 },
2501};
2502
2503static struct clk tegra_pciex_clk = {
2504 .name = "pciex",
2505 .parent = &tegra_pll_e,
2506 .ops = &tegra_pciex_clk_ops,
2507 .max_rate = 100000000,
2508 .u.periph = {
2509 .clk_num = 74,
2510 },
2511};
2512
2513/* Audio sync clocks */
2514#define SYNC_SOURCE(_id) \
2515 { \
2516 .name = #_id "_sync", \
2517 .rate = 24000000, \
2518 .max_rate = 24000000, \
2519 .ops = &tegra_sync_source_ops \
2520 }
2521static struct clk tegra_sync_source_list[] = {
2522 SYNC_SOURCE(spdif_in),
2523 SYNC_SOURCE(i2s0),
2524 SYNC_SOURCE(i2s1),
2525 SYNC_SOURCE(i2s2),
2526 SYNC_SOURCE(i2s3),
2527 SYNC_SOURCE(i2s4),
2528 SYNC_SOURCE(vimclk),
2529};
2530
2531static struct clk_mux_sel mux_audio_sync_clk[] = {
2532 { .input = &tegra_sync_source_list[0], .value = 0},
2533 { .input = &tegra_sync_source_list[1], .value = 1},
2534 { .input = &tegra_sync_source_list[2], .value = 2},
2535 { .input = &tegra_sync_source_list[3], .value = 3},
2536 { .input = &tegra_sync_source_list[4], .value = 4},
2537 { .input = &tegra_sync_source_list[5], .value = 5},
2538 { .input = &tegra_pll_a_out0, .value = 6},
2539 { .input = &tegra_sync_source_list[6], .value = 7},
2540 { 0, 0 }
2541};
2542
2543#define AUDIO_SYNC_CLK(_id, _index) \
2544 { \
2545 .name = #_id, \
2546 .inputs = mux_audio_sync_clk, \
2547 .reg = 0x4A0 + (_index) * 4, \
2548 .max_rate = 24000000, \
2549 .ops = &tegra_audio_sync_clk_ops \
2550 }
2551static struct clk tegra_clk_audio_list[] = {
2552 AUDIO_SYNC_CLK(audio0, 0),
2553 AUDIO_SYNC_CLK(audio1, 1),
2554 AUDIO_SYNC_CLK(audio2, 2),
2555 AUDIO_SYNC_CLK(audio3, 3),
2556 AUDIO_SYNC_CLK(audio4, 4),
2557 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
2558};
2559
2560#define AUDIO_SYNC_2X_CLK(_id, _index) \
2561 { \
2562 .name = #_id "_2x", \
2563 .flags = PERIPH_NO_RESET, \
2564 .max_rate = 48000000, \
2565 .ops = &tegra_clk_double_ops, \
2566 .reg = 0x49C, \
2567 .reg_shift = 24 + (_index), \
2568 .parent = &tegra_clk_audio_list[(_index)], \
2569 .u.periph = { \
2570 .clk_num = 113 + (_index), \
2571 }, \
2572 }
2573static struct clk tegra_clk_audio_2x_list[] = {
2574 AUDIO_SYNC_2X_CLK(audio0, 0),
2575 AUDIO_SYNC_2X_CLK(audio1, 1),
2576 AUDIO_SYNC_2X_CLK(audio2, 2),
2577 AUDIO_SYNC_2X_CLK(audio3, 3),
2578 AUDIO_SYNC_2X_CLK(audio4, 4),
2579 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
2580};
2581
2582#define MUX_I2S_SPDIF(_id, _index) \
2583static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
2584 {.input = &tegra_pll_a_out0, .value = 0}, \
2585 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
2586 {.input = &tegra_pll_p, .value = 2}, \
2587 {.input = &tegra_clk_m, .value = 3}, \
2588 { 0, 0}, \
2589}
2590MUX_I2S_SPDIF(audio0, 0);
2591MUX_I2S_SPDIF(audio1, 1);
2592MUX_I2S_SPDIF(audio2, 2);
2593MUX_I2S_SPDIF(audio3, 3);
2594MUX_I2S_SPDIF(audio4, 4);
2595MUX_I2S_SPDIF(audio, 5); /* SPDIF */
2596
2597/* External clock outputs (through PMC) */
2598#define MUX_EXTERN_OUT(_id) \
2599static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
2600 {.input = &tegra_clk_m, .value = 0}, \
2601 {.input = &tegra_clk_m_div2, .value = 1}, \
2602 {.input = &tegra_clk_m_div4, .value = 2}, \
2603 {.input = NULL, .value = 3}, /* placeholder */ \
2604 { 0, 0}, \
2605}
2606MUX_EXTERN_OUT(1);
2607MUX_EXTERN_OUT(2);
2608MUX_EXTERN_OUT(3);
2609
2610static struct clk_mux_sel *mux_extern_out_list[] = {
2611 mux_clkm_clkm2_clkm4_extern1,
2612 mux_clkm_clkm2_clkm4_extern2,
2613 mux_clkm_clkm2_clkm4_extern3,
2614};
2615
2616#define CLK_OUT_CLK(_id) \
2617 { \
2618 .name = "clk_out_" #_id, \
2619 .lookup = { \
2620 .dev_id = "clk_out_" #_id, \
2621 .con_id = "extern" #_id, \
2622 }, \
2623 .ops = &tegra_clk_out_ops, \
2624 .reg = 0x1a8, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2626 .flags = MUX_CLK_OUT, \
2627 .max_rate = 216000000, \
2628 .u.periph = { \
2629 .clk_num = (_id - 1) * 8 + 2, \
2630 }, \
2631 }
2632static struct clk tegra_clk_out_list[] = {
2633 CLK_OUT_CLK(1),
2634 CLK_OUT_CLK(2),
2635 CLK_OUT_CLK(3),
2636};
2637
2638/* called after peripheral external clocks are initialized */
2639static void init_clk_out_mux(void)
2640{
2641 int i;
2642 struct clk *c;
2643
2644 /* output clock con_id is the name of peripheral
2645 external clock connected to input 3 of the output mux */
2646 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
2647 c = tegra_get_clock_by_name(
2648 tegra_clk_out_list[i].lookup.con_id);
2649 if (!c)
2650 pr_err("%s: could not find clk %s\n", __func__,
2651 tegra_clk_out_list[i].lookup.con_id);
2652 mux_extern_out_list[i][3].input = c;
2653 }
2654}
2655
2656/* Peripheral muxes */
2657static struct clk_mux_sel mux_sclk[] = {
2658 { .input = &tegra_clk_m, .value = 0},
2659 { .input = &tegra_pll_c_out1, .value = 1},
2660 { .input = &tegra_pll_p_out4, .value = 2},
2661 { .input = &tegra_pll_p_out3, .value = 3},
2662 { .input = &tegra_pll_p_out2, .value = 4},
2663 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
2664 { .input = &tegra_clk_32k, .value = 6},
2665 { .input = &tegra_pll_m_out1, .value = 7},
2666 { 0, 0},
2667}; 2219};
2668 2220
2669static struct clk tegra_clk_sclk = { 2221struct clk_ops tegra_pciex_clk_ops = {
2670 .name = "sclk", 2222 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2671 .inputs = mux_sclk,
2672 .reg = 0x28,
2673 .ops = &tegra_super_ops,
2674 .max_rate = 334000000,
2675 .min_rate = 40000000,
2676}; 2223};
2677
2678static struct clk tegra_clk_blink = {
2679 .name = "blink",
2680 .parent = &tegra_clk_32k,
2681 .reg = 0x40,
2682 .ops = &tegra_blink_clk_ops,
2683 .max_rate = 32768,
2684};
2685
2686static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2687 { .input = &tegra_pll_m, .value = 0},
2688 { .input = &tegra_pll_c, .value = 1},
2689 { .input = &tegra_pll_p, .value = 2},
2690 { .input = &tegra_pll_a_out0, .value = 3},
2691 { 0, 0},
2692};
2693
2694static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2695 { .input = &tegra_pll_p, .value = 0},
2696 { .input = &tegra_pll_c, .value = 1},
2697 { .input = &tegra_pll_m, .value = 2},
2698 { .input = &tegra_clk_m, .value = 3},
2699 { 0, 0},
2700};
2701
2702static struct clk_mux_sel mux_pllp_clkm[] = {
2703 { .input = &tegra_pll_p, .value = 0},
2704 { .input = &tegra_clk_m, .value = 3},
2705 { 0, 0},
2706};
2707
2708static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2709 {.input = &tegra_pll_p, .value = 0},
2710 {.input = &tegra_pll_d_out0, .value = 1},
2711 {.input = &tegra_pll_c, .value = 2},
2712 {.input = &tegra_clk_m, .value = 3},
2713 { 0, 0},
2714};
2715
2716static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
2717 {.input = &tegra_pll_p, .value = 0},
2718 {.input = &tegra_pll_m, .value = 1},
2719 {.input = &tegra_pll_d_out0, .value = 2},
2720 {.input = &tegra_pll_a_out0, .value = 3},
2721 {.input = &tegra_pll_c, .value = 4},
2722 {.input = &tegra_pll_d2_out0, .value = 5},
2723 {.input = &tegra_clk_m, .value = 6},
2724 { 0, 0},
2725};
2726
2727static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
2728 { .input = &tegra_pll_a_out0, .value = 0},
2729 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
2730 { .input = &tegra_pll_p, .value = 2},
2731 { .input = &tegra_clk_m, .value = 3},
2732 { 0, 0},
2733};
2734
2735static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
2736 {.input = &tegra_pll_p, .value = 0},
2737 {.input = &tegra_pll_c, .value = 1},
2738 {.input = &tegra_clk_32k, .value = 2},
2739 {.input = &tegra_clk_m, .value = 3},
2740 { 0, 0},
2741};
2742
2743static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
2744 {.input = &tegra_pll_p, .value = 0},
2745 {.input = &tegra_pll_c, .value = 1},
2746 {.input = &tegra_clk_m, .value = 2},
2747 {.input = &tegra_clk_32k, .value = 3},
2748 { 0, 0},
2749};
2750
2751static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2752 {.input = &tegra_pll_p, .value = 0},
2753 {.input = &tegra_pll_c, .value = 1},
2754 {.input = &tegra_pll_m, .value = 2},
2755 { 0, 0},
2756};
2757
2758static struct clk_mux_sel mux_clk_m[] = {
2759 { .input = &tegra_clk_m, .value = 0},
2760 { 0, 0},
2761};
2762
2763static struct clk_mux_sel mux_pllp_out3[] = {
2764 { .input = &tegra_pll_p_out3, .value = 0},
2765 { 0, 0},
2766};
2767
2768static struct clk_mux_sel mux_plld_out0[] = {
2769 { .input = &tegra_pll_d_out0, .value = 0},
2770 { 0, 0},
2771};
2772
2773static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
2774 { .input = &tegra_pll_d_out0, .value = 0},
2775 { .input = &tegra_pll_d2_out0, .value = 1},
2776 { 0, 0},
2777};
2778
2779static struct clk_mux_sel mux_clk_32k[] = {
2780 { .input = &tegra_clk_32k, .value = 0},
2781 { 0, 0},
2782};
2783
2784static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
2785 { .input = &tegra_pll_a_out0, .value = 0},
2786 { .input = &tegra_clk_32k, .value = 1},
2787 { .input = &tegra_pll_p, .value = 2},
2788 { .input = &tegra_clk_m, .value = 3},
2789 { .input = &tegra_pll_e, .value = 4},
2790 { 0, 0},
2791};
2792
2793static struct clk_mux_sel mux_cclk_g[] = {
2794 { .input = &tegra_clk_m, .value = 0},
2795 { .input = &tegra_pll_c, .value = 1},
2796 { .input = &tegra_clk_32k, .value = 2},
2797 { .input = &tegra_pll_m, .value = 3},
2798 { .input = &tegra_pll_p, .value = 4},
2799 { .input = &tegra_pll_p_out4, .value = 5},
2800 { .input = &tegra_pll_p_out3, .value = 6},
2801 { .input = &tegra_pll_x, .value = 8},
2802 { 0, 0},
2803};
2804
2805static struct clk tegra_clk_cclk_g = {
2806 .name = "cclk_g",
2807 .flags = DIV_U71 | DIV_U71_INT,
2808 .inputs = mux_cclk_g,
2809 .reg = 0x368,
2810 .ops = &tegra_super_ops,
2811 .max_rate = 1700000000,
2812};
2813
2814static struct clk tegra30_clk_twd = {
2815 .parent = &tegra_clk_cclk_g,
2816 .name = "twd",
2817 .ops = &tegra30_twd_ops,
2818 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
2819 .mul = 1,
2820 .div = 2,
2821};
2822
2823#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2824 { \
2825 .name = _name, \
2826 .lookup = { \
2827 .dev_id = _dev, \
2828 .con_id = _con, \
2829 }, \
2830 .ops = &tegra_periph_clk_ops, \
2831 .reg = _reg, \
2832 .inputs = _inputs, \
2833 .flags = _flags, \
2834 .max_rate = _max, \
2835 .u.periph = { \
2836 .clk_num = _clk_num, \
2837 }, \
2838 }
2839
2840#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
2841 _flags, _ops) \
2842 { \
2843 .name = _name, \
2844 .lookup = { \
2845 .dev_id = _dev, \
2846 .con_id = _con, \
2847 }, \
2848 .ops = _ops, \
2849 .reg = _reg, \
2850 .inputs = _inputs, \
2851 .flags = _flags, \
2852 .max_rate = _max, \
2853 .u.periph = { \
2854 .clk_num = _clk_num, \
2855 }, \
2856 }
2857
2858#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
2859 { \
2860 .name = _name, \
2861 .lookup = { \
2862 .dev_id = _dev, \
2863 .con_id = _con, \
2864 }, \
2865 .ops = &tegra_clk_shared_bus_ops, \
2866 .parent = _parent, \
2867 .u.shared_bus_user = { \
2868 .client_id = _id, \
2869 .client_div = _div, \
2870 .mode = _mode, \
2871 }, \
2872 }
2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2878 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
2879 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2880 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2881 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
2882 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2883 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2884 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2885 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2893 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2894 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2895 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2896 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
2897 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2898 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2899 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2900 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2901 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2902 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2903 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2904 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2905 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
2906 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
2907 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2908 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2909 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2910 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2911 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2912 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2913 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2914 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2915 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2916 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2917 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2918 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2919 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2920 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2921 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2922 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2923 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2935 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2936 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
2937 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2938 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2939 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2940 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2941 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2942 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
2943 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
2944 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2945 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2946 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2947 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2948 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2949 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2950 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
2951 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
2952 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
2953 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2954 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2955
2956 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
2957 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
2958 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2959 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2960 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2961 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2962 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
2963 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
2964 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2965};
2966
2967#define CLK_DUPLICATE(_name, _dev, _con) \
2968 { \
2969 .name = _name, \
2970 .lookup = { \
2971 .dev_id = _dev, \
2972 .con_id = _con, \
2973 }, \
2974 }
2975
2976/* Some clocks may be used by different drivers depending on the board
2977 * configuration. List those here to register them twice in the clock lookup
2978 * table under two names.
2979 */
2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2989 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2996 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
2997 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
2998 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
2999 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
3000 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
3001 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
3002 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
3003 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
3004 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
3005 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
3006 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
3007 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
3008 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
3009 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
3010 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
3011 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3012 CLK_DUPLICATE("twd", "smp_twd", NULL),
3013 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3014 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
3015 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
3016 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
3017 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
3018 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
3019 CLK_DUPLICATE("dam0", NULL, "dam0"),
3020 CLK_DUPLICATE("dam1", NULL, "dam1"),
3021 CLK_DUPLICATE("dam2", NULL, "dam2"),
3022 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
3023};
3024
3025struct clk *tegra_ptr_clks[] = {
3026 &tegra_clk_32k,
3027 &tegra_clk_m,
3028 &tegra_clk_m_div2,
3029 &tegra_clk_m_div4,
3030 &tegra_pll_ref,
3031 &tegra_pll_m,
3032 &tegra_pll_m_out1,
3033 &tegra_pll_c,
3034 &tegra_pll_c_out1,
3035 &tegra_pll_p,
3036 &tegra_pll_p_out1,
3037 &tegra_pll_p_out2,
3038 &tegra_pll_p_out3,
3039 &tegra_pll_p_out4,
3040 &tegra_pll_a,
3041 &tegra_pll_a_out0,
3042 &tegra_pll_d,
3043 &tegra_pll_d_out0,
3044 &tegra_pll_d2,
3045 &tegra_pll_d2_out0,
3046 &tegra_pll_u,
3047 &tegra_pll_x,
3048 &tegra_pll_x_out0,
3049 &tegra_pll_e,
3050 &tegra_clk_cclk_g,
3051 &tegra_cml0_clk,
3052 &tegra_cml1_clk,
3053 &tegra_pciex_clk,
3054 &tegra_clk_sclk,
3055 &tegra_clk_blink,
3056 &tegra30_clk_twd,
3057};
3058
3059
3060static void tegra30_init_one_clock(struct clk *c)
3061{
3062 clk_init(c);
3063 INIT_LIST_HEAD(&c->shared_bus_list);
3064 if (!c->lookup.dev_id && !c->lookup.con_id)
3065 c->lookup.con_id = c->name;
3066 c->lookup.clk = c;
3067 clkdev_add(&c->lookup);
3068}
3069
3070void __init tegra30_init_clocks(void)
3071{
3072 int i;
3073 struct clk *c;
3074
3075 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
3076 tegra30_init_one_clock(tegra_ptr_clks[i]);
3077
3078 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
3079 tegra30_init_one_clock(&tegra_list_clks[i]);
3080
3081 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
3082 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
3083 if (!c) {
3084 pr_err("%s: Unknown duplicate clock %s\n", __func__,
3085 tegra_clk_duplicates[i].name);
3086 continue;
3087 }
3088
3089 tegra_clk_duplicates[i].lookup.clk = c;
3090 clkdev_add(&tegra_clk_duplicates[i].lookup);
3091 }
3092
3093 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
3094 tegra30_init_one_clock(&tegra_sync_source_list[i]);
3095 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
3096 tegra30_init_one_clock(&tegra_clk_audio_list[i]);
3097 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
3098 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
3099
3100 init_clk_out_mux();
3101 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
3102 tegra30_init_one_clock(&tegra_clk_out_list[i]);
3103
3104}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f2f88fef6b8b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H
19
20extern struct clk_ops tegra30_clk_32k_ops;
21extern struct clk_ops tegra30_clk_m_ops;
22extern struct clk_ops tegra_clk_m_div_ops;
23extern struct clk_ops tegra_pll_ref_ops;
24extern struct clk_ops tegra30_pll_ops;
25extern struct clk_ops tegra30_pll_div_ops;
26extern struct clk_ops tegra_plld_ops;
27extern struct clk_ops tegra30_plle_ops;
28extern struct clk_ops tegra_cml_clk_ops;
29extern struct clk_ops tegra_pciex_clk_ops;
30extern struct clk_ops tegra_sync_source_ops;
31extern struct clk_ops tegra30_audio_sync_clk_ops;
32extern struct clk_ops tegra30_clk_double_ops;
33extern struct clk_ops tegra_clk_out_ops;
34extern struct clk_ops tegra30_super_ops;
35extern struct clk_ops tegra30_blink_clk_ops;
36extern struct clk_ops tegra30_twd_ops;
37extern struct clk_ops tegra30_periph_clk_ops;
38extern struct clk_ops tegra30_dsib_clk_ops;
39extern struct clk_ops tegra_nand_clk_ops;
40extern struct clk_ops tegra_vi_clk_ops;
41extern struct clk_ops tegra_dtv_clk_ops;
42extern struct clk_ops tegra_clk_shared_bus_ops;
43
44int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
45 enum tegra_clk_ex_param p, u32 setting);
46void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
47int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
48 enum tegra_clk_ex_param p, u32 setting);
49int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
50 enum tegra_clk_ex_param p, u32 setting);
51int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
52 enum tegra_clk_ex_param p, u32 setting);
53#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..34b61a4934a3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1369 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/cpufreq.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra30_clocks.h"
35
36#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
37 _parent_names, _parents, _parent) \
38 static struct clk tegra_##_name = { \
39 .hw = &tegra_##_name##_hw.hw, \
40 .name = #_name, \
41 .rate = _rate, \
42 .ops = _ops, \
43 .flags = _flags, \
44 .parent_names = _parent_names, \
45 .parents = _parents, \
46 .num_parents = ARRAY_SIZE(_parent_names), \
47 .parent = _parent, \
48 };
49
50static struct clk tegra_clk_32k;
51static struct clk_tegra tegra_clk_32k_hw = {
52 .hw = {
53 .clk = &tegra_clk_32k,
54 },
55 .fixed_rate = 32768,
56};
57static struct clk tegra_clk_32k = {
58 .name = "clk_32k",
59 .hw = &tegra_clk_32k_hw.hw,
60 .ops = &tegra30_clk_32k_ops,
61 .flags = CLK_IS_ROOT,
62};
63
64static struct clk tegra_clk_m;
65static struct clk_tegra tegra_clk_m_hw = {
66 .hw = {
67 .clk = &tegra_clk_m,
68 },
69 .flags = ENABLE_ON_INIT,
70 .reg = 0x1fc,
71 .reg_shift = 28,
72 .max_rate = 48000000,
73};
74static struct clk tegra_clk_m = {
75 .name = "clk_m",
76 .hw = &tegra_clk_m_hw.hw,
77 .ops = &tegra30_clk_m_ops,
78 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
79};
80
81static const char *clk_m_div_parent_names[] = {
82 "clk_m",
83};
84
85static struct clk *clk_m_div_parents[] = {
86 &tegra_clk_m,
87};
88
89static struct clk tegra_clk_m_div2;
90static struct clk_tegra tegra_clk_m_div2_hw = {
91 .hw = {
92 .clk = &tegra_clk_m_div2,
93 },
94 .mul = 1,
95 .div = 2,
96 .max_rate = 24000000,
97};
98DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
99 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
100
101static struct clk tegra_clk_m_div4;
102static struct clk_tegra tegra_clk_m_div4_hw = {
103 .hw = {
104 .clk = &tegra_clk_m_div4,
105 },
106 .mul = 1,
107 .div = 4,
108 .max_rate = 12000000,
109};
110DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
111 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
112
113static struct clk tegra_pll_ref;
114static struct clk_tegra tegra_pll_ref_hw = {
115 .hw = {
116 .clk = &tegra_pll_ref,
117 },
118 .flags = ENABLE_ON_INIT,
119 .max_rate = 26000000,
120};
121DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
122 clk_m_div_parents, &tegra_clk_m);
123
124#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
125 _input_max, _cf_min, _cf_max, _vco_min, \
126 _vco_max, _freq_table, _lock_delay, _ops, \
127 _fixed_rate, _clk_cfg_ex, _parent) \
128 static struct clk tegra_##_name; \
129 static const char *_name##_parent_names[] = { \
130 #_parent, \
131 }; \
132 static struct clk *_name##_parents[] = { \
133 &tegra_##_parent, \
134 }; \
135 static struct clk_tegra tegra_##_name##_hw = { \
136 .hw = { \
137 .clk = &tegra_##_name, \
138 }, \
139 .flags = _flags, \
140 .reg = _reg, \
141 .max_rate = _max_rate, \
142 .u.pll = { \
143 .input_min = _input_min, \
144 .input_max = _input_max, \
145 .cf_min = _cf_min, \
146 .cf_max = _cf_max, \
147 .vco_min = _vco_min, \
148 .vco_max = _vco_max, \
149 .freq_table = _freq_table, \
150 .lock_delay = _lock_delay, \
151 .fixed_rate = _fixed_rate, \
152 }, \
153 .clk_cfg_ex = _clk_cfg_ex, \
154 }; \
155 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
156 _name##_parent_names, _name##_parents, \
157 &tegra_##_parent);
158
159#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
160 _max_rate, _ops, _parent, _clk_flags) \
161 static const char *_name##_parent_names[] = { \
162 #_parent, \
163 }; \
164 static struct clk *_name##_parents[] = { \
165 &tegra_##_parent, \
166 }; \
167 static struct clk tegra_##_name; \
168 static struct clk_tegra tegra_##_name##_hw = { \
169 .hw = { \
170 .clk = &tegra_##_name, \
171 }, \
172 .flags = _flags, \
173 .reg = _reg, \
174 .max_rate = _max_rate, \
175 .reg_shift = _reg_shift, \
176 }; \
177 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
178 _clk_flags, _name##_parent_names, \
179 _name##_parents, &tegra_##_parent);
180
181static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
182 { 12000000, 1040000000, 520, 6, 1, 8},
183 { 13000000, 1040000000, 480, 6, 1, 8},
184 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
185 { 19200000, 1040000000, 325, 6, 1, 6},
186 { 26000000, 1040000000, 520, 13, 1, 8},
187
188 { 12000000, 832000000, 416, 6, 1, 8},
189 { 13000000, 832000000, 832, 13, 1, 8},
190 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
191 { 19200000, 832000000, 260, 6, 1, 8},
192 { 26000000, 832000000, 416, 13, 1, 8},
193
194 { 12000000, 624000000, 624, 12, 1, 8},
195 { 13000000, 624000000, 624, 13, 1, 8},
196 { 16800000, 600000000, 520, 14, 1, 8},
197 { 19200000, 624000000, 520, 16, 1, 8},
198 { 26000000, 624000000, 624, 26, 1, 8},
199
200 { 12000000, 600000000, 600, 12, 1, 8},
201 { 13000000, 600000000, 600, 13, 1, 8},
202 { 16800000, 600000000, 500, 14, 1, 8},
203 { 19200000, 600000000, 375, 12, 1, 6},
204 { 26000000, 600000000, 600, 26, 1, 8},
205
206 { 12000000, 520000000, 520, 12, 1, 8},
207 { 13000000, 520000000, 520, 13, 1, 8},
208 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
209 { 19200000, 520000000, 325, 12, 1, 6},
210 { 26000000, 520000000, 520, 26, 1, 8},
211
212 { 12000000, 416000000, 416, 12, 1, 8},
213 { 13000000, 416000000, 416, 13, 1, 8},
214 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
215 { 19200000, 416000000, 260, 12, 1, 6},
216 { 26000000, 416000000, 416, 26, 1, 8},
217 { 0, 0, 0, 0, 0, 0 },
218};
219
220DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
221 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
222 tegra30_pll_ops, 0, NULL, pll_ref);
223
224DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
225 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
226
227static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
228 { 12000000, 666000000, 666, 12, 1, 8},
229 { 13000000, 666000000, 666, 13, 1, 8},
230 { 16800000, 666000000, 555, 14, 1, 8},
231 { 19200000, 666000000, 555, 16, 1, 8},
232 { 26000000, 666000000, 666, 26, 1, 8},
233 { 12000000, 600000000, 600, 12, 1, 8},
234 { 13000000, 600000000, 600, 13, 1, 8},
235 { 16800000, 600000000, 500, 14, 1, 8},
236 { 19200000, 600000000, 375, 12, 1, 6},
237 { 26000000, 600000000, 600, 26, 1, 8},
238 { 0, 0, 0, 0, 0, 0 },
239};
240
241DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
242 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
243 300, tegra30_pll_ops, 0, NULL, pll_ref);
244
245DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
246 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
247
248static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
249 { 12000000, 216000000, 432, 12, 2, 8},
250 { 13000000, 216000000, 432, 13, 2, 8},
251 { 16800000, 216000000, 360, 14, 2, 8},
252 { 19200000, 216000000, 360, 16, 2, 8},
253 { 26000000, 216000000, 432, 26, 2, 8},
254 { 0, 0, 0, 0, 0, 0 },
255};
256
257DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
258 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
259 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
260 pll_ref);
261
262DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
263 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
264DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
265 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
266DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
267 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
268DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
269 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
270
271static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
272 { 9600000, 564480000, 294, 5, 1, 4},
273 { 9600000, 552960000, 288, 5, 1, 4},
274 { 9600000, 24000000, 5, 2, 1, 1},
275
276 { 28800000, 56448000, 49, 25, 1, 1},
277 { 28800000, 73728000, 64, 25, 1, 1},
278 { 28800000, 24000000, 5, 6, 1, 1},
279 { 0, 0, 0, 0, 0, 0 },
280};
281
282DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
283 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
284 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
285
286DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
287 pll_a, CLK_IGNORE_UNUSED);
288
289static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
290 { 12000000, 216000000, 216, 12, 1, 4},
291 { 13000000, 216000000, 216, 13, 1, 4},
292 { 16800000, 216000000, 180, 14, 1, 4},
293 { 19200000, 216000000, 180, 16, 1, 4},
294 { 26000000, 216000000, 216, 26, 1, 4},
295
296 { 12000000, 594000000, 594, 12, 1, 8},
297 { 13000000, 594000000, 594, 13, 1, 8},
298 { 16800000, 594000000, 495, 14, 1, 8},
299 { 19200000, 594000000, 495, 16, 1, 8},
300 { 26000000, 594000000, 594, 26, 1, 8},
301
302 { 12000000, 1000000000, 1000, 12, 1, 12},
303 { 13000000, 1000000000, 1000, 13, 1, 12},
304 { 19200000, 1000000000, 625, 12, 1, 8},
305 { 26000000, 1000000000, 1000, 26, 1, 12},
306
307 { 0, 0, 0, 0, 0, 0 },
308};
309
310DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
311 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
312 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
313
314DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
315 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
316
317DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
318 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
319 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
320 pll_ref);
321
322DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
323 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
324
325static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
326 { 12000000, 480000000, 960, 12, 2, 12},
327 { 13000000, 480000000, 960, 13, 2, 12},
328 { 16800000, 480000000, 400, 7, 2, 5},
329 { 19200000, 480000000, 200, 4, 2, 3},
330 { 26000000, 480000000, 960, 26, 2, 12},
331 { 0, 0, 0, 0, 0, 0 },
332};
333
334DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
335 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
336 1000, tegra30_pll_ops, 0, NULL, pll_ref);
337
338static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
339 /* 1.7 GHz */
340 { 12000000, 1700000000, 850, 6, 1, 8},
341 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
342 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
344 { 26000000, 1700000000, 850, 13, 1, 8},
345
346 /* 1.6 GHz */
347 { 12000000, 1600000000, 800, 6, 1, 8},
348 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
349 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
350 { 19200000, 1600000000, 500, 6, 1, 8},
351 { 26000000, 1600000000, 800, 13, 1, 8},
352
353 /* 1.5 GHz */
354 { 12000000, 1500000000, 750, 6, 1, 8},
355 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
356 { 16800000, 1500000000, 625, 7, 1, 8},
357 { 19200000, 1500000000, 625, 8, 1, 8},
358 { 26000000, 1500000000, 750, 13, 1, 8},
359
360 /* 1.4 GHz */
361 { 12000000, 1400000000, 700, 6, 1, 8},
362 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
363 { 16800000, 1400000000, 1000, 12, 1, 8},
364 { 19200000, 1400000000, 875, 12, 1, 8},
365 { 26000000, 1400000000, 700, 13, 1, 8},
366
367 /* 1.3 GHz */
368 { 12000000, 1300000000, 975, 9, 1, 8},
369 { 13000000, 1300000000, 1000, 10, 1, 8},
370 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
371 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 26000000, 1300000000, 650, 13, 1, 8},
373
374 /* 1.2 GHz */
375 { 12000000, 1200000000, 1000, 10, 1, 8},
376 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
377 { 16800000, 1200000000, 1000, 14, 1, 8},
378 { 19200000, 1200000000, 1000, 16, 1, 8},
379 { 26000000, 1200000000, 600, 13, 1, 8},
380
381 /* 1.1 GHz */
382 { 12000000, 1100000000, 825, 9, 1, 8},
383 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
384 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
385 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
386 { 26000000, 1100000000, 550, 13, 1, 8},
387
388 /* 1 GHz */
389 { 12000000, 1000000000, 1000, 12, 1, 8},
390 { 13000000, 1000000000, 1000, 13, 1, 8},
391 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
392 { 19200000, 1000000000, 625, 12, 1, 8},
393 { 26000000, 1000000000, 1000, 26, 1, 8},
394
395 { 0, 0, 0, 0, 0, 0 },
396};
397
398DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
399 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
400 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
401
402DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
403 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
404
405static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
406 /* PLLE special case: use cpcon field to store cml divider value */
407 { 12000000, 100000000, 150, 1, 18, 11},
408 { 216000000, 100000000, 200, 18, 24, 13},
409 { 0, 0, 0, 0, 0, 0 },
410};
411
412DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
413 12000000, 12000000, 1200000000, 2400000000U,
414 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
415 pll_ref);
416
417static const char *mux_plle[] = {
418 "pll_e",
419};
420
421static struct clk *mux_plle_p[] = {
422 &tegra_pll_e,
423};
424
425static struct clk tegra_cml0;
426static struct clk_tegra tegra_cml0_hw = {
427 .hw = {
428 .clk = &tegra_cml0,
429 },
430 .reg = 0x48c,
431 .fixed_rate = 100000000,
432 .u.periph = {
433 .clk_num = 0,
434 },
435};
436DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
437 mux_plle_p, &tegra_pll_e);
438
439static struct clk tegra_cml1;
440static struct clk_tegra tegra_cml1_hw = {
441 .hw = {
442 .clk = &tegra_cml1,
443 },
444 .reg = 0x48c,
445 .fixed_rate = 100000000,
446 .u.periph = {
447 .clk_num = 1,
448 },
449};
450DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
451 mux_plle_p, &tegra_pll_e);
452
453static struct clk tegra_pciex;
454static struct clk_tegra tegra_pciex_hw = {
455 .hw = {
456 .clk = &tegra_pciex,
457 },
458 .reg = 0x48c,
459 .fixed_rate = 100000000,
460 .reset = tegra30_periph_clk_reset,
461 .u.periph = {
462 .clk_num = 74,
463 },
464};
465DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
466 mux_plle_p, &tegra_pll_e);
467
468#define SYNC_SOURCE(_name) \
469 static struct clk tegra_##_name##_sync; \
470 static struct clk_tegra tegra_##_name##_sync_hw = { \
471 .hw = { \
472 .clk = &tegra_##_name##_sync, \
473 }, \
474 .max_rate = 24000000, \
475 .fixed_rate = 24000000, \
476 }; \
477 static struct clk tegra_##_name##_sync = { \
478 .name = #_name "_sync", \
479 .hw = &tegra_##_name##_sync_hw.hw, \
480 .ops = &tegra_sync_source_ops, \
481 .flags = CLK_IS_ROOT, \
482 };
483
484SYNC_SOURCE(spdif_in);
485SYNC_SOURCE(i2s0);
486SYNC_SOURCE(i2s1);
487SYNC_SOURCE(i2s2);
488SYNC_SOURCE(i2s3);
489SYNC_SOURCE(i2s4);
490SYNC_SOURCE(vimclk);
491
492static struct clk *tegra_sync_source_list[] = {
493 &tegra_spdif_in_sync,
494 &tegra_i2s0_sync,
495 &tegra_i2s1_sync,
496 &tegra_i2s2_sync,
497 &tegra_i2s3_sync,
498 &tegra_i2s4_sync,
499 &tegra_vimclk_sync,
500};
501
502static const char *mux_audio_sync_clk[] = {
503 "spdif_in_sync",
504 "i2s0_sync",
505 "i2s1_sync",
506 "i2s2_sync",
507 "i2s3_sync",
508 "i2s4_sync",
509 "vimclk_sync",
510};
511
512#define AUDIO_SYNC_CLK(_name, _index) \
513 static struct clk tegra_##_name; \
514 static struct clk_tegra tegra_##_name##_hw = { \
515 .hw = { \
516 .clk = &tegra_##_name, \
517 }, \
518 .max_rate = 24000000, \
519 .reg = 0x4A0 + (_index) * 4, \
520 }; \
521 static struct clk tegra_##_name = { \
522 .name = #_name, \
523 .ops = &tegra30_audio_sync_clk_ops, \
524 .hw = &tegra_##_name##_hw.hw, \
525 .parent_names = mux_audio_sync_clk, \
526 .parents = tegra_sync_source_list, \
527 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
528 };
529
530AUDIO_SYNC_CLK(audio0, 0);
531AUDIO_SYNC_CLK(audio1, 1);
532AUDIO_SYNC_CLK(audio2, 2);
533AUDIO_SYNC_CLK(audio3, 3);
534AUDIO_SYNC_CLK(audio4, 4);
535AUDIO_SYNC_CLK(audio5, 5);
536
537static struct clk *tegra_clk_audio_list[] = {
538 &tegra_audio0,
539 &tegra_audio1,
540 &tegra_audio2,
541 &tegra_audio3,
542 &tegra_audio4,
543 &tegra_audio5, /* SPDIF */
544};
545
546#define AUDIO_SYNC_2X_CLK(_name, _index) \
547 static const char *_name##_parent_names[] = { \
548 "tegra_" #_name, \
549 }; \
550 static struct clk *_name##_parents[] = { \
551 &tegra_##_name, \
552 }; \
553 static struct clk tegra_##_name##_2x; \
554 static struct clk_tegra tegra_##_name##_2x_hw = { \
555 .hw = { \
556 .clk = &tegra_##_name##_2x, \
557 }, \
558 .flags = PERIPH_NO_RESET, \
559 .max_rate = 48000000, \
560 .reg = 0x49C, \
561 .reg_shift = 24 + (_index), \
562 .u.periph = { \
563 .clk_num = 113 + (_index), \
564 }, \
565 }; \
566 static struct clk tegra_##_name##_2x = { \
567 .name = #_name "_2x", \
568 .ops = &tegra30_clk_double_ops, \
569 .hw = &tegra_##_name##_2x_hw.hw, \
570 .parent_names = _name##_parent_names, \
571 .parents = _name##_parents, \
572 .parent = &tegra_##_name, \
573 .num_parents = 1, \
574 };
575
576AUDIO_SYNC_2X_CLK(audio0, 0);
577AUDIO_SYNC_2X_CLK(audio1, 1);
578AUDIO_SYNC_2X_CLK(audio2, 2);
579AUDIO_SYNC_2X_CLK(audio3, 3);
580AUDIO_SYNC_2X_CLK(audio4, 4);
581AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
582
583static struct clk *tegra_clk_audio_2x_list[] = {
584 &tegra_audio0_2x,
585 &tegra_audio1_2x,
586 &tegra_audio2_2x,
587 &tegra_audio3_2x,
588 &tegra_audio4_2x,
589 &tegra_audio5_2x, /* SPDIF */
590};
591
592#define MUX_I2S_SPDIF(_id) \
593static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
594 "pll_a_out0", \
595 #_id "_2x", \
596 "pll_p", \
597 "clk_m", \
598}; \
599static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
600 &tegra_pll_a_out0, \
601 &tegra_##_id##_2x, \
602 &tegra_pll_p, \
603 &tegra_clk_m, \
604};
605
606MUX_I2S_SPDIF(audio0);
607MUX_I2S_SPDIF(audio1);
608MUX_I2S_SPDIF(audio2);
609MUX_I2S_SPDIF(audio3);
610MUX_I2S_SPDIF(audio4);
611MUX_I2S_SPDIF(audio5); /* SPDIF */
612
613static struct clk tegra_extern1;
614static struct clk tegra_extern2;
615static struct clk tegra_extern3;
616
617/* External clock outputs (through PMC) */
618#define MUX_EXTERN_OUT(_id) \
619static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
620 "clk_m", \
621 "clk_m_div2", \
622 "clk_m_div4", \
623 "extern" #_id, \
624}; \
625static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
626 &tegra_clk_m, \
627 &tegra_clk_m_div2, \
628 &tegra_clk_m_div4, \
629 &tegra_extern##_id, \
630};
631
632MUX_EXTERN_OUT(1);
633MUX_EXTERN_OUT(2);
634MUX_EXTERN_OUT(3);
635
636#define CLK_OUT_CLK(_name, _index) \
637 static struct clk tegra_##_name; \
638 static struct clk_tegra tegra_##_name##_hw = { \
639 .hw = { \
640 .clk = &tegra_##_name, \
641 }, \
642 .lookup = { \
643 .dev_id = #_name, \
644 .con_id = "extern" #_index, \
645 }, \
646 .flags = MUX_CLK_OUT, \
647 .fixed_rate = 216000000, \
648 .reg = 0x1a8, \
649 .u.periph = { \
650 .clk_num = (_index - 1) * 8 + 2, \
651 }, \
652 }; \
653 static struct clk tegra_##_name = { \
654 .name = #_name, \
655 .ops = &tegra_clk_out_ops, \
656 .hw = &tegra_##_name##_hw.hw, \
657 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
658 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
659 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
660 };
661
662CLK_OUT_CLK(clk_out_1, 1);
663CLK_OUT_CLK(clk_out_2, 2);
664CLK_OUT_CLK(clk_out_3, 3);
665
666static struct clk *tegra_clk_out_list[] = {
667 &tegra_clk_out_1,
668 &tegra_clk_out_2,
669 &tegra_clk_out_3,
670};
671
672static const char *mux_sclk[] = {
673 "clk_m",
674 "pll_c_out1",
675 "pll_p_out4",
676 "pll_p_out3",
677 "pll_p_out2",
678 "dummy",
679 "clk_32k",
680 "pll_m_out1",
681};
682
683static struct clk *mux_sclk_p[] = {
684 &tegra_clk_m,
685 &tegra_pll_c_out1,
686 &tegra_pll_p_out4,
687 &tegra_pll_p_out3,
688 &tegra_pll_p_out2,
689 NULL,
690 &tegra_clk_32k,
691 &tegra_pll_m_out1,
692};
693
694static struct clk tegra_clk_sclk;
695static struct clk_tegra tegra_clk_sclk_hw = {
696 .hw = {
697 .clk = &tegra_clk_sclk,
698 },
699 .reg = 0x28,
700 .max_rate = 334000000,
701 .min_rate = 40000000,
702};
703
704static struct clk tegra_clk_sclk = {
705 .name = "sclk",
706 .ops = &tegra30_super_ops,
707 .hw = &tegra_clk_sclk_hw.hw,
708 .parent_names = mux_sclk,
709 .parents = mux_sclk_p,
710 .num_parents = ARRAY_SIZE(mux_sclk),
711};
712
713static const char *mux_blink[] = {
714 "clk_32k",
715};
716
717static struct clk *mux_blink_p[] = {
718 &tegra_clk_32k,
719};
720
721static struct clk tegra_clk_blink;
722static struct clk_tegra tegra_clk_blink_hw = {
723 .hw = {
724 .clk = &tegra_clk_blink,
725 },
726 .reg = 0x40,
727 .max_rate = 32768,
728};
729static struct clk tegra_clk_blink = {
730 .name = "blink",
731 .ops = &tegra30_blink_clk_ops,
732 .hw = &tegra_clk_blink_hw.hw,
733 .parent = &tegra_clk_32k,
734 .parent_names = mux_blink,
735 .parents = mux_blink_p,
736 .num_parents = ARRAY_SIZE(mux_blink),
737};
738
739static const char *mux_pllm_pllc_pllp_plla[] = {
740 "pll_m",
741 "pll_c",
742 "pll_p",
743 "pll_a_out0",
744};
745
746static const char *mux_pllp_pllc_pllm_clkm[] = {
747 "pll_p",
748 "pll_c",
749 "pll_m",
750 "clk_m",
751};
752
753static const char *mux_pllp_clkm[] = {
754 "pll_p",
755 "dummy",
756 "dummy",
757 "clk_m",
758};
759
760static const char *mux_pllp_plld_pllc_clkm[] = {
761 "pll_p",
762 "pll_d_out0",
763 "pll_c",
764 "clk_m",
765};
766
767static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
768 "pll_p",
769 "pll_m",
770 "pll_d_out0",
771 "pll_a_out0",
772 "pll_c",
773 "pll_d2_out0",
774 "clk_m",
775};
776
777static const char *mux_plla_pllc_pllp_clkm[] = {
778 "pll_a_out0",
779 "dummy",
780 "pll_p",
781 "clk_m"
782};
783
784static const char *mux_pllp_pllc_clk32_clkm[] = {
785 "pll_p",
786 "pll_c",
787 "clk_32k",
788 "clk_m",
789};
790
791static const char *mux_pllp_pllc_clkm_clk32[] = {
792 "pll_p",
793 "pll_c",
794 "clk_m",
795 "clk_32k",
796};
797
798static const char *mux_pllp_pllc_pllm[] = {
799 "pll_p",
800 "pll_c",
801 "pll_m",
802};
803
804static const char *mux_clk_m[] = {
805 "clk_m",
806};
807
808static const char *mux_pllp_out3[] = {
809 "pll_p_out3",
810};
811
812static const char *mux_plld_out0[] = {
813 "pll_d_out0",
814};
815
816static const char *mux_plld_out0_plld2_out0[] = {
817 "pll_d_out0",
818 "pll_d2_out0",
819};
820
821static const char *mux_clk_32k[] = {
822 "clk_32k",
823};
824
825static const char *mux_plla_clk32_pllp_clkm_plle[] = {
826 "pll_a_out0",
827 "clk_32k",
828 "pll_p",
829 "clk_m",
830 "pll_e",
831};
832
833static const char *mux_cclk_g[] = {
834 "clk_m",
835 "pll_c",
836 "clk_32k",
837 "pll_m",
838 "pll_p",
839 "pll_p_out4",
840 "pll_p_out3",
841 "dummy",
842 "pll_x",
843};
844
845static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
846 &tegra_pll_m,
847 &tegra_pll_c,
848 &tegra_pll_p,
849 &tegra_pll_a_out0,
850};
851
852static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
853 &tegra_pll_p,
854 &tegra_pll_c,
855 &tegra_pll_m,
856 &tegra_clk_m,
857};
858
859static struct clk *mux_pllp_clkm_p[] = {
860 &tegra_pll_p,
861 NULL,
862 NULL,
863 &tegra_clk_m,
864};
865
866static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
867 &tegra_pll_p,
868 &tegra_pll_d_out0,
869 &tegra_pll_c,
870 &tegra_clk_m,
871};
872
873static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
874 &tegra_pll_p,
875 &tegra_pll_m,
876 &tegra_pll_d_out0,
877 &tegra_pll_a_out0,
878 &tegra_pll_c,
879 &tegra_pll_d2_out0,
880 &tegra_clk_m,
881};
882
883static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
884 &tegra_pll_a_out0,
885 NULL,
886 &tegra_pll_p,
887 &tegra_clk_m,
888};
889
890static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
891 &tegra_pll_p,
892 &tegra_pll_c,
893 &tegra_clk_32k,
894 &tegra_clk_m,
895};
896
897static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
898 &tegra_pll_p,
899 &tegra_pll_c,
900 &tegra_clk_m,
901 &tegra_clk_32k,
902};
903
904static struct clk *mux_pllp_pllc_pllm_p[] = {
905 &tegra_pll_p,
906 &tegra_pll_c,
907 &tegra_pll_m,
908};
909
910static struct clk *mux_clk_m_p[] = {
911 &tegra_clk_m,
912};
913
914static struct clk *mux_pllp_out3_p[] = {
915 &tegra_pll_p_out3,
916};
917
918static struct clk *mux_plld_out0_p[] = {
919 &tegra_pll_d_out0,
920};
921
922static struct clk *mux_plld_out0_plld2_out0_p[] = {
923 &tegra_pll_d_out0,
924 &tegra_pll_d2_out0,
925};
926
927static struct clk *mux_clk_32k_p[] = {
928 &tegra_clk_32k,
929};
930
931static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
932 &tegra_pll_a_out0,
933 &tegra_clk_32k,
934 &tegra_pll_p,
935 &tegra_clk_m,
936 &tegra_pll_e,
937};
938
939static struct clk *mux_cclk_g_p[] = {
940 &tegra_clk_m,
941 &tegra_pll_c,
942 &tegra_clk_32k,
943 &tegra_pll_m,
944 &tegra_pll_p,
945 &tegra_pll_p_out4,
946 &tegra_pll_p_out3,
947 NULL,
948 &tegra_pll_x,
949};
950
951static struct clk tegra_clk_cclk_g;
952static struct clk_tegra tegra_clk_cclk_g_hw = {
953 .hw = {
954 .clk = &tegra_clk_cclk_g,
955 },
956 .flags = DIV_U71 | DIV_U71_INT,
957 .reg = 0x368,
958 .max_rate = 1700000000,
959};
960static struct clk tegra_clk_cclk_g = {
961 .name = "cclk_g",
962 .ops = &tegra30_super_ops,
963 .hw = &tegra_clk_cclk_g_hw.hw,
964 .parent_names = mux_cclk_g,
965 .parents = mux_cclk_g_p,
966 .num_parents = ARRAY_SIZE(mux_cclk_g),
967};
968
969static const char *mux_twd[] = {
970 "cclk_g",
971};
972
973static struct clk *mux_twd_p[] = {
974 &tegra_clk_cclk_g,
975};
976
977static struct clk tegra30_clk_twd;
978static struct clk_tegra tegra30_clk_twd_hw = {
979 .hw = {
980 .clk = &tegra30_clk_twd,
981 },
982 .max_rate = 1400000000,
983 .mul = 1,
984 .div = 2,
985};
986
987static struct clk tegra30_clk_twd = {
988 .name = "twd",
989 .ops = &tegra30_twd_ops,
990 .hw = &tegra30_clk_twd_hw.hw,
991 .parent = &tegra_clk_cclk_g,
992 .parent_names = mux_twd,
993 .parents = mux_twd_p,
994 .num_parents = ARRAY_SIZE(mux_twd),
995};
996
997#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
998 _max, _inputs, _flags) \
999 static struct clk tegra_##_name; \
1000 static struct clk_tegra tegra_##_name##_hw = { \
1001 .hw = { \
1002 .clk = &tegra_##_name, \
1003 }, \
1004 .lookup = { \
1005 .dev_id = _dev, \
1006 .con_id = _con, \
1007 }, \
1008 .reg = _reg, \
1009 .flags = _flags, \
1010 .max_rate = _max, \
1011 .u.periph = { \
1012 .clk_num = _clk_num, \
1013 }, \
1014 .reset = &tegra30_periph_clk_reset, \
1015 }; \
1016 static struct clk tegra_##_name = { \
1017 .name = #_name, \
1018 .ops = &tegra30_periph_clk_ops, \
1019 .hw = &tegra_##_name##_hw.hw, \
1020 .parent_names = _inputs, \
1021 .parents = _inputs##_p, \
1022 .num_parents = ARRAY_SIZE(_inputs), \
1023 };
1024
1025PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1026PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1027PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1028PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1029PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1030PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1031PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1032PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1033PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1034PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1035PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1036PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1037PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1038PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1039PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1040PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1041PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1042PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1043PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1044PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1045PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1046PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1047PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1048PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1049PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1050PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1051PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1052PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1053PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1054PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1055PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1056PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1057PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1058PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1059PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1060PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1061PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1062PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1063PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1064PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1065PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1066PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1067PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1068PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1069PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1070PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1071PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1072PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1073PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1074PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1079PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1082PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1083PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1084PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1085PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1086PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1087PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1088PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1089PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1090PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1091PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1092PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1093PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1094PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1095PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1096PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1097PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1098PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1099PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1100PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1101PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1102PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1103PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1104PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1105PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1106PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1107PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1108PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1109PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1110PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1111PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1112PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1113PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1114
1115static struct clk tegra_dsib;
1116static struct clk_tegra tegra_dsib_hw = {
1117 .hw = {
1118 .clk = &tegra_dsib,
1119 },
1120 .lookup = {
1121 .dev_id = "tegradc.1",
1122 .con_id = "dsib",
1123 },
1124 .reg = 0xd0,
1125 .flags = MUX | PLLD,
1126 .max_rate = 500000000,
1127 .u.periph = {
1128 .clk_num = 82,
1129 },
1130 .reset = &tegra30_periph_clk_reset,
1131};
1132static struct clk tegra_dsib = {
1133 .name = "dsib",
1134 .ops = &tegra30_dsib_clk_ops,
1135 .hw = &tegra_dsib_hw.hw,
1136 .parent_names = mux_plld_out0_plld2_out0,
1137 .parents = mux_plld_out0_plld2_out0_p,
1138 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1139};
1140
1141struct clk *tegra_list_clks[] = {
1142 &tegra_apbdma,
1143 &tegra_rtc,
1144 &tegra_kbc,
1145 &tegra_kfuse,
1146 &tegra_fuse,
1147 &tegra_fuse_burn,
1148 &tegra_apbif,
1149 &tegra_i2s0,
1150 &tegra_i2s1,
1151 &tegra_i2s2,
1152 &tegra_i2s3,
1153 &tegra_i2s4,
1154 &tegra_spdif_out,
1155 &tegra_spdif_in,
1156 &tegra_pwm,
1157 &tegra_d_audio,
1158 &tegra_dam0,
1159 &tegra_dam1,
1160 &tegra_dam2,
1161 &tegra_hda,
1162 &tegra_hda2codec_2x,
1163 &tegra_hda2hdmi,
1164 &tegra_sbc1,
1165 &tegra_sbc2,
1166 &tegra_sbc3,
1167 &tegra_sbc4,
1168 &tegra_sbc5,
1169 &tegra_sbc6,
1170 &tegra_sata_oob,
1171 &tegra_sata,
1172 &tegra_sata_cold,
1173 &tegra_ndflash,
1174 &tegra_ndspeed,
1175 &tegra_vfir,
1176 &tegra_sdmmc1,
1177 &tegra_sdmmc2,
1178 &tegra_sdmmc3,
1179 &tegra_sdmmc4,
1180 &tegra_vcp,
1181 &tegra_bsea,
1182 &tegra_bsev,
1183 &tegra_vde,
1184 &tegra_csite,
1185 &tegra_la,
1186 &tegra_owr,
1187 &tegra_nor,
1188 &tegra_mipi,
1189 &tegra_i2c1,
1190 &tegra_i2c2,
1191 &tegra_i2c3,
1192 &tegra_i2c4,
1193 &tegra_i2c5,
1194 &tegra_uarta,
1195 &tegra_uartb,
1196 &tegra_uartc,
1197 &tegra_uartd,
1198 &tegra_uarte,
1199 &tegra_vi,
1200 &tegra_3d,
1201 &tegra_3d2,
1202 &tegra_2d,
1203 &tegra_vi_sensor,
1204 &tegra_epp,
1205 &tegra_mpe,
1206 &tegra_host1x,
1207 &tegra_cve,
1208 &tegra_tvo,
1209 &tegra_dtv,
1210 &tegra_hdmi,
1211 &tegra_tvdac,
1212 &tegra_disp1,
1213 &tegra_disp2,
1214 &tegra_usbd,
1215 &tegra_usb2,
1216 &tegra_usb3,
1217 &tegra_dsia,
1218 &tegra_dsib,
1219 &tegra_csi,
1220 &tegra_isp,
1221 &tegra_csus,
1222 &tegra_tsensor,
1223 &tegra_actmon,
1224 &tegra_extern1,
1225 &tegra_extern2,
1226 &tegra_extern3,
1227 &tegra_i2cslow,
1228 &tegra_pcie,
1229 &tegra_afi,
1230 &tegra_se,
1231};
1232
1233#define CLK_DUPLICATE(_name, _dev, _con) \
1234 { \
1235 .name = _name, \
1236 .lookup = { \
1237 .dev_id = _dev, \
1238 .con_id = _con, \
1239 }, \
1240 }
1241
1242/* Some clocks may be used by different drivers depending on the board
1243 * configuration. List those here to register them twice in the clock lookup
1244 * table under two names.
1245 */
1246struct clk_duplicate tegra_clk_duplicates[] = {
1247 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1248 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1249 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1250 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1251 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1252 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1253 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1254 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1255 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1256 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1257 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1258 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1259 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1260 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1261 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1262 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1263 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1264 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1265 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1266 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1267 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1268 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1269 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1270 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1271 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1272 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1273 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1274 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1275 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1276 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1277 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1278 CLK_DUPLICATE("twd", "smp_twd", NULL),
1279 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1280 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1281 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1282 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1283 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1284 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1285 CLK_DUPLICATE("dam0", NULL, "dam0"),
1286 CLK_DUPLICATE("dam1", NULL, "dam1"),
1287 CLK_DUPLICATE("dam2", NULL, "dam2"),
1288 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1289};
1290
1291struct clk *tegra_ptr_clks[] = {
1292 &tegra_clk_32k,
1293 &tegra_clk_m,
1294 &tegra_clk_m_div2,
1295 &tegra_clk_m_div4,
1296 &tegra_pll_ref,
1297 &tegra_pll_m,
1298 &tegra_pll_m_out1,
1299 &tegra_pll_c,
1300 &tegra_pll_c_out1,
1301 &tegra_pll_p,
1302 &tegra_pll_p_out1,
1303 &tegra_pll_p_out2,
1304 &tegra_pll_p_out3,
1305 &tegra_pll_p_out4,
1306 &tegra_pll_a,
1307 &tegra_pll_a_out0,
1308 &tegra_pll_d,
1309 &tegra_pll_d_out0,
1310 &tegra_pll_d2,
1311 &tegra_pll_d2_out0,
1312 &tegra_pll_u,
1313 &tegra_pll_x,
1314 &tegra_pll_x_out0,
1315 &tegra_pll_e,
1316 &tegra_clk_cclk_g,
1317 &tegra_cml0,
1318 &tegra_cml1,
1319 &tegra_pciex,
1320 &tegra_clk_sclk,
1321 &tegra_clk_blink,
1322 &tegra30_clk_twd,
1323};
1324
1325static void tegra30_init_one_clock(struct clk *c)
1326{
1327 struct clk_tegra *clk = to_clk_tegra(c->hw);
1328 __clk_init(NULL, c);
1329 INIT_LIST_HEAD(&clk->shared_bus_list);
1330 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1331 clk->lookup.con_id = c->name;
1332 clk->lookup.clk = c;
1333 clkdev_add(&clk->lookup);
1334 tegra_clk_add(c);
1335}
1336
1337void __init tegra30_init_clocks(void)
1338{
1339 int i;
1340 struct clk *c;
1341
1342 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1343 tegra30_init_one_clock(tegra_ptr_clks[i]);
1344
1345 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1346 tegra30_init_one_clock(tegra_list_clks[i]);
1347
1348 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1349 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1350 if (!c) {
1351 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1352 tegra_clk_duplicates[i].name);
1353 continue;
1354 }
1355
1356 tegra_clk_duplicates[i].lookup.clk = c;
1357 clkdev_add(&tegra_clk_duplicates[i].lookup);
1358 }
1359
1360 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1361 tegra30_init_one_clock(tegra_sync_source_list[i]);
1362 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1363 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1364 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1365 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1366
1367 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1368 tegra30_init_one_clock(tegra_clk_out_list[i]);
1369}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 23:48:42 -0500