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authorOlof Johansson <olof@lixom.net>2012-09-16 20:15:29 -0400
committerOlof Johansson <olof@lixom.net>2012-09-16 20:15:29 -0400
commit26a806c064b7be25fc7c255b5d83646cf4645a93 (patch)
tree9fa30cb5b806f37ebf1a0c9f99d7b596a417a0b7
parente5567598c61907187261aba7095ac825d8060827 (diff)
parent7852399cc666fda491e481575bdbf61bace58f00 (diff)
Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
ARM i.MX SoC updates * tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6: ARM: i.MX35: Implement camera and keypad clocks ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible ARM i.MX53: register CAN clocks arm imx31: add a few pinmux settings the tt01 needs
-rw-r--r--arch/arm/mach-imx/clk-imx35.c11
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c14
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h5
-rw-r--r--arch/arm/plat-mxc/ssi-fiq.S89
4 files changed, 75 insertions, 44 deletions
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb10bae..cebc71d5a5af 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@ enum mx35_clks {
62 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, 62 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
63 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, 63 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
64 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, 64 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
65 wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate, 65 wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
66 clk_max 66 gpu2d_gate, clk_max
67}; 67};
68 68
69static struct clk *clk[clk_max]; 69static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@ int __init mx35_clocks_init()
142 142
143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); 143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
144 144
145 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
146 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
147
145 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); 148 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
146 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); 149 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
147 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); 150 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
@@ -192,7 +195,7 @@ int __init mx35_clocks_init()
192 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); 195 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
193 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); 196 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
194 197
195 clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0); 198 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
196 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); 199 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
197 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); 200 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
198 201
@@ -228,6 +231,7 @@ int __init mx35_clocks_init()
228 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2"); 231 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
229 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); 232 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
230 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); 233 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
234 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
231 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); 235 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
232 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 236 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
233 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0"); 237 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
@@ -255,6 +259,7 @@ int __init mx35_clocks_init()
255 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); 259 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
256 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 260 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
257 clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0"); 261 clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
262 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
258 263
259 clk_prepare_enable(clk[spba_gate]); 264 clk_prepare_enable(clk[spba_gate]);
260 clk_prepare_enable(clk[gpio1_gate]); 265 clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa97bd98..db70d23f95fa 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -49,6 +49,7 @@ static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
49static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; 49static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
50static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 50static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
51static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 51static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
52static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
52 53
53enum imx5_clks { 54enum imx5_clks {
54 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, 55 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@ enum imx5_clks {
82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, 83 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, 84 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, 85 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
86 can_sel, can1_serial_gate, can1_ipg_gate,
85 clk_max 87 clk_max
86}; 88};
87 89
@@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
421 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 423 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
422 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); 424 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
423 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); 425 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
424 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6); 426 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
425 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); 427 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
428 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
429 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
430 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
431 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
426 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 432 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
427 433
428 for (i = 0; i < ARRAY_SIZE(clk); i++) 434 for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
455 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi"); 461 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
456 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi"); 462 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
457 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi"); 463 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
464 clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
465 clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
466 clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
467 clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
458 468
459 /* set SDHC root clock to 200MHZ*/ 469 /* set SDHC root clock to 200MHZ*/
460 clk_set_rate(clk[esdhc_a_podf], 200000000); 470 clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index d8b65b51f2a9..f79f78a1c0ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -512,12 +512,16 @@ enum iomux_pins {
512#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) 512#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
513#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) 513#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
514#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) 514#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
515#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
515#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) 516#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
517#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
516#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) 518#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
519#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
517#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) 520#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
518#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) 521#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
519#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) 522#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
520#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) 523#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
524#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
521#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) 525#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
522#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) 526#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
523#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) 527#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
@@ -721,6 +725,7 @@ enum iomux_pins {
721#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) 725#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
722#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) 726#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
723#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) 727#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
724#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) 729#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
725#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) 730#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
726#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) 731#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2dd19f2..a8b93c5f29b5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
34 .global imx_ssi_fiq_rx_buffer 34 .global imx_ssi_fiq_rx_buffer
35 .global imx_ssi_fiq_tx_buffer 35 .global imx_ssi_fiq_tx_buffer
36 36
37/*
38 * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
39 * using ENDPROC(). imx_ssi_fiq_start and imx_ssi_fiq_end are used to
40 * mark the function body so that it can be copied to the FIQ vector in
41 * the vectors page. imx_ssi_fiq_start should only be called as the result
42 * of an FIQ: calling it directly will not work.
43 */
37imx_ssi_fiq_start: 44imx_ssi_fiq_start:
38 ldr r12, imx_ssi_fiq_base 45 ldr r12, .L_imx_ssi_fiq_base
39 46
40 /* TX */ 47 /* TX */
41 ldr r11, imx_ssi_fiq_tx_buffer 48 ldr r13, .L_imx_ssi_fiq_tx_buffer
42 49
43 /* shall we send? */ 50 /* shall we send? */
44 ldr r13, [r12, #SSI_SIER] 51 ldr r11, [r12, #SSI_SIER]
45 tst r13, #SSI_SIER_TFE0_EN 52 tst r11, #SSI_SIER_TFE0_EN
46 beq 1f 53 beq 1f
47 54
48 /* TX FIFO empty? */ 55 /* TX FIFO empty? */
49 ldr r13, [r12, #SSI_SISR] 56 ldr r11, [r12, #SSI_SISR]
50 tst r13, #SSI_SISR_TFE0 57 tst r11, #SSI_SISR_TFE0
51 beq 1f 58 beq 1f
52 59
53 mov r10, #0x10000 60 mov r10, #0x10000
54 sub r10, #1 61 sub r10, #1
55 and r10, r10, r8 /* r10: current buffer offset */ 62 and r10, r10, r8 /* r10: current buffer offset */
56 63
57 add r11, r11, r10 64 add r13, r13, r10
58 65
59 ldrh r13, [r11] 66 ldrh r11, [r13]
60 strh r13, [r12, #SSI_STX0] 67 strh r11, [r12, #SSI_STX0]
61 68
62 ldrh r13, [r11, #2] 69 ldrh r11, [r13, #2]
63 strh r13, [r12, #SSI_STX0] 70 strh r11, [r12, #SSI_STX0]
64 71
65 ldrh r13, [r11, #4] 72 ldrh r11, [r13, #4]
66 strh r13, [r12, #SSI_STX0] 73 strh r11, [r12, #SSI_STX0]
67 74
68 ldrh r13, [r11, #6] 75 ldrh r11, [r13, #6]
69 strh r13, [r12, #SSI_STX0] 76 strh r11, [r12, #SSI_STX0]
70 77
71 add r10, #8 78 add r10, #8
72 lsr r13, r8, #16 /* r13: buffer size */ 79 lsr r11, r8, #16 /* r11: buffer size */
73 cmp r10, r13 80 cmp r10, r11
74 lslgt r8, r13, #16 81 lslgt r8, r11, #16
75 addle r8, #8 82 addle r8, #8
761: 831:
77 /* RX */ 84 /* RX */
78 85
79 /* shall we receive? */ 86 /* shall we receive? */
80 ldr r13, [r12, #SSI_SIER] 87 ldr r11, [r12, #SSI_SIER]
81 tst r13, #SSI_SIER_RFF0_EN 88 tst r11, #SSI_SIER_RFF0_EN
82 beq 1f 89 beq 1f
83 90
84 /* RX FIFO full? */ 91 /* RX FIFO full? */
85 ldr r13, [r12, #SSI_SISR] 92 ldr r11, [r12, #SSI_SISR]
86 tst r13, #SSI_SISR_RFF0 93 tst r11, #SSI_SISR_RFF0
87 beq 1f 94 beq 1f
88 95
89 ldr r11, imx_ssi_fiq_rx_buffer 96 ldr r13, .L_imx_ssi_fiq_rx_buffer
90 97
91 mov r10, #0x10000 98 mov r10, #0x10000
92 sub r10, #1 99 sub r10, #1
93 and r10, r10, r9 /* r10: current buffer offset */ 100 and r10, r10, r9 /* r10: current buffer offset */
94 101
95 add r11, r11, r10 102 add r13, r13, r10
96 103
97 ldr r13, [r12, #SSI_SACNT] 104 ldr r11, [r12, #SSI_SACNT]
98 tst r13, #SSI_SACNT_AC97EN 105 tst r11, #SSI_SACNT_AC97EN
99 106
100 ldr r13, [r12, #SSI_SRX0] 107 ldr r11, [r12, #SSI_SRX0]
101 strh r13, [r11] 108 strh r11, [r13]
102 109
103 ldr r13, [r12, #SSI_SRX0] 110 ldr r11, [r12, #SSI_SRX0]
104 strh r13, [r11, #2] 111 strh r11, [r13, #2]
105 112
106 /* dummy read to skip slot 12 */ 113 /* dummy read to skip slot 12 */
107 ldrne r13, [r12, #SSI_SRX0] 114 ldrne r11, [r12, #SSI_SRX0]
108 115
109 ldr r13, [r12, #SSI_SRX0] 116 ldr r11, [r12, #SSI_SRX0]
110 strh r13, [r11, #4] 117 strh r11, [r13, #4]
111 118
112 ldr r13, [r12, #SSI_SRX0] 119 ldr r11, [r12, #SSI_SRX0]
113 strh r13, [r11, #6] 120 strh r11, [r13, #6]
114 121
115 /* dummy read to skip slot 12 */ 122 /* dummy read to skip slot 12 */
116 ldrne r13, [r12, #SSI_SRX0] 123 ldrne r11, [r12, #SSI_SRX0]
117 124
118 add r10, #8 125 add r10, #8
119 lsr r13, r9, #16 /* r13: buffer size */ 126 lsr r11, r9, #16 /* r11: buffer size */
120 cmp r10, r13 127 cmp r10, r11
121 lslgt r9, r13, #16 128 lslgt r9, r11, #16
122 addle r9, #8 129 addle r9, #8
123 130
1241: 1311:
@@ -126,11 +133,15 @@ imx_ssi_fiq_start:
126 subs pc, lr, #4 133 subs pc, lr, #4
127 134
128 .align 135 .align
136.L_imx_ssi_fiq_base:
129imx_ssi_fiq_base: 137imx_ssi_fiq_base:
130 .word 0x0 138 .word 0x0
139.L_imx_ssi_fiq_rx_buffer:
131imx_ssi_fiq_rx_buffer: 140imx_ssi_fiq_rx_buffer:
132 .word 0x0 141 .word 0x0
142.L_imx_ssi_fiq_tx_buffer:
133imx_ssi_fiq_tx_buffer: 143imx_ssi_fiq_tx_buffer:
134 .word 0x0 144 .word 0x0
145.L_imx_ssi_fiq_end:
135imx_ssi_fiq_end: 146imx_ssi_fiq_end:
136 147