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authorBen Skeggs <bskeggs@redhat.com>2013-05-06 02:00:20 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-06-30 23:50:36 -0400
commitcb1e06e0e3c3b10c99276a37b3b5884e7ec7f549 (patch)
treefd5f744320f71129f2ecb5001b8c1c147c84466b
parent507cd5b553d88216a8d74ac9f2c73caceb3cd236 (diff)
drm/nvf0/gr: initial register/context setup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c260
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc59
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h77
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc74
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h955
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nve0.c114
6 files changed, 1057 insertions, 482 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
index f884ffbd408e..574a1deffcb9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
@@ -2190,6 +2190,15 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
2190static void 2190static void
2191nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) 2191nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
2192{ 2192{
2193 switch (nv_device(priv)->chipset) {
2194 case 0xf0:
2195 nv_wr32(priv, 0x404004, 0x00000000);
2196 nv_wr32(priv, 0x404008, 0x00000000);
2197 nv_wr32(priv, 0x40400c, 0x00000000);
2198 break;
2199 default:
2200 break;
2201 }
2193 nv_wr32(priv, 0x404010, 0x0); 2202 nv_wr32(priv, 0x404010, 0x0);
2194 nv_wr32(priv, 0x404014, 0x0); 2203 nv_wr32(priv, 0x404014, 0x0);
2195 nv_wr32(priv, 0x404018, 0x0); 2204 nv_wr32(priv, 0x404018, 0x0);
@@ -2197,6 +2206,19 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
2197 nv_wr32(priv, 0x404020, 0x0); 2206 nv_wr32(priv, 0x404020, 0x0);
2198 nv_wr32(priv, 0x404024, 0xe000); 2207 nv_wr32(priv, 0x404024, 0xe000);
2199 nv_wr32(priv, 0x404028, 0x0); 2208 nv_wr32(priv, 0x404028, 0x0);
2209 switch (nv_device(priv)->chipset) {
2210 case 0xf0:
2211 nv_wr32(priv, 0x40402c, 0x00000000);
2212 nv_wr32(priv, 0x404030, 0x00000000);
2213 nv_wr32(priv, 0x404034, 0x00000000);
2214 nv_wr32(priv, 0x404038, 0x00000000);
2215 nv_wr32(priv, 0x40403c, 0x00000000);
2216 nv_wr32(priv, 0x404040, 0x00000000);
2217 nv_wr32(priv, 0x404044, 0x00000000);
2218 break;
2219 default:
2220 break;
2221 }
2200 nv_wr32(priv, 0x4040a8, 0x0); 2222 nv_wr32(priv, 0x4040a8, 0x0);
2201 nv_wr32(priv, 0x4040ac, 0x0); 2223 nv_wr32(priv, 0x4040ac, 0x0);
2202 nv_wr32(priv, 0x4040b0, 0x0); 2224 nv_wr32(priv, 0x4040b0, 0x0);
@@ -2214,6 +2236,22 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
2214 nv_wr32(priv, 0x4040e4, 0x0); 2236 nv_wr32(priv, 0x4040e4, 0x0);
2215 nv_wr32(priv, 0x4040e8, 0x1000); 2237 nv_wr32(priv, 0x4040e8, 0x1000);
2216 nv_wr32(priv, 0x4040f8, 0x0); 2238 nv_wr32(priv, 0x4040f8, 0x0);
2239 switch (nv_device(priv)->chipset) {
2240 case 0xf0:
2241 nv_wr32(priv, 0x404100, 0x00000000);
2242 nv_wr32(priv, 0x404104, 0x00000000);
2243 nv_wr32(priv, 0x404108, 0x00000000);
2244 nv_wr32(priv, 0x40410c, 0x00000000);
2245 nv_wr32(priv, 0x404110, 0x00000000);
2246 nv_wr32(priv, 0x404114, 0x00000000);
2247 nv_wr32(priv, 0x404118, 0x00000000);
2248 nv_wr32(priv, 0x40411c, 0x00000000);
2249 nv_wr32(priv, 0x404120, 0x00000000);
2250 nv_wr32(priv, 0x404124, 0x00000000);
2251 break;
2252 default:
2253 break;
2254 }
2217 nv_wr32(priv, 0x404130, 0x0); 2255 nv_wr32(priv, 0x404130, 0x0);
2218 nv_wr32(priv, 0x404134, 0x0); 2256 nv_wr32(priv, 0x404134, 0x0);
2219 nv_wr32(priv, 0x404138, 0x20000040); 2257 nv_wr32(priv, 0x404138, 0x20000040);
@@ -2221,14 +2259,32 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
2221 nv_wr32(priv, 0x404154, 0x400); 2259 nv_wr32(priv, 0x404154, 0x400);
2222 nv_wr32(priv, 0x404158, 0x200); 2260 nv_wr32(priv, 0x404158, 0x200);
2223 nv_wr32(priv, 0x404164, 0x55); 2261 nv_wr32(priv, 0x404164, 0x55);
2262 switch (nv_device(priv)->chipset) {
2263 case 0xf0:
2264 nv_wr32(priv, 0x40417c, 0x00000000);
2265 nv_wr32(priv, 0x404180, 0x00000000);
2266 break;
2267 default:
2268 break;
2269 }
2224 nv_wr32(priv, 0x4041a0, 0x0); 2270 nv_wr32(priv, 0x4041a0, 0x0);
2225 nv_wr32(priv, 0x4041a4, 0x0); 2271 nv_wr32(priv, 0x4041a4, 0x0);
2226 nv_wr32(priv, 0x4041a8, 0x0); 2272 nv_wr32(priv, 0x4041a8, 0x0);
2227 nv_wr32(priv, 0x4041ac, 0x0); 2273 nv_wr32(priv, 0x4041ac, 0x0);
2228 nv_wr32(priv, 0x404200, 0x0); 2274 switch (nv_device(priv)->chipset) {
2229 nv_wr32(priv, 0x404204, 0x0); 2275 case 0xf0:
2230 nv_wr32(priv, 0x404208, 0x0); 2276 nv_wr32(priv, 0x404200, 0xa197);
2231 nv_wr32(priv, 0x40420c, 0x0); 2277 nv_wr32(priv, 0x404204, 0xa1c0);
2278 nv_wr32(priv, 0x404208, 0xa140);
2279 nv_wr32(priv, 0x40420c, 0x902d);
2280 break;
2281 default:
2282 nv_wr32(priv, 0x404200, 0x0);
2283 nv_wr32(priv, 0x404204, 0x0);
2284 nv_wr32(priv, 0x404208, 0x0);
2285 nv_wr32(priv, 0x40420c, 0x0);
2286 break;
2287 }
2232} 2288}
2233 2289
2234static void 2290static void
@@ -2246,7 +2302,13 @@ nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv)
2246 nv_wr32(priv, 0x404428, 0x0); 2302 nv_wr32(priv, 0x404428, 0x0);
2247 nv_wr32(priv, 0x40442c, 0x0); 2303 nv_wr32(priv, 0x40442c, 0x0);
2248 nv_wr32(priv, 0x404430, 0x0); 2304 nv_wr32(priv, 0x404430, 0x0);
2249 nv_wr32(priv, 0x404434, 0x0); 2305 switch (nv_device(priv)->chipset) {
2306 case 0xf0:
2307 break;
2308 default:
2309 nv_wr32(priv, 0x404434, 0x0);
2310 break;
2311 }
2250 nv_wr32(priv, 0x404438, 0x0); 2312 nv_wr32(priv, 0x404438, 0x0);
2251 nv_wr32(priv, 0x404460, 0x0); 2313 nv_wr32(priv, 0x404460, 0x0);
2252 nv_wr32(priv, 0x404464, 0x0); 2314 nv_wr32(priv, 0x404464, 0x0);
@@ -2339,12 +2401,26 @@ nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv)
2339{ 2401{
2340 nv_wr32(priv, 0x405b00, 0x0); 2402 nv_wr32(priv, 0x405b00, 0x0);
2341 nv_wr32(priv, 0x405b10, 0x1000); 2403 nv_wr32(priv, 0x405b10, 0x1000);
2404 switch (nv_device(priv)->chipset) {
2405 case 0xf0:
2406 nv_wr32(priv, 0x405b20, 0x04000000);
2407 break;
2408 default:
2409 break;
2410 }
2342} 2411}
2343 2412
2344static void 2413static void
2345nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv) 2414nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv)
2346{ 2415{
2347 nv_wr32(priv, 0x406020, 0x4103c1); 2416 switch (nv_device(priv)->chipset) {
2417 case 0xf0:
2418 nv_wr32(priv, 0x406020, 0x34103c1);
2419 break;
2420 default:
2421 nv_wr32(priv, 0x406020, 0x4103c1);
2422 break;
2423 }
2348 nv_wr32(priv, 0x406028, 0x1); 2424 nv_wr32(priv, 0x406028, 0x1);
2349 nv_wr32(priv, 0x40602c, 0x1); 2425 nv_wr32(priv, 0x40602c, 0x1);
2350 nv_wr32(priv, 0x406030, 0x1); 2426 nv_wr32(priv, 0x406030, 0x1);
@@ -2356,11 +2432,27 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
2356{ 2432{
2357 nv_wr32(priv, 0x4064a8, 0x0); 2433 nv_wr32(priv, 0x4064a8, 0x0);
2358 nv_wr32(priv, 0x4064ac, 0x3fff); 2434 nv_wr32(priv, 0x4064ac, 0x3fff);
2435 switch (nv_device(priv)->chipset) {
2436 case 0xf0:
2437 nv_wr32(priv, 0x4064b0, 0x0);
2438 break;
2439 default:
2440 break;
2441 }
2359 nv_wr32(priv, 0x4064b4, 0x0); 2442 nv_wr32(priv, 0x4064b4, 0x0);
2360 nv_wr32(priv, 0x4064b8, 0x0); 2443 nv_wr32(priv, 0x4064b8, 0x0);
2361 nv_wr32(priv, 0x4064c0, 0x801a00f0); 2444 switch (nv_device(priv)->chipset) {
2362 nv_wr32(priv, 0x4064c4, 0x192ffff); 2445 case 0xf0:
2363 nv_wr32(priv, 0x4064c8, 0x1800600); 2446 nv_wr32(priv, 0x4064c0, 0x802000f0);
2447 nv_wr32(priv, 0x4064c4, 0x192ffff);
2448 nv_wr32(priv, 0x4064c8, 0x18007c0);
2449 break;
2450 default:
2451 nv_wr32(priv, 0x4064c0, 0x801a00f0);
2452 nv_wr32(priv, 0x4064c4, 0x192ffff);
2453 nv_wr32(priv, 0x4064c8, 0x1800600);
2454 break;
2455 }
2364 nv_wr32(priv, 0x4064cc, 0x0); 2456 nv_wr32(priv, 0x4064cc, 0x0);
2365 nv_wr32(priv, 0x4064d0, 0x0); 2457 nv_wr32(priv, 0x4064d0, 0x0);
2366 nv_wr32(priv, 0x4064d4, 0x0); 2458 nv_wr32(priv, 0x4064d4, 0x0);
@@ -2376,7 +2468,13 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
2376static void 2468static void
2377nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv) 2469nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv)
2378{ 2470{
2379 nv_wr32(priv, 0x407040, 0x0); 2471 switch (nv_device(priv)->chipset) {
2472 case 0xf0:
2473 break;
2474 default:
2475 nv_wr32(priv, 0x407040, 0x0);
2476 break;
2477 }
2380} 2478}
2381 2479
2382static void 2480static void
@@ -2408,9 +2506,23 @@ nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv)
2408static void 2506static void
2409nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv) 2507nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)
2410{ 2508{
2411 nv_wr32(priv, 0x408800, 0x2802a3c); 2509 switch (nv_device(priv)->chipset) {
2510 case 0xf0:
2511 nv_wr32(priv, 0x408800, 0x12802a3c);
2512 break;
2513 default:
2514 nv_wr32(priv, 0x408800, 0x2802a3c);
2515 break;
2516 }
2412 nv_wr32(priv, 0x408804, 0x40); 2517 nv_wr32(priv, 0x408804, 0x40);
2413 nv_wr32(priv, 0x408808, 0x1043e005); 2518 switch (nv_device(priv)->chipset) {
2519 case 0xf0:
2520 nv_wr32(priv, 0x408808, 0x1003e005);
2521 break;
2522 default:
2523 nv_wr32(priv, 0x408808, 0x1043e005);
2524 break;
2525 }
2414 nv_wr32(priv, 0x408840, 0xb); 2526 nv_wr32(priv, 0x408840, 0xb);
2415 nv_wr32(priv, 0x408900, 0x3080b801); 2527 nv_wr32(priv, 0x408900, 0x3080b801);
2416 nv_wr32(priv, 0x408904, 0x62000001); 2528 nv_wr32(priv, 0x408904, 0x62000001);
@@ -2447,7 +2559,14 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
2447 nv_wr32(priv, 0x418710, 0x0); 2559 nv_wr32(priv, 0x418710, 0x0);
2448 nv_wr32(priv, 0x418800, 0x7006860a); 2560 nv_wr32(priv, 0x418800, 0x7006860a);
2449 nv_wr32(priv, 0x418808, 0x0); 2561 nv_wr32(priv, 0x418808, 0x0);
2450 nv_wr32(priv, 0x41880c, 0x0); 2562 switch (nv_device(priv)->chipset) {
2563 case 0xf0:
2564 nv_wr32(priv, 0x41880c, 0x30);
2565 break;
2566 default:
2567 nv_wr32(priv, 0x41880c, 0x0);
2568 break;
2569 }
2451 nv_wr32(priv, 0x418810, 0x0); 2570 nv_wr32(priv, 0x418810, 0x0);
2452 nv_wr32(priv, 0x418828, 0x44); 2571 nv_wr32(priv, 0x418828, 0x44);
2453 nv_wr32(priv, 0x418830, 0x10000001); 2572 nv_wr32(priv, 0x418830, 0x10000001);
@@ -2493,6 +2612,13 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
2493 nv_wr32(priv, 0x418c6c, 0x1); 2612 nv_wr32(priv, 0x418c6c, 0x1);
2494 nv_wr32(priv, 0x418c80, 0x20200004); 2613 nv_wr32(priv, 0x418c80, 0x20200004);
2495 nv_wr32(priv, 0x418c8c, 0x1); 2614 nv_wr32(priv, 0x418c8c, 0x1);
2615 switch (nv_device(priv)->chipset) {
2616 case 0xf0:
2617 nv_wr32(priv, 0x418d24, 0x0);
2618 break;
2619 default:
2620 break;
2621 }
2496 nv_wr32(priv, 0x419000, 0x780); 2622 nv_wr32(priv, 0x419000, 0x780);
2497 nv_wr32(priv, 0x419004, 0x0); 2623 nv_wr32(priv, 0x419004, 0x0);
2498 nv_wr32(priv, 0x419008, 0x0); 2624 nv_wr32(priv, 0x419008, 0x0);
@@ -2512,31 +2638,71 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
2512 nv_wr32(priv, 0x419a10, 0x0); 2638 nv_wr32(priv, 0x419a10, 0x0);
2513 nv_wr32(priv, 0x419a14, 0x200); 2639 nv_wr32(priv, 0x419a14, 0x200);
2514 nv_wr32(priv, 0x419a1c, 0xc000); 2640 nv_wr32(priv, 0x419a1c, 0xc000);
2515 nv_wr32(priv, 0x419a20, 0x800); 2641 switch (nv_device(priv)->chipset) {
2642 case 0xf0:
2643 nv_wr32(priv, 0x419a20, 0x20800);
2644 break;
2645 default:
2646 nv_wr32(priv, 0x419a20, 0x800);
2647 break;
2648 }
2516 nv_wr32(priv, 0x419a30, 0x1); 2649 nv_wr32(priv, 0x419a30, 0x1);
2517 nv_wr32(priv, 0x419ac4, 0x37f440); 2650 nv_wr32(priv, 0x419ac4, 0x37f440);
2518 nv_wr32(priv, 0x419c00, 0xa); 2651 switch (nv_device(priv)->chipset) {
2652 case 0xf0:
2653 nv_wr32(priv, 0x419c00, 0x1a);
2654 break;
2655 default:
2656 nv_wr32(priv, 0x419c00, 0xa);
2657 break;
2658 }
2519 nv_wr32(priv, 0x419c04, 0x80000006); 2659 nv_wr32(priv, 0x419c04, 0x80000006);
2520 nv_wr32(priv, 0x419c08, 0x2); 2660 nv_wr32(priv, 0x419c08, 0x2);
2521 nv_wr32(priv, 0x419c20, 0x0); 2661 nv_wr32(priv, 0x419c20, 0x0);
2522 nv_wr32(priv, 0x419c24, 0x84210); 2662 nv_wr32(priv, 0x419c24, 0x84210);
2523 nv_wr32(priv, 0x419c28, 0x3efbefbe); 2663 nv_wr32(priv, 0x419c28, 0x3efbefbe);
2524 nv_wr32(priv, 0x419ce8, 0x0); 2664 nv_wr32(priv, 0x419ce8, 0x0);
2525 nv_wr32(priv, 0x419cf4, 0x3203); 2665 switch (nv_device(priv)->chipset) {
2526 nv_wr32(priv, 0x419e04, 0x0); 2666 case 0xf0:
2527 nv_wr32(priv, 0x419e08, 0x0); 2667 nv_wr32(priv, 0x419cf4, 0x203);
2528 nv_wr32(priv, 0x419e0c, 0x0); 2668 nv_wr32(priv, 0x419e04, 0x0);
2529 nv_wr32(priv, 0x419e10, 0x402); 2669 nv_wr32(priv, 0x419e08, 0x1d);
2670 nv_wr32(priv, 0x419e0c, 0x0);
2671 nv_wr32(priv, 0x419e10, 0x1c02);
2672
2673 break;
2674 default:
2675 nv_wr32(priv, 0x419cf4, 0x3203);
2676 nv_wr32(priv, 0x419e04, 0x0);
2677 nv_wr32(priv, 0x419e08, 0x0);
2678 nv_wr32(priv, 0x419e0c, 0x0);
2679 nv_wr32(priv, 0x419e10, 0x402);
2680 break;
2681 }
2530 nv_wr32(priv, 0x419e44, 0x13eff2); 2682 nv_wr32(priv, 0x419e44, 0x13eff2);
2531 nv_wr32(priv, 0x419e48, 0x0); 2683 nv_wr32(priv, 0x419e48, 0x0);
2532 nv_wr32(priv, 0x419e4c, 0x7f); 2684 nv_wr32(priv, 0x419e4c, 0x7f);
2533 nv_wr32(priv, 0x419e50, 0x0); 2685 nv_wr32(priv, 0x419e50, 0x0);
2534 nv_wr32(priv, 0x419e54, 0x0); 2686 nv_wr32(priv, 0x419e54, 0x0);
2535 nv_wr32(priv, 0x419e58, 0x0); 2687 switch (nv_device(priv)->chipset) {
2688 case 0xf0:
2689 nv_wr32(priv, 0x419e58, 0x1);
2690 break;
2691 default:
2692 nv_wr32(priv, 0x419e58, 0x0);
2693 break;
2694 }
2536 nv_wr32(priv, 0x419e5c, 0x0); 2695 nv_wr32(priv, 0x419e5c, 0x0);
2537 nv_wr32(priv, 0x419e60, 0x0); 2696 nv_wr32(priv, 0x419e60, 0x0);
2538 nv_wr32(priv, 0x419e64, 0x0); 2697 nv_wr32(priv, 0x419e64, 0x0);
2539 nv_wr32(priv, 0x419e68, 0x0); 2698 switch (nv_device(priv)->chipset) {
2699 case 0xf0:
2700 nv_wr32(priv, 0x419e68, 0x2);
2701 break;
2702 default:
2703 nv_wr32(priv, 0x419e68, 0x0);
2704 break;
2705 }
2540 nv_wr32(priv, 0x419e6c, 0x0); 2706 nv_wr32(priv, 0x419e6c, 0x0);
2541 nv_wr32(priv, 0x419e70, 0x0); 2707 nv_wr32(priv, 0x419e70, 0x0);
2542 nv_wr32(priv, 0x419e74, 0x0); 2708 nv_wr32(priv, 0x419e74, 0x0);
@@ -2553,37 +2719,49 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
2553 case 0xe7: 2719 case 0xe7:
2554 case 0xe6: 2720 case 0xe6:
2555 nv_wr32(priv, 0x419eac, 0x1f8f); 2721 nv_wr32(priv, 0x419eac, 0x1f8f);
2722 nv_wr32(priv, 0x419eb0, 0xd3f);
2723 break;
2724 case 0xf0:
2725 nv_wr32(priv, 0x419eac, 0x1fcf);
2726 nv_wr32(priv, 0x419eb0, 0xdb00da0);
2727 nv_wr32(priv, 0x419eb8, 0x0);
2556 break; 2728 break;
2557 default: 2729 default:
2558 nv_wr32(priv, 0x419eac, 0x1fcf); 2730 nv_wr32(priv, 0x419eac, 0x1fcf);
2731 nv_wr32(priv, 0x419eb0, 0xd3f);
2559 break; 2732 break;
2560 } 2733 }
2561 nv_wr32(priv, 0x419eb0, 0xd3f);
2562 nv_wr32(priv, 0x419ec8, 0x1304f); 2734 nv_wr32(priv, 0x419ec8, 0x1304f);
2563 nv_wr32(priv, 0x419f30, 0x0); 2735 nv_wr32(priv, 0x419f30, 0x0);
2564 nv_wr32(priv, 0x419f34, 0x0); 2736 nv_wr32(priv, 0x419f34, 0x0);
2565 nv_wr32(priv, 0x419f38, 0x0); 2737 nv_wr32(priv, 0x419f38, 0x0);
2566 nv_wr32(priv, 0x419f3c, 0x0); 2738 nv_wr32(priv, 0x419f3c, 0x0);
2567 nv_wr32(priv, 0x419f40, 0x0);
2568 nv_wr32(priv, 0x419f44, 0x0);
2569 nv_wr32(priv, 0x419f48, 0x0);
2570 nv_wr32(priv, 0x419f4c, 0x0);
2571 nv_wr32(priv, 0x419f58, 0x0);
2572 switch (nv_device(priv)->chipset) { 2739 switch (nv_device(priv)->chipset) {
2573 case 0xe7: 2740 case 0xf0:
2574 case 0xe6: 2741 nv_wr32(priv, 0x419f40, 0x18);
2575 nv_wr32(priv, 0x419f70, 0x0);
2576 break; 2742 break;
2577 default: 2743 default:
2744 nv_wr32(priv, 0x419f40, 0x0);
2578 break; 2745 break;
2579 } 2746 }
2580 nv_wr32(priv, 0x419f78, 0xb); 2747 nv_wr32(priv, 0x419f44, 0x0);
2748 nv_wr32(priv, 0x419f48, 0x0);
2749 nv_wr32(priv, 0x419f4c, 0x0);
2750 nv_wr32(priv, 0x419f58, 0x0);
2581 switch (nv_device(priv)->chipset) { 2751 switch (nv_device(priv)->chipset) {
2582 case 0xe7: 2752 case 0xe7:
2583 case 0xe6: 2753 case 0xe6:
2754 nv_wr32(priv, 0x419f70, 0x0);
2755 nv_wr32(priv, 0x419f78, 0xb);
2584 nv_wr32(priv, 0x419f7c, 0x27a); 2756 nv_wr32(priv, 0x419f7c, 0x27a);
2585 break; 2757 break;
2758 case 0xf0:
2759 nv_wr32(priv, 0x419f70, 0x7300);
2760 nv_wr32(priv, 0x419f78, 0xeb);
2761 nv_wr32(priv, 0x419f7c, 0x404);
2762 break;
2586 default: 2763 default:
2764 nv_wr32(priv, 0x419f78, 0xb);
2587 break; 2765 break;
2588 } 2766 }
2589} 2767}
@@ -2592,9 +2770,23 @@ static void
2592nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv) 2770nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv)
2593{ 2771{
2594 nv_wr32(priv, 0x41be24, 0x6); 2772 nv_wr32(priv, 0x41be24, 0x6);
2595 nv_wr32(priv, 0x41bec0, 0x12180000); 2773 switch (nv_device(priv)->chipset) {
2774 case 0xf0:
2775 nv_wr32(priv, 0x41bec0, 0x10000000);
2776 break;
2777 default:
2778 nv_wr32(priv, 0x41bec0, 0x12180000);
2779 break;
2780 }
2596 nv_wr32(priv, 0x41bec4, 0x37f7f); 2781 nv_wr32(priv, 0x41bec4, 0x37f7f);
2597 nv_wr32(priv, 0x41bee4, 0x6480430); 2782 switch (nv_device(priv)->chipset) {
2783 case 0xf0:
2784 nv_wr32(priv, 0x41bee4, 0x0);
2785 break;
2786 default:
2787 nv_wr32(priv, 0x41bee4, 0x6480430);
2788 break;
2789 }
2598 nv_wr32(priv, 0x41bf00, 0xa418820); 2790 nv_wr32(priv, 0x41bf00, 0xa418820);
2599 nv_wr32(priv, 0x41bf04, 0x62080e6); 2791 nv_wr32(priv, 0x41bf04, 0x62080e6);
2600 nv_wr32(priv, 0x41bf08, 0x20398a4); 2792 nv_wr32(priv, 0x41bf08, 0x20398a4);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index 2aed9a54062d..e906ca68674d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -62,6 +62,11 @@ chipsets:
62.b16 #nve4_gpc_mmio_tail 62.b16 #nve4_gpc_mmio_tail
63.b16 #nve6_tpc_mmio_head 63.b16 #nve6_tpc_mmio_head
64.b16 #nve6_tpc_mmio_tail 64.b16 #nve6_tpc_mmio_tail
65.b8 0xf0 0 0 0
66.b16 #nvf0_gpc_mmio_head
67.b16 #nvf0_gpc_mmio_tail
68.b16 #nvf0_tpc_mmio_head
69.b16 #nvf0_tpc_mmio_tail
65.b8 0 0 0 0 70.b8 0 0 0 0
66 71
67// GPC mmio lists 72// GPC mmio lists
@@ -101,6 +106,37 @@ mmctx_data(0x0031d0, 1)
101mmctx_data(0x0031e0, 2) 106mmctx_data(0x0031e0, 2)
102nve4_gpc_mmio_tail: 107nve4_gpc_mmio_tail:
103 108
109nvf0_gpc_mmio_head:
110mmctx_data(0x000380, 1)
111mmctx_data(0x000400, 2)
112mmctx_data(0x00040c, 3)
113mmctx_data(0x000450, 9)
114mmctx_data(0x000600, 1)
115mmctx_data(0x000684, 1)
116mmctx_data(0x000700, 5)
117mmctx_data(0x000800, 1)
118mmctx_data(0x000808, 3)
119mmctx_data(0x000828, 1)
120mmctx_data(0x000830, 1)
121mmctx_data(0x0008d8, 1)
122mmctx_data(0x0008e0, 1)
123mmctx_data(0x0008e8, 6)
124mmctx_data(0x00091c, 1)
125mmctx_data(0x000924, 3)
126mmctx_data(0x000b00, 1)
127mmctx_data(0x000b08, 6)
128mmctx_data(0x000bb8, 1)
129mmctx_data(0x000c08, 1)
130mmctx_data(0x000c10, 8)
131mmctx_data(0x000c40, 1)
132mmctx_data(0x000c6c, 1)
133mmctx_data(0x000c80, 1)
134mmctx_data(0x000c8c, 1)
135mmctx_data(0x000d24, 1)
136mmctx_data(0x001000, 3)
137mmctx_data(0x001014, 1)
138nvf0_gpc_mmio_tail:
139
104// TPC mmio lists 140// TPC mmio lists
105nve4_tpc_mmio_head: 141nve4_tpc_mmio_head:
106mmctx_data(0x000048, 1) 142mmctx_data(0x000048, 1)
@@ -145,6 +181,29 @@ mmctx_data(0x000770, 1)
145mmctx_data(0x000778, 2) 181mmctx_data(0x000778, 2)
146nve6_tpc_mmio_tail: 182nve6_tpc_mmio_tail:
147 183
184nvf0_tpc_mmio_head:
185mmctx_data(0x000048, 1)
186mmctx_data(0x000064, 1)
187mmctx_data(0x000088, 1)
188mmctx_data(0x000200, 6)
189mmctx_data(0x00021c, 2)
190mmctx_data(0x000230, 1)
191mmctx_data(0x0002c4, 1)
192mmctx_data(0x000400, 3)
193mmctx_data(0x000420, 3)
194mmctx_data(0x0004e8, 1)
195mmctx_data(0x0004f4, 1)
196mmctx_data(0x000604, 4)
197mmctx_data(0x000644, 22)
198mmctx_data(0x0006ac, 2)
199mmctx_data(0x0006b8, 1)
200mmctx_data(0x0006c8, 1)
201mmctx_data(0x000730, 8)
202mmctx_data(0x000758, 1)
203mmctx_data(0x000770, 1)
204mmctx_data(0x000778, 2)
205nvf0_tpc_mmio_tail:
206
148.section #nve0_grgpc_code 207.section #nve0_grgpc_code
149bra #init 208bra #init
150define(`include_code') 209define(`include_code')
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 1f33a66f96af..592433954d41 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -34,16 +34,19 @@ uint32_t nve0_grgpc_data[] = {
34 0x00000000, 34 0x00000000,
35/* 0x0064: chipsets */ 35/* 0x0064: chipsets */
36 0x000000e4, 36 0x000000e4,
37 0x0110008c, 37 0x011c0098,
38 0x01580110, 38 0x01d4018c,
39 0x000000e7, 39 0x000000e7,
40 0x0110008c, 40 0x011c0098,
41 0x01a40158, 41 0x022001d4,
42 0x000000e6, 42 0x000000e6,
43 0x0110008c, 43 0x011c0098,
44 0x01a40158, 44 0x022001d4,
45 0x000000f0,
46 0x018c011c,
47 0x02700220,
45 0x00000000, 48 0x00000000,
46/* 0x008c: nve4_gpc_mmio_head */ 49/* 0x0098: nve4_gpc_mmio_head */
47 0x00000380, 50 0x00000380,
48 0x04000400, 51 0x04000400,
49 0x0800040c, 52 0x0800040c,
@@ -77,8 +80,38 @@ uint32_t nve0_grgpc_data[] = {
77 0x14003100, 80 0x14003100,
78 0x000031d0, 81 0x000031d0,
79 0x040031e0, 82 0x040031e0,
80/* 0x0110: nve4_gpc_mmio_tail */ 83/* 0x011c: nve4_gpc_mmio_tail */
81/* 0x0110: nve4_tpc_mmio_head */ 84/* 0x011c: nvf0_gpc_mmio_head */
85 0x00000380,
86 0x04000400,
87 0x0800040c,
88 0x20000450,
89 0x00000600,
90 0x00000684,
91 0x10000700,
92 0x00000800,
93 0x08000808,
94 0x00000828,
95 0x00000830,
96 0x000008d8,
97 0x000008e0,
98 0x140008e8,
99 0x0000091c,
100 0x08000924,
101 0x00000b00,
102 0x14000b08,
103 0x00000bb8,
104 0x00000c08,
105 0x1c000c10,
106 0x00000c40,
107 0x00000c6c,
108 0x00000c80,
109 0x00000c8c,
110 0x00000d24,
111 0x08001000,
112 0x00001014,
113/* 0x018c: nvf0_gpc_mmio_tail */
114/* 0x018c: nve4_tpc_mmio_head */
82 0x00000048, 115 0x00000048,
83 0x00000064, 116 0x00000064,
84 0x00000088, 117 0x00000088,
@@ -97,8 +130,29 @@ uint32_t nve0_grgpc_data[] = {
97 0x1c000730, 130 0x1c000730,
98 0x00000758, 131 0x00000758,
99 0x00000778, 132 0x00000778,
100/* 0x0158: nve4_tpc_mmio_tail */ 133/* 0x01d4: nve4_tpc_mmio_tail */
101/* 0x0158: nve6_tpc_mmio_head */ 134/* 0x01d4: nve6_tpc_mmio_head */
135 0x00000048,
136 0x00000064,
137 0x00000088,
138 0x14000200,
139 0x0400021c,
140 0x00000230,
141 0x000002c4,
142 0x08000400,
143 0x08000420,
144 0x000004e8,
145 0x000004f4,
146 0x0c000604,
147 0x54000644,
148 0x040006ac,
149 0x000006c8,
150 0x1c000730,
151 0x00000758,
152 0x00000770,
153 0x04000778,
154/* 0x0220: nve6_tpc_mmio_tail */
155/* 0x0220: nvf0_tpc_mmio_head */
102 0x00000048, 156 0x00000048,
103 0x00000064, 157 0x00000064,
104 0x00000088, 158 0x00000088,
@@ -113,6 +167,7 @@ uint32_t nve0_grgpc_data[] = {
113 0x0c000604, 167 0x0c000604,
114 0x54000644, 168 0x54000644,
115 0x040006ac, 169 0x040006ac,
170 0x000006b8,
116 0x000006c8, 171 0x000006c8,
117 0x1c000730, 172 0x1c000730,
118 0x00000758, 173 0x00000758,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
index 7fe9d7cf486b..b57a3db8df71 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
@@ -37,6 +37,15 @@ hub_mmio_list_tail: .b32 0
37 37
38ctx_current: .b32 0 38ctx_current: .b32 0
39 39
40.align 256
41chan_data:
42chan_mmio_count: .b32 0
43chan_mmio_address: .b32 0
44
45.align 256
46xfer_data: .b32 0
47
48.align 256
40chipsets: 49chipsets:
41.b8 0xe4 0 0 0 50.b8 0xe4 0 0 0
42.b16 #nve4_hub_mmio_head 51.b16 #nve4_hub_mmio_head
@@ -47,6 +56,9 @@ chipsets:
47.b8 0xe6 0 0 0 56.b8 0xe6 0 0 0
48.b16 #nve4_hub_mmio_head 57.b16 #nve4_hub_mmio_head
49.b16 #nve4_hub_mmio_tail 58.b16 #nve4_hub_mmio_tail
59.b8 0xf0 0 0 0
60.b16 #nvf0_hub_mmio_head
61.b16 #nvf0_hub_mmio_tail
50.b8 0 0 0 0 62.b8 0 0 0 0
51 63
52nve4_hub_mmio_head: 64nve4_hub_mmio_head:
@@ -103,13 +115,61 @@ mmctx_data(0x408900, 3)
103mmctx_data(0x408980, 1) 115mmctx_data(0x408980, 1)
104nve4_hub_mmio_tail: 116nve4_hub_mmio_tail:
105 117
106.align 256 118nvf0_hub_mmio_head:
107chan_data: 119mmctx_data(0x17e91c, 2)
108chan_mmio_count: .b32 0 120mmctx_data(0x400204, 2)
109chan_mmio_address: .b32 0 121mmctx_data(0x404004, 17)
110 122mmctx_data(0x4040a8, 9)
111.align 256 123mmctx_data(0x4040d0, 7)
112xfer_data: .b32 0 124mmctx_data(0x4040f8, 1)
125mmctx_data(0x404100, 10)
126mmctx_data(0x404130, 3)
127mmctx_data(0x404150, 3)
128mmctx_data(0x404164, 1)
129mmctx_data(0x40417c, 2)
130mmctx_data(0x4041a0, 4)
131mmctx_data(0x404200, 4)
132mmctx_data(0x404404, 12)
133mmctx_data(0x404438, 1)
134mmctx_data(0x404460, 4)
135mmctx_data(0x404480, 1)
136mmctx_data(0x404498, 1)
137mmctx_data(0x404604, 4)
138mmctx_data(0x404618, 4)
139mmctx_data(0x40462c, 2)
140mmctx_data(0x404640, 1)
141mmctx_data(0x404654, 1)
142mmctx_data(0x404660, 1)
143mmctx_data(0x404678, 19)
144mmctx_data(0x4046c8, 3)
145mmctx_data(0x404700, 3)
146mmctx_data(0x404718, 10)
147mmctx_data(0x404744, 2)
148mmctx_data(0x404754, 1)
149mmctx_data(0x405800, 1)
150mmctx_data(0x405830, 3)
151mmctx_data(0x405854, 1)
152mmctx_data(0x405870, 4)
153mmctx_data(0x405a00, 2)
154mmctx_data(0x405a18, 1)
155mmctx_data(0x405b00, 1)
156mmctx_data(0x405b10, 1)
157mmctx_data(0x405b20, 1)
158mmctx_data(0x406020, 1)
159mmctx_data(0x406028, 4)
160mmctx_data(0x4064a8, 5)
161mmctx_data(0x4064c0, 12)
162mmctx_data(0x4064fc, 1)
163mmctx_data(0x407804, 1)
164mmctx_data(0x40780c, 6)
165mmctx_data(0x4078bc, 1)
166mmctx_data(0x408000, 7)
167mmctx_data(0x408064, 1)
168mmctx_data(0x408800, 3)
169mmctx_data(0x408840, 1)
170mmctx_data(0x408900, 3)
171mmctx_data(0x408980, 1)
172nvf0_hub_mmio_tail:
113 173
114.section #nve0_grhub_code 174.section #nve0_grhub_code
115bra #init 175bra #init
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index e3421af68ab9..f22422e09045 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -28,67 +28,7 @@ uint32_t nve0_grhub_data[] = {
28 0x00000000, 28 0x00000000,
29/* 0x0058: ctx_current */ 29/* 0x0058: ctx_current */
30 0x00000000, 30 0x00000000,
31/* 0x005c: chipsets */
32 0x000000e4,
33 0x01440078,
34 0x000000e7,
35 0x01440078,
36 0x000000e6,
37 0x01440078,
38 0x00000000, 31 0x00000000,
39/* 0x0078: nve4_hub_mmio_head */
40 0x0417e91c,
41 0x04400204,
42 0x18404010,
43 0x204040a8,
44 0x184040d0,
45 0x004040f8,
46 0x08404130,
47 0x08404150,
48 0x00404164,
49 0x0c4041a0,
50 0x0c404200,
51 0x34404404,
52 0x0c404460,
53 0x00404480,
54 0x00404498,
55 0x0c404604,
56 0x0c404618,
57 0x0440462c,
58 0x00404640,
59 0x00404654,
60 0x00404660,
61 0x48404678,
62 0x084046c8,
63 0x08404700,
64 0x24404718,
65 0x04404744,
66 0x00404754,
67 0x00405800,
68 0x08405830,
69 0x00405854,
70 0x0c405870,
71 0x04405a00,
72 0x00405a18,
73 0x00405b00,
74 0x00405b10,
75 0x00406020,
76 0x0c406028,
77 0x044064a8,
78 0x044064b4,
79 0x2c4064c0,
80 0x004064fc,
81 0x00407040,
82 0x00407804,
83 0x1440780c,
84 0x004078bc,
85 0x18408000,
86 0x00408064,
87 0x08408800,
88 0x00408840,
89 0x08408900,
90 0x00408980,
91/* 0x0144: nve4_hub_mmio_tail */
92 0x00000000, 32 0x00000000,
93 0x00000000, 33 0x00000000,
94 0x00000000, 34 0x00000000,
@@ -129,6 +69,26 @@ uint32_t nve0_grhub_data[] = {
129 0x00000000, 69 0x00000000,
130 0x00000000, 70 0x00000000,
131 0x00000000, 71 0x00000000,
72/* 0x0100: chan_data */
73/* 0x0100: chan_mmio_count */
74 0x00000000,
75/* 0x0104: chan_mmio_address */
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
132 0x00000000, 92 0x00000000,
133 0x00000000, 93 0x00000000,
134 0x00000000, 94 0x00000000,
@@ -136,10 +96,7 @@ uint32_t nve0_grhub_data[] = {
136 0x00000000, 96 0x00000000,
137 0x00000000, 97 0x00000000,
138 0x00000000, 98 0x00000000,
139/* 0x0200: chan_data */
140/* 0x0200: chan_mmio_count */
141 0x00000000, 99 0x00000000,
142/* 0x0204: chan_mmio_address */
143 0x00000000, 100 0x00000000,
144 0x00000000, 101 0x00000000,
145 0x00000000, 102 0x00000000,
@@ -179,6 +136,7 @@ uint32_t nve0_grhub_data[] = {
179 0x00000000, 136 0x00000000,
180 0x00000000, 137 0x00000000,
181 0x00000000, 138 0x00000000,
139/* 0x0200: xfer_data */
182 0x00000000, 140 0x00000000,
183 0x00000000, 141 0x00000000,
184 0x00000000, 142 0x00000000,
@@ -203,8 +161,163 @@ uint32_t nve0_grhub_data[] = {
203 0x00000000, 161 0x00000000,
204 0x00000000, 162 0x00000000,
205 0x00000000, 163 0x00000000,
206/* 0x0300: xfer_data */
207 0x00000000, 164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204/* 0x0300: chipsets */
205 0x000000e4,
206 0x03f00324,
207 0x000000e7,
208 0x03f00324,
209 0x000000e6,
210 0x03f00324,
211 0x000000f0,
212 0x04c403f0,
213 0x00000000,
214/* 0x0324: nve4_hub_mmio_head */
215 0x0417e91c,
216 0x04400204,
217 0x18404010,
218 0x204040a8,
219 0x184040d0,
220 0x004040f8,
221 0x08404130,
222 0x08404150,
223 0x00404164,
224 0x0c4041a0,
225 0x0c404200,
226 0x34404404,
227 0x0c404460,
228 0x00404480,
229 0x00404498,
230 0x0c404604,
231 0x0c404618,
232 0x0440462c,
233 0x00404640,
234 0x00404654,
235 0x00404660,
236 0x48404678,
237 0x084046c8,
238 0x08404700,
239 0x24404718,
240 0x04404744,
241 0x00404754,
242 0x00405800,
243 0x08405830,
244 0x00405854,
245 0x0c405870,
246 0x04405a00,
247 0x00405a18,
248 0x00405b00,
249 0x00405b10,
250 0x00406020,
251 0x0c406028,
252 0x044064a8,
253 0x044064b4,
254 0x2c4064c0,
255 0x004064fc,
256 0x00407040,
257 0x00407804,
258 0x1440780c,
259 0x004078bc,
260 0x18408000,
261 0x00408064,
262 0x08408800,
263 0x00408840,
264 0x08408900,
265 0x00408980,
266/* 0x03f0: nve4_hub_mmio_tail */
267/* 0x03f0: nvf0_hub_mmio_head */
268 0x0417e91c,
269 0x04400204,
270 0x40404004,
271 0x204040a8,
272 0x184040d0,
273 0x004040f8,
274 0x24404100,
275 0x08404130,
276 0x08404150,
277 0x00404164,
278 0x0440417c,
279 0x0c4041a0,
280 0x0c404200,
281 0x2c404404,
282 0x00404438,
283 0x0c404460,
284 0x00404480,
285 0x00404498,
286 0x0c404604,
287 0x0c404618,
288 0x0440462c,
289 0x00404640,
290 0x00404654,
291 0x00404660,
292 0x48404678,
293 0x084046c8,
294 0x08404700,
295 0x24404718,
296 0x04404744,
297 0x00404754,
298 0x00405800,
299 0x08405830,
300 0x00405854,
301 0x0c405870,
302 0x04405a00,
303 0x00405a18,
304 0x00405b00,
305 0x00405b10,
306 0x00405b20,
307 0x00406020,
308 0x0c406028,
309 0x104064a8,
310 0x2c4064c0,
311 0x004064fc,
312 0x00407804,
313 0x1440780c,
314 0x004078bc,
315 0x18408000,
316 0x00408064,
317 0x08408800,
318 0x00408840,
319 0x08408900,
320 0x00408980,
208}; 321};
209 322
210uint32_t nve0_grhub_code[] = { 323uint32_t nve0_grhub_code[] = {
@@ -440,7 +553,7 @@ uint32_t nve0_grhub_code[] = {
440 0x0017f100, 553 0x0017f100,
441 0x0227f012, 554 0x0227f012,
442 0xf10012d0, 555 0xf10012d0,
443 0xfe05b917, 556 0xfe05ba17,
444 0x17f10010, 557 0x17f10010,
445 0x10d00400, 558 0x10d00400,
446 0x0437f1c0, 559 0x0437f1c0,
@@ -474,385 +587,385 @@ uint32_t nve0_grhub_code[] = {
474 0x4021d000, 587 0x4021d000,
475 0x080027f1, 588 0x080027f1,
476 0xcf0624b6, 589 0xcf0624b6,
477 0xf7f00022, 590 0xf7f10022,
478/* 0x03a9: init_find_chipset */ 591/* 0x03aa: init_find_chipset */
479 0x08f0b654, 592 0xf0b602f8,
480 0xb800f398, 593 0x00f39808,
481 0x0bf40432, 594 0xf40432b8,
482 0x0034b00b, 595 0x34b00b0b,
483 0xf8f11bf4, 596 0xf11bf400,
484/* 0x03bd: init_context */ 597/* 0x03be: init_context */
485 0x0017f100, 598 0x17f100f8,
486 0x02fe5801, 599 0xfe580100,
487 0xf003ff58, 600 0x03ff5802,
488 0x0e8000e3, 601 0x8000e3f0,
489 0x150f8014, 602 0x0f80140e,
490 0x013d21f5, 603 0x3d21f515,
491 0x070037f1, 604 0x0037f101,
492 0x950634b6, 605 0x0634b607,
493 0x34d00814, 606 0xd0081495,
494 0x4034d000, 607 0x34d00034,
495 0x130030b7, 608 0x0030b740,
496 0xb6001fbb, 609 0x001fbb13,
497 0x3fd002f5, 610 0xd002f5b6,
498 0x0815b600, 611 0x15b6003f,
499 0xb60110b6, 612 0x0110b608,
500 0x1fb90814, 613 0xb90814b6,
501 0x6321f502, 614 0x21f5021f,
502 0x001fbb02, 615 0x1fbb0263,
503 0xf1000398, 616 0x00039800,
504 0xf0200047, 617 0x200047f1,
505/* 0x040e: init_gpc */ 618/* 0x040f: init_gpc */
506 0x4ea05043, 619 0xa05043f0,
507 0x1fb90804, 620 0xb908044e,
508 0x8d21f402, 621 0x21f4021f,
509 0x08004ea0, 622 0x004ea08d,
510 0xf4022fb9, 623 0x022fb908,
511 0x4ea08d21,
512 0xf4bd010c,
513 0xa08d21f4, 624 0xa08d21f4,
514 0xf401044e, 625 0xbd010c4e,
515 0x4ea08d21, 626 0x8d21f4f4,
516 0xf7f00100, 627 0x01044ea0,
517 0x8d21f402, 628 0xa08d21f4,
518 0x08004ea0, 629 0xf001004e,
519/* 0x0440: init_gpc_wait */ 630 0x21f402f7,
520 0xc86821f4, 631 0x004ea08d,
521 0x0bf41fff, 632/* 0x0441: init_gpc_wait */
522 0x044ea0fa,
523 0x6821f408, 633 0x6821f408,
524 0xb7001fbb, 634 0xf41fffc8,
525 0xb6800040, 635 0x4ea0fa0b,
526 0x1bf40132, 636 0x21f40804,
527 0x0027f1b4, 637 0x001fbb68,
528 0x0624b608, 638 0x800040b7,
529 0xb74021d0, 639 0xf40132b6,
530 0xbd080020, 640 0x27f1b41b,
531 0x1f19f014, 641 0x24b60800,
532/* 0x0473: main */ 642 0x4021d006,
533 0xf40021d0, 643 0x080020b7,
534 0x28f40031, 644 0x19f014bd,
535 0x08d7f000, 645 0x0021d01f,
536 0xf43921f4, 646/* 0x0474: main */
537 0xe4b1f401, 647 0xf40031f4,
538 0x1bf54001, 648 0xd7f00028,
539 0x87f100d1, 649 0x3921f408,
540 0x84b6083c, 650 0xb1f401f4,
541 0xf094bd06, 651 0xf54001e4,
542 0x89d00499, 652 0xf100d11b,
543 0x0017f100,
544 0x0614b60b,
545 0xcf4012cf,
546 0x13c80011,
547 0x7e0bf41f,
548 0xf41f23c8,
549 0x20f95a0b,
550 0xf10212b9,
551 0xb6083c87, 653 0xb6083c87,
552 0x94bd0684, 654 0x94bd0684,
553 0xd00799f0, 655 0xd00499f0,
554 0x32f40089, 656 0x17f10089,
555 0x0231f401, 657 0x14b60b00,
556 0x07fb21f5, 658 0x4012cf06,
557 0x085c87f1, 659 0xc80011cf,
660 0x0bf41f13,
661 0x1f23c87e,
662 0xf95a0bf4,
663 0x0212b920,
664 0x083c87f1,
558 0xbd0684b6, 665 0xbd0684b6,
559 0x0799f094, 666 0x0799f094,
560 0xfc0089d0, 667 0xf40089d0,
561 0x3c87f120, 668 0x31f40132,
669 0xfc21f502,
670 0x5c87f107,
562 0x0684b608, 671 0x0684b608,
563 0x99f094bd, 672 0x99f094bd,
564 0x0089d006, 673 0x0089d007,
565 0xf50131f4, 674 0x87f120fc,
566 0xf107fb21, 675 0x84b6083c,
567 0xb6085c87, 676 0xf094bd06,
568 0x94bd0684, 677 0x89d00699,
569 0xd00699f0, 678 0x0131f400,
570 0x0ef40089, 679 0x07fc21f5,
571/* 0x0509: chsw_prev_no_next */
572 0xb920f931,
573 0x32f40212,
574 0x0232f401,
575 0x07fb21f5,
576 0x17f120fc,
577 0x14b60b00,
578 0x0012d006,
579/* 0x0527: chsw_no_prev */
580 0xc8130ef4,
581 0x0bf41f23,
582 0x0131f40d,
583 0xf50232f4,
584/* 0x0537: chsw_done */
585 0xf107fb21,
586 0xb60b0c17,
587 0x27f00614,
588 0x0012d001,
589 0x085c87f1, 680 0x085c87f1,
590 0xbd0684b6, 681 0xbd0684b6,
591 0x0499f094, 682 0x0699f094,
592 0xf50089d0, 683 0xf40089d0,
593/* 0x0557: main_not_ctx_switch */ 684/* 0x050a: chsw_prev_no_next */
594 0xb0ff200e, 685 0x20f9310e,
595 0x1bf401e4, 686 0xf40212b9,
596 0x02f2b90d, 687 0x32f40132,
597 0x078f21f5, 688 0xfc21f502,
598/* 0x0567: main_not_ctx_chan */ 689 0xf120fc07,
599 0xb0420ef4, 690 0xb60b0017,
600 0x1bf402e4, 691 0x12d00614,
601 0x3c87f12e, 692 0x130ef400,
693/* 0x0528: chsw_no_prev */
694 0xf41f23c8,
695 0x31f40d0b,
696 0x0232f401,
697 0x07fc21f5,
698/* 0x0538: chsw_done */
699 0x0b0c17f1,
700 0xf00614b6,
701 0x12d00127,
702 0x5c87f100,
602 0x0684b608, 703 0x0684b608,
603 0x99f094bd, 704 0x99f094bd,
604 0x0089d007, 705 0x0089d004,
605 0xf40132f4, 706 0xff200ef5,
606 0x21f50232, 707/* 0x0558: main_not_ctx_switch */
607 0x87f107fb, 708 0xf401e4b0,
608 0x84b6085c, 709 0xf2b90d1b,
710 0x9021f502,
711 0x420ef407,
712/* 0x0568: main_not_ctx_chan */
713 0xf402e4b0,
714 0x87f12e1b,
715 0x84b6083c,
609 0xf094bd06, 716 0xf094bd06,
610 0x89d00799, 717 0x89d00799,
611 0x110ef400, 718 0x0132f400,
612/* 0x0598: main_not_ctx_save */ 719 0xf50232f4,
613 0xf010ef94, 720 0xf107fc21,
614 0x21f501f5, 721 0xb6085c87,
615 0x0ef502ec, 722 0x94bd0684,
616/* 0x05a6: main_done */ 723 0xd00799f0,
617 0x17f1fed1, 724 0x0ef40089,
618 0x14b60820, 725/* 0x0599: main_not_ctx_save */
619 0xf024bd06, 726 0x10ef9411,
620 0x12d01f29, 727 0xf501f5f0,
621 0xbe0ef500, 728 0xf502ec21,
622/* 0x05b9: ih */ 729/* 0x05a7: main_done */
623 0xfe80f9fe, 730 0xf1fed10e,
624 0x80f90188, 731 0xb6082017,
625 0xa0f990f9, 732 0x24bd0614,
626 0xd0f9b0f9, 733 0xd01f29f0,
627 0xf0f9e0f9, 734 0x0ef50012,
628 0xc4800acf, 735/* 0x05ba: ih */
629 0x0bf404ab, 736 0x80f9febe,
630 0x00b7f11d, 737 0xf90188fe,
631 0x08d7f019, 738 0xf990f980,
632 0xcf40becf, 739 0xf9b0f9a0,
633 0x21f400bf, 740 0xf9e0f9d0,
634 0x00b0b704, 741 0x800acff0,
635 0x01e7f004, 742 0xf404abc4,
636/* 0x05ef: ih_no_fifo */ 743 0xb7f11d0b,
637 0xe400bed0, 744 0xd7f01900,
638 0xf40100ab, 745 0x40becf08,
639 0xd7f00d0b, 746 0xf400bfcf,
640 0x01e7f108, 747 0xb0b70421,
641 0x0421f440, 748 0xe7f00400,
642/* 0x0600: ih_no_ctxsw */ 749 0x00bed001,
643 0x0104b7f1, 750/* 0x05f0: ih_no_fifo */
644 0xabffb0bd, 751 0x0100abe4,
645 0x0d0bf4b4, 752 0xf00d0bf4,
646 0x0c1ca7f1, 753 0xe7f108d7,
647 0xd006a4b6, 754 0x21f44001,
648/* 0x0616: ih_no_other */ 755/* 0x0601: ih_no_ctxsw */
649 0x0ad000ab, 756 0x04b7f104,
650 0xfcf0fc40, 757 0xffb0bd01,
651 0xfcd0fce0, 758 0x0bf4b4ab,
652 0xfca0fcb0, 759 0x1ca7f10d,
653 0xfe80fc90, 760 0x06a4b60c,
654 0x80fc0088, 761/* 0x0617: ih_no_other */
655 0xf80032f4, 762 0xd000abd0,
656/* 0x0631: ctx_4170s */ 763 0xf0fc400a,
657 0x70e7f101, 764 0xd0fce0fc,
765 0xa0fcb0fc,
766 0x80fc90fc,
767 0xfc0088fe,
768 0x0032f480,
769/* 0x0632: ctx_4170s */
770 0xe7f101f8,
771 0xe3f04170,
772 0x10f5f040,
773 0xf88d21f4,
774/* 0x0641: ctx_4170w */
775 0x70e7f100,
658 0x40e3f041, 776 0x40e3f041,
659 0xf410f5f0, 777 0xf06821f4,
660 0x00f88d21, 778 0x1bf410f4,
661/* 0x0640: ctx_4170w */ 779/* 0x0653: ctx_redswitch */
662 0x4170e7f1, 780 0xf100f8f3,
663 0xf440e3f0, 781 0xb60614e7,
664 0xf4f06821, 782 0xf7f106e4,
665 0xf31bf410, 783 0xefd00270,
666/* 0x0652: ctx_redswitch */ 784 0x08f7f000,
667 0xe7f100f8, 785/* 0x0664: ctx_redswitch_delay */
668 0xe4b60614, 786 0xf401f2b6,
669 0x70f7f106, 787 0xf7f1fd1b,
670 0x00efd002, 788 0xefd00770,
671/* 0x0663: ctx_redswitch_delay */ 789/* 0x0673: ctx_86c */
672 0xb608f7f0, 790 0xf100f800,
673 0x1bf401f2, 791 0xb6086ce7,
674 0x70f7f1fd, 792 0xefd006e4,
675 0x00efd007, 793 0x14e7f100,
676/* 0x0672: ctx_86c */ 794 0x40e3f08a,
677 0xe7f100f8, 795 0xf18d21f4,
678 0xe4b6086c, 796 0xf0a86ce7,
679 0x00efd006, 797 0x21f441e3,
680 0x8a14e7f1, 798/* 0x0693: ctx_load */
681 0xf440e3f0, 799 0xf100f88d,
682 0xe7f18d21,
683 0xe3f0a86c,
684 0x8d21f441,
685/* 0x0692: ctx_load */
686 0x87f100f8,
687 0x84b6083c,
688 0xf094bd06,
689 0x89d00599,
690 0x0ca7f000,
691 0xf1c921f4,
692 0xb60a2417,
693 0x10d00614,
694 0x0037f100,
695 0x0634b60b,
696 0xf14032d0,
697 0xb60a0c17,
698 0x47f00614,
699 0x0012d007,
700/* 0x06cb: ctx_chan_wait_0 */
701 0xcf4014d0,
702 0x44f04014,
703 0xfa1bf41f,
704 0xfe0032d0,
705 0x2af0000b,
706 0x0424b61f,
707 0xf10220b6,
708 0xb6083c87, 800 0xb6083c87,
709 0x94bd0684, 801 0x94bd0684,
710 0xd00899f0, 802 0xd00599f0,
711 0x17f10089, 803 0xa7f00089,
712 0x14b60a04, 804 0xc921f40c,
713 0x0012d006, 805 0x0a2417f1,
714 0x0a2017f1, 806 0xd00614b6,
807 0x37f10010,
808 0x34b60b00,
809 0x4032d006,
810 0x0a0c17f1,
715 0xf00614b6, 811 0xf00614b6,
716 0x23f10227, 812 0x12d00747,
717 0x12d08000, 813 0x4014d000,
718 0x1017f000, 814/* 0x06cc: ctx_chan_wait_0 */
719 0x030027f1, 815 0xf04014cf,
720 0xfa0223f0, 816 0x1bf41f44,
721 0x03f80512, 817 0x0032d0fa,
722 0x085c87f1, 818 0xf0000bfe,
819 0x24b61f2a,
820 0x0220b604,
821 0x083c87f1,
723 0xbd0684b6, 822 0xbd0684b6,
724 0x0899f094, 823 0x0899f094,
725 0x980089d0, 824 0xf10089d0,
726 0x14b6c101, 825 0xb60a0417,
727 0xc0029818, 826 0x12d00614,
728 0xfd0825b6, 827 0x2017f100,
729 0x01800512, 828 0x0614b60a,
730 0x3c87f116, 829 0xf10227f0,
830 0xd0800023,
831 0x17f00012,
832 0x0027f110,
833 0x0223f002,
834 0xf80512fa,
835 0x5c87f103,
731 0x0684b608, 836 0x0684b608,
732 0x99f094bd, 837 0x99f094bd,
733 0x0089d009, 838 0x0089d008,
734 0x0a0427f1, 839 0xb6810198,
735 0xd00624b6, 840 0x02981814,
736 0x27f00021, 841 0x0825b680,
737 0x2017f101, 842 0x800512fd,
738 0x0614b60a, 843 0x87f11601,
739 0xf10012d0, 844 0x84b6083c,
740 0xf0020017, 845 0xf094bd06,
741 0x01fa0613, 846 0x89d00999,
742 0xf103f805, 847 0x0427f100,
848 0x0624b60a,
849 0xf00021d0,
850 0x17f10127,
851 0x14b60a20,
852 0x0012d006,
853 0x010017f1,
854 0xfa0613f0,
855 0x03f80501,
856 0x085c87f1,
857 0xbd0684b6,
858 0x0999f094,
859 0xf10089d0,
743 0xb6085c87, 860 0xb6085c87,
744 0x94bd0684, 861 0x94bd0684,
745 0xd00999f0, 862 0xd00599f0,
746 0x87f10089, 863 0x00f80089,
747 0x84b6085c, 864/* 0x0790: ctx_chan */
748 0xf094bd06, 865 0x069321f5,
749 0x89d00599, 866 0xf40ca7f0,
750/* 0x078f: ctx_chan */ 867 0x17f1c921,
751 0xf500f800, 868 0x14b60a10,
752 0xf0069221, 869 0x0527f006,
753 0x21f40ca7, 870/* 0x07a7: ctx_chan_wait */
754 0x1017f1c9, 871 0xcf0012d0,
755 0x0614b60a, 872 0x22fd0012,
756 0xd00527f0, 873 0xfa1bf405,
757/* 0x07a6: ctx_chan_wait */ 874/* 0x07b2: ctx_mmio_exec */
758 0x12cf0012, 875 0x039800f8,
759 0x0522fd00, 876 0x0427f141,
760 0xf8fa1bf4, 877 0x0624b60a,
761/* 0x07b1: ctx_mmio_exec */ 878 0xbd0023d0,
762 0x81039800, 879/* 0x07c1: ctx_mmio_loop */
763 0x0a0427f1, 880 0xff34c434,
764 0xd00624b6, 881 0xf10f1bf4,
765 0x34bd0023, 882 0xf0020057,
766/* 0x07c0: ctx_mmio_loop */ 883 0x35fa0653,
767 0xf4ff34c4, 884/* 0x07d3: ctx_mmio_pull */
768 0x57f10f1b, 885 0x9803f805,
769 0x53f00300, 886 0x4f98804e,
770 0x0535fa06, 887 0x8d21f481,
771/* 0x07d2: ctx_mmio_pull */ 888 0xb60830b6,
772 0x4e9803f8, 889 0x1bf40112,
773 0xc14f98c0, 890/* 0x07e5: ctx_mmio_done */
774 0xb68d21f4, 891 0x160398df,
775 0x12b60830, 892 0x800023d0,
776 0xdf1bf401, 893 0x17f14000,
777/* 0x07e4: ctx_mmio_done */ 894 0x13f00100,
778 0xd0160398, 895 0x0601fa06,
779 0x00800023, 896 0x00f803f8,
780 0x0017f180, 897/* 0x07fc: ctx_xfer */
781 0x0613f002, 898 0x0c00f7f1,
782 0xf80601fa, 899 0xf006f4b6,
783/* 0x07fb: ctx_xfer */ 900 0xfed004e7,
784 0xf100f803, 901/* 0x0809: ctx_xfer_idle */
785 0xb60c00f7, 902 0x00fecf80,
786 0xe7f006f4, 903 0x2000e4f1,
787 0x80fed004, 904 0xf4f91bf4,
788/* 0x0808: ctx_xfer_idle */ 905 0x02f40611,
789 0xf100fecf, 906/* 0x0819: ctx_xfer_pre */
790 0xf42000e4, 907 0x10f7f00d,
791 0x11f4f91b, 908 0x067321f5,
792 0x0d02f406, 909/* 0x0823: ctx_xfer_pre_load */
793/* 0x0818: ctx_xfer_pre */ 910 0xf01c11f4,
794 0xf510f7f0, 911 0x21f502f7,
795 0xf4067221, 912 0x21f50632,
796/* 0x0822: ctx_xfer_pre_load */ 913 0x21f50641,
797 0xf7f01c11, 914 0xf4bd0653,
798 0x3121f502, 915 0x063221f5,
799 0x4021f506, 916 0x069321f5,
800 0x5221f506, 917/* 0x083c: ctx_xfer_exec */
801 0xf5f4bd06, 918 0xf1160198,
802 0xf5063121, 919 0xb6041427,
803/* 0x083b: ctx_xfer_exec */ 920 0x20d00624,
804 0x98069221, 921 0x00e7f100,
805 0x27f11601, 922 0x41e3f0a5,
806 0x24b60414, 923 0xf4021fb9,
807 0x0020d006, 924 0xe0b68d21,
808 0xa500e7f1, 925 0x01fcf004,
809 0xb941e3f0, 926 0xb6022cf0,
810 0x21f4021f, 927 0xf2fd0124,
811 0x04e0b68d, 928 0x8d21f405,
812 0xf001fcf0, 929 0x4afc17f1,
813 0x24b6022c, 930 0xf00213f0,
814 0x05f2fd01, 931 0x12d00c27,
815 0xf18d21f4, 932 0x0721f500,
816 0xf04afc17, 933 0xfc27f102,
817 0x27f00213, 934 0x0223f047,
818 0x0012d00c, 935 0xf00020d0,
819 0x020721f5, 936 0x20b6012c,
820 0x47fc27f1, 937 0x0012d003,
821 0xd00223f0, 938 0xf001acf0,
822 0x2cf00020, 939 0xb7f006a5,
823 0x0320b601, 940 0x140c9800,
824 0xf00012d0, 941 0xf0150d98,
825 0xa5f001ac, 942 0x21f500e7,
826 0x00b7f006, 943 0xa7f0015c,
827 0x98140c98, 944 0x0321f508,
828 0xe7f0150d, 945 0x0721f501,
829 0x5c21f500, 946 0x2201f402,
830 0x08a7f001, 947 0xf40ca7f0,
831 0x010321f5, 948 0x17f1c921,
832 0x020721f5, 949 0x14b60a10,
833 0xf02201f4, 950 0x0527f006,
834 0x21f40ca7, 951/* 0x08c3: ctx_xfer_post_save_wait */
835 0x1017f1c9, 952 0xcf0012d0,
836 0x0614b60a, 953 0x22fd0012,
837 0xd00527f0, 954 0xfa1bf405,
838/* 0x08c2: ctx_xfer_post_save_wait */ 955/* 0x08cf: ctx_xfer_post */
839 0x12cf0012, 956 0xf02e02f4,
840 0x0522fd00, 957 0x21f502f7,
841 0xf4fa1bf4, 958 0xf4bd0632,
842/* 0x08ce: ctx_xfer_post */ 959 0x067321f5,
843 0xf7f02e02, 960 0x022621f5,
844 0x3121f502, 961 0x064121f5,
845 0xf5f4bd06, 962 0x21f5f4bd,
846 0xf5067221, 963 0x11f40632,
847 0xf5022621, 964 0x40019810,
848 0xbd064021, 965 0xf40511fd,
849 0x3121f5f4, 966 0x21f5070b,
850 0x1011f406, 967/* 0x08fa: ctx_xfer_no_post_mmio */
851 0xfd800198, 968/* 0x08fa: ctx_xfer_done */
852 0x0bf40511, 969 0x00f807b2,
853 0xb121f507,
854/* 0x08f9: ctx_xfer_no_post_mmio */
855/* 0x08f9: ctx_xfer_done */
856 0x0000f807,
857 0x00000000, 970 0x00000000,
858}; 971};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
index c80132c8f01e..9a3c2a31a533 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
@@ -517,6 +517,13 @@ nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
517{ 517{
518 nv_wr32(priv, 0x40415c, 0x00000000); 518 nv_wr32(priv, 0x40415c, 0x00000000);
519 nv_wr32(priv, 0x404170, 0x00000000); 519 nv_wr32(priv, 0x404170, 0x00000000);
520 switch (nv_device(priv)->chipset) {
521 case 0xf0:
522 nv_wr32(priv, 0x4041b4, 0x00000000);
523 break;
524 default:
525 break;
526 }
520} 527}
521 528
522static void 529static void
@@ -551,7 +558,14 @@ nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
551{ 558{
552 nv_wr32(priv, 0x405844, 0x00ffffff); 559 nv_wr32(priv, 0x405844, 0x00ffffff);
553 nv_wr32(priv, 0x405850, 0x00000000); 560 nv_wr32(priv, 0x405850, 0x00000000);
554 nv_wr32(priv, 0x405900, 0x0000ff34); 561 switch (nv_device(priv)->chipset) {
562 case 0xf0:
563 nv_wr32(priv, 0x405900, 0x0000ff00);
564 break;
565 default:
566 nv_wr32(priv, 0x405900, 0x0000ff34);
567 break;
568 }
555 nv_wr32(priv, 0x405908, 0x00000000); 569 nv_wr32(priv, 0x405908, 0x00000000);
556 nv_wr32(priv, 0x405928, 0x00000000); 570 nv_wr32(priv, 0x405928, 0x00000000);
557 nv_wr32(priv, 0x40592c, 0x00000000); 571 nv_wr32(priv, 0x40592c, 0x00000000);
@@ -567,11 +581,26 @@ static void
567nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv) 581nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)
568{ 582{
569 nv_wr32(priv, 0x407010, 0x00000000); 583 nv_wr32(priv, 0x407010, 0x00000000);
584 switch (nv_device(priv)->chipset) {
585 case 0xf0:
586 nv_wr32(priv, 0x407040, 0x80440424);
587 nv_wr32(priv, 0x407048, 0x0000000a);
588 break;
589 default:
590 break;
591 }
570} 592}
571 593
572static void 594static void
573nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv) 595nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)
574{ 596{
597 switch (nv_device(priv)->chipset) {
598 case 0xf0:
599 nv_wr32(priv, 0x505b44, 0x00000000);
600 break;
601 default:
602 break;
603 }
575 nv_wr32(priv, 0x405b50, 0x00000000); 604 nv_wr32(priv, 0x405b50, 0x00000000);
576} 605}
577 606
@@ -610,11 +639,25 @@ nve0_graph_init_gpc(struct nvc0_graph_priv *priv)
610 nv_wr32(priv, 0x418d00, 0x00000000); 639 nv_wr32(priv, 0x418d00, 0x00000000);
611 nv_wr32(priv, 0x418d28, 0x00000000); 640 nv_wr32(priv, 0x418d28, 0x00000000);
612 nv_wr32(priv, 0x418d2c, 0x00000000); 641 nv_wr32(priv, 0x418d2c, 0x00000000);
613 nv_wr32(priv, 0x418f00, 0x00000000); 642 switch (nv_device(priv)->chipset) {
643 case 0xf0:
644 nv_wr32(priv, 0x418f00, 0x00000400);
645 break;
646 default:
647 nv_wr32(priv, 0x418f00, 0x00000000);
648 break;
649 }
614 nv_wr32(priv, 0x418f08, 0x00000000); 650 nv_wr32(priv, 0x418f08, 0x00000000);
615 nv_wr32(priv, 0x418f20, 0x00000000); 651 nv_wr32(priv, 0x418f20, 0x00000000);
616 nv_wr32(priv, 0x418f24, 0x00000000); 652 nv_wr32(priv, 0x418f24, 0x00000000);
617 nv_wr32(priv, 0x418e00, 0x00000060); 653 switch (nv_device(priv)->chipset) {
654 case 0xf0:
655 nv_wr32(priv, 0x418e00, 0x00000000);
656 break;
657 default:
658 nv_wr32(priv, 0x418e00, 0x00000060);
659 break;
660 }
618 nv_wr32(priv, 0x418e08, 0x00000000); 661 nv_wr32(priv, 0x418e08, 0x00000000);
619 nv_wr32(priv, 0x418e1c, 0x00000000); 662 nv_wr32(priv, 0x418e1c, 0x00000000);
620 nv_wr32(priv, 0x418e20, 0x00000000); 663 nv_wr32(priv, 0x418e20, 0x00000000);
@@ -630,9 +673,24 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
630 nv_wr32(priv, 0x419ab0, 0x00000000); 673 nv_wr32(priv, 0x419ab0, 0x00000000);
631 nv_wr32(priv, 0x419ac8, 0x00000000); 674 nv_wr32(priv, 0x419ac8, 0x00000000);
632 nv_wr32(priv, 0x419ab8, 0x000000e7); 675 nv_wr32(priv, 0x419ab8, 0x000000e7);
676 switch (nv_device(priv)->chipset) {
677 case 0xf0:
678 nv_wr32(priv, 0x419aec, 0x00000000);
679 break;
680 default:
681 break;
682 }
633 nv_wr32(priv, 0x419abc, 0x00000000); 683 nv_wr32(priv, 0x419abc, 0x00000000);
634 nv_wr32(priv, 0x419ac0, 0x00000000); 684 nv_wr32(priv, 0x419ac0, 0x00000000);
635 nv_wr32(priv, 0x419ab4, 0x00000000); 685 nv_wr32(priv, 0x419ab4, 0x00000000);
686 switch (nv_device(priv)->chipset) {
687 case 0xf0:
688 nv_wr32(priv, 0x419aa8, 0x00000000);
689 nv_wr32(priv, 0x419aac, 0x00000000);
690 break;
691 default:
692 break;
693 }
636 nv_wr32(priv, 0x41980c, 0x00000010); 694 nv_wr32(priv, 0x41980c, 0x00000010);
637 nv_wr32(priv, 0x419844, 0x00000000); 695 nv_wr32(priv, 0x419844, 0x00000000);
638 nv_wr32(priv, 0x419850, 0x00000004); 696 nv_wr32(priv, 0x419850, 0x00000004);
@@ -644,23 +702,59 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
644 nv_wr32(priv, 0x419cb4, 0x00000000); 702 nv_wr32(priv, 0x419cb4, 0x00000000);
645 nv_wr32(priv, 0x419cb8, 0x00b08bea); 703 nv_wr32(priv, 0x419cb8, 0x00b08bea);
646 nv_wr32(priv, 0x419c84, 0x00010384); 704 nv_wr32(priv, 0x419c84, 0x00010384);
647 nv_wr32(priv, 0x419cbc, 0x28137646); 705 switch (nv_device(priv)->chipset) {
706 case 0xf0:
707 nv_wr32(priv, 0x419cbc, 0x281b3646);
708 break;
709 default:
710 nv_wr32(priv, 0x419cbc, 0x28137646);
711 break;
712 }
648 nv_wr32(priv, 0x419cc0, 0x00000000); 713 nv_wr32(priv, 0x419cc0, 0x00000000);
649 nv_wr32(priv, 0x419cc4, 0x00000000); 714 nv_wr32(priv, 0x419cc4, 0x00000000);
650 nv_wr32(priv, 0x419c80, 0x00020232); 715 switch (nv_device(priv)->chipset) {
651 nv_wr32(priv, 0x419c0c, 0x00000000); 716 case 0xf0:
652 nv_wr32(priv, 0x419e00, 0x00000000); 717 nv_wr32(priv, 0x419c80, 0x00020230);
718 nv_wr32(priv, 0x419ccc, 0x00000000);
719 nv_wr32(priv, 0x419cd0, 0x00000000);
720 nv_wr32(priv, 0x419c0c, 0x00000000);
721 nv_wr32(priv, 0x419e00, 0x00000080);
722 break;
723 default:
724 nv_wr32(priv, 0x419c80, 0x00020232);
725 nv_wr32(priv, 0x419c0c, 0x00000000);
726 nv_wr32(priv, 0x419e00, 0x00000000);
727 break;
728 }
653 nv_wr32(priv, 0x419ea0, 0x00000000); 729 nv_wr32(priv, 0x419ea0, 0x00000000);
654 nv_wr32(priv, 0x419ee4, 0x00000000); 730 nv_wr32(priv, 0x419ee4, 0x00000000);
655 nv_wr32(priv, 0x419ea4, 0x00000100); 731 nv_wr32(priv, 0x419ea4, 0x00000100);
656 nv_wr32(priv, 0x419ea8, 0x00000000); 732 nv_wr32(priv, 0x419ea8, 0x00000000);
657 nv_wr32(priv, 0x419eb4, 0x00000000); 733 nv_wr32(priv, 0x419eb4, 0x00000000);
658 nv_wr32(priv, 0x419eb8, 0x00000000); 734 switch (nv_device(priv)->chipset) {
735 case 0xf0:
736 break;
737 default:
738 nv_wr32(priv, 0x419eb8, 0x00000000);
739 break;
740 }
659 nv_wr32(priv, 0x419ebc, 0x00000000); 741 nv_wr32(priv, 0x419ebc, 0x00000000);
660 nv_wr32(priv, 0x419ec0, 0x00000000); 742 nv_wr32(priv, 0x419ec0, 0x00000000);
661 nv_wr32(priv, 0x419edc, 0x00000000); 743 nv_wr32(priv, 0x419edc, 0x00000000);
662 nv_wr32(priv, 0x419f00, 0x00000000); 744 nv_wr32(priv, 0x419f00, 0x00000000);
663 nv_wr32(priv, 0x419f74, 0x00000555); 745 switch (nv_device(priv)->chipset) {
746 case 0xf0:
747 nv_wr32(priv, 0x419ed0, 0x00003234);
748 nv_wr32(priv, 0x419f74, 0x00015555);
749 nv_wr32(priv, 0x419f80, 0x00000000);
750 nv_wr32(priv, 0x419f84, 0x00000000);
751 nv_wr32(priv, 0x419f88, 0x00000000);
752 nv_wr32(priv, 0x419f8c, 0x00000000);
753 break;
754 default:
755 nv_wr32(priv, 0x419f74, 0x00000555);
756 break;
757 }
664} 758}
665 759
666static void 760static void
@@ -726,6 +820,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv)
726 switch (nv_device(priv)->chipset) { 820 switch (nv_device(priv)->chipset) {
727 case 0xe7: 821 case 0xe7:
728 case 0xe6: 822 case 0xe6:
823 case 0xf0:
729 nv_wr32(priv, 0x407020, 0x40000000); 824 nv_wr32(priv, 0x407020, 0x40000000);
730 break; 825 break;
731 default: 826 default:
@@ -971,6 +1066,7 @@ nve0_graph_init(struct nouveau_object *object)
971 switch (nv_device(priv)->chipset) { 1066 switch (nv_device(priv)->chipset) {
972 case 0xe7: 1067 case 0xe7:
973 case 0xe6: 1068 case 0xe6:
1069 case 0xf0:
974 nve0_graph_init_unk40xx(priv); 1070 nve0_graph_init_unk40xx(priv);
975 nve0_graph_init_unk44xx(priv); 1071 nve0_graph_init_unk44xx(priv);
976 nve0_graph_init_unk78xx(priv); 1072 nve0_graph_init_unk78xx(priv);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 08:29:09 -0400