drm/nve7/gr: update initial register/context values

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

4 files changed, 12 insertions, 3 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
index d4e54745876b..f884ffbd408e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
@@ -750,6 +750,7 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x000842, 0x00400008);
         nv_icmd(priv, 0x000843, 0x08000080);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 break;
         default:
@@ -869,6 +870,7 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x000814, 0x00000008);
         nv_icmd(priv, 0x000957, 0x00000003);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 break;
         default:
@@ -2178,6 +2180,7 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
         case 0xe6:
                 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
                 break;
+        case 0xe7:
         default:
                 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
                 break;
@@ -2547,6 +2550,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x419e94, 0x0);
         nv_wr32(priv, 0x419e98, 0x0);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nv_wr32(priv, 0x419eac, 0x1f8f);
                 break;
@@ -2566,6 +2570,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x419f4c, 0x0);
         nv_wr32(priv, 0x419f58, 0x0);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nv_wr32(priv, 0x419f70, 0x0);
                 break;
@@ -2574,6 +2579,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
         }
         nv_wr32(priv, 0x419f78, 0xb);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nv_wr32(priv, 0x419f7c, 0x27a);
                 break;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index f58c4d0762d3..2aed9a54062d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -55,8 +55,8 @@ chipsets:
 .b8  0xe7 0 0 0
 .b16 #nve4_gpc_mmio_head
 .b16 #nve4_gpc_mmio_tail
-.b16 #nve4_tpc_mmio_head
-.b16 #nve4_tpc_mmio_tail
+.b16 #nve6_tpc_mmio_head
+.b16 #nve6_tpc_mmio_tail
 .b8  0xe6 0 0 0
 .b16 #nve4_gpc_mmio_head
 .b16 #nve4_gpc_mmio_tail
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 321834f15311..1f33a66f96af 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -38,7 +38,7 @@ uint32_t nve0_grgpc_data[] = {
         0x01580110,
         0x000000e7,
         0x0110008c,
-        0x01580110,
+        0x01a40158,
         0x000000e6,
         0x0110008c,
         0x01a40158,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
index b7324138df02..c80132c8f01e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
@@ -709,6 +709,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x409ffc, 0x00000000);
         nv_wr32(priv, 0x409c14, 0x00003e3e);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nv_wr32(priv, 0x409c24, 0x000f0001);
                 break;
@@ -723,6 +724,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x404490, 0xc0000000);
         nv_wr32(priv, 0x406018, 0xc0000000);
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nv_wr32(priv, 0x407020, 0x40000000);
                 break;
@@ -967,6 +969,7 @@ nve0_graph_init(struct nouveau_object *object)
         nve0_graph_init_regs(priv);
 
         switch (nv_device(priv)->chipset) {
+        case 0xe7:
         case 0xe6:
                 nve0_graph_init_unk40xx(priv);
                 nve0_graph_init_unk44xx(priv);