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authorBen Skeggs <bskeggs@redhat.com>2013-05-05 21:35:37 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-06-30 23:50:35 -0400
commit99bd5537bd22256866d83033e0aab2586616bcc2 (patch)
treea790d7d925946874d8f9b92a62431eee97cb35f4
parentc4c7044ffc1ba973e2ec0f0dc94980b49101d877 (diff)
drm/nve6/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c217
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc26
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h23
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nve0.c230
4 files changed, 383 insertions, 113 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
index ae27dae3fe38..d4e54745876b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
@@ -749,31 +749,37 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
749 nv_icmd(priv, 0x000841, 0x08000080); 749 nv_icmd(priv, 0x000841, 0x08000080);
750 nv_icmd(priv, 0x000842, 0x00400008); 750 nv_icmd(priv, 0x000842, 0x00400008);
751 nv_icmd(priv, 0x000843, 0x08000080); 751 nv_icmd(priv, 0x000843, 0x08000080);
752 nv_icmd(priv, 0x000818, 0x00000000); 752 switch (nv_device(priv)->chipset) {
753 nv_icmd(priv, 0x000819, 0x00000000); 753 case 0xe6:
754 nv_icmd(priv, 0x00081a, 0x00000000); 754 break;
755 nv_icmd(priv, 0x00081b, 0x00000000); 755 default:
756 nv_icmd(priv, 0x00081c, 0x00000000); 756 nv_icmd(priv, 0x000818, 0x00000000);
757 nv_icmd(priv, 0x00081d, 0x00000000); 757 nv_icmd(priv, 0x000819, 0x00000000);
758 nv_icmd(priv, 0x00081e, 0x00000000); 758 nv_icmd(priv, 0x00081a, 0x00000000);
759 nv_icmd(priv, 0x00081f, 0x00000000); 759 nv_icmd(priv, 0x00081b, 0x00000000);
760 nv_icmd(priv, 0x000848, 0x00000000); 760 nv_icmd(priv, 0x00081c, 0x00000000);
761 nv_icmd(priv, 0x000849, 0x00000000); 761 nv_icmd(priv, 0x00081d, 0x00000000);
762 nv_icmd(priv, 0x00084a, 0x00000000); 762 nv_icmd(priv, 0x00081e, 0x00000000);
763 nv_icmd(priv, 0x00084b, 0x00000000); 763 nv_icmd(priv, 0x00081f, 0x00000000);
764 nv_icmd(priv, 0x00084c, 0x00000000); 764 nv_icmd(priv, 0x000848, 0x00000000);
765 nv_icmd(priv, 0x00084d, 0x00000000); 765 nv_icmd(priv, 0x000849, 0x00000000);
766 nv_icmd(priv, 0x00084e, 0x00000000); 766 nv_icmd(priv, 0x00084a, 0x00000000);
767 nv_icmd(priv, 0x00084f, 0x00000000); 767 nv_icmd(priv, 0x00084b, 0x00000000);
768 nv_icmd(priv, 0x000850, 0x00000000); 768 nv_icmd(priv, 0x00084c, 0x00000000);
769 nv_icmd(priv, 0x000851, 0x00000000); 769 nv_icmd(priv, 0x00084d, 0x00000000);
770 nv_icmd(priv, 0x000852, 0x00000000); 770 nv_icmd(priv, 0x00084e, 0x00000000);
771 nv_icmd(priv, 0x000853, 0x00000000); 771 nv_icmd(priv, 0x00084f, 0x00000000);
772 nv_icmd(priv, 0x000854, 0x00000000); 772 nv_icmd(priv, 0x000850, 0x00000000);
773 nv_icmd(priv, 0x000855, 0x00000000); 773 nv_icmd(priv, 0x000851, 0x00000000);
774 nv_icmd(priv, 0x000856, 0x00000000); 774 nv_icmd(priv, 0x000852, 0x00000000);
775 nv_icmd(priv, 0x000857, 0x00000000); 775 nv_icmd(priv, 0x000853, 0x00000000);
776 nv_icmd(priv, 0x000738, 0x00000000); 776 nv_icmd(priv, 0x000854, 0x00000000);
777 nv_icmd(priv, 0x000855, 0x00000000);
778 nv_icmd(priv, 0x000856, 0x00000000);
779 nv_icmd(priv, 0x000857, 0x00000000);
780 nv_icmd(priv, 0x000738, 0x00000000);
781 break;
782 }
777 nv_icmd(priv, 0x0006aa, 0x00000001); 783 nv_icmd(priv, 0x0006aa, 0x00000001);
778 nv_icmd(priv, 0x0006ab, 0x00000002); 784 nv_icmd(priv, 0x0006ab, 0x00000002);
779 nv_icmd(priv, 0x0006ac, 0x00000080); 785 nv_icmd(priv, 0x0006ac, 0x00000080);
@@ -862,31 +868,37 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
862 nv_icmd(priv, 0x000813, 0x00000006); 868 nv_icmd(priv, 0x000813, 0x00000006);
863 nv_icmd(priv, 0x000814, 0x00000008); 869 nv_icmd(priv, 0x000814, 0x00000008);
864 nv_icmd(priv, 0x000957, 0x00000003); 870 nv_icmd(priv, 0x000957, 0x00000003);
865 nv_icmd(priv, 0x000818, 0x00000000); 871 switch (nv_device(priv)->chipset) {
866 nv_icmd(priv, 0x000819, 0x00000000); 872 case 0xe6:
867 nv_icmd(priv, 0x00081a, 0x00000000); 873 break;
868 nv_icmd(priv, 0x00081b, 0x00000000); 874 default:
869 nv_icmd(priv, 0x00081c, 0x00000000); 875 nv_icmd(priv, 0x000818, 0x00000000);
870 nv_icmd(priv, 0x00081d, 0x00000000); 876 nv_icmd(priv, 0x000819, 0x00000000);
871 nv_icmd(priv, 0x00081e, 0x00000000); 877 nv_icmd(priv, 0x00081a, 0x00000000);
872 nv_icmd(priv, 0x00081f, 0x00000000); 878 nv_icmd(priv, 0x00081b, 0x00000000);
873 nv_icmd(priv, 0x000848, 0x00000000); 879 nv_icmd(priv, 0x00081c, 0x00000000);
874 nv_icmd(priv, 0x000849, 0x00000000); 880 nv_icmd(priv, 0x00081d, 0x00000000);
875 nv_icmd(priv, 0x00084a, 0x00000000); 881 nv_icmd(priv, 0x00081e, 0x00000000);
876 nv_icmd(priv, 0x00084b, 0x00000000); 882 nv_icmd(priv, 0x00081f, 0x00000000);
877 nv_icmd(priv, 0x00084c, 0x00000000); 883 nv_icmd(priv, 0x000848, 0x00000000);
878 nv_icmd(priv, 0x00084d, 0x00000000); 884 nv_icmd(priv, 0x000849, 0x00000000);
879 nv_icmd(priv, 0x00084e, 0x00000000); 885 nv_icmd(priv, 0x00084a, 0x00000000);
880 nv_icmd(priv, 0x00084f, 0x00000000); 886 nv_icmd(priv, 0x00084b, 0x00000000);
881 nv_icmd(priv, 0x000850, 0x00000000); 887 nv_icmd(priv, 0x00084c, 0x00000000);
882 nv_icmd(priv, 0x000851, 0x00000000); 888 nv_icmd(priv, 0x00084d, 0x00000000);
883 nv_icmd(priv, 0x000852, 0x00000000); 889 nv_icmd(priv, 0x00084e, 0x00000000);
884 nv_icmd(priv, 0x000853, 0x00000000); 890 nv_icmd(priv, 0x00084f, 0x00000000);
885 nv_icmd(priv, 0x000854, 0x00000000); 891 nv_icmd(priv, 0x000850, 0x00000000);
886 nv_icmd(priv, 0x000855, 0x00000000); 892 nv_icmd(priv, 0x000851, 0x00000000);
887 nv_icmd(priv, 0x000856, 0x00000000); 893 nv_icmd(priv, 0x000852, 0x00000000);
888 nv_icmd(priv, 0x000857, 0x00000000); 894 nv_icmd(priv, 0x000853, 0x00000000);
889 nv_icmd(priv, 0x000738, 0x00000000); 895 nv_icmd(priv, 0x000854, 0x00000000);
896 nv_icmd(priv, 0x000855, 0x00000000);
897 nv_icmd(priv, 0x000856, 0x00000000);
898 nv_icmd(priv, 0x000857, 0x00000000);
899 nv_icmd(priv, 0x000738, 0x00000000);
900 break;
901 }
890 nv_icmd(priv, 0x000b07, 0x00000002); 902 nv_icmd(priv, 0x000b07, 0x00000002);
891 nv_icmd(priv, 0x000b08, 0x00000100); 903 nv_icmd(priv, 0x000b08, 0x00000100);
892 nv_icmd(priv, 0x000b09, 0x00000100); 904 nv_icmd(priv, 0x000b09, 0x00000100);
@@ -2162,7 +2174,14 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
2162 nv_mthd(priv, 0x902d, 0x0244, 0x00000080); 2174 nv_mthd(priv, 0x902d, 0x0244, 0x00000080);
2163 nv_mthd(priv, 0x902d, 0x0248, 0x00000100); 2175 nv_mthd(priv, 0x902d, 0x0248, 0x00000100);
2164 nv_mthd(priv, 0x902d, 0x024c, 0x00000100); 2176 nv_mthd(priv, 0x902d, 0x024c, 0x00000100);
2165 nv_mthd(priv, 0x902d, 0x3410, 0x00000000); 2177 switch (nv_device(priv)->chipset) {
2178 case 0xe6:
2179 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
2180 break;
2181 default:
2182 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
2183 break;
2184 }
2166} 2185}
2167 2186
2168static void 2187static void
@@ -2310,6 +2329,11 @@ nve0_graph_generate_unk58xx(struct nvc0_graph_priv *priv)
2310 nv_wr32(priv, 0x405a00, 0x0); 2329 nv_wr32(priv, 0x405a00, 0x0);
2311 nv_wr32(priv, 0x405a04, 0x0); 2330 nv_wr32(priv, 0x405a04, 0x0);
2312 nv_wr32(priv, 0x405a18, 0x0); 2331 nv_wr32(priv, 0x405a18, 0x0);
2332}
2333
2334static void
2335nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv)
2336{
2313 nv_wr32(priv, 0x405b00, 0x0); 2337 nv_wr32(priv, 0x405b00, 0x0);
2314 nv_wr32(priv, 0x405b10, 0x1000); 2338 nv_wr32(priv, 0x405b10, 0x1000);
2315} 2339}
@@ -2394,6 +2418,8 @@ nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)
2394static void 2418static void
2395nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) 2419nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
2396{ 2420{
2421 int i;
2422
2397 nv_wr32(priv, 0x418380, 0x16); 2423 nv_wr32(priv, 0x418380, 0x16);
2398 nv_wr32(priv, 0x418400, 0x38004e00); 2424 nv_wr32(priv, 0x418400, 0x38004e00);
2399 nv_wr32(priv, 0x418404, 0x71e0ffff); 2425 nv_wr32(priv, 0x418404, 0x71e0ffff);
@@ -2434,62 +2460,15 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
2434 nv_wr32(priv, 0x418924, 0x0); 2460 nv_wr32(priv, 0x418924, 0x0);
2435 nv_wr32(priv, 0x418928, 0xffff00); 2461 nv_wr32(priv, 0x418928, 0xffff00);
2436 nv_wr32(priv, 0x41892c, 0xff00); 2462 nv_wr32(priv, 0x41892c, 0xff00);
2437 nv_wr32(priv, 0x418a00, 0x0); 2463 for (i = 0; i < 8; i++) {
2438 nv_wr32(priv, 0x418a04, 0x0); 2464 nv_wr32(priv, 0x418a00 + (i * 0x20), 0x0);
2439 nv_wr32(priv, 0x418a08, 0x0); 2465 nv_wr32(priv, 0x418a04 + (i * 0x20), 0x0);
2440 nv_wr32(priv, 0x418a0c, 0x10000); 2466 nv_wr32(priv, 0x418a08 + (i * 0x20), 0x0);
2441 nv_wr32(priv, 0x418a10, 0x0); 2467 nv_wr32(priv, 0x418a0c + (i * 0x20), 0x10000);
2442 nv_wr32(priv, 0x418a14, 0x0); 2468 nv_wr32(priv, 0x418a10 + (i * 0x20), 0x0);
2443 nv_wr32(priv, 0x418a18, 0x0); 2469 nv_wr32(priv, 0x418a14 + (i * 0x20), 0x0);
2444 nv_wr32(priv, 0x418a20, 0x0); 2470 nv_wr32(priv, 0x418a18 + (i * 0x20), 0x0);
2445 nv_wr32(priv, 0x418a24, 0x0); 2471 }
2446 nv_wr32(priv, 0x418a28, 0x0);
2447 nv_wr32(priv, 0x418a2c, 0x10000);
2448 nv_wr32(priv, 0x418a30, 0x0);
2449 nv_wr32(priv, 0x418a34, 0x0);
2450 nv_wr32(priv, 0x418a38, 0x0);
2451 nv_wr32(priv, 0x418a40, 0x0);
2452 nv_wr32(priv, 0x418a44, 0x0);
2453 nv_wr32(priv, 0x418a48, 0x0);
2454 nv_wr32(priv, 0x418a4c, 0x10000);
2455 nv_wr32(priv, 0x418a50, 0x0);
2456 nv_wr32(priv, 0x418a54, 0x0);
2457 nv_wr32(priv, 0x418a58, 0x0);
2458 nv_wr32(priv, 0x418a60, 0x0);
2459 nv_wr32(priv, 0x418a64, 0x0);
2460 nv_wr32(priv, 0x418a68, 0x0);
2461 nv_wr32(priv, 0x418a6c, 0x10000);
2462 nv_wr32(priv, 0x418a70, 0x0);
2463 nv_wr32(priv, 0x418a74, 0x0);
2464 nv_wr32(priv, 0x418a78, 0x0);
2465 nv_wr32(priv, 0x418a80, 0x0);
2466 nv_wr32(priv, 0x418a84, 0x0);
2467 nv_wr32(priv, 0x418a88, 0x0);
2468 nv_wr32(priv, 0x418a8c, 0x10000);
2469 nv_wr32(priv, 0x418a90, 0x0);
2470 nv_wr32(priv, 0x418a94, 0x0);
2471 nv_wr32(priv, 0x418a98, 0x0);
2472 nv_wr32(priv, 0x418aa0, 0x0);
2473 nv_wr32(priv, 0x418aa4, 0x0);
2474 nv_wr32(priv, 0x418aa8, 0x0);
2475 nv_wr32(priv, 0x418aac, 0x10000);
2476 nv_wr32(priv, 0x418ab0, 0x0);
2477 nv_wr32(priv, 0x418ab4, 0x0);
2478 nv_wr32(priv, 0x418ab8, 0x0);
2479 nv_wr32(priv, 0x418ac0, 0x0);
2480 nv_wr32(priv, 0x418ac4, 0x0);
2481 nv_wr32(priv, 0x418ac8, 0x0);
2482 nv_wr32(priv, 0x418acc, 0x10000);
2483 nv_wr32(priv, 0x418ad0, 0x0);
2484 nv_wr32(priv, 0x418ad4, 0x0);
2485 nv_wr32(priv, 0x418ad8, 0x0);
2486 nv_wr32(priv, 0x418ae0, 0x0);
2487 nv_wr32(priv, 0x418ae4, 0x0);
2488 nv_wr32(priv, 0x418ae8, 0x0);
2489 nv_wr32(priv, 0x418aec, 0x10000);
2490 nv_wr32(priv, 0x418af0, 0x0);
2491 nv_wr32(priv, 0x418af4, 0x0);
2492 nv_wr32(priv, 0x418af8, 0x0);
2493 nv_wr32(priv, 0x418b00, 0x6); 2472 nv_wr32(priv, 0x418b00, 0x6);
2494 nv_wr32(priv, 0x418b08, 0xa418820); 2473 nv_wr32(priv, 0x418b08, 0xa418820);
2495 nv_wr32(priv, 0x418b0c, 0x62080e6); 2474 nv_wr32(priv, 0x418b0c, 0x62080e6);
@@ -2567,7 +2546,14 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
2567 nv_wr32(priv, 0x419e90, 0x0); 2546 nv_wr32(priv, 0x419e90, 0x0);
2568 nv_wr32(priv, 0x419e94, 0x0); 2547 nv_wr32(priv, 0x419e94, 0x0);
2569 nv_wr32(priv, 0x419e98, 0x0); 2548 nv_wr32(priv, 0x419e98, 0x0);
2570 nv_wr32(priv, 0x419eac, 0x1fcf); 2549 switch (nv_device(priv)->chipset) {
2550 case 0xe6:
2551 nv_wr32(priv, 0x419eac, 0x1f8f);
2552 break;
2553 default:
2554 nv_wr32(priv, 0x419eac, 0x1fcf);
2555 break;
2556 }
2571 nv_wr32(priv, 0x419eb0, 0xd3f); 2557 nv_wr32(priv, 0x419eb0, 0xd3f);
2572 nv_wr32(priv, 0x419ec8, 0x1304f); 2558 nv_wr32(priv, 0x419ec8, 0x1304f);
2573 nv_wr32(priv, 0x419f30, 0x0); 2559 nv_wr32(priv, 0x419f30, 0x0);
@@ -2579,7 +2565,21 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
2579 nv_wr32(priv, 0x419f48, 0x0); 2565 nv_wr32(priv, 0x419f48, 0x0);
2580 nv_wr32(priv, 0x419f4c, 0x0); 2566 nv_wr32(priv, 0x419f4c, 0x0);
2581 nv_wr32(priv, 0x419f58, 0x0); 2567 nv_wr32(priv, 0x419f58, 0x0);
2568 switch (nv_device(priv)->chipset) {
2569 case 0xe6:
2570 nv_wr32(priv, 0x419f70, 0x0);
2571 break;
2572 default:
2573 break;
2574 }
2582 nv_wr32(priv, 0x419f78, 0xb); 2575 nv_wr32(priv, 0x419f78, 0xb);
2576 switch (nv_device(priv)->chipset) {
2577 case 0xe6:
2578 nv_wr32(priv, 0x419f7c, 0x27a);
2579 break;
2580 default:
2581 break;
2582 }
2583} 2583}
2584 2584
2585static void 2585static void
@@ -2624,6 +2624,7 @@ nve0_grctx_generate(struct nvc0_graph_priv *priv)
2624 nve0_graph_generate_unk46xx(priv); 2624 nve0_graph_generate_unk46xx(priv);
2625 nve0_graph_generate_unk47xx(priv); 2625 nve0_graph_generate_unk47xx(priv);
2626 nve0_graph_generate_unk58xx(priv); 2626 nve0_graph_generate_unk58xx(priv);
2627 nve0_graph_generate_unk5bxx(priv);
2627 nve0_graph_generate_unk60xx(priv); 2628 nve0_graph_generate_unk60xx(priv);
2628 nve0_graph_generate_unk64xx(priv); 2629 nve0_graph_generate_unk64xx(priv);
2629 nve0_graph_generate_unk70xx(priv); 2630 nve0_graph_generate_unk70xx(priv);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index 62ab231cd6b6..f58c4d0762d3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -60,8 +60,8 @@ chipsets:
60.b8 0xe6 0 0 0 60.b8 0xe6 0 0 0
61.b16 #nve4_gpc_mmio_head 61.b16 #nve4_gpc_mmio_head
62.b16 #nve4_gpc_mmio_tail 62.b16 #nve4_gpc_mmio_tail
63.b16 #nve4_tpc_mmio_head 63.b16 #nve6_tpc_mmio_head
64.b16 #nve4_tpc_mmio_tail 64.b16 #nve6_tpc_mmio_tail
65.b8 0 0 0 0 65.b8 0 0 0 0
66 66
67// GPC mmio lists 67// GPC mmio lists
@@ -123,6 +123,28 @@ mmctx_data(0x000758, 1)
123mmctx_data(0x000778, 1) 123mmctx_data(0x000778, 1)
124nve4_tpc_mmio_tail: 124nve4_tpc_mmio_tail:
125 125
126nve6_tpc_mmio_head:
127mmctx_data(0x000048, 1)
128mmctx_data(0x000064, 1)
129mmctx_data(0x000088, 1)
130mmctx_data(0x000200, 6)
131mmctx_data(0x00021c, 2)
132mmctx_data(0x000230, 1)
133mmctx_data(0x0002c4, 1)
134mmctx_data(0x000400, 3)
135mmctx_data(0x000420, 3)
136mmctx_data(0x0004e8, 1)
137mmctx_data(0x0004f4, 1)
138mmctx_data(0x000604, 4)
139mmctx_data(0x000644, 22)
140mmctx_data(0x0006ac, 2)
141mmctx_data(0x0006c8, 1)
142mmctx_data(0x000730, 8)
143mmctx_data(0x000758, 1)
144mmctx_data(0x000770, 1)
145mmctx_data(0x000778, 2)
146nve6_tpc_mmio_tail:
147
126.section #nve0_grgpc_code 148.section #nve0_grgpc_code
127bra #init 149bra #init
128define(`include_code') 150define(`include_code')
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 09ee4702c8b2..321834f15311 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -41,7 +41,7 @@ uint32_t nve0_grgpc_data[] = {
41 0x01580110, 41 0x01580110,
42 0x000000e6, 42 0x000000e6,
43 0x0110008c, 43 0x0110008c,
44 0x01580110, 44 0x01a40158,
45 0x00000000, 45 0x00000000,
46/* 0x008c: nve4_gpc_mmio_head */ 46/* 0x008c: nve4_gpc_mmio_head */
47 0x00000380, 47 0x00000380,
@@ -97,6 +97,27 @@ uint32_t nve0_grgpc_data[] = {
97 0x1c000730, 97 0x1c000730,
98 0x00000758, 98 0x00000758,
99 0x00000778, 99 0x00000778,
100/* 0x0158: nve4_tpc_mmio_tail */
101/* 0x0158: nve6_tpc_mmio_head */
102 0x00000048,
103 0x00000064,
104 0x00000088,
105 0x14000200,
106 0x0400021c,
107 0x00000230,
108 0x000002c4,
109 0x08000400,
110 0x08000420,
111 0x000004e8,
112 0x000004f4,
113 0x0c000604,
114 0x54000644,
115 0x040006ac,
116 0x000006c8,
117 0x1c000730,
118 0x00000758,
119 0x00000770,
120 0x04000778,
100}; 121};
101 122
102uint32_t nve0_grgpc_code[] = { 123uint32_t nve0_grgpc_code[] = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
index 84249f8c99c6..b7324138df02 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
@@ -513,18 +513,223 @@ nve0_graph_init_regs(struct nvc0_graph_priv *priv)
513} 513}
514 514
515static void 515static void
516nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
517{
518 nv_wr32(priv, 0x40415c, 0x00000000);
519 nv_wr32(priv, 0x404170, 0x00000000);
520}
521
522static void
523nve0_graph_init_unk44xx(struct nvc0_graph_priv *priv)
524{
525 nv_wr32(priv, 0x404488, 0x00000000);
526 nv_wr32(priv, 0x40448c, 0x00000000);
527}
528
529static void
530nve0_graph_init_unk78xx(struct nvc0_graph_priv *priv)
531{
532 nv_wr32(priv, 0x407808, 0x00000000);
533}
534
535static void
536nve0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
537{
538 nv_wr32(priv, 0x406024, 0x00000000);
539}
540
541static void
542nve0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
543{
544 nv_wr32(priv, 0x4064f0, 0x00000000);
545 nv_wr32(priv, 0x4064f4, 0x00000000);
546 nv_wr32(priv, 0x4064f8, 0x00000000);
547}
548
549static void
550nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
551{
552 nv_wr32(priv, 0x405844, 0x00ffffff);
553 nv_wr32(priv, 0x405850, 0x00000000);
554 nv_wr32(priv, 0x405900, 0x0000ff34);
555 nv_wr32(priv, 0x405908, 0x00000000);
556 nv_wr32(priv, 0x405928, 0x00000000);
557 nv_wr32(priv, 0x40592c, 0x00000000);
558}
559
560static void
561nve0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
562{
563 nv_wr32(priv, 0x40803c, 0x00000000);
564}
565
566static void
567nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)
568{
569 nv_wr32(priv, 0x407010, 0x00000000);
570}
571
572static void
573nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)
574{
575 nv_wr32(priv, 0x405b50, 0x00000000);
576}
577
578static void
579nve0_graph_init_gpc(struct nvc0_graph_priv *priv)
580{
581 nv_wr32(priv, 0x418408, 0x00000000);
582 nv_wr32(priv, 0x4184a0, 0x00000000);
583 nv_wr32(priv, 0x4184a4, 0x00000000);
584 nv_wr32(priv, 0x4184a8, 0x00000000);
585 nv_wr32(priv, 0x418604, 0x00000000);
586 nv_wr32(priv, 0x418680, 0x00000000);
587 nv_wr32(priv, 0x418714, 0x00000000);
588 nv_wr32(priv, 0x418384, 0x00000000);
589 nv_wr32(priv, 0x418814, 0x00000000);
590 nv_wr32(priv, 0x418818, 0x00000000);
591 nv_wr32(priv, 0x41881c, 0x00000000);
592 nv_wr32(priv, 0x418b04, 0x00000000);
593 nv_wr32(priv, 0x4188c8, 0x00000000);
594 nv_wr32(priv, 0x4188cc, 0x00000000);
595 nv_wr32(priv, 0x4188d0, 0x00010000);
596 nv_wr32(priv, 0x4188d4, 0x00000001);
597 nv_wr32(priv, 0x418910, 0x00010001);
598 nv_wr32(priv, 0x418914, 0x00000301);
599 nv_wr32(priv, 0x418918, 0x00800000);
600 nv_wr32(priv, 0x418980, 0x77777770);
601 nv_wr32(priv, 0x418984, 0x77777777);
602 nv_wr32(priv, 0x418988, 0x77777777);
603 nv_wr32(priv, 0x41898c, 0x77777777);
604 nv_wr32(priv, 0x418c04, 0x00000000);
605 nv_wr32(priv, 0x418c64, 0x00000000);
606 nv_wr32(priv, 0x418c68, 0x00000000);
607 nv_wr32(priv, 0x418c88, 0x00000000);
608 nv_wr32(priv, 0x418cb4, 0x00000000);
609 nv_wr32(priv, 0x418cb8, 0x00000000);
610 nv_wr32(priv, 0x418d00, 0x00000000);
611 nv_wr32(priv, 0x418d28, 0x00000000);
612 nv_wr32(priv, 0x418d2c, 0x00000000);
613 nv_wr32(priv, 0x418f00, 0x00000000);
614 nv_wr32(priv, 0x418f08, 0x00000000);
615 nv_wr32(priv, 0x418f20, 0x00000000);
616 nv_wr32(priv, 0x418f24, 0x00000000);
617 nv_wr32(priv, 0x418e00, 0x00000060);
618 nv_wr32(priv, 0x418e08, 0x00000000);
619 nv_wr32(priv, 0x418e1c, 0x00000000);
620 nv_wr32(priv, 0x418e20, 0x00000000);
621 nv_wr32(priv, 0x41900c, 0x00000000);
622 nv_wr32(priv, 0x419018, 0x00000000);
623}
624
625static void
626nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
627{
628 nv_wr32(priv, 0x419d0c, 0x00000000);
629 nv_wr32(priv, 0x419d10, 0x00000014);
630 nv_wr32(priv, 0x419ab0, 0x00000000);
631 nv_wr32(priv, 0x419ac8, 0x00000000);
632 nv_wr32(priv, 0x419ab8, 0x000000e7);
633 nv_wr32(priv, 0x419abc, 0x00000000);
634 nv_wr32(priv, 0x419ac0, 0x00000000);
635 nv_wr32(priv, 0x419ab4, 0x00000000);
636 nv_wr32(priv, 0x41980c, 0x00000010);
637 nv_wr32(priv, 0x419844, 0x00000000);
638 nv_wr32(priv, 0x419850, 0x00000004);
639 nv_wr32(priv, 0x419854, 0x00000000);
640 nv_wr32(priv, 0x419858, 0x00000000);
641 nv_wr32(priv, 0x419c98, 0x00000000);
642 nv_wr32(priv, 0x419ca8, 0x00000000);
643 nv_wr32(priv, 0x419cb0, 0x01000000);
644 nv_wr32(priv, 0x419cb4, 0x00000000);
645 nv_wr32(priv, 0x419cb8, 0x00b08bea);
646 nv_wr32(priv, 0x419c84, 0x00010384);
647 nv_wr32(priv, 0x419cbc, 0x28137646);
648 nv_wr32(priv, 0x419cc0, 0x00000000);
649 nv_wr32(priv, 0x419cc4, 0x00000000);
650 nv_wr32(priv, 0x419c80, 0x00020232);
651 nv_wr32(priv, 0x419c0c, 0x00000000);
652 nv_wr32(priv, 0x419e00, 0x00000000);
653 nv_wr32(priv, 0x419ea0, 0x00000000);
654 nv_wr32(priv, 0x419ee4, 0x00000000);
655 nv_wr32(priv, 0x419ea4, 0x00000100);
656 nv_wr32(priv, 0x419ea8, 0x00000000);
657 nv_wr32(priv, 0x419eb4, 0x00000000);
658 nv_wr32(priv, 0x419eb8, 0x00000000);
659 nv_wr32(priv, 0x419ebc, 0x00000000);
660 nv_wr32(priv, 0x419ec0, 0x00000000);
661 nv_wr32(priv, 0x419edc, 0x00000000);
662 nv_wr32(priv, 0x419f00, 0x00000000);
663 nv_wr32(priv, 0x419f74, 0x00000555);
664}
665
666static void
667nve0_graph_init_tpcunk(struct nvc0_graph_priv *priv)
668{
669 nv_wr32(priv, 0x41be04, 0x00000000);
670 nv_wr32(priv, 0x41be08, 0x00000004);
671 nv_wr32(priv, 0x41be0c, 0x00000000);
672 nv_wr32(priv, 0x41be10, 0x003b8bc7);
673 nv_wr32(priv, 0x41be14, 0x00000000);
674 nv_wr32(priv, 0x41be18, 0x00000000);
675 nv_wr32(priv, 0x41bfd4, 0x00800000);
676 nv_wr32(priv, 0x41bfdc, 0x00000000);
677 nv_wr32(priv, 0x41bff8, 0x00000000);
678 nv_wr32(priv, 0x41bffc, 0x00000000);
679 nv_wr32(priv, 0x41becc, 0x00000000);
680 nv_wr32(priv, 0x41bee8, 0x00000000);
681 nv_wr32(priv, 0x41beec, 0x00000000);
682}
683
684static void
685nve0_graph_init_unk88xx(struct nvc0_graph_priv *priv)
686{
687 nv_wr32(priv, 0x40880c, 0x00000000);
688 nv_wr32(priv, 0x408850, 0x00000004);
689 nv_wr32(priv, 0x408910, 0x00000000);
690 nv_wr32(priv, 0x408914, 0x00000000);
691 nv_wr32(priv, 0x408918, 0x00000000);
692 nv_wr32(priv, 0x40891c, 0x00000000);
693 nv_wr32(priv, 0x408920, 0x00000000);
694 nv_wr32(priv, 0x408924, 0x00000000);
695 nv_wr32(priv, 0x408928, 0x00000000);
696 nv_wr32(priv, 0x40892c, 0x00000000);
697 nv_wr32(priv, 0x408930, 0x00000000);
698 nv_wr32(priv, 0x408950, 0x00000000);
699 nv_wr32(priv, 0x408954, 0x0000ffff);
700 nv_wr32(priv, 0x408958, 0x00000034);
701 nv_wr32(priv, 0x408984, 0x00000000);
702 nv_wr32(priv, 0x408988, 0x08040201);
703 nv_wr32(priv, 0x40898c, 0x80402010);
704}
705
706static void
516nve0_graph_init_units(struct nvc0_graph_priv *priv) 707nve0_graph_init_units(struct nvc0_graph_priv *priv)
517{ 708{
518 nv_wr32(priv, 0x409ffc, 0x00000000); 709 nv_wr32(priv, 0x409ffc, 0x00000000);
519 nv_wr32(priv, 0x409c14, 0x00003e3e); 710 nv_wr32(priv, 0x409c14, 0x00003e3e);
520 nv_wr32(priv, 0x409c24, 0x000f0000); 711 switch (nv_device(priv)->chipset) {
712 case 0xe6:
713 nv_wr32(priv, 0x409c24, 0x000f0001);
714 break;
715 default:
716 nv_wr32(priv, 0x409c24, 0x000f0000);
717 break;
718 }
521 719
522 nv_wr32(priv, 0x404000, 0xc0000000); 720 nv_wr32(priv, 0x404000, 0xc0000000);
523 nv_wr32(priv, 0x404600, 0xc0000000); 721 nv_wr32(priv, 0x404600, 0xc0000000);
524 nv_wr32(priv, 0x408030, 0xc0000000); 722 nv_wr32(priv, 0x408030, 0xc0000000);
525 nv_wr32(priv, 0x404490, 0xc0000000); 723 nv_wr32(priv, 0x404490, 0xc0000000);
526 nv_wr32(priv, 0x406018, 0xc0000000); 724 nv_wr32(priv, 0x406018, 0xc0000000);
527 nv_wr32(priv, 0x407020, 0xc0000000); 725 switch (nv_device(priv)->chipset) {
726 case 0xe6:
727 nv_wr32(priv, 0x407020, 0x40000000);
728 break;
729 default:
730 nv_wr32(priv, 0x407020, 0xc0000000);
731 break;
732 }
528 nv_wr32(priv, 0x405840, 0xc0000000); 733 nv_wr32(priv, 0x405840, 0xc0000000);
529 nv_wr32(priv, 0x405844, 0x00ffffff); 734 nv_wr32(priv, 0x405844, 0x00ffffff);
530 735
@@ -760,6 +965,27 @@ nve0_graph_init(struct nouveau_object *object)
760 965
761 nve0_graph_init_obj418880(priv); 966 nve0_graph_init_obj418880(priv);
762 nve0_graph_init_regs(priv); 967 nve0_graph_init_regs(priv);
968
969 switch (nv_device(priv)->chipset) {
970 case 0xe6:
971 nve0_graph_init_unk40xx(priv);
972 nve0_graph_init_unk44xx(priv);
973 nve0_graph_init_unk78xx(priv);
974 nve0_graph_init_unk60xx(priv);
975 nve0_graph_init_unk64xx(priv);
976 nve0_graph_init_unk58xx(priv);
977 nve0_graph_init_unk80xx(priv);
978 nve0_graph_init_unk70xx(priv);
979 nve0_graph_init_unk5bxx(priv);
980 nve0_graph_init_gpc(priv);
981 nve0_graph_init_tpc(priv);
982 nve0_graph_init_tpcunk(priv);
983 nve0_graph_init_unk88xx(priv);
984 break;
985 default:
986 break;
987 }
988
763 nve0_graph_init_gpc_0(priv); 989 nve0_graph_init_gpc_0(priv);
764 990
765 nv_wr32(priv, 0x400500, 0x00010001); 991 nv_wr32(priv, 0x400500, 0x00010001);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 03:04:05 -0400