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authorLen Brown <len.brown@intel.com>2011-07-14 00:53:24 -0400
committerH. Peter Anvin <hpa@linux.intel.com>2011-07-14 15:13:42 -0400
commitabe48b108247e9b90b4c6739662a2e5c765ed114 (patch)
treef2a3b48cf0973834933c50d745be5a38dbd61b39
parent620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc (diff)
x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS
Since 2.6.36 (23016bf0d25), Linux prints the existence of "epb" in /proc/cpuinfo, Since 2.6.38 (d5532ee7b40), the x86_energy_perf_policy(8) utility has been available in-tree to update MSR_IA32_ENERGY_PERF_BIAS. However, the typical BIOS fails to initialize the MSR, presumably because this is handled by high-volume shrink-wrap operating systems... Linux distros, on the other hand, do not yet invoke x86_energy_perf_policy(8). As a result, WSM-EP, SNB, and later hardware from Intel will run in its default hardware power-on state (performance), which assumes that users care for performance at all costs and not for energy efficiency. While that is fine for performance benchmarks, the hardware's intended default operating point is "normal" mode... Initialize the MSR to the "normal" by default during kernel boot. x86_energy_perf_policy(8) is available to change the default after boot, should the user have a different preference. Signed-off-by: Len Brown <len.brown@intel.com> Link: http://lkml.kernel.org/r/alpine.LFD.2.02.1107140051020.18606@x980 Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: <stable@kernel.org>
-rw-r--r--arch/x86/include/asm/msr-index.h3
-rw-r--r--arch/x86/kernel/cpu/intel.c18
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 485b4f1f079b..23a9d898baad 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -259,6 +259,9 @@
259#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 259#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
260 260
261#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 261#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
262#define ENERGY_PERF_BIAS_PERFORMANCE 0
263#define ENERGY_PERF_BIAS_NORMAL 6
264#define ENERGY_PERF_BIAS_POWERSWAVE 15
262 265
263#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 266#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
264 267
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba4fb2b..da0d779ecd9e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -456,6 +456,24 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
456 456
457 if (cpu_has(c, X86_FEATURE_VMX)) 457 if (cpu_has(c, X86_FEATURE_VMX))
458 detect_vmx_virtcap(c); 458 detect_vmx_virtcap(c);
459
460 /*
461 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
462 * x86_energy_perf_policy(8) is available to change it at run-time
463 */
464 if (cpu_has(c, X86_FEATURE_EPB)) {
465 u64 epb;
466
467 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
468 if ((epb & 0xF) == 0) {
469 printk_once(KERN_WARNING, "x86: updated energy_perf_bias"
470 " to 'normal' from 'performance'\n"
471 "You can view and update epb via utility,"
472 " such as x86_energy_perf_policy(8)\n");
473 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
474 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
475 }
476 }
459} 477}
460 478
461#ifdef CONFIG_X86_32 479#ifdef CONFIG_X86_32