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authorLee Jones <lee.jones@linaro.org>2014-03-20 05:20:53 -0400
committerBrian Norris <computersforpeace@gmail.com>2014-03-20 07:17:18 -0400
commita37b2f5aee630b35deccb4841a4d60fa45c15b3e (patch)
tree4954e97dd38fb15fe310b76bc039328048748959
parent249516c9c3c8665527db89ac871f55a07ecc89b2 (diff)
mtd: st_spi_fsm: Provide the default read/write configurations
Message sequences can vary depending on how many pads (lines) are required to address the chip (mode & dummy), how many data pads (lines) are required to write out to the chip which will determine speed amongst other things which are detailed by the SFDP specification. We are able to use multiple configurations for each chip, but they need to me matched to a device's capabilities. These configurations are listed in preference order - most preferred first. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-rw-r--r--drivers/mtd/devices/st_spi_fsm.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 5683443e7261..03b49a44970d 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -375,6 +375,33 @@ static struct flash_info flash_types[] = {
375 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL }, 375 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
376}; 376};
377 377
378/*
379 * FSM message sequence configurations:
380 *
381 * All configs are presented in order of preference
382 */
383
384/* Default READ configurations, in order of preference */
385static struct seq_rw_config default_read_configs[] = {
386 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4},
387 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0},
388 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0},
389 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
390 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
391 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
392 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
393};
394
395/* Default WRITE configurations */
396static struct seq_rw_config default_write_configs[] = {
397 {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
398 {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
399 {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
400 {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
401 {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0},
402 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
403};
404
378static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ 405static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */
379 406
380static struct stfsm_seq stfsm_seq_read_jedec = { 407static struct stfsm_seq stfsm_seq_read_jedec = {