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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-12 12:16:56 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-12 12:16:56 -0500
commita26be149facb22d30cd92cadb26f651d6fe802c9 (patch)
treec467bd0cae818ef793e9a694b4cd2bdc88d9ff6b
parentcdd305454ebd181fa35b648c0921fe7df27d6f3b (diff)
parenta20cc76b9efae10c20123049df361adcd7f0e0b3 (diff)
Merge tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: "This time with: - Generic page-table framework for ARM IOMMUs using the LPAE page-table format, ARM-SMMU and Renesas IPMMU make use of it already. - Break out the IO virtual address allocator from the Intel IOMMU so that it can be used by other DMA-API implementations too. The first user will be the ARM64 common DMA-API implementation for IOMMUs - Device tree support for Renesas IPMMU - Various fixes and cleanups all over the place" * tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (36 commits) iommu/amd: Convert non-returned local variable to boolean when relevant iommu: Update my email address iommu/amd: Use wait_event in put_pasid_state_wait iommu/amd: Fix amd_iommu_free_device() iommu/arm-smmu: Avoid build warning iommu/fsl: Various cleanups iommu/fsl: Use %pa to print phys_addr_t iommu/omap: Print phys_addr_t using %pa iommu: Make more drivers depend on COMPILE_TEST iommu/ipmmu-vmsa: Fix IOMMU lookup when multiple IOMMUs are registered iommu: Disable on !MMU builds iommu/fsl: Remove unused fsl_of_pamu_ids[] iommu/fsl: Fix section mismatch iommu/ipmmu-vmsa: Use the ARM LPAE page table allocator iommu: Fix trace_map() to report original iova and original size iommu/arm-smmu: add support for iova_to_phys through ATS1PR iopoll: Introduce memory-mapped IO polling macros iommu/arm-smmu: don't touch the secure STLBIALL register iommu/arm-smmu: make use of generic LPAE allocator iommu: io-pgtable-arm: add non-secure quirk ...
-rw-r--r--Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt41
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm64/Kconfig1
-rw-r--r--arch/powerpc/include/asm/fsl_pamu_stash.h4
-rw-r--r--drivers/iommu/Kconfig51
-rw-r--r--drivers/iommu/Makefile5
-rw-r--r--drivers/iommu/amd_iommu.c14
-rw-r--r--drivers/iommu/amd_iommu_init.c2
-rw-r--r--drivers/iommu/amd_iommu_proto.h2
-rw-r--r--drivers/iommu/amd_iommu_types.h2
-rw-r--r--drivers/iommu/amd_iommu_v2.c35
-rw-r--r--drivers/iommu/arm-smmu.c935
-rw-r--r--drivers/iommu/fsl_pamu.c216
-rw-r--r--drivers/iommu/fsl_pamu.h15
-rw-r--r--drivers/iommu/fsl_pamu_domain.c173
-rw-r--r--drivers/iommu/intel-iommu.c45
-rw-r--r--drivers/iommu/io-pgtable-arm.c986
-rw-r--r--drivers/iommu/io-pgtable.c82
-rw-r--r--drivers/iommu/io-pgtable.h143
-rw-r--r--drivers/iommu/iommu.c7
-rw-r--r--drivers/iommu/iova.c53
-rw-r--r--drivers/iommu/ipmmu-vmsa.c674
-rw-r--r--drivers/iommu/irq_remapping.h2
-rw-r--r--drivers/iommu/omap-iommu.c2
-rw-r--r--include/linux/iopoll.h144
-rw-r--r--include/linux/iova.h41
-rw-r--r--include/linux/platform_data/ipmmu-vmsa.h24
-rw-r--r--include/trace/events/iommu.h31
28 files changed, 2239 insertions, 1492 deletions
<
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
new file mode 100644
index 000000000000..cd29083e16ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -0,0 +1,41 @@
1* Renesas VMSA-Compatible IOMMU
2
3The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
4It provides address translation for bus masters outside of the CPU, each
5connected to the IPMMU through a port called micro-TLB.
6
7
8Required Properties:
9
10 - compatible: Must contain "renesas,ipmmu-vmsa".
11 - reg: Base address and size of the IPMMU registers.
12 - interrupts: Specifiers for the MMU fault interrupts. For instances that
13 support secure mode two interrupts must be specified, for non-secure and
14 secure mode, in that order. For instances that don't support secure mode a
15 single interrupt must be specified.
16
17 - #iommu-cells: Must be 1.
18
19Each bus master connected to an IPMMU must reference the IPMMU in its device
20node with the following property:
21
22 - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
23 to the IPMMU and the second cell the number of the micro-TLB that the
24 device is connected to.
25
26
27Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
28
29 ipmmu_mx: mmu@fe951000 {
30 compatible = "renasas,ipmmu-vmsa";
31 reg = <0 0xfe951000 0 0x1000>;
32 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
33 <0 221 IRQ_TYPE_LEVEL_HIGH>;
34 #iommu-cells = <1>;
35 };
36
37 vsp1@fe928000 {
38 ...
39 iommus = <&ipmmu_mx 13>;
40 ...
41 };
diff --git a/MAINTAINERS b/MAINTAINERS
index c4a8703ab493..22999654195a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1606,6 +1606,7 @@ M: Will Deacon <will.deacon@arm.com>
1606L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1606L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1607S: Maintained 1607S: Maintained
1608F: drivers/iommu/arm-smmu.c 1608F: drivers/iommu/arm-smmu.c
1609F: drivers/iommu/io-pgtable-arm.c
1609 1610
1610ARM64 PORT (AARCH64 ARCHITECTURE) 1611ARM64 PORT (AARCH64 ARCHITECTURE)
1611M: Catalin Marinas <catalin.marinas@arm.com> 1612M: Catalin Marinas <catalin.marinas@arm.com>
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 2814304cec04..676454a65af8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -350,7 +350,6 @@ config ARM64_VA_BITS_42
350 350
351config ARM64_VA_BITS_48 351config ARM64_VA_BITS_48
352 bool "48-bit" 352 bool "48-bit"
353 depends on !ARM_SMMU
354 353
355endchoice 354endchoice
356 355
diff --git a/arch/powerpc/include/asm/fsl_pamu_stash.h b/arch/powerpc/include/asm/fsl_pamu_stash.h
index caa1b21c25cd..38311c98eed9 100644
--- a/arch/powerpc/include/asm/fsl_pamu_stash.h
+++ b/arch/powerpc/include/asm/fsl_pamu_stash.h
@@ -32,8 +32,8 @@ enum pamu_stash_target {
32 */ 32 */
33 33
34struct pamu_stash_attribute { 34struct pamu_stash_attribute {
35 u32 cpu; /* cpu number */ 35 u32 cpu; /* cpu number */
36 u32 cache; /* cache to stash to: L1,L2,L3 */ 36 u32 cache; /* cache to stash to: L1,L2,L3 */
37}; 37};
38 38
39#endif /* __FSL_PAMU_STASH_H */ 39#endif /* __FSL_PAMU_STASH_H */
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 325188eef1c1..baa0d9786f50 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -4,6 +4,7 @@ config IOMMU_API
4 4
5menuconfig IOMMU_SUPPORT 5menuconfig IOMMU_SUPPORT
6 bool "IOMMU Hardware Support" 6 bool "IOMMU Hardware Support"
7 depends on MMU
7 default y 8 default y
8 ---help--- 9 ---help---
9 Say Y here if you want to compile device drivers for IO Memory 10 Say Y here if you want to compile device drivers for IO Memory
@@ -13,13 +14,43 @@ menuconfig IOMMU_SUPPORT
13 14
14if IOMMU_SUPPORT 15if IOMMU_SUPPORT
15 16
17menu "Generic IOMMU Pagetable Support"
18
19# Selected by the actual pagetable implementations
20config IOMMU_IO_PGTABLE
21 bool
22
23config IOMMU_IO_PGTABLE_LPAE
24 bool "ARMv7/v8 Long Descriptor Format"
25 select IOMMU_IO_PGTABLE
26 help
27 Enable support for the ARM long descriptor pagetable format.
28 This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page
29 sizes at both stage-1 and stage-2, as well as address spaces
30 up to 48-bits in size.
31
32config IOMMU_IO_PGTABLE_LPAE_SELFTEST
33 bool "LPAE selftests"
34 depends on IOMMU_IO_PGTABLE_LPAE
35 help
36 Enable self-tests for LPAE page table allocator. This performs
37 a series of page-table consistency checks during boot.
38
39 If unsure, say N here.
40
41endmenu
42
43config IOMMU_IOVA
44 bool
45
16config OF_IOMMU 46config OF_IOMMU
17 def_bool y 47 def_bool y
18 depends on OF && IOMMU_API 48 depends on OF && IOMMU_API
19 49
20config FSL_PAMU 50config FSL_PAMU
21 bool "Freescale IOMMU support" 51 bool "Freescale IOMMU support"
22 depends on PPC_E500MC 52 depends on PPC32
53 depends on PPC_E500MC || COMPILE_TEST
23 select IOMMU_API 54 select IOMMU_API
24 select GENERIC_ALLOCATOR 55 select GENERIC_ALLOCATOR
25 help 56 help
@@ -30,7 +61,8 @@ config FSL_PAMU
30# MSM IOMMU support