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authorDave Airlie <airlied@redhat.com>2012-05-29 06:09:06 -0400
committerDave Airlie <airlied@redhat.com>2012-05-29 06:09:06 -0400
commita21f976094819d2862f8fdbd39ab5b22e7d27a1a (patch)
tree67e2cb074ac4ccb46d1e9e0544e03c5ff58f891e
parent1ebf169ad4dc68f18cc0dab35163b0f324fc6c41 (diff)
parentef12dab779acdb907eb4c3fa723e1c6f035ee13c (diff)
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: tune down the noise of the RP irq limit fail drm/i915: Remove the error message for unbinding pinned buffers drm/i915: Limit page allocations to lowmem (dma32) for i965 drm/i915: always use RPNSWREQ for turbo change requests drm/i915: reject doubleclocked cea modes on dp drm/i915: Adding TV Out Missing modes. drm/i915: wait for a vblank to pass after tv detect drm/i915: no lvds quirk for HP t5740e Thin Client drm/i915: enable vdd when switching off the eDP panel drm/i915: Fix PCH PLL assertions to not assume CRTC:PLL relationship drm/i915: Always update RPS interrupts thresholds along with frequency drm/i915: properly handle interlaced bit for sdvo dtd conversion drm/i915: fix module unload since error_state rework drm/i915: be more careful when returning -ENXIO in gmbus transfer
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c16
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c37
-rw-r--r--drivers/gpu/drm/i915/intel_display.c56
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c24
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c21
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c8
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c64
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c12
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h5
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c53
11 files changed, 197 insertions, 101 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index eb2b3c25b9e1..5363e9c66c27 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2032,6 +2032,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
2032 1, minor); 2032 1, minor);
2033 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, 2033 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2034 1, minor); 2034 1, minor);
2035 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2036 1, minor);
2035} 2037}
2036 2038
2037#endif /* CONFIG_DEBUG_FS */ 2039#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c1e5c66553df..288d7b8f49ae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2063,10 +2063,8 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2063 if (obj->gtt_space == NULL) 2063 if (obj->gtt_space == NULL)
2064 return 0; 2064 return 0;
2065 2065
2066 if (obj->pin_count != 0) { 2066 if (obj->pin_count)
2067 DRM_ERROR("Attempting to unbind pinned buffer\n"); 2067 return -EBUSY;
2068 return -EINVAL;
2069 }
2070 2068
2071 ret = i915_gem_object_finish_gpu(obj); 2069 ret = i915_gem_object_finish_gpu(obj);
2072 if (ret) 2070 if (ret)
@@ -3293,6 +3291,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3293 struct drm_i915_private *dev_priv = dev->dev_private; 3291 struct drm_i915_private *dev_priv = dev->dev_private;
3294 struct drm_i915_gem_object *obj; 3292 struct drm_i915_gem_object *obj;
3295 struct address_space *mapping; 3293 struct address_space *mapping;
3294 u32 mask;
3296 3295
3297 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 3296 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3298 if (obj == NULL) 3297 if (obj == NULL)
@@ -3303,8 +3302,15 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3303 return NULL; 3302 return NULL;
3304 } 3303 }
3305 3304
3305 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3306 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3307 /* 965gm cannot relocate objects above 4GiB. */
3308 mask &= ~__GFP_HIGHMEM;
3309 mask |= __GFP_DMA32;
3310 }
3311
3306 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; 3312 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3307 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); 3313 mapping_set_gfp_mask(mapping, mask);
3308 3314
3309 i915_gem_info_add_obj(dev_priv, size); 3315 i915_gem_info_add_obj(dev_priv, size);
3310 3316
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cc4a63307611..1417660a93ec 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -350,8 +350,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
350{ 350{
351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work); 352 rps_work);
353 u8 new_delay = dev_priv->cur_delay;
354 u32 pm_iir, pm_imr; 353 u32 pm_iir, pm_imr;
354 u8 new_delay;
355 355
356 spin_lock_irq(&dev_priv->rps_lock); 356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir; 357 pm_iir = dev_priv->pm_iir;
@@ -360,41 +360,18 @@ static void gen6_pm_rps_work(struct work_struct *work)
360 I915_WRITE(GEN6_PMIMR, 0); 360 I915_WRITE(GEN6_PMIMR, 0);
361 spin_unlock_irq(&dev_priv->rps_lock); 361 spin_unlock_irq(&dev_priv->rps_lock);
362 362
363 if (!pm_iir) 363 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
364 return; 364 return;
365 365
366 mutex_lock(&dev_priv->dev->struct_mutex); 366 mutex_lock(&dev_priv->dev->struct_mutex);
367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 367
368 if (dev_priv->cur_delay != dev_priv->max_delay) 368 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
369 new_delay = dev_priv->cur_delay + 1; 369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay) 370 else
371 new_delay = dev_priv->max_delay; 371 new_delay = dev_priv->cur_delay - 1;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
373 gen6_gt_force_wake_get(dev_priv);
374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
387 gen6_gt_force_wake_put(dev_priv);
388 }
389 372
390 gen6_set_rps(dev_priv->dev, new_delay); 373 gen6_set_rps(dev_priv->dev, new_delay);
391 dev_priv->cur_delay = new_delay;
392 374
393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
398 mutex_unlock(&dev_priv->dev->struct_mutex); 375 mutex_unlock(&dev_priv->dev->struct_mutex);
399} 376}
400 377
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee61ad1e642b..914789420906 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -910,9 +910,10 @@ static void assert_pll(struct drm_i915_private *dev_priv,
910 910
911/* For ILK+ */ 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv, 912static void assert_pch_pll(struct drm_i915_private *dev_priv,
913 struct intel_crtc *intel_crtc, bool state) 913 struct intel_pch_pll *pll,
914 struct intel_crtc *crtc,
915 bool state)
914{ 916{
915 int reg;
916 u32 val; 917 u32 val;
917 bool cur_state; 918 bool cur_state;
918 919
@@ -921,30 +922,37 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
921 return; 922 return;
922 } 923 }
923 924
924 if (!intel_crtc->pch_pll) { 925 if (WARN (!pll,
925 WARN(1, "asserting PCH PLL enabled with no PLL\n"); 926 "asserting PCH PLL %s with no PLL\n", state_string(state)))
926 return; 927 return;
927 }
928 928
929 if (HAS_PCH_CPT(dev_priv->dev)) { 929 val = I915_READ(pll->pll_reg);
930 cur_state = !!(val & DPLL_VCO_ENABLE);
931 WARN(cur_state != state,
932 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
933 pll->pll_reg, state_string(state), state_string(cur_state), val);
934
935 /* Make sure the selected PLL is correctly attached to the transcoder */
936 if (crtc && HA