Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next

* 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix fence driver for dma ring when wb is disabled
  drm/radeon/si: add VM CS checker support for CP DMA
  drm/radeon/cayman: add VM CS checker support for CP DMA
  drm/radeon: add support for CP DMA packet to evergreen CS checker
  drm/radeon: add support for CP DMA packet to r6xx/r7xx CS checker
  drm/radeon: add register headers for CP DMA on r6xx-SI
  drm/radeon: improve mc_stop/mc_resume on r5xx-r7xx
  drm/radeon: fix amd afusion gpu setup aka sumo v2
  drm/radeon: do not move bo to different placement at each cs

14 files changed, 516 insertions, 32 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index c66251e4a9b9..8dbc69a6e5bd 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1821,7 +1821,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         case CHIP_SUMO:
                 rdev->config.evergreen.num_ses = 1;
                 rdev->config.evergreen.max_pipes = 4;
-                rdev->config.evergreen.max_tile_pipes = 2;
+                rdev->config.evergreen.max_tile_pipes = 4;
                 if (rdev->pdev->device == 0x9648)
                         rdev->config.evergreen.max_simds = 3;
                 else if ((rdev->pdev->device == 0x9647) ||
@@ -1844,7 +1844,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
+                gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_SUMO2:
                 rdev->config.evergreen.num_ses = 1;
@@ -1866,7 +1866,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
+                gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_BARTS:
                 rdev->config.evergreen.num_ses = 2;
@@ -1914,7 +1914,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 break;
         case CHIP_CAICOS:
                 rdev->config.evergreen.num_ses = 1;
-                rdev->config.evergreen.max_pipes = 4;
+                rdev->config.evergreen.max_pipes = 2;
                 rdev->config.evergreen.max_tile_pipes = 2;
                 rdev->config.evergreen.max_simds = 2;
                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index c042e497e450..62c227104781 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -2232,6 +2232,95 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                         ib[idx+2] = upper_32_bits(offset) & 0xff;
                 }
                 break;
+        case PACKET3_CP_DMA:
+        {
+                u32 command, size, info;
+                u64 offset, tmp;
+                if (pkt->count != 4) {
+                        DRM_ERROR("bad CP DMA\n");
+                        return -EINVAL;
+                }
+                command = radeon_get_ib_value(p, idx+4);
+                size = command & 0x1fffff;
+                info = radeon_get_ib_value(p, idx+1);
+                if (command & PACKET3_CP_DMA_CMD_SAS) {
+                        /* src address space is register */
+                        /* GDS is ok */
+                        if (((info & 0x60000000) >> 29) != 1) {
+                                DRM_ERROR("CP DMA SAS not supported\n");
+                                return -EINVAL;
+                        }
+                } else {
+                        if (command & PACKET3_CP_DMA_CMD_SAIC) {
+                                DRM_ERROR("CP DMA SAIC only supported for registers\n");
+                                return -EINVAL;
+                        }
+                        /* src address space is memory */
+                        if (((info & 0x60000000) >> 29) == 0) {
+                                r = evergreen_cs_packet_next_reloc(p, &reloc);
+                                if (r) {
+                                        DRM_ERROR("bad CP DMA SRC\n");
+                                        return -EINVAL;
+                                }
+
+                                tmp = radeon_get_ib_value(p, idx) +
+                                        ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
+
+                                offset = reloc->lobj.gpu_offset + tmp;
+
+                                if ((tmp + size) > radeon_bo_size(reloc->robj)) {
+                                        dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
+                                                 tmp + size, radeon_bo_size(reloc->robj));
+                                        return -EINVAL;
+                                }
+
+                                ib[idx] = offset;
+                                ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
+                        } else if (((info & 0x60000000) >> 29) != 2) {
+                                DRM_ERROR("bad CP DMA SRC_SEL\n");
+                                return -EINVAL;
+                        }
+                }
+                if (command & PACKET3_CP_DMA_CMD_DAS) {
+                        /* dst address space is register */
+                        /* GDS is ok */
+                        if (((info & 0x00300000) >> 20) != 1) {
+                                DRM_ERROR("CP DMA DAS not supported\n");
+                                return -EINVAL;
+                        }
+                } else {
+                        /* dst address space is memory */
+                        if (command & PACKET3_CP_DMA_CMD_DAIC) {
+                                DRM_ERROR("CP DMA DAIC only supported for registers\n");
+                                return -EINVAL;
+                        }
+                        if (((info & 0x00300000) >> 20) == 0) {
+                                r = evergreen_cs_packet_next_reloc(p, &reloc);
+                                if (r) {
+                                        DRM_ERROR("bad CP DMA DST\n");
+                                        return -EINVAL;
+                                }
+
+                                tmp = radeon_get_ib_value(p, idx+2) +
+                                        ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
+
+                                offset = reloc->lobj.gpu_offset + tmp;
+
+                                if ((tmp + size) > radeon_bo_size(reloc->robj)) {
+                                        dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
+                                                 tmp + size, radeon_bo_size(reloc->robj));
+                                        return -EINVAL;
+                                }
+
+                                ib[idx+2] = offset;
+                                ib[idx+3] = upper_32_bits(offset) & 0xff;
+                        } else {
+                                DRM_ERROR("bad CP DMA DST_SEL\n");
+                                return -EINVAL;
+                        }
+                }
+                break;
+        }
         case PACKET3_SURFACE_SYNC:
                 if (pkt->count != 3) {
                         DRM_ERROR("bad SURFACE_SYNC\n");
@@ -2843,6 +2932,7 @@ static int evergreen_vm_packet3_check(struct radeon_device *rdev,
         u32 idx = pkt->idx + 1;
         u32 idx_value = ib[idx];
         u32 start_reg, end_reg, reg, i;
+        u32 command, info;