Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next

Alex writes:
"adds support for the
asynchronous DMA engines on r6xx-SI.  These engines are used
for ttm bo moves and VM page table updates currently.  They
could also be exposed via the CS ioctl for userspace use,
but I haven't had a chance to add proper CS checker patches
for them yet.  These patches have been tested extensively
internally for months, so they should be pretty solid."

* 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: use DMA engine for VM page table updates on SI
  drm/radeon: add dma engine support for vm pt updates on si (v2)
  drm/radeon: use DMA engine for VM page table updates on cayman/TN
  drm/radeon: add dma engine support for vm pt updates on ni (v5)
  drm/radeon: use async dma for ttm buffer moves on 6xx-SI
  drm/radeon/kms: add support for dma rings to radeon_test_moves()
  drm/radeon/kms: Add initial support for async DMA on SI
  drm/radeon/kms: Add initial support for async DMA on cayman/TN
  drm/radeon/kms: Add initial support for async DMA on evergreen
  drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx

14 files changed, 1742 insertions, 101 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 78de2e4097b5..c66251e4a9b9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2034,6 +2034,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         WREG32(GB_ADDR_CONFIG, gb_addr_config);
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+        WREG32(DMA_TILING_CONFIG, gb_addr_config);
 
         tmp = gb_addr_config & NUM_PIPES_MASK;
         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
@@ -2403,8 +2404,12 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
                 cayman_cp_int_cntl_setup(rdev, 1, 0);
                 cayman_cp_int_cntl_setup(rdev, 2, 0);
+                tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
+                WREG32(CAYMAN_DMA1_CNTL, tmp);
         } else
                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+        tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
+        WREG32(DMA_CNTL, tmp);
         WREG32(GRBM_INT_CNTL, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -2457,6 +2462,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
         u32 grbm_int_cntl = 0;
         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
+        u32 dma_cntl, dma_cntl1 = 0;
 
         if (!rdev->irq.installed) {
                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -2484,6 +2490,8 @@ int evergreen_irq_set(struct radeon_device *rdev)
         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
 
+        dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
+
         if (rdev->family >= CHIP_CAYMAN) {
                 /* enable CP interrupts on all rings */
                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
@@ -2506,6 +2514,19 @@ int evergreen_irq_set(struct radeon_device *rdev)
                 }
         }
 
+        if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
+                DRM_DEBUG("r600_irq_set: sw int dma\n");
+                dma_cntl |= TRAP_ENABLE;
+        }
+
+        if (rdev->family >= CHIP_CAYMAN) {
+                dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
+                if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
+                        DRM_DEBUG("r600_irq_set: sw int dma1\n");
+                        dma_cntl1 |= TRAP_ENABLE;
+                }
+        }
+
         if (rdev->irq.crtc_vblank_int[0] ||
             atomic_read(&rdev->irq.pflip[0])) {
                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
@@ -2591,6 +2612,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
         } else
                 WREG32(CP_INT_CNTL, cp_int_cntl);
+
+        WREG32(DMA_CNTL, dma_cntl);
+
+        if (rdev->family >= CHIP_CAYMAN)
+                WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
+
         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
 
         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
@@ -3126,9 +3153,19 @@ restart_ih:
                         } else
                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
                         break;
+                case 224: /* DMA trap event */
+                        DRM_DEBUG("IH: DMA trap\n");
+                        radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
+                        break;
                 case 233: /* GUI IDLE */
                         DRM_DEBUG("IH: GUI idle\n");
                         break;
+                case 244: /* DMA trap event */
+                        if (rdev->family >= CHIP_CAYMAN) {
+                                DRM_DEBUG("IH: DMA1 trap\n");
+                                radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
+                        }
+                        break;
                 default:
                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
                         break;
@@ -3154,6 +3191,143 @@ restart_ih:
         return IRQ_HANDLED;
 }
 
+/**
+ * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
+ *
+ * @rdev: radeon_device pointer
+ * @fence: radeon fence object
+ *
+ * Add a DMA fence packet to the ring to write
+ * the fence seq number and DMA trap packet to generate
+ * an interrupt if needed (evergreen-SI).
+ */
+void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
+                                   struct radeon_fence *fence)
+{
+        struct radeon_ring *ring = &rdev->ring[fence->ring];
+        u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+        /* write the fence */
+        radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
+        radeon_ring_write(ring, addr & 0xfffffffc);
+        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
+        radeon_ring_write(ring, fence->seq);
+        /* generate an interrupt */
+        radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
+        /* flush HDP */
+        radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
+        radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
+        radeon_ring_write(ring, 1);
+}
+
+/**
+ * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
+ *
+ * @rdev: radeon_device pointer
+ * @ib: IB object to schedule
+ *
+ * Schedule an IB in the DMA ring (evergreen).
+ */
+void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
+                                   struct radeon_ib *ib)