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authorOlof Johansson <olof@lixom.net>2012-11-26 03:22:48 -0500
committerOlof Johansson <olof@lixom.net>2012-11-26 03:22:48 -0500
commit97c0bd411c188158d4a7e6d4bdee9382dc036be9 (patch)
tree3258f0bc1f1256c521edeeb02421ca14ee029ca0
parent0f327cb11f2b8bd0b6535640e5b46746e43bbfb2 (diff)
parentb1ce101bb9e52dcd5b143f7f376a04f1db95014c (diff)
Merge branch 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim: This is adding support for exynos5440, including Quad ARM Cortex-A15 cores and its reference board SSDK5440. Note, at this moment, just enabled minimal system part for initial kernel boot and pinctrl driver. * 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC ARM: dts: add initial dts file for EXYNOS5440, SSDK5440 ARM: EXYNOS: add support for EXYNOS5440 SoC Add/add conflict in arch/arm/boot/dts/Makefile. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts46
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi159
-rw-r--r--arch/arm/mach-exynos/Kconfig11
-rw-r--r--arch/arm/mach-exynos/Makefile2
-rw-r--r--arch/arm/mach-exynos/common.c68
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c31
-rw-r--r--arch/arm/mach-exynos/mct.c11
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h8
-rw-r--r--drivers/pinctrl/Kconfig5
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c919
-rw-r--r--drivers/tty/serial/samsung.c3
17 files changed, 1258 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8585bc0d5c0a..f872edff9c2c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
24dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 24dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
25 exynos4210-smdkv310.dtb \ 25 exynos4210-smdkv310.dtb \
26 exynos4210-trats.dtb \ 26 exynos4210-trats.dtb \
27 exynos5250-smdk5250.dtb 27 exynos5250-smdk5250.dtb \
28 exynos5440-ssdk5440.dtb
28dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 29dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
29 ecx-2000.dtb 30 ecx-2000.dtb
30dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 31dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
new file mode 100644
index 000000000000..921c83cf694f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -0,0 +1,46 @@
1/*
2 * SAMSUNG SSDK5440 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5440.dtsi"
14
15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18
19 memory {
20 reg = <0x80000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
25 };
26
27 spi {
28 status = "disabled";
29 };
30
31 i2c@F0000 {
32 status = "disabled";
33 };
34
35 i2c@100000 {
36 status = "disabled";
37 };
38
39 watchdog {
40 status = "disabled";
41 };
42
43 rtc {
44 status = "disabled";
45 };
46};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
new file mode 100644
index 000000000000..024269de8ee5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -0,0 +1,159 @@
1/*
2 * SAMSUNG EXYNOS5440 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "samsung,exynos5440";
16
17 interrupt-parent = <&gic>;
18
19 gic:interrupt-controller@2E0000 {
20 compatible = "arm,cortex-a15-gic";
21 #interrupt-cells = <3>;
22 interrupt-controller;
23 reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a15";
29 timer {
30 compatible = "arm,armv7-timer";
31 interrupts = <1 13 0xf08>;
32 clock-frequency = <1000000>;
33 };
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a15";
37 timer {
38 compatible = "arm,armv7-timer";
39 interrupts = <1 14 0xf08>;
40 clock-frequency = <1000000>;
41 };
42 };
43 cpu@2 {
44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 interrupts = <1 14 0xf08>;
48 clock-frequency = <1000000>;
49 };
50 };
51 cpu@3 {
52 compatible = "arm,cortex-a15";
53 timer {
54 compatible = "arm,armv7-timer";
55 interrupts = <1 14 0xf08>;
56 clock-frequency = <1000000>;
57 };
58 };
59 };
60
61 common {
62 compatible = "samsung,exynos5440";
63
64 };
65
66 serial@B0000 {
67 compatible = "samsung,exynos4210-uart";
68 reg = <0xB0000 0x1000>;
69 interrupts = <0 2 0>;
70 };
71
72 serial@C0000 {
73 compatible = "samsung,exynos4210-uart";
74 reg = <0xC0000 0x1000>;
75 interrupts = <0 3 0>;
76 };
77
78 spi {
79 compatible = "samsung,exynos4210-spi";
80 reg = <0xD0000 0x1000>;
81 interrupts = <0 4 0>;
82 tx-dma-channel = <&pdma0 5>; /* preliminary */
83 rx-dma-channel = <&pdma0 4>; /* preliminary */
84 #address-cells = <1>;
85 #size-cells = <0>;
86 };
87
88 pinctrl {
89 compatible = "samsung,pinctrl-exynos5440";
90 reg = <0xE0000 0x1000>;
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 #gpio-cells = <2>;
94
95 fan: fan {
96 samsung,exynos5440-pin-function = <1>;
97 };
98
99 hdd_led0: hdd_led0 {
100 samsung,exynos5440-pin-function = <2>;
101 };
102
103 hdd_led1: hdd_led1 {
104 samsung,exynos5440-pin-function = <3>;
105 };
106
107 uart1: uart1 {
108 samsung,exynos5440-pin-function = <4>;
109 };
110 };
111
112 i2c@F0000 {
113 compatible = "samsung,s3c2440-i2c";
114 reg = <0xF0000 0x1000>;
115 interrupts = <0 5 0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119
120 i2c@100000 {
121 compatible = "samsung,s3c2440-i2c";
122 reg = <0x100000 0x1000>;
123 interrupts = <0 6 0>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
128 watchdog {
129 compatible = "samsung,s3c2410-wdt";
130 reg = <0x110000 0x1000>;
131 interrupts = <0 1 0>;
132 };
133
134 amba {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "arm,amba-bus";
138 interrupt-parent = <&gic>;
139 ranges;
140
141 pdma0: pdma@121A0000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0x120000 0x1000>;
144 interrupts = <0 34 0>;
145 };
146
147 pdma1: pdma@121B0000 {
148 compatible = "arm,pl330", "arm,primecell";
149 reg = <0x121000 0x1000>;
150 interrupts = <0 35 0>;
151 };
152 };
153
154 rtc {
155 compatible = "samsung,s3c6410-rtc";
156 reg = <0x130000 0x1000>;
157 interrupts = <0 16 0>, <0 17 0>;
158 };
159};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index da55107033dd..ed17e353956e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -67,6 +67,15 @@ config SOC_EXYNOS5250
67 help 67 help
68 Enable EXYNOS5250 SoC support 68 Enable EXYNOS5250 SoC support
69 69
70config SOC_EXYNOS5440
71 bool "SAMSUNG EXYNOS5440"
72 default y
73 depends on ARCH_EXYNOS5
74 select ARM_ARCH_TIMER
75 select AUTO_ZRELADDR
76 help
77 Enable EXYNOS5440 SoC support
78
70config EXYNOS4_MCT 79config EXYNOS4_MCT
71 bool 80 bool
72 default y 81 default y
@@ -417,9 +426,9 @@ config MACH_EXYNOS4_DT
417 426
418config MACH_EXYNOS5_DT 427config MACH_EXYNOS5_DT
419 bool "SAMSUNG EXYNOS5 Machine using device tree" 428 bool "SAMSUNG EXYNOS5 Machine using device tree"
429 default y
420 depends on ARCH_EXYNOS5 430 depends on ARCH_EXYNOS5
421 select ARM_AMBA 431 select ARM_AMBA
422 select SOC_EXYNOS5250
423 select USE_OF 432 select USE_OF
424 help 433 help
425 Machine support for Samsung EXYNOS5 machine with device tree enabled. 434 Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024f7d43..1a076df02bd8 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,9 +14,9 @@ obj- :=
14 14
15obj-$(CONFIG_ARCH_EXYNOS) += common.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o 16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
18obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
19obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
20 20
21obj-$(CONFIG_PM) += pm.o 21obj-$(CONFIG_PM) += pm.o
22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1947be8e5f5b..94f1dedc0617 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -58,9 +58,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
58static const char name_exynos4212[] = "EXYNOS4212"; 58static const char name_exynos4212[] = "EXYNOS4212";
59static const char name_exynos4412[] = "EXYNOS4412"; 59static const char name_exynos4412[] = "EXYNOS4412";
60static const char name_exynos5250[] = "EXYNOS5250"; 60static const char name_exynos5250[] = "EXYNOS5250";
61static const char name_exynos5440[] = "EXYNOS5440";
61 62
62static void exynos4_map_io(void); 63static void exynos4_map_io(void);
63static void exynos5_map_io(void); 64static void exynos5_map_io(void);
65static void exynos5440_map_io(void);
64static void exynos4_init_clocks(int xtal); 66static void exynos4_init_clocks(int xtal);
65static void exynos5_init_clocks(int xtal); 67static void exynos5_init_clocks(int xtal);
66static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no); 68static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
@@ -99,6 +101,12 @@ static struct cpu_table cpu_ids[] __initdata = {
99 .init_uarts = exynos_init_uarts, 101 .init_uarts = exynos_init_uarts,
100 .init = exynos_init, 102 .init = exynos_init,
101 .name = name_exynos5250, 103 .name = name_exynos5250,
104 }, {
105 .idcode = EXYNOS5440_SOC_ID,
106 .idmask = EXYNOS5_SOC_MASK,
107 .map_io = exynos5440_map_io,
108 .init = exynos_init,
109 .name = name_exynos5440,
102 }, 110 },
103}; 111};
104 112
@@ -113,6 +121,15 @@ static struct map_desc exynos_iodesc[] __initdata = {
113 }, 121 },
114}; 122};
115 123
124static struct map_desc exynos5440_iodesc[] __initdata = {
125 {
126 .virtual = (unsigned long)S5P_VA_CHIPID,
127 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
128 .length = SZ_4K,
129 .type = MT_DEVICE,
130 },
131};
132
116static struct map_desc exynos4_iodesc[] __initdata = { 133static struct map_desc exynos4_iodesc[] __initdata = {
117 { 134 {
118 .virtual = (unsigned long)S3C_VA_SYS, 135 .virtual = (unsigned long)S3C_VA_SYS,
@@ -279,6 +296,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
279 }, 296 },
280}; 297};
281 298
299static struct map_desc exynos5440_iodesc0[] __initdata = {
300 {
301 .virtual = (unsigned long)S3C_VA_UART,
302 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
303 .length = SZ_512K,
304 .type = MT_DEVICE,
305 },
306};
307
282void exynos4_restart(char mode, const char *cmd) 308void exynos4_restart(char mode, const char *cmd)
283{ 309{
284 __raw_writel(0x1, S5P_SWRESET); 310 __raw_writel(0x1, S5P_SWRESET);
@@ -286,11 +312,29 @@ void exynos4_restart(char mode, const char *cmd)
286 312
287void exynos5_restart(char mode, const char *cmd) 313void exynos5_restart(char mode, const char *cmd)
288{ 314{
289 __raw_writel(0x1, EXYNOS_SWRESET); 315 u32 val;
316 void __iomem *addr;
317
318 if (of_machine_is_compatible("samsung,exynos5250")) {
319 val = 0x1;
320 addr = EXYNOS_SWRESET;
321 } else if (of_machine_is_compatible("samsung,exynos5440")) {
322 val = (0x10 << 20) | (0x1 << 16);
323 addr = EXYNOS5440_SWRESET;
324 } else {
325 pr_err("%s: cannot support non-DT\n", __func__);
326 return;
327 }
328
329 __raw_writel(val, addr);
290} 330}
291 331
292void __init exynos_init_late(void) 332void __init exynos_init_late(void)
293{ 333{
334 if (of_machine_is_compatible("samsung,exynos5440"))
335 /* to be supported later */
336 return;
337
294 exynos_pm_late_initcall(); 338 exynos_pm_late_initcall();
295} 339}
296 340
@@ -303,7 +347,11 @@ void __init exynos_init_late(void)
303void __init exynos_init_io(struct map_desc *mach_desc, int size) 347void __init exynos_init_io(struct map_desc *mach_desc, int size)
304{ 348{
305 /* initialize the io descriptors we need for initialization */ 349 /* initialize the io descriptors we need for initialization */
306 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); 350 if (of_machine_is_compatible("samsung,exynos5440"))
351 iotable_init(exynos5440_iodesc, ARRAY_SIZE(exynos5440_iodesc));
352 else
353 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
354
307 if (mach_desc) 355 if (mach_desc)
308 iotable_init(mach_desc, size); 356 iotable_init(mach_desc, size);
309 357
@@ -389,6 +437,11 @@ static void __init exynos4_init_clocks(int xtal)
389 exynos4_setup_clocks(); 437 exynos4_setup_clocks();
390} 438}
391 439
440static void __init exynos5440_map_io(void)
441{
442 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
443}
444
392static void __init exynos5_init_clocks(int xtal) 445static void __init exynos5_init_clocks(int xtal)
393{ 446{
394 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 447 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -604,8 +657,9 @@ int __init combiner_of_init(struct device_node *np, struct device_node *parent)
604 return 0; 657 return 0;
605} 658}
606 659
607static const struct of_device_id exynos4_dt_irq_match[] = { 660static const struct of_device_id exynos_dt_irq_match[] = {
608 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 661 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
662 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
609 { .compatible = "samsung,exynos4210-combiner", 663 { .compatible = "samsung,exynos4210-combiner",
610 .data = combiner_of_init, }, 664 .data = combiner_of_init, },
611 {}, 665 {},
@@ -622,7 +676,7 @@ void __init exynos4_init_irq(void)
622 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); 676 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
623#ifdef CONFIG_OF 677#ifdef CONFIG_OF
624 else 678 else
625 of_irq_init(exynos4_dt_irq_match); 679 of_irq_init(exynos_dt_irq_match);
626#endif 680#endif
627 681
628 if (!of_have_populated_dt()) 682 if (!of_have_populated_dt())
@@ -639,7 +693,7 @@ void __init exynos4_init_irq(void)
639void __init exynos5_init_irq(void) 693void __init exynos5_init_irq(void)
640{ 694{
641#ifdef CONFIG_OF 695#ifdef CONFIG_OF
642 of_irq_init(exynos4_dt_irq_match); 696 of_irq_init(exynos_dt_irq_match);
643#endif 697#endif
644 /* 698 /*
645 * The parameters of s5p_init_irq() are for VIC init. 699 * The parameters of s5p_init_irq() are for VIC init.
@@ -669,7 +723,7 @@ static int __init exynos4_l2x0_cache_init(void)
669{ 723{
670 int ret; 724 int ret;
671 725
672 if (soc_is_exynos5250()) 726 if (soc_is_exynos5250() || soc_is_exynos5440())
673 return 0; 727 return 0;
674 728
675 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); 729 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
@@ -1010,6 +1064,8 @@ static int __init exynos_init_irq_eint(void)
1010 } 1064 }
1011 } 1065 }
1012#endif 1066#endif
1067 if (soc_is_exynos5440())
1068 return 0;
1013 1069
1014 if (soc_is_exynos5250()) 1070 if (soc_is_exynos5250())
1015 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); 1071 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6f9092..f43a96ca6f98 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -333,6 +333,11 @@
333#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126) 333#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
334#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) 334#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
335 335
336/* EXYNOS5440 */
337
338#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
339#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
340
336#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) 341#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
337 342
338#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) 343#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 8480849affb9..aa3760e1d668 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -53,6 +53,7 @@
53#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 53#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
54 54
55#define EXYNOS_PA_CHIPID 0x10000000 55#define EXYNOS_PA_CHIPID 0x10000000
56#define EXYNOS5440_PA_CHIPID 0x00160000
56 57
57#define EXYNOS4_PA_SYSCON 0x10010000 58#define EXYNOS4_PA_SYSCON 0x10010000
58#define EXYNOS5_PA_SYSCON 0x10050100 59#define EXYNOS5_PA_SYSCON 0x10050100
@@ -281,6 +282,10 @@
281#define EXYNOS5_PA_UART3 0x12C30000 282#define EXYNOS5_PA_UART3 0x12C30000
282#define EXYNOS5_SZ_UART SZ_256 283#define EXYNOS5_SZ_UART SZ_256
283 284
285#define EXYNOS5440_PA_UART0 0x000B0000
286#define EXYNOS5440_PA_UART1 0x000C0000
287#define EXYNOS5440_SZ_UART SZ_256
288
284#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 289#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
285 290
286#endif /* __ASM_ARCH_MAP_H */ 291#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b811a3..c0b74f388178 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
31 31
32#define S5P_SWRESET S5P_PMUREG(0x0400) 32#define S5P_SWRESET S5P_PMUREG(0x0400)
33#define EXYNOS_SWRESET S5P_PMUREG(0x0400) 33#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
34#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
34 35
35#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 36#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 37#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8eacf28..4db2ee1238b4 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -75,20 +75,33 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
75 {}, 75 {},
76}; 76};
77 77
78static void __init exynos5250_dt_map_io(void) 78static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
79 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
80 "exynos4210-uart.0", NULL),
81 {},
82};
83
84static void __init exynos5_dt_map_io(void)
79{ 85{
80 exynos_init_io(NULL, 0); 86 exynos_init_io(NULL, 0);
81 s3c24xx_init_clocks(24000000); 87
88 if (of_machine_is_compatible("samsung,exynos5250"))
89 s3c24xx_init_clocks(24000000);
82} 90}
83 91
84static void __init exynos5250_dt_machine_init(void) 92static void __init exynos5_dt_machine_init(void)
85{ 93{
86 of_platform_populate(NULL, of_default_bus_match_table, 94 if (of_machine_is_compatible("samsung,exynos5250"))
87 exynos5250_auxdata_lookup, NULL); 95 of_platform_populate(NULL, of_default_bus_match_table,
96 exynos5250_auxdata_lookup, NULL);
97 else if (of_machine_is_compatible("samsung,exynos5440"))
98 of_platform_populate(NULL, of_default_bus_match_table,
99 exynos5440_auxdata_lookup, NULL);
88} 100}
89 101
90static char const *exynos5250_dt_compat[] __initdata = { 102static char const *exynos5_dt_compat[] __initdata = {
91 "samsung,exynos5250", 103 "samsung,exynos5250",
104 "samsung,exynos5440",
92 NULL 105 NULL
93}; 106};
94 107
@@ -96,11 +109,11 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
96 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 109 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
97 .init_irq = exynos5_init_irq, 110 .init_irq = exynos5_init_irq,
98 .smp = smp_ops(exynos_smp_ops), 111 .smp = smp_ops(exynos_smp_ops),
99 .map_io = exynos5250_dt_map_io, 112 .map_io = exynos5_dt_map_io,
100 .handle_irq = gic_handle_irq, 113 .handle_irq = gic_handle_irq,
101 .init_machine = exynos5250_dt_machine_init, 114 .init_machine = exynos5_dt_machine_init,
102 .init_late = exynos_init_late, 115 .init_late = exynos_init_late,
103 .timer = &exynos4_timer, 116 .timer = &exynos4_timer,
104 .dt_compat = exynos5250_dt_compat, 117 .dt_compat = exynos5_dt_compat,
105 .restart = exynos5_restart, 118 .restart = exynos5_restart,
106MACHINE_END 119MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8a408b..57668eb68e75 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -19,7 +19,9 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/percpu.h> 21#include <linux/percpu.h>
22#include <linux/of.h>
22 23
24#include <asm/arch_timer.h>
23#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
24#include <asm/localtimer.h> 26#include <asm/localtimer.h>
25 27
@@ -476,8 +478,13 @@ static void __init exynos4_timer_resources(void)
476#endif /* CONFIG_LOCAL_TIMERS */ 478#endif /* CONFIG_LOCAL_TIMERS */
477} 479}
478 480
479static void __init exynos4_timer_init(void) 481static void __init exynos_timer_init(void)
480{ 482{
483 if (soc_is_exynos5440()) {
484 arch_timer_of_register();
485 return;
486 }
487
481 if ((soc_is_exynos4210()) || (soc_is_exynos5250())) 488 if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
482 mct_int_type = MCT_INT_SPI; 489 mct_int_type = MCT_INT_SPI;
483 else 490 else
@@ -489,5 +496,5 @@ static void __init exynos4_timer_init(void)
489} 496}
490 497
491struct sys_timer exynos4_timer = { 498struct sys_timer exynos4_timer = {
492 .init = exynos4_timer_init, 499 .init = exynos_timer_init,
493}; 500};
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index 5700f23629f7..e2d9dfbf102c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -20,7 +20,7 @@ struct platform_device; /* don't need the contents */
20 20
21void s3c_i2c0_cfg_gpio(struct platform_device *dev) 21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{ 22{
23 if (soc_is_exynos5250()) 23 if (soc_is_exynos5250() || soc_is_exynos5440())
24 /* will be implemented with gpio function */ 24 /* will be implemented with gpio function */
25 return; 25 return;
26 26
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index ace4451b7651..e0072ce8d6e9 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,7 @@ extern unsigned long samsung_cpu_id;
43#define EXYNOS4_CPU_MASK 0xFFFE0000 43#define EXYNOS4_CPU_MASK 0xFFFE0000
44 44
45#define EXYNOS5250_SOC_ID 0x43520000 45#define EXYNOS5250_SOC_ID 0x43520000
46#define EXYNOS5440_SOC_ID 0x54400000
46#define EXYNOS5_SOC_MASK 0xFFFFF000 47#define EXYNOS5_SOC_MASK 0xFFFFF000
47 48
48#define IS_SAMSUNG_CPU(name, id, mask) \ 49#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -62,6 +63,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
62IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 63IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
63IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) 64IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
64IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) 65IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
66IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
65 67
66#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 68#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
67 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ 69 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -130,6 +132,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
130# define soc_is_exynos5250() 0 132# define soc_is_exynos5250() 0
131#endif 133#endif
132 134
135#if defined(CONFIG_SOC_EXYNOS5440)
136# define soc_is_exynos5440() is_samsung_exynos5440()
137#else
138# define soc_is_exynos5440() 0
139#endif
140
133#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 141#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
134 142
135#ifndef KHZ 143#ifndef KHZ
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d96caefd914a..dd08b490d091 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -188,6 +188,11 @@ config PINCTRL_EXYNOS4
188 depends on OF && GPIOLIB 188 depends on OF && GPIOLIB
189 select PINCTRL_SAMSUNG 189 select PINCTRL_SAMSUNG
190 190
191config PINCTRL_EXYNOS5440
192 bool "Samsung EXYNOS5440 SoC pinctrl driver"
193 select PINMUX
194 select PINCONF
195
191config PINCTRL_MVEBU 196config PINCTRL_MVEBU
192 bool 197 bool
193 depends on ARCH_MVEBU 198 depends on ARCH_MVEBU
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f395ba5cec25..476928bb97c2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
36obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 36obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
37obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o 37obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
38obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o 38obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o
39obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
39obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o 40obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
40obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o 41obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
41obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o 42obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
new file mode 100644
index 000000000000..b8635f634e91
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -0,0 +1,919 @@
1/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
23#include "core.h"
24
25/* EXYNOS5440 GPIO and Pinctrl register offsets */
26#define GPIO_MUX 0x00
27#define GPIO_IE 0x04
28#define GPIO_INT 0x08
29#define GPIO_TYPE 0x0C
30#define GPIO_VAL 0x10
31#define GPIO_OE 0x14
32#define GPIO_IN 0x18
33#define GPIO_PE 0x1C
34#define GPIO_PS 0x20
35#define GPIO_SR 0x24
36#define GPIO_DS0 0x28
37#define GPIO_DS1 0x2C
38
39#define EXYNOS5440_MAX_PINS 23
40#define PIN_NAME_LENGTH 10
41
42#define GROUP_SUFFIX "-grp"
43#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
44#define FUNCTION_SUFFIX "-mux"
45#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
46
47/*
48 * pin configuration type and its value are packed together into a 16-bits.
49 * The upper 8-bits represent the configuration type and the lower 8-bits
50 * hold the value of the configuration type.
51 */
52#define PINCFG_TYPE_MASK 0xFF
53#define PINCFG_VALUE_SHIFT 8
54#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
55#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
56#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
57#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
58 PINCFG_VALUE_SHIFT)
59
60/**
61 * enum pincfg_type - possible pin configuration types supported.
62 * @PINCFG_TYPE_PUD: Pull up/down configuration.
63 * @PINCFG_TYPE_DRV: Drive strength configuration.
64 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
65 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
66 */
67enum pincfg_type {
68 PINCFG_TYPE_PUD,
69 PINCFG_TYPE_DRV,
70 PINCFG_TYPE_SKEW_RATE,
71 PINCFG_TYPE_INPUT_TYPE
72};
73
74/**
75 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
76 * @name: name of the pin group, used to lookup the group.
77 * @pins: the pins included in this group.
78 * @num_pins: number of pins included in this group.
79 */
80struct exynos5440_pin_group {
81 const char *name;
82 const unsigned int *pins;
83 u8 num_pins;
84};
85
86/**
87 * struct exynos5440_pmx_func: represent a pin function.
88 * @name: name of the pin function, used to lookup the function.
89 * @groups: one or more names of pin groups that provide this function.
90 * @num_groups: number of groups included in @groups.
91 * @function: the function number to be programmed when selected.
92 */
93struct exynos5440_pmx_func {
94 const char *name;
95 const char **groups;
96 u8 num_groups;
97 unsigned long function;
98};
99
100/**
101 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
102 * @reg_base: ioremapped based address of the register space.
103 * @gc: gpio chip registered with gpiolib.
104 * @pin_groups: list of pin groups parsed from device tree.
105 * @nr_groups: number of pin groups available.
106 * @pmx_functions: list of pin functions parsed from device tree.
107 * @nr_functions: number of pin functions available.
108 */
109struct exynos5440_pinctrl_priv_data {
110 void __iomem *reg_base;
111 struct gpio_chip *gc;
112
113 const struct exynos5440_pin_group *pin_groups;
114 unsigned int nr_groups;
115 const struct exynos5440_pmx_func *pmx_functions;
116 unsigned int nr_functions;
117};
118
119/* list of all possible config options supported */
120struct pin_config {
121 char *prop_cfg;
122 unsigned int cfg_type;
123} pcfgs[] = {
124 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
125 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
126 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
127 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
128};
129
130/* check if the selector is a valid pin group selector */
131static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
132{
133 struct exynos5440_pinctrl_priv_data *priv;
134
135 priv = pinctrl_dev_get_drvdata(pctldev);
136 return priv->nr_groups;
137}
138
139/* return the name of the group selected by the group selector */
140static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
141 unsigned selector)
142{
143 struct exynos5440_pinctrl_priv_data *priv;
144
145 priv = pinctrl_dev_get_drvdata(pctldev);
146 return priv->pin_groups[selector].name;
147}
148
149/* return the pin numbers associated with the specified group */
150static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
151 unsigned selector, const unsigned **pins, unsigned *num_pins)
152{
153 struct exynos5440_pinctrl_priv_data *priv;
154
155 priv = pinctrl_dev_get_drvdata(pctldev);
156 *pins = priv->pin_groups[selector].pins;
157 *num_pins = priv->pin_groups[selector].num_pins;
158 return 0;
159}
160
161/* create pinctrl_map entries by parsing device tree nodes */
162static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
163 struct device_node *np, struct pinctrl_map **maps,
164 unsigned *nmaps)
165{
166 struct device *dev = pctldev->dev;
167 struct pinctrl_map *map;
168 unsigned long *cfg = NULL;
169 char *gname, *fname;
170 int cfg_cnt = 0, map_cnt = 0, idx = 0;
171
172 /* count the number of config options specfied in the node */
173 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
174 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
175 cfg_cnt++;
176
177 /*
178 * Find out the number of map entries to create. All the config options
179 * can be accomadated into a single config map entry.
180 */
181 if (cfg_cnt)
182 map_cnt = 1;
183 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
184 map_cnt++;
185 if (!map_cnt) {
186 dev_err(dev, "node %s does not have either config or function "
187 "configurations\n", np->name);
188 return -EINVAL;
189 }
190
191 /* Allocate memory for pin-map entries */
192 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
193 if (!map) {
194 dev_err(dev, "could not alloc memory for pin-maps\n");
195 return -ENOMEM;
196 }
197 *nmaps = 0;
198
199 /*
200 * Allocate memory for pin group name. The pin group name is derived
201 * from the node name from which these map entries are be created.
202 */
203 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
204 if (!gname) {
205 dev_err(dev, "failed to alloc memory for group name\n");
206 goto free_map;
207 }
208 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
209
210 /*
211 * don't have config options? then skip over to creating function
212 * map entries.
213 */
214 if (!cfg_cnt)
215 goto skip_cfgs;
216
217 /* Allocate memory for config entries */
218 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
219 if (!cfg) {
220 dev_err(dev, "failed to alloc memory for configs\n");
221 goto free_gname;
222 }
223
224 /* Prepare a list of config settings */
225 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
226 u32 value;
227 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
228 cfg[cfg_cnt++] =
229 PINCFG_PACK(pcfgs[idx].cfg_type, value);
230 }
231
232 /* create the config map entry */
233 map[*nmaps].data.configs.group_or_pin = gname;
234 map[*nmaps].data.configs.configs = cfg;
235 map[*nmaps].data.configs.num_configs = cfg_cnt;
236 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
237 *nmaps += 1;
238
239skip_cfgs:
240 /* create the function map entry */
241 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
242 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
243 if (!fname) {
244 dev_err(dev, "failed to alloc memory for func name\n");
245 goto free_cfg;
246 }
247 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
248
249 map[*nmaps].data.mux.group = gname;
250 map[*nmaps].data.mux.function = fname;
251 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
252 *nmaps += 1;
253 }
254
255 *maps = map;
256 return 0;
257
258free_cfg:
259 kfree(cfg);
260free_gname:
261 kfree(gname);
262free_map:
263 kfree(map);
264 return -ENOMEM;
265}
266
267/* free the memory allocated to hold the pin-map table */
268static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
269 struct pinctrl_map *map, unsigned num_maps)
270{
271 int idx;
272
273 for (idx = 0; idx < num_maps; idx++) {
274 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
275 kfree(map[idx].data.mux.function);
276 if (!idx)
277 kfree(map[idx].data.mux.group);
278 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
279 kfree(map[idx].data.configs.configs);
280 if (!idx)
281 kfree(map[idx].data.configs.group_or_pin);
282 }
283 };
284
285 kfree(map);
286}
287
288/* list of pinctrl callbacks for the pinctrl core */
289static struct pinctrl_ops exynos5440_pctrl_ops = {
290 .get_groups_count = exynos5440_get_group_count,
291 .get_group_name = exynos5440_get_group_name,
292 .get_group_pins = exynos5440_get_group_pins,
293 .dt_node_to_map = exynos5440_dt_node_to_map,
294 .dt_free_map = exynos5440_dt_free_map,
295};
296
297/* check if the selector is a valid pin function selector */
298static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
299{
300 struct exynos5440_pinctrl_priv_data *priv;
301
302 priv = pinctrl_dev_get_drvdata(pctldev);
303 return priv->nr_functions;
304}
305
306/* return the name of the pin function specified */
307static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
308 unsigned selector)
309{
310 struct exynos5440_pinctrl_priv_data *priv;
311
312 priv = pinctrl_dev_get_drvdata(pctldev);
313 return priv->pmx_functions[selector].name;
314}
315
316/* return the groups associated for the specified function selector */
317static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
318 unsigned selector, const char * const **groups,
319 unsigned * const num_groups)
320{
321 struct exynos5440_pinctrl_priv_data *priv;
322
323 priv = pinctrl_dev_get_drvdata(pctldev);
324 *groups = priv->pmx_functions[selector].groups;
325 *num_groups = priv->pmx_functions[selector].num_groups;
326 return 0;
327}
328
329/* enable or disable a pinmux function */
330static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
331 unsigned group, bool enable)
332{
333 struct exynos5440_pinctrl_priv_data *priv;
334 void __iomem *base;
335 u32 function;
336 u32 data;
337
338 priv = pinctrl_dev_get_drvdata(pctldev);
339 base = priv->reg_base;
340 function = priv->pmx_functions[selector].function;
341
342 data = readl(base + GPIO_MUX);
343 if (enable)
344 data |= (1 << function);
345 else
346 data &= ~(1 << function);
347 writel(data, base + GPIO_MUX);
348}
349
350/* enable a specified pinmux by writing to registers */
351static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
352 unsigned group)
353{
354 exynos5440_pinmux_setup(pctldev, selector, group, true);
355 return 0;
356}
357
358/* disable a specified pinmux by writing to registers */
359static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
360 unsigned selector, unsigned group)
361{
362 exynos5440_pinmux_setup(pctldev, selector, group, false);
363}
364
365/*
366 * The calls to gpio_direction_output() and gpio_direction_input()
367 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
368 * function called from the gpiolib interface).
369 */
370static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
371 struct pinctrl_gpio_range *range, unsigned offset, bool input)
372{
373 return 0;
374}
375
376/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
377static struct pinmux_ops exynos5440_pinmux_ops = {
378 .get_functions_count = exynos5440_get_functions_count,
379 .get_function_name = exynos5440_pinmux_get_fname,
380 .get_function_groups = exynos5440_pinmux_get_groups,
381 .enable = exynos5440_pinmux_enable,
382 .disable = exynos5440_pinmux_disable,
383 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
384};
385
386/* set the pin config settings for a specified pin */
387static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
388 unsigned long config)
389{
390 struct exynos5440_pinctrl_priv_data *priv;
391 void __iomem *base;
392 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
393 u32 cfg_value = PINCFG_UNPACK_VALUE(config);
394 u32 data;
395
396 priv = pinctrl_dev_get_drvdata(pctldev);
397 base = priv->reg_base;
398
399 switch (cfg_type) {
400 case PINCFG_TYPE_PUD:
401 /* first set pull enable/disable bit */
402 data = readl(base + GPIO_PE);
403 data &= ~(1 << pin);
404 if (cfg_value)
405 data |= (1 << pin);
406 writel(data, base + GPIO_PE);
407
408 /* then set pull up/down bit */
409 data = readl(base + GPIO_PS);
410 data &= ~(1 << pin);
411 if (cfg_value == 2)
412 data |= (1 << pin);
413 writel(data, base + GPIO_PS);
414 break;
415
416 case PINCFG_TYPE_DRV:
417 /* set the first bit of the drive strength */
418 data = readl(base + GPIO_DS0);
419 data &= ~(1 << pin);
420 data |= ((cfg_value & 1) << pin);
421 writel(data, base + GPIO_DS0);
422 cfg_value >>= 1;
423
424 /* set the second bit of the driver strength */
425 data = readl(base + GPIO_DS1);
426 data &= ~(1 << pin);
427 data |= ((cfg_value & 1) << pin);
428 writel(data, base + GPIO_DS1);
429 break;
430 case PINCFG_TYPE_SKEW_RATE:
431 data = readl(base + GPIO_SR);
432 data &= ~(1 << pin);
433 data |= ((cfg_value & 1) << pin);
434 writel(data, base + GPIO_SR);
435 break;
436 case PINCFG_TYPE_INPUT_TYPE:
437 data = readl(base + GPIO_TYPE);
438 data &= ~(1 << pin);
439 data |= ((cfg_value & 1) << pin);
440 writel(data, base + GPIO_TYPE);
441 break;
442 default:
443 WARN_ON(1);
444 return -EINVAL;
445 }
446
447 return 0;
448}
449
450/* get the pin config settings for a specified pin */
451static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
452 unsigned long *config)
453{
454 struct exynos5440_pinctrl_priv_data *priv;
455 void __iomem *base;
456 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
457 u32 data;
458
459 priv = pinctrl_dev_get_drvdata(pctldev);
460 base = priv->reg_base;
461
462 switch (cfg_type) {
463 case PINCFG_TYPE_PUD:
464 data = readl(base + GPIO_PE);
465 data = (data >> pin) & 1;
466 if (!data)
467 *config = 0;
468 else
469 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
470 break;
471 case PINCFG_TYPE_DRV:
472 data = readl(base + GPIO_DS0);
473 data = (data >> pin) & 1;
474 *config = data;
475 data = readl(base + GPIO_DS1);
476 data = (data >> pin) & 1;
477 *config |= (data << 1);
478 break;
479 case PINCFG_TYPE_SKEW_RATE:
480 data = readl(base + GPIO_SR);
481 *config = (data >> pin) & 1;
482 break;
483 case PINCFG_TYPE_INPUT_TYPE:
484 data = readl(base + GPIO_TYPE);
485 *config = (data >> pin) & 1;
486 break;
487 default:
488 WARN_ON(1);
489 return -EINVAL;
490 }
491
492 return 0;
493}
494
495/* set the pin config settings for a specified pin group */
496static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
497 unsigned group, unsigned long config)
498{
499 struct exynos5440_pinctrl_priv_data *priv;
500 const unsigned int *pins;
501 unsigned int cnt;
502
503 priv = pinctrl_dev_get_drvdata(pctldev);
504 pins = priv->pin_groups[group].pins;
505
506 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
507 exynos5440_pinconf_set(pctldev, pins[cnt], config);
508
509 return 0;
510}
511
512/* get the pin config settings for a specified pin group */
513static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
514 unsigned int group, unsigned long *config)
515{
516 struct exynos5440_pinctrl_priv_data *priv;
517 const unsigned int *pins;
518
519 priv = pinctrl_dev_get_drvdata(pctldev);
520 pins = priv->pin_groups[group].pins;
521 exynos5440_pinconf_get(pctldev, pins[0], config);
522 return 0;
523}
524
525/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
526static struct pinconf_ops exynos5440_pinconf_ops = {
527 .pin_config_get = exynos5440_pinconf_get,
528 .pin_config_set = exynos5440_pinconf_set,
529 .pin_config_group_get = exynos5440_pinconf_group_get,
530 .pin_config_group_set = exynos5440_pinconf_group_set,
531};
532
533/* gpiolib gpio_set callback function */
534static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
535{
536 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
537 void __iomem *base = priv->reg_base;
538 u32 data;
539
540 data = readl(base + GPIO_VAL);
541 data &= ~(1 << offset);
542 if (value)
543 data |= 1 << offset;
544 writel(data, base + GPIO_VAL);
545}
546
547/* gpiolib gpio_get callback function */
548static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
549{
550 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
551 void __iomem *base = priv->reg_base;
552 u32 data;
553
554 data = readl(base + GPIO_IN);
555 data >>= offset;
556 data &= 1;
557 return data;
558}
559
560/* gpiolib gpio_direction_input callback function */
561static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
562{
563 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
564 void __iomem *base = priv->reg_base;
565 u32 data;
566
567 /* first disable the data output enable on this pin */
568 data = readl(base + GPIO_OE);
569 data &= ~(1 << offset);
570 writel(data, base + GPIO_OE);
571
572 /* now enable input on this pin */
573 data = readl(base + GPIO_IE);
574 data |= 1 << offset;
575 writel(data, base + GPIO_IE);
576 return 0;
577}
578
579/* gpiolib gpio_direction_output callback function */
580static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
581 int value)
582{
583 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
584 void __iomem *base = priv->reg_base;
585 u32 data;
586
587 exynos5440_gpio_set(gc, offset, value);
588
589 /* first disable the data input enable on this pin */
590 data = readl(base + GPIO_IE);
591 data &= ~(1 << offset);
592 writel(data, base + GPIO_IE);
593
594 /* now enable output on this pin */
595 data = readl(base + GPIO_OE);
596 data |= 1 << offset;
597 writel(data, base + GPIO_OE);
598 return 0;
599}
600
601/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
602static int __init exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
603 struct device_node *cfg_np, unsigned int **pin_list,
604 unsigned int *npins)
605{
606 struct device *dev = &pdev->dev;
607 struct property *prop;
608
609 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
610 if (!prop)
611 return -ENOENT;
612
613 *npins = prop->length / sizeof(unsigned long);
614 if (!*npins) {
615 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
616 return -EINVAL;
617 }
618
619 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
620 if (!*pin_list) {
621 dev_err(dev, "failed to allocate memory for pin list\n");
622 return -ENOMEM;
623 }
624
625 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
626 *pin_list, *npins);
627}
628
629/*
630 * Parse the information about all the available pin groups and pin functions
631 * from device node of the pin-controller.
632 */
633static int __init exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
634 struct exynos5440_pinctrl_priv_data *priv)
635{
636 struct device *dev = &pdev->dev;
637 struct device_node *dev_np = dev->of_node;
638 struct device_node *cfg_np;
639 struct exynos5440_pin_group *groups, *grp;
640 struct exynos5440_pmx_func *functions, *func;
641 unsigned *pin_list;
642 unsigned int npins, grp_cnt, func_idx = 0;
643 char *gname, *fname;
644 int ret;
645
646 grp_cnt = of_get_child_count(dev_np);
647 if (!grp_cnt)
648 return -EINVAL;
649
650 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
651 if (!groups) {
652 dev_err(dev, "failed allocate memory for ping group list\n");
653 return -EINVAL;
654 }
655 grp = groups;
656
657 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
658 if (!functions) {
659 dev_err(dev, "failed to allocate memory for function list\n");
660 return -EINVAL;
661 }
662 func = functions;
663
664 /*
665 * Iterate over all the child nodes of the pin controller node
666 * and create pin groups and pin function lists.
667 */
668 for_each_child_of_node(dev_np, cfg_np) {
669 u32 function;
670
671 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
672 &pin_list, &npins);
673 if (ret)
674 return ret;
675
676 /* derive pin group name from the node name */
677 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
678 GFP_KERNEL);
679 if (!gname) {
680 dev_err(dev, "failed to alloc memory for group name\n");
681 return -ENOMEM;
682 }
683 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
684
685 grp->name = gname;
686 grp->pins = pin_list;
687 grp->num_pins = npins;
688 grp++;
689
690 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
691 &function);
692 if (ret)
693 continue;
694
695 /* derive function name from the node name */
696 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
697 GFP_KERNEL);
698 if (!fname) {
699 dev_err(dev, "failed to alloc memory for func name\n");
700 return -ENOMEM;
701 }
702 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
703
704 func->name = fname;
705 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
706 if (!func->groups) {
707 dev_err(dev, "failed to alloc memory for group list "
708 "in pin function");
709 return -ENOMEM;
710 }
711 func->groups[0] = gname;
712 func->num_groups = 1;
713 func->function = function;
714 func++;
715 func_idx++;
716 }
717
718 priv->pin_groups = groups;
719 priv->nr_groups = grp_cnt;
720 priv->pmx_functions = functions;
721 priv->nr_functions = func_idx;
722 return 0;
723}
724
725/* register the pinctrl interface with the pinctrl subsystem */
726static int __init exynos5440_pinctrl_register(struct platform_device *pdev,
727 struct exynos5440_pinctrl_priv_data *priv)
728{
729 struct device *dev = &pdev->dev;
730 struct pinctrl_desc *ctrldesc;
731 struct pinctrl_dev *pctl_dev;
732 struct pinctrl_pin_desc *pindesc, *pdesc;
733 struct pinctrl_gpio_range grange;
734 char *pin_names;
735 int pin, ret;
736
737 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
738 if (!ctrldesc) {
739 dev_err(dev, "could not allocate memory for pinctrl desc\n");
740 return -ENOMEM;
741 }
742
743 ctrldesc->name = "exynos5440-pinctrl";
744 ctrldesc->owner = THIS_MODULE;
745 ctrldesc->pctlops = &exynos5440_pctrl_ops;
746 ctrldesc->pmxops = &exynos5440_pinmux_ops;
747 ctrldesc->confops = &exynos5440_pinconf_ops;
748
749 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
750 EXYNOS5440_MAX_PINS, GFP_KERNEL);
751 if (!pindesc) {
752 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
753 return -ENOMEM;
754 }
755 ctrldesc->pins = pindesc;
756 ctrldesc->npins = EXYNOS5440_MAX_PINS;
757
758 /* dynamically populate the pin number and pin name for pindesc */
759 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
760 pdesc->number = pin;
761
762 /*
763 * allocate space for storing the dynamically generated names for all
764 * the pins which belong to this pin-controller.
765 */
766 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
767 ctrldesc->npins, GFP_KERNEL);
768 if (!pin_names) {
769 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
770 return -ENOMEM;
771 }
772
773 /* for each pin, set the name of the pin */
774 for (pin = 0; pin < ctrldesc->npins; pin++) {
775 sprintf(pin_names, "gpio%02d", pin);
776 pdesc = pindesc + pin;
777 pdesc->name = pin_names;
778 pin_names += PIN_NAME_LENGTH;
779 }
780
781 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
782 if (ret)
783 return ret;
784
785 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
786 if (!pctl_dev) {
787 dev_err(&pdev->dev, "could not register pinctrl driver\n");
788 return -EINVAL;
789 }
790
791 grange.name = "exynos5440-pctrl-gpio-range";
792 grange.id = 0;
793 grange.base = 0;
794 grange.npins = EXYNOS5440_MAX_PINS;
795 grange.gc = priv->gc;
796 pinctrl_add_gpio_range(pctl_dev, &grange);
797 return 0;
798}
799
800/* register the gpiolib interface with the gpiolib subsystem */
801static int __init exynos5440_gpiolib_register(struct platform_device *pdev,
802 struct exynos5440_pinctrl_priv_data *priv)
803{
804 struct gpio_chip *gc;
805 int ret;
806
807 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
808 if (!gc) {
809 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
810 return -ENOMEM;
811 }
812
813 priv->gc = gc;
814 gc->base = 0;
815 gc->ngpio = EXYNOS5440_MAX_PINS;
816 gc->dev = &pdev->dev;
817 gc->set = exynos5440_gpio_set;
818 gc->get = exynos5440_gpio_get;
819 gc->direction_input = exynos5440_gpio_direction_input;
820 gc->direction_output = exynos5440_gpio_direction_output;
821 gc->label = "gpiolib-exynos5440";
822 gc->owner = THIS_MODULE;
823 ret = gpiochip_add(gc);
824 if (ret) {
825 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
826 "code: %d\n", gc->label, ret);
827 return ret;
828 }
829
830 return 0;
831}
832
833/* unregister the gpiolib interface with the gpiolib subsystem */
834static int __init exynos5440_gpiolib_unregister(struct platform_device *pdev,
835 struct exynos5440_pinctrl_priv_data *priv)
836{
837 int ret = gpiochip_remove(priv->gc);
838 if (ret) {
839 dev_err(&pdev->dev, "gpio chip remove failed\n");
840 return ret;
841 }
842 return 0;
843}
844
845static int __devinit exynos5440_pinctrl_probe(struct platform_device *pdev)
846{
847 struct device *dev = &pdev->dev;
848 struct exynos5440_pinctrl_priv_data *priv;
849 struct resource *res;
850 int ret;
851
852 if (!dev->of_node) {
853 dev_err(dev, "device tree node not found\n");
854 return -ENODEV;
855 }
856
857 priv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);
858 if (!priv) {
859 dev_err(dev, "could not allocate memory for private data\n");
860 return -ENOMEM;
861 }
862
863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 if (!res) {
865 dev_err(dev, "cannot find IO resource\n");
866 return -ENOENT;
867 }
868
869 priv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
870 if (!priv->reg_base) {
871 dev_err(dev, "ioremap failed\n");
872 return -ENODEV;
873 }
874
875 ret = exynos5440_gpiolib_register(pdev, priv);
876 if (ret)
877 return ret;
878
879 ret = exynos5440_pinctrl_register(pdev, priv);
880 if (ret) {
881 exynos5440_gpiolib_unregister(pdev, priv);
882 return ret;
883 }
884
885 platform_set_drvdata(pdev, priv);
886 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
887 return 0;
888}
889
890static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
891 { .compatible = "samsung,exynos5440-pinctrl" },
892 {},
893};
894MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
895
896static struct platform_driver exynos5440_pinctrl_driver = {
897 .probe = exynos5440_pinctrl_probe,
898 .driver = {
899 .name = "exynos5440-pinctrl",
900 .owner = THIS_MODULE,
901 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
902 },
903};
904
905static int __init exynos5440_pinctrl_drv_register(void)
906{
907 return platform_driver_register(&exynos5440_pinctrl_driver);
908}
909postcore_initcall(exynos5440_pinctrl_drv_register);
910
911static void __exit exynos5440_pinctrl_drv_unregister(void)
912{
913 platform_driver_unregister(&exynos5440_pinctrl_driver);
914}
915module_exit(exynos5440_pinctrl_drv_unregister);
916
917MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
918MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
919MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 7f04717176aa..0e26a1656fa6 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1646,7 +1646,8 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1646#endif 1646#endif
1647 1647
1648#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \ 1648#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1649 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) 1649 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1650 defined(CONFIG_SOC_EXYNOS5440)
1650static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 1651static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1651 .info = &(struct s3c24xx_uart_info) { 1652 .info = &(struct s3c24xx_uart_info) {
1652 .name = "Samsung Exynos4 UART", 1653 .name = "Samsung Exynos4 UART",
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 22:47:45 -0400