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authorOlof Johansson <olof@lixom.net>2012-11-26 02:34:36 -0500
committerOlof Johansson <olof@lixom.net>2012-11-26 02:35:14 -0500
commit0f327cb11f2b8bd0b6535640e5b46746e43bbfb2 (patch)
treedc5323ff331ea879cf7a470a2cbce237f21d0cbc
parenta623f57c38eecb4069f61ea523bdc2641cd56124 (diff)
parent2b254693bef4f1299de0afb231890fe348df11c6 (diff)
Merge tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer: ARM i.MX SoC updates for v3.8 * tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6: ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt191
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt9
-rw-r--r--arch/arm/boot/dts/imx51.dtsi57
-rw-r--r--arch/arm/boot/dts/imx53.dtsi66
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi16
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c26
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c40
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c72
-rw-r--r--arch/arm/mach-imx/clk.h3
-rw-r--r--arch/arm/mach-imx/imx51-dt.c28
-rw-r--r--arch/arm/mach-imx/mach-imx53.c31
11 files changed, 386 insertions, 153 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
1* Clock bindings for Freescale i.MX5
2
3Required properties:
4- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX5
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_di 26
42 tve_s 27
43 uart1_ipg_gate 28
44 uart1_per_gate 29
45 uart2_ipg_gate 30
46 uart2_per_gate 31
47 uart3_ipg_gate 32
48 uart3_per_gate 33
49 i2c1_gate 34
50 i2c2_gate 35
51 gpt_ipg_gate 36
52 pwm1_ipg_gate 37
53 pwm1_hf_gate 38
54 pwm2_ipg_gate 39
55 pwm2_hf_gate 40
56 gpt_hf_gate 41
57 fec_gate 42
58 usboh3_per_gate 43
59 esdhc1_ipg_gate 44
60 esdhc2_ipg_gate 45
61 esdhc3_ipg_gate 46
62 esdhc4_ipg_gate 47
63 ssi1_ipg_gate 48
64 ssi2_ipg_gate 49
65 ssi3_ipg_gate 50
66 ecspi1_ipg_gate 51
67 ecspi1_per_gate 52
68 ecspi2_ipg_gate 53
69 ecspi2_per_gate 54
70 cspi_ipg_gate 55
71 sdma_gate 56
72 emi_slow_gate 57
73 ipu_s 58
74 ipu_gate 59
75 nfc_gate 60
76 ipu_di1_gate 61
77 vpu_s 62
78 vpu_gate 63
79 vpu_reference_gate 64
80 uart4_ipg_gate 65
81 uart4_per_gate 66
82 uart5_ipg_gate 67
83 uart5_per_gate 68
84 tve_gate 69
85 tve_pred 70
86 esdhc1_per_gate 71
87 esdhc2_per_gate 72
88 esdhc3_per_gate 73
89 esdhc4_per_gate 74
90 usb_phy_gate 75
91 hsi2c_gate 76
92 mipi_hsc1_gate 77
93 mipi_hsc2_gate 78
94 mipi_esc_gate 79
95 mipi_hsp_gate 80
96 ldb_di1_div_3_5 81
97 ldb_di1_div 82
98 ldb_di0_div_3_5 83
99 ldb_di0_div 84
100 ldb_di1_gate 85
101 can2_serial_gate 86
102 can2_ipg_gate 87
103 i2c3_gate 88
104 lp_apm 89
105 periph_apm 90
106 main_bus 91
107 ahb_max 92
108 aips_tz1 93
109 aips_tz2 94
110 tmax1 95
111 tmax2 96
112 tmax3 97
113 spba 98
114 uart_sel 99
115 esdhc_a_sel 100
116 esdhc_b_sel 101
117 esdhc_a_podf 102
118 esdhc_b_podf 103
119 ecspi_sel 104
120 usboh3_sel 105
121 usb_phy_sel 106
122 iim_gate 107
123 usboh3_gate 108
124 emi_fast_gate 109
125 ipu_di0_gate 110
126 gpc_dvfs 111
127 pll1_sw 112
128 pll2_sw 113
129 pll3_sw 114
130 ipu_di0_sel 115
131 ipu_di1_sel 116
132 tve_ext_sel 117
133 mx51_mipi 118
134 pll4_sw 119
135 ldb_di1_sel 120
136 di_pll4_podf 121
137 ldb_di0_sel 122
138 ldb_di0_gate 123
139 usb_phy1_gate 124
140 usb_phy2_gate 125
141 per_lp_apm 126
142 per_pred1 127
143 per_pred2 128
144 per_podf 129
145 per_root 130
146 ssi_apm 131
147 ssi1_root_sel 132
148 ssi2_root_sel 133
149 ssi3_root_sel 134
150 ssi_ext1_sel 135
151 ssi_ext2_sel 136
152 ssi_ext1_com_sel 137
153 ssi_ext2_com_sel 138
154 ssi1_root_pred 139
155 ssi1_root_podf 140
156 ssi2_root_pred 141
157 ssi2_root_podf 142
158 ssi_ext1_pred 143
159 ssi_ext1_podf 144
160 ssi_ext2_pred 145
161 ssi_ext2_podf 146
162 ssi1_root_gate 147
163 ssi2_root_gate 148
164 ssi3_root_gate 149
165 ssi_ext1_gate 150
166 ssi_ext2_gate 151
167 epit1_ipg_gate 152
168 epit1_hf_gate 153
169 epit2_ipg_gate 154
170 epit2_hf_gate 155
171 can_sel 156
172 can1_serial_gate 157
173 can1_ipg_gate 158
174
175Examples (for mx53):
176
177clks: ccm@53fd4000{
178 compatible = "fsl,imx53-ccm";
179 reg = <0x53fd4000 0x4000>;
180 interrupts = <0 71 0x04 0 72 0x04>;
181 #clock-cells = <1>;
182};
183
184can1: can@53fc8000 {
185 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
186 reg = <0x53fc8000 0x4000>;
187 interrupts = <82>;
188 clocks = <&clks 158>, <&clks 157>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 492bd991d52a..d77b4e68dc42 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -187,9 +187,9 @@ clocks and IDs.
187 pll3_usb_otg 172 187 pll3_usb_otg 172
188 pll4_audio 173 188 pll4_audio 173
189 pll5_video 174 189 pll5_video 174
190 pll6_mlb 175 190 pll8_mlb 175
191 pll7_usb_host 176 191 pll7_usb_host 176
192 pll8_enet 177 192 pll6_enet 177
193 ssi1_ipg 178 193 ssi1_ipg 178
194 ssi2_ipg 179 194 ssi2_ipg 179
195 ssi3_ipg 180 195 ssi3_ipg 180
@@ -198,6 +198,11 @@ clocks and IDs.
198 usbphy2 183 198 usbphy2 183
199 ldb_di0_div_3_5 184 199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185 200 ldb_di1_div_3_5 185
201 sata_ref 186
202 sata_ref_100m 187
203 pcie_ref 188
204 pcie_ref_125m 189
205 enet_ref 190
201 206
202Examples: 207Examples:
203 208
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 44c7af791fa5..2781e47cff0d 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -87,6 +87,8 @@
87 compatible = "fsl,imx51-esdhc"; 87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>; 88 reg = <0x70004000 0x4000>;
89 interrupts = <1>; 89 interrupts = <1>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
90 status = "disabled"; 92 status = "disabled";
91 }; 93 };
92 94
@@ -94,6 +96,8 @@
94 compatible = "fsl,imx51-esdhc"; 96 compatible = "fsl,imx51-esdhc";
95 reg = <0x70008000 0x4000>; 97 reg = <0x70008000 0x4000>;
96 interrupts = <2>; 98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
97 status = "disabled"; 101 status = "disabled";
98 }; 102 };
99 103
@@ -101,6 +105,8 @@
101 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 105 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
102 reg = <0x7000c000 0x4000>; 106 reg = <0x7000c000 0x4000>;
103 interrupts = <33>; 107 interrupts = <33>;
108 clocks = <&clks 32>, <&clks 33>;
109 clock-names = "ipg", "per";
104 status = "disabled"; 110 status = "disabled";
105 }; 111 };
106 112
@@ -110,6 +116,8 @@
110 compatible = "fsl,imx51-ecspi"; 116 compatible = "fsl,imx51-ecspi";
111 reg = <0x70010000 0x4000>; 117 reg = <0x70010000 0x4000>;
112 interrupts = <36>; 118 interrupts = <36>;
119 clocks = <&clks 51>, <&clks 52>;
120 clock-names = "ipg", "per";
113 status = "disabled"; 121 status = "disabled";
114 }; 122 };
115 123
@@ -117,6 +125,7 @@
117 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 125 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
118 reg = <0x70014000 0x4000>; 126 reg = <0x70014000 0x4000>;
119 interrupts = <30>; 127 interrupts = <30>;
128 clocks = <&clks 49>;
120 fsl,fifo-depth = <15>; 129 fsl,fifo-depth = <15>;
121 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 130 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
122 status = "disabled"; 131 status = "disabled";
@@ -126,6 +135,8 @@
126 compatible = "fsl,imx51-esdhc"; 135 compatible = "fsl,imx51-esdhc";
127 reg = <0x70020000 0x4000>; 136 reg = <0x70020000 0x4000>;
128 interrupts = <3>; 137 interrupts = <3>;
138 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
139 clock-names = "ipg", "ahb", "per";
129 status = "disabled"; 140 status = "disabled";
130 }; 141 };
131 142
@@ -133,6 +144,8 @@
133 compatible = "fsl,imx51-esdhc"; 144 compatible = "fsl,imx51-esdhc";
134 reg = <0x70024000 0x4000>; 145 reg = <0x70024000 0x4000>;
135 interrupts = <4>; 146 interrupts = <4>;
147 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
148 clock-names = "ipg", "ahb", "per";
136 status = "disabled"; 149 status = "disabled";
137 }; 150 };
138 }; 151 };
@@ -209,12 +222,14 @@
209 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 222 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
210 reg = <0x73f98000 0x4000>; 223 reg = <0x73f98000 0x4000>;
211 interrupts = <58>; 224 interrupts = <58>;
225 clocks = <&clks 0>;
212 }; 226 };
213 227
214 wdog@73f9c000 { /* WDOG2 */ 228 wdog@73f9c000 { /* WDOG2 */
215 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 229 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
216 reg = <0x73f9c000 0x4000>; 230 reg = <0x73f9c000 0x4000>;
217 interrupts = <59>; 231 interrupts = <59>;
232 clocks = <&clks 0>;
218 status = "disabled"; 233 status = "disabled";
219 }; 234 };
220 235
@@ -394,10 +409,30 @@
394 }; 409 };
395 }; 410 };
396 411
412 pwm1: pwm@73fb4000 {
413 #pwm-cells = <2>;
414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb4000 0x4000>;
416 clocks = <&clks 37>, <&clks 38>;
417 clock-names = "ipg", "per";
418 interrupts = <61>;
419 };
420
421 pwm2: pwm@73fb8000 {
422 #pwm-cells = <2>;
423 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
424 reg = <0x73fb8000 0x4000>;
425 clocks = <&clks 39>, <&clks 40>;
426 clock-names = "ipg", "per";
427 interrupts = <94>;
428 };
429
397 uart1: serial@73fbc000 { 430 uart1: serial@73fbc000 {
398 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 431 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
399 reg = <0x73fbc000 0x4000>; 432 reg = <0x73fbc000 0x4000>;
400 interrupts = <31>; 433 interrupts = <31>;
434 clocks = <&clks 28>, <&clks 29>;
435 clock-names = "ipg", "per";
401 status = "disabled"; 436 status = "disabled";
402 }; 437 };
403 438
@@ -405,8 +440,17 @@
405 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 440 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
406 reg = <0x73fc0000 0x4000>; 441 reg = <0x73fc0000 0x4000>;
407 interrupts = <32>; 442 interrupts = <32>;
443 clocks = <&clks 30>, <&clks 31>;
444 clock-names = "ipg", "per";
408 status = "disabled"; 445 status = "disabled";
409 }; 446 };
447
448 clks: ccm@73fd4000{
449 compatible = "fsl,imx51-ccm";
450 reg = <0x73fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
452 #clock-cells = <1>;
453 };
410 }; 454 };
411 455
412 aips@80000000 { /* AIPS2 */ 456 aips@80000000 { /* AIPS2 */
@@ -422,6 +466,8 @@
422 compatible = "fsl,imx51-ecspi"; 466 compatible = "fsl,imx51-ecspi";
423 reg = <0x83fac000 0x4000>; 467 reg = <0x83fac000 0x4000>;
424 interrupts = <37>; 468 interrupts = <37>;
469 clocks = <&clks 53>, <&clks 54>;
470 clock-names = "ipg", "per";
425 status = "disabled"; 471 status = "disabled";
426 }; 472 };
427 473
@@ -429,6 +475,8 @@
429 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 475 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
430 reg = <0x83fb0000 0x4000>; 476 reg = <0x83fb0000 0x4000>;
431 interrupts = <6>; 477 interrupts = <6>;
478 clocks = <&clks 56>, <&clks 56>;
479 clock-names = "ipg", "ahb";
432 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 480 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
433 }; 481 };
434 482
@@ -438,6 +486,8 @@
438 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 486 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
439 reg = <0x83fc0000 0x4000>; 487 reg = <0x83fc0000 0x4000>;
440 interrupts = <38>; 488 interrupts = <38>;
489 clocks = <&clks 55>, <&clks 0>;
490 clock-names = "ipg", "per";
441 status = "disabled"; 491 status = "disabled";
442 }; 492 };
443 493
@@ -447,6 +497,7 @@
447 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
448 reg = <0x83fc4000 0x4000>; 498 reg = <0x83fc4000 0x4000>;
449 interrupts = <63>; 499 interrupts = <63>;
500 clocks = <&clks 35>;
450 status = "disabled"; 501 status = "disabled";
451 }; 502 };
452 503
@@ -456,6 +507,7 @@
456 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 507 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
457 reg = <0x83fc8000 0x4000>; 508 reg = <0x83fc8000 0x4000>;
458 interrupts = <62>; 509 interrupts = <62>;
510 clocks = <&clks 34>;
459 status = "disabled"; 511 status = "disabled";
460 }; 512 };
461 513
@@ -463,6 +515,7 @@
463 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 515 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
464 reg = <0x83fcc000 0x4000>; 516 reg = <0x83fcc000 0x4000>;
465 interrupts = <29>; 517 interrupts = <29>;
518 clocks = <&clks 48>;
466 fsl,fifo-depth = <15>; 519 fsl,fifo-depth = <15>;
467 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 520 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
468 status = "disabled"; 521 status = "disabled";
@@ -478,6 +531,7 @@
478 compatible = "fsl,imx51-nand"; 531 compatible = "fsl,imx51-nand";
479 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 532 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
480 interrupts = <8>; 533 interrupts = <8>;
534 clocks = <&clks 60>;
481 status = "disabled"; 535 status = "disabled";
482 }; 536 };
483 537
@@ -485,6 +539,7 @@
485 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 539 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
486 reg = <0x83fe8000 0x4000>; 540 reg = <0x83fe8000 0x4000>;
487 interrupts = <96>; 541 interrupts = <96>;
542 clocks = <&clks 50>;
488 fsl,fifo-depth = <15>; 543 fsl,fifo-depth = <15>;
489 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 544 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
490 status = "disabled"; 545 status = "disabled";
@@ -494,6 +549,8 @@
494 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 549 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
495 reg = <0x83fec000 0x4000>; 550 reg = <0x83fec000 0x4000>;
496 interrupts = <87>; 551 interrupts = <87>;
552 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
553 clock-names = "ipg", "ahb", "ptp";
497 status = "disabled"; 554 status = "disabled";
498 }; 555 };
499 }; 556 };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 8317a1727118..da9a047ce4cf 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -92,6 +92,8 @@
92 compatible = "fsl,imx53-esdhc"; 92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>; 93 reg = <0x50004000 0x4000>;
94 interrupts = <1>; 94 interrupts = <1>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
95 status = "disabled"; 97 status = "disabled";
96 }; 98 };
97 99
@@ -99,6 +101,8 @@
99 compatible = "fsl,imx53-esdhc"; 101 compatible = "fsl,imx53-esdhc";
100 reg = <0x50008000 0x4000>; 102 reg = <0x50008000 0x4000>;
101 interrupts = <2>; 103 interrupts = <2>;
104 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
105 clock-names = "ipg", "ahb", "per";
102 status = "disabled"; 106 status = "disabled";
103 }; 107 };
104 108
@@ -106,6 +110,8 @@
106 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 110 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
107 reg = <0x5000c000 0x4000>; 111 reg = <0x5000c000 0x4000>;
108 interrupts = <33>; 112 interrupts = <33>;
113 clocks = <&clks 32>, <&clks 33>;
114 clock-names = "ipg", "per";
109 status = "disabled"; 115 status = "disabled";
110 }; 116 };
111 117
@@ -115,6 +121,8 @@
115 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 121 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
116 reg = <0x50010000 0x4000>; 122 reg = <0x50010000 0x4000>;
117 interrupts = <36>; 123 interrupts = <36>;
124 clocks = <&clks 51>, <&clks 52>;
125 clock-names = "ipg", "per";
118 status = "disabled"; 126 status = "disabled";
119 }; 127 };
120 128
@@ -122,6 +130,7 @@
122 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 130 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
123 reg = <0x50014000 0x4000>; 131 reg = <0x50014000 0x4000>;
124 interrupts = <30>; 132 interrupts = <30>;
133 clocks = <&clks 49>;
125 fsl,fifo-depth = <15>; 134 fsl,fifo-depth = <15>;
126 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 135 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
127 status = "disabled"; 136 status = "disabled";
@@ -131,6 +140,8 @@
131 compatible = "fsl,imx53-esdhc"; 140 compatible = "fsl,imx53-esdhc";
132 reg = <0x50020000 0x4000>; 141 reg = <0x50020000 0x4000>;
133 interrupts = <3>; 142 interrupts = <3>;
143 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
144 clock-names = "ipg", "ahb", "per";
134 status = "disabled"; 145 status = "disabled";
135 }; 146 };
136 147
@@ -138,6 +149,8 @@
138 compatible = "fsl,imx53-esdhc"; 149 compatible = "fsl,imx53-esdhc";
139 reg = <0x50024000 0x4000>; 150 reg = <0x50024000 0x4000>;
140 interrupts = <4>; 151 interrupts = <4>;
152 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
153 clock-names = "ipg", "ahb", "per";
141 status = "disabled"; 154 status = "disabled";
142 }; 155 };
143 }; 156 };
@@ -214,12 +227,14 @@
214 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 227 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
215 reg = <0x53f98000 0x4000>; 228 reg = <0x53f98000 0x4000>;
216 interrupts = <58>; 229 interrupts = <58>;
230 clocks = <&clks 0>;
217 }; 231 };
218 232
219 wdog@53f9c000 { /* WDOG2 */ 233 wdog@53f9c000 { /* WDOG2 */
220 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
221 reg = <0x53f9c000 0x4000>; 235 reg = <0x53f9c000 0x4000>;
222 interrupts = <59>; 236 interrupts = <59>;
237 clocks = <&clks 0>;
223 status = "disabled"; 238 status = "disabled";
224 }; 239 };
225 240
@@ -378,10 +393,30 @@
378 }; 393 };
379 }; 394 };
380 395
396 pwm1: pwm@53fb4000 {
397 #pwm-cells = <2>;
398 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
399 reg = <0x53fb4000 0x4000>;
400 clocks = <&clks 37>, <&clks 38>;
401 clock-names = "ipg", "per";
402 interrupts = <61>;
403 };
404
405 pwm2: pwm@53fb8000 {
406 #pwm-cells = <2>;
407 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
408 reg = <0x53fb8000 0x4000>;
409 clocks = <&clks 39>, <&clks 40>;
410 clock-names = "ipg", "per";
411 interrupts = <94>;
412 };
413
381 uart1: serial@53fbc000 { 414 uart1: serial@53fbc000 {
382 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 415 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
383 reg = <0x53fbc000 0x4000>; 416 reg = <0x53fbc000 0x4000>;
384 interrupts = <31>; 417 interrupts = <31>;
418 clocks = <&clks 28>, <&clks 29>;
419 clock-names = "ipg", "per";
385 status = "disabled"; 420 status = "disabled";
386 }; 421 };
387 422
@@ -389,6 +424,8 @@
389 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 424 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
390 reg = <0x53fc0000 0x4000>; 425 reg = <0x53fc0000 0x4000>;
391 interrupts = <32>; 426 interrupts = <32>;
427 clocks = <&clks 30>, <&clks 31>;
428 clock-names = "ipg", "per";
392 status = "disabled"; 429 status = "disabled";
393 }; 430 };
394 431
@@ -396,6 +433,8 @@
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 433 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fc8000 0x4000>; 434 reg = <0x53fc8000 0x4000>;
398 interrupts = <82>; 435 interrupts = <82>;
436 clocks = <&clks 158>, <&clks 157>;
437 clock-names = "ipg", "per";
399 status = "disabled"; 438 status = "disabled";
400 }; 439 };
401 440
@@ -403,9 +442,18 @@
403 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 442 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
404 reg = <0x53fcc000 0x4000>; 443 reg = <0x53fcc000 0x4000>;
405 interrupts = <83>; 444 interrupts = <83>;
445 clocks = <&clks 158>, <&clks 157>;
446 clock-names = "ipg", "per";
406 status = "disabled"; 447 status = "disabled";
407 }; 448 };
408 449
450 clks: ccm@53fd4000{
451 compatible = "fsl,imx53-ccm";
452 reg = <0x53fd4000 0x4000>;
453 interrupts = <0 71 0x04 0 72 0x04>;
454 #clock-cells = <1>;
455 };
456
409 gpio5: gpio@53fdc000 { 457 gpio5: gpio@53fdc000 {
410 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 458 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
411 reg = <0x53fdc000 0x4000>; 459 reg = <0x53fdc000 0x4000>;
@@ -442,6 +490,7 @@
442 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 490 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
443 reg = <0x53fec000 0x4000>; 491 reg = <0x53fec000 0x4000>;
444 interrupts = <64>; 492 interrupts = <64>;
493 clocks = <&clks 88>;
445 status = "disabled"; 494 status = "disabled";
446 }; 495 };
447 496
@@ -449,6 +498,8 @@
449 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 498 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
450 reg = <0x53ff0000 0x4000>; 499 reg = <0x53ff0000 0x4000>;
451 interrupts = <13>; 500 interrupts = <13>;
501 clocks = <&clks 65>, <&clks 66>;
502 clock-names = "ipg", "per";
452 status = "disabled"; 503 status = "disabled";
453 }; 504 };
454 }; 505 };
@@ -464,6 +515,8 @@
464 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 515 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
465 reg = <0x63f90000 0x4000>; 516 reg = <0x63f90000 0x4000>;
466 interrupts = <86>; 517 interrupts = <86>;
518 clocks = <&clks 67>, <&clks 68>;
519 clock-names = "ipg", "per";
467 status = "disabled"; 520 status = "disabled";
468 }; 521 };
469 522
@@ -473,6 +526,8 @@
473 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 526 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
474 reg = <0x63fac000 0x4000>; 527 reg = <0x63fac000 0x4000>;
475 interrupts = <37>; 528 interrupts = <37>;
529 clocks = <&clks 53>, <&clks 54>;
530 clock-names = "ipg", "per";
476 status = "disabled"; 531 status = "disabled";
477 }; 532 };
478 533
@@ -480,6 +535,8 @@
480 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 535 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
481 reg = <0x63fb0000 0x4000>; 536 reg = <0x63fb0000 0x4000>;
482 interrupts = <6>; 537 interrupts = <6>;
538 clocks = <&clks 56>, <&clks 56>;
539 clock-names = "ipg", "ahb";
483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
484 }; 541 };
485 542
@@ -489,6 +546,8 @@
489 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 546 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
490 reg = <0x63fc0000 0x4000>; 547 reg = <0x63fc0000 0x4000>;
491 interrupts = <38>; 548 interrupts = <38>;
549 clocks = <&clks 55>, <&clks 0>;
550 clock-names = "ipg", "per";
492 status = "disabled"; 551 status = "disabled";
493 }; 552 };
494 553
@@ -498,6 +557,7 @@
498 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 557 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
499 reg = <0x63fc4000 0x4000>; 558 reg = <0x63fc4000 0x4000>;
500 interrupts = <63>; 559 interrupts = <63>;
560 clocks = <&clks 35>;
501 status = "disabled"; 561 status = "disabled";
502 }; 562 };
503 563
@@ -507,6 +567,7 @@
507 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 567 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
508 reg = <0x63fc8000 0x4000>; 568 reg = <0x63fc8000 0x4000>;
509 interrupts = <62>; 569 interrupts = <62>;
570 clocks = <&clks 34>;
510 status = "disabled"; 571 status = "disabled";
511 }; 572 };
512 573
@@ -514,6 +575,7 @@
514 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 575 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
515 reg = <0x63fcc000 0x4000>; 576 reg = <0x63fcc000 0x4000>;
516 interrupts = <29>; 577 interrupts = <29>;
578 clocks = <&clks 48>;
517 fsl,fifo-depth = <15>; 579 fsl,fifo-depth = <15>;
518 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 580 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
519 status = "disabled"; 581 status = "disabled";
@@ -529,6 +591,7 @@
529 compatible = "fsl,imx53-nand"; 591 compatible = "fsl,imx53-nand";
530 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 592 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
531 interrupts = <8>; 593 interrupts = <8>;
594 clocks = <&clks 60>;
532 status = "disabled"; 595 status = "disabled";
533 }; 596 };
534 597
@@ -536,6 +599,7 @@
536 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 599 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
537 reg = <0x63fe8000 0x4000>; 600 reg = <0x63fe8000 0x4000>;
538 interrupts = <96>; 601 interrupts = <96>;
602 clocks = <&clks 50>;
539 fsl,fifo-depth = <15>; 603 fsl,fifo-depth = <15>;
540 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ 604 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
541 status = "disabled"; 605 status = "disabled";
@@ -545,6 +609,8 @@
545 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 609 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
546 reg = <0x63fec000 0x4000>; 610 reg = <0x63fec000 0x4000>;
547 interrupts = <87>; 611 interrupts = <87>;
612 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
613 clock-names = "ipg", "ahb", "ptp";
548 status = "disabled"; 614 status = "disabled";
549 }; 615 };
550 }; 616 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 69fe8f46e3e6..d907d062e5dd 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -268,23 +268,39 @@
268 }; 268 };
269 269
270 pwm@02080000 { /* PWM1 */ 270 pwm@02080000 { /* PWM1 */
271 #pwm-cells = <2>;
272 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
271 reg = <0x02080000 0x4000>; 273 reg = <0x02080000 0x4000>;
272 interrupts = <0 83 0x04>; 274 interrupts = <0 83 0x04>;
275 clocks = <&clks 62>, <&clks 145>;
276 clock-names = "ipg", "per";
273 }; 277 };
274 278
275 pwm@02084000 { /* PWM2 */ 279 pwm@02084000 { /* PWM2 */
280 #pwm-cells = <2>;
281 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
276 reg = <0x02084000 0x4000>; 282 reg = <0x02084000 0x4000>;
277 interrupts = <0 84 0x04>; 283 interrupts = <0 84 0x04>;
284 clocks = <&clks 62>, <&clks 146>;
285 clock-names = "ipg", "per";
278 }; 286 };
279 287
280 pwm@02088000 { /* PWM3 */ 288 pwm@02088000 { /* PWM3 */
289 #pwm-cells = <2>;
290 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
281 reg = <0x02088000 0x4000>; 291 reg = <0x02088000 0x4000>;
282 interrupts = <0 85 0x04>; 292 interrupts = <0 85 0x04>;
293 clocks = <&clks 62>, <&clks 147>;
294 clock-names = "ipg", "per";
283 }; 295 };
284 296
285 pwm@0208c000 { /* PWM4 */ 297 pwm@0208c000 { /* PWM4 */
298 #pwm-cells = <2>;
299 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
286 reg = <0x0208c000 0x4000>; 300 reg = <0x0208c000 0x4000>;
287 interrupts = <0 86 0x04>; 301 interrupts = <0 86 0x04>;
302 clocks = <&clks 62>, <&clks 148>;
303 clock-names = "ipg", "per";
288 }; 304 };
289 305
290 flexcan@02090000 { /* CAN1 */ 306 flexcan@02090000 { /* CAN1 */
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 73b241db63c8..e8c0473c7568 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -87,6 +87,7 @@ enum imx5_clks {
87}; 87};
88 88
89static struct clk *clk[clk_max]; 89static struct clk *clk[clk_max];
90static struct clk_onecell_data clk_data;
90 91
91static void __init mx5_clocks_common_init(unsigned long rate_ckil, 92static void __init mx5_clocks_common_init(unsigned long rate_ckil,
92 unsigned long rate_osc, unsigned long rate_ckih1, 93 unsigned long rate_osc, unsigned long rate_ckih1,
@@ -318,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
318 unsigned long rate_ckih1, unsigned long rate_ckih2) 319 unsigned long rate_ckih1, unsigned long rate_ckih2)
319{ 320{
320 int i; 321 int i;
322 struct device_node *np;
321 323
322 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 324 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
323 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); 325 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -346,6 +348,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
346 pr_err("i.MX51 clk %d: register failed with %ld\n", 348 pr_err("i.MX51 clk %d: register failed with %ld\n",
347 i, PTR_ERR(clk[i])); 349 i, PTR_ERR(clk[i]));
348 350
351 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
352 clk_data.clks = clk;
353 clk_data.clk_num = ARRAY_SIZE(clk);
354 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
355
349 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); 356 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
350 357
351 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); 358 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
@@ -368,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
368 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); 375 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
369 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); 376 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
370 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); 377 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
371 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
372 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
373 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
374 clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
375 378
376 /* set the usboh3 parent to pll2_sw */ 379 /* set the usboh3 parent to pll2_sw */
377 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); 380 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -395,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
395{ 398{
396 int i; 399 int i;
397 unsigned long r; 400 unsigned long r;
401 struct device_node *np;
398 402
399 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 403 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
400 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 404 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -439,6 +443,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
439 pr_err("i.MX53 clk %d: register failed with %ld\n", 443 pr_err("i.MX53 clk %d: register failed with %ld\n",
440 i, PTR_ERR(clk[i])); 444 i, PTR_ERR(clk[i]));
441 445
446 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
447 clk_data.clks = clk;
448 clk_data.clk_num = ARRAY_SIZE(clk);
449 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
450
442 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); 451 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
443 452
444 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); 453 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
@@ -461,15 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
461 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); 470 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
462 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); 471 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
463 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); 472 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
464 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
465 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
466 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
467 clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
468 clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
469 clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
470 clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
471 clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
472 clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
473 473
474 /* set SDHC root clock to 200MHZ*/ 474 /* set SDHC root clock to 200MHZ*/
475 clk_set_rate(clk[esdhc_a_podf], 200000000); 475 clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index a37756c22bb4..448476958e7f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -152,8 +152,9 @@ enum mx6q_clks {
152 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, 152 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
153 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 153 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
154 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 154 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
155 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, 155 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
156 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 156 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
157 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
157 clk_max 158 clk_max
158}; 159};
159 160
@@ -164,6 +165,13 @@ static enum mx6q_clks const clks_init_on[] __initconst = {
164 mmdc_ch0_axi, rom, 165 mmdc_ch0_axi, rom,
165}; 166};
166 167
168static struct clk_div_table clk_enet_ref_table[] = {
169 { .val = 0, .div = 20, },
170 { .val = 1, .div = 10, },
171 { .val = 2, .div = 5, },
172 { .val = 3, .div = 4, },
173};
174
167int __init mx6q_clocks_init(void) 175int __init mx6q_clocks_init(void)
168{ 176{
169 struct device_node *np; 177 struct device_node *np;
@@ -190,19 +198,29 @@ int __init mx6q_clocks_init(void)
190 base = of_iomap(np, 0); 198 base = of_iomap(np, 0);
191 WARN_ON(!base); 199 WARN_ON(!base);
192 200
193 /* type name parent_name base gate_mask div_mask */ 201 /* type name parent_name base div_mask */
194 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f); 202 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
195 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1); 203 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
196 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3); 204 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
197 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f); 205 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
198 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f); 206 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
199 clk[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0); 207 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
200 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); 208 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
201 clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); 209 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
202 210
203 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); 211 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
204 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); 212 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
205 213
214 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
215 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
216
217 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
218 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
219
220 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
221 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
222 &imx_ccm_lock);
223
206 /* name parent_name reg idx */ 224 /* name parent_name reg idx */
207 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 225 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
208 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 226 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
@@ -358,7 +376,7 @@ int __init mx6q_clocks_init(void)
358 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 376 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
359 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 377 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
360 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 378 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
361 clk[mlb] = imx_clk_gate2("mlb", "pll6_mlb", base + 0x74, 18); 379 clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
362 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); 380 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
363 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 381 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
364 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 382 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 36aac947bce1..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
31 * @clk_hw: clock source 31 * @clk_hw: clock source
32 * @base: base address of PLL registers 32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL 33 * @powerup_set: set POWER bit to power up the PLL
34 * @gate_mask: mask of gate bits
35 * @div_mask: mask of divider bits 34 * @div_mask: mask of divider bits
36 * 35 *
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
41 struct clk_hw hw; 40 struct clk_hw hw;
42 void __iomem *base; 41 void __iomem *base;
43 bool powerup_set; 42 bool powerup_set;
44 u32 gate_mask;
45 u32 div_mask; 43 u32 div_mask;
46}; 44};
47 45
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
89 u32 val; 87 u32 val;
90 88
91 val = readl_relaxed(pll->base); 89 val = readl_relaxed(pll->base);
92 val |= pll->gate_mask; 90 val |= BM_PLL_ENABLE;
93 writel_relaxed(val, pll->base); 91 writel_relaxed(val, pll->base);
94 92
95 return 0; 93 return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
101 u32 val; 99 u32 val;
102 100
103 val = readl_relaxed(pll->base); 101 val = readl_relaxed(pll->base);
104 val &= ~pll->gate_mask; 102 val &= ~BM_PLL_ENABLE;
105 writel_relaxed(val, pll->base); 103 writel_relaxed(val, pll->base);
106} 104}
107 105
@@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
287static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 285static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
288 unsigned long parent_rate) 286 unsigned long parent_rate)
289{ 287{
290 struct clk_pllv3 *pll = to_clk_pllv3(hw); 288 return 500000000;
291 u32 div = readl_relaxed(pll->base) & pll->div_mask;
292
293 switch (div) {
294 case 0:
295 return 25000000;
296 case 1:
297 return 50000000;
298 case 2:
299 return 100000000;
300 case 3:
301 return 125000000;
302 }
303
304 return 0;
305}
306
307static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long *prate)
309{
310 if (rate >= 125000000)
311 rate = 125000000;
312 else if (rate >= 100000000)
313 rate = 100000000;
314 else if (rate >= 50000000)
315 rate = 50000000;
316 else
317 rate = 25000000;
318 return rate;
319}
320
321static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
323{
324 struct clk_pllv3 *pll = to_clk_pllv3(hw);
325 u32 val, div;
326
327 switch (rate) {
328 case 25000000:
329 div = 0;
330 break;
331 case 50000000:
332 div = 1;
333 break;
334 case 100000000:
335 div = 2;
336 break;
337 case 125000000:
338 div = 3;
339 break;
340 default:
341 return -EINVAL;
342 }
343
344 val = readl_relaxed(pll->base);
345 val &= ~pll->div_mask;
346 val |= div;
347 writel_relaxed(val, pll->base);
348
349 return 0;
350} 289}
351 290
352static const struct clk_ops clk_pllv3_enet_ops = { 291static const struct clk_ops clk_pllv3_enet_ops = {
@@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
355 .enable = clk_pllv3_enable, 294 .enable = clk_pllv3_enable,
356 .disable = clk_pllv3_disable, 295 .disable = clk_pllv3_disable,
357 .recalc_rate = clk_pllv3_enet_recalc_rate, 296 .recalc_rate = clk_pllv3_enet_recalc_rate,
358 .round_rate = clk_pllv3_enet_round_rate,
359 .set_rate = clk_pllv3_enet_set_rate,
360}; 297};
361 298
362static const struct clk_ops clk_pllv3_mlb_ops = { 299static const struct clk_ops clk_pllv3_mlb_ops = {
@@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
368 305
369struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 306struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
370 const char *parent_name, void __iomem *base, 307 const char *parent_name, void __iomem *base,
371 u32 gate_mask, u32 div_mask) 308 u32 div_mask)
372{ 309{
373 struct clk_pllv3 *pll; 310 struct clk_pllv3 *pll;
374 const struct clk_ops *ops; 311 const struct clk_ops *ops;
@@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
400 ops = &clk_pllv3_ops; 337 ops = &clk_pllv3_ops;
401 } 338 }
402 pll->base = base; 339 pll->base = base;
403 pll->gate_mask = gate_mask;
404 pll->div_mask = div_mask; 340 pll->div_mask = div_mask;
405 341
406 init.name = name; 342 init.name = name;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 5f2d8acca25f..9d1f3b99d1d3 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -22,8 +22,7 @@ enum imx_pllv3_type {
22}; 22};
23 23
24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
25 const char *parent_name, void __iomem *base, u32 gate_mask, 25 const char *parent_name, void __iomem *base, u32 div_mask);
26 u32 div_mask);
27 26
28struct clk *clk_register_gate2(struct device *dev, const char *name, 27struct clk *clk_register_gate2(struct device *dev, const char *name,
29 const char *parent_name, unsigned long flags, 28 const char *parent_name, unsigned long flags,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 50742990a136..5ffa40c673f8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -19,35 +19,9 @@
19#include "common.h" 19#include "common.h"
20#include "mx51.h" 20#include "mx51.h"
21 21
22/*
23 * Lookup table for attaching a specific name and platform_data pointer to
24 * devices as they get created by of_platform_populate(). Ideally this table
25 * would not exist, but the current clock implementation depends on some devices
26 * having a specific name.
27 */
28static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
29 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
30 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
31 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
32 OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
33 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
34 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
35 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
36 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
37 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
38 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
39 OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
40 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
43 OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
44 { /* sentinel */ }
45};
46
47static void __init imx51_dt_init(void) 22static void __init imx51_dt_init(void)
48{ 23{
49 of_platform_populate(NULL, of_default_bus_match_table, 24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
50 imx51_auxdata_lookup, NULL);
51} 25}
52 26
53static void __init imx51_timer_init(void) 27static void __init imx51_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index e71e62610eba..860284dea0e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -23,34 +23,6 @@
23#include "common.h" 23#include "common.h"
24#include "mx53.h" 24#include "mx53.h"
25 25
26/*
27 * Lookup table for attaching a specific name and platform_data pointer to
28 * devices as they get created by of_platform_populate(). Ideally this table
29 * would not exist, but the current clock implementation depends on some devices
30 * having a specific name.
31 */
32static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
33 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
34 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
35 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
36 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
37 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
38 OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
39 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
40 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
41 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
42 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
43 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
44 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
45 OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
46 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
47 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
48 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx21-i2c.2", NULL),
49 OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
50 OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
51 { /* sentinel */ }
52};
53
54static void __init imx53_qsb_init(void) 26static void __init imx53_qsb_init(void)
55{ 27{
56 struct clk *clk; 28 struct clk *clk;
@@ -69,8 +41,7 @@ static void __init imx53_dt_init(void)
69 if (of_machine_is_compatible("fsl,imx53-qsb")) 41 if (of_machine_is_compatible("fsl,imx53-qsb"))
70 imx53_qsb_init(); 42 imx53_qsb_init();
71 43
72 of_platform_populate(NULL, of_default_bus_match_table, 44 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
73 imx53_auxdata_lookup, NULL);
74} 45}
75 46
76static void __init imx53_timer_init(void) 47static void __init imx53_timer_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 05:22:56 -0400