1 files changed, 13 insertions, 13 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 73b241db63c8..e8c0473c7568 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -87,6 +87,7 @@ enum imx5_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
                 unsigned long rate_osc, unsigned long rate_ckih1,
@@ -318,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
         int i;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -346,6 +348,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX51 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
@@ -368,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -395,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 {
         int i;
         unsigned long r;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -439,6 +443,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX53 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
@@ -461,15 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
-        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
-        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
-        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
-        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
-        clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);