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authorTony Lindgren <tony@atomide.com>2013-10-17 13:37:27 -0400
committerTony Lindgren <tony@atomide.com>2013-10-17 13:37:27 -0400
commit811e7c87340b75dce5c488d9496075b00853942b (patch)
tree121b2724c2b8c24f51841ceb6cc9bfe8b488d837
parent254f57a92987b6cde6004f58d6b847813dfb9e0e (diff)
parent70b0d5f5838e0c9dfecabefe4ff43b5a2e7c1e8b (diff)
Merge tag 'for-v3.13/am43xx-support' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod
Add hwmod and PRCM data for the TI AM43xx family of SoCs. Under normal circumstances, these patches would not be merged. The hwmod and PRCM data should be moved out either to DT data or to drivers/. Also, the current implementation trades off lines of diff by dynamically rewriting static data at runtime, which is a bad practice - it causes future maintenance headaches. However, after speaking with my upstream, it sounds like it's better to merge these patches in their current state, due to long term considerations. Basic test logs are here: http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/ Due to the lack of an AM43xx board and any available public documentation, it's impossible for me to review or test that platform in any meaningful way. But at least the tests above verify that the patches don't affect existing platforms - particularly AM33xx.
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile9
-rw-r--r--arch/arm/mach-omap2/clockdomain.h4
-rw-r--r--arch/arm/mach-omap2/clockdomains43xx_data.c196
-rw-r--r--arch/arm/mach-omap2/cm33xx.c16
-rw-r--r--arch/arm/mach-omap2/cm33xx.h12
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c29
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h26
-rw-r--r--arch/arm/mach-omap2/io.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h163
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c643
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c1469
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c1979
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c758
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/powerdomains43xx_data.c136
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h146
18 files changed, 3586 insertions, 2016 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index afb457c3135b..cb7b527d61bd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -112,13 +112,13 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
112obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 112obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
113obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 113obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
114obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o 114obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
115obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o
116omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 115omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
117 prcm_mpu44xx.o prminst44xx.o \ 116 prcm_mpu44xx.o prminst44xx.o \
118 vc44xx_data.o vp44xx_data.o 117 vc44xx_data.o vp44xx_data.o
119obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 118obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
120obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 119obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
121obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) 120obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
121obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)
122 122
123# OMAP voltage domains 123# OMAP voltage domains
124voltagedomain-common := voltage.o vc.o vp.o 124voltagedomain-common := voltage.o vc.o vp.o
@@ -146,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
146obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) 146obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
147obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 147obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
148obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) 148obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
149obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o
149obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 150obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
150obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o 151obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
151obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) 152obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
@@ -165,6 +166,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
165obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) 166obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
166obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 167obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
167obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) 168obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
169obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
168obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 170obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
169obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o 171obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
170obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) 172obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
@@ -210,6 +212,11 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
210obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o 212obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
211obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 213obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
212obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 214obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
215obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o
216obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
217obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
218obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
219obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
213obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 220obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
214obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 221obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
215obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o 222obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 4b03394fa0c5..f17f00697cc0 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -132,7 +132,7 @@ struct clockdomain {
132 u8 _flags; 132 u8 _flags;
133 const u8 dep_bit; 133 const u8 dep_bit;
134 const u8 prcm_partition; 134 const u8 prcm_partition;
135 const s16 cm_inst; 135 const u16 cm_inst;
136 const u16 clkdm_offs; 136 const u16 clkdm_offs;
137 struct clkdm_dep *wkdep_srcs; 137 struct clkdm_dep *wkdep_srcs;
138 struct clkdm_dep *sleepdep_srcs; 138 struct clkdm_dep *sleepdep_srcs;
@@ -218,6 +218,7 @@ extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void); 219extern void __init omap54xx_clockdomains_init(void);
220extern void __init dra7xx_clockdomains_init(void); 220extern void __init dra7xx_clockdomains_init(void);
221void am43xx_clockdomains_init(void);
221 222
222extern void clkdm_add_autodeps(struct clockdomain *clkdm); 223extern void clkdm_add_autodeps(struct clockdomain *clkdm);
223extern void clkdm_del_autodeps(struct clockdomain *clkdm); 224extern void clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_operations;
226extern struct clkdm_ops omap3_clkdm_operations; 227extern struct clkdm_ops omap3_clkdm_operations;
227extern struct clkdm_ops omap4_clkdm_operations; 228extern struct clkdm_ops omap4_clkdm_operations;
228extern struct clkdm_ops am33xx_clkdm_operations; 229extern struct clkdm_ops am33xx_clkdm_operations;
230extern struct clkdm_ops am43xx_clkdm_operations;
229 231
230extern struct clkdm_dep gfx_24xx_wkdeps[]; 232extern struct clkdm_dep gfx_24xx_wkdeps[];
231extern struct clkdm_dep dsp_24xx_wkdeps[]; 233extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
new file mode 100644
index 000000000000..6d71c6082a24
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -0,0 +1,196 @@
1/*
2 * AM43xx Clock domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/io.h>
13
14#include "clockdomain.h"
15#include "prcm44xx.h"
16#include "prcm43xx.h"
17
18static struct clockdomain l4_cefuse_43xx_clkdm = {
19 .name = "l4_cefuse_clkdm",
20 .pwrdm = { .name = "cefuse_pwrdm" },
21 .prcm_partition = AM43XX_CM_PARTITION,
22 .cm_inst = AM43XX_CM_CEFUSE_INST,
23 .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
24 .flags = CLKDM_CAN_SWSUP,
25};
26
27static struct clockdomain mpu_43xx_clkdm = {
28 .name = "mpu_clkdm",
29 .pwrdm = { .name = "mpu_pwrdm" },
30 .prcm_partition = AM43XX_CM_PARTITION,
31 .cm_inst = AM43XX_CM_MPU_INST,
32 .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
33 .flags = CLKDM_CAN_HWSUP_SWSUP,
34};
35
36static struct clockdomain l4ls_43xx_clkdm = {
37 .name = "l4ls_clkdm",
38 .pwrdm = { .name = "per_pwrdm" },
39 .prcm_partition = AM43XX_CM_PARTITION,
40 .cm_inst = AM43XX_CM_PER_INST,
41 .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
42 .flags = CLKDM_CAN_SWSUP,
43};
44
45static struct clockdomain tamper_43xx_clkdm = {
46 .name = "tamper_clkdm",
47 .pwrdm = { .name = "tamper_pwrdm" },
48 .prcm_partition = AM43XX_CM_PARTITION,
49 .cm_inst = AM43XX_CM_TAMPER_INST,
50 .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
51 .flags = CLKDM_CAN_SWSUP,
52};
53
54static struct clockdomain l4_rtc_43xx_clkdm = {
55 .name = "l4_rtc_clkdm",
56 .pwrdm = { .name = "rtc_pwrdm" },
57 .prcm_partition = AM43XX_CM_PARTITION,
58 .cm_inst = AM43XX_CM_RTC_INST,
59 .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
60 .flags = CLKDM_CAN_SWSUP,
61};
62
63static struct clockdomain pruss_ocp_43xx_clkdm = {
64 .name = "pruss_ocp_clkdm",
65 .pwrdm = { .name = "per_pwrdm" },
66 .prcm_partition = AM43XX_CM_PARTITION,
67 .cm_inst = AM43XX_CM_PER_INST,
68 .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
69 .flags = CLKDM_CAN_SWSUP,
70};
71
72static struct clockdomain ocpwp_l3_43xx_clkdm = {
73 .name = "ocpwp_l3_clkdm",
74 .pwrdm = { .name = "per_pwrdm" },
75 .prcm_partition = AM43XX_CM_PARTITION,
76 .cm_inst = AM43XX_CM_PER_INST,
77 .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
78 .flags = CLKDM_CAN_SWSUP,
79};
80
81static struct clockdomain l3s_tsc_43xx_clkdm = {
82 .name = "l3s_tsc_clkdm",
83 .pwrdm = { .name = "wkup_pwrdm" },
84 .prcm_partition = AM43XX_CM_PARTITION,
85 .cm_inst = AM43XX_CM_WKUP_INST,
86 .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
87 .flags = CLKDM_CAN_SWSUP,
88};
89
90static struct clockdomain dss_43xx_clkdm = {
91 .name = "dss_clkdm",
92 .pwrdm = { .name = "per_pwrdm" },
93 .prcm_partition = AM43XX_CM_PARTITION,
94 .cm_inst = AM43XX_CM_PER_INST,
95 .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
96 .flags = CLKDM_CAN_SWSUP,
97};
98
99static struct clockdomain l3_aon_43xx_clkdm = {
100 .name = "l3_aon_clkdm",
101 .pwrdm = { .name = "wkup_pwrdm" },
102 .prcm_partition = AM43XX_CM_PARTITION,
103 .cm_inst = AM43XX_CM_WKUP_INST,
104 .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
105 .flags = CLKDM_CAN_SWSUP,
106};
107
108static struct clockdomain emif_43xx_clkdm = {
109 .name = "emif_clkdm",
110 .pwrdm = { .name = "per_pwrdm" },
111 .prcm_partition = AM43XX_CM_PARTITION,
112 .cm_inst = AM43XX_CM_PER_INST,
113 .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
114 .flags = CLKDM_CAN_SWSUP,
115};
116
117static struct clockdomain l4_wkup_aon_43xx_clkdm = {
118 .name = "l4_wkup_aon_clkdm",
119 .pwrdm = { .name = "wkup_pwrdm" },
120 .prcm_partition = AM43XX_CM_PARTITION,
121 .cm_inst = AM43XX_CM_WKUP_INST,
122 .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
123};
124
125static struct clockdomain l3_43xx_clkdm = {
126 .name = "l3_clkdm",
127 .pwrdm = { .name = "per_pwrdm" },
128 .prcm_partition = AM43XX_CM_PARTITION,
129 .cm_inst = AM43XX_CM_PER_INST,
130 .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
131 .flags = CLKDM_CAN_SWSUP,
132};
133
134static struct clockdomain l4_wkup_43xx_clkdm = {
135 .name = "l4_wkup_clkdm",
136 .pwrdm = { .name = "wkup_pwrdm" },
137 .prcm_partition = AM43XX_CM_PARTITION,
138 .cm_inst = AM43XX_CM_WKUP_INST,
139 .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
140 .flags = CLKDM_CAN_SWSUP,
141};
142
143static struct clockdomain cpsw_125mhz_43xx_clkdm = {
144 .name = "cpsw_125mhz_clkdm",
145 .pwrdm = { .name = "per_pwrdm" },
146 .prcm_partition = AM43XX_CM_PARTITION,
147 .cm_inst = AM43XX_CM_PER_INST,
148 .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
149 .flags = CLKDM_CAN_SWSUP,
150};
151
152static struct clockdomain gfx_l3_43xx_clkdm = {
153 .name = "gfx_l3_clkdm",
154 .pwrdm = { .name = "gfx_pwrdm" },
155 .prcm_partition = AM43XX_CM_PARTITION,
156 .cm_inst = AM43XX_CM_GFX_INST,
157 .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
158 .flags = CLKDM_CAN_SWSUP,
159};
160
161static struct clockdomain l3s_43xx_clkdm = {
162 .name = "l3s_clkdm",
163 .pwrdm = { .name = "per_pwrdm" },
164 .prcm_partition = AM43XX_CM_PARTITION,
165 .cm_inst = AM43XX_CM_PER_INST,
166 .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
167 .flags = CLKDM_CAN_SWSUP,
168};
169
170static struct clockdomain *clockdomains_am43xx[] __initdata = {
171 &l4_cefuse_43xx_clkdm,
172 &mpu_43xx_clkdm,
173 &l4ls_43xx_clkdm,
174 &tamper_43xx_clkdm,
175 &l4_rtc_43xx_clkdm,
176 &pruss_ocp_43xx_clkdm,
177 &ocpwp_l3_43xx_clkdm,
178 &l3s_tsc_43xx_clkdm,
179 &dss_43xx_clkdm,
180 &l3_aon_43xx_clkdm,
181 &emif_43xx_clkdm,
182 &l4_wkup_aon_43xx_clkdm,
183 &l3_43xx_clkdm,
184 &l4_wkup_43xx_clkdm,
185 &cpsw_125mhz_43xx_clkdm,
186 &gfx_l3_43xx_clkdm,
187 &l3s_43xx_clkdm,
188 NULL
189};
190
191void __init am43xx_clockdomains_init(void)
192{
193 clkdm_register_platform_funcs(&am43xx_clkdm_operations);
194 clkdm_register_clkdms(clockdomains_am43xx);
195 clkdm_complete_init();
196}
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 325a51576576..40a22e5649ae 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -48,13 +48,13 @@
48/* Private functions */ 48/* Private functions */
49 49
50/* Read a register in a CM instance */ 50/* Read a register in a CM instance */
51static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) 51static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
52{ 52{
53 return __raw_readl(cm_base + inst + idx); 53 return __raw_readl(cm_base + inst + idx);
54} 54}
55 55
56/* Write into a register in a CM */ 56/* Write into a register in a CM */
57static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) 57static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
58{ 58{
59 __raw_writel(val, cm_base + inst + idx); 59 __raw_writel(val, cm_base + inst + idx);
60} 60}
@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
138 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 138 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
139 * will handle the shift itself. 139 * will handle the shift itself.
140 */ 140 */
141static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) 141static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
142{ 142{
143 u32 v; 143 u32 v;
144 144
@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
158 * Returns true if the clockdomain referred to by (@inst, @cdoffs) 158 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
159 * is in hardware-supervised idle mode, or 0 otherwise. 159 * is in hardware-supervised idle mode, or 0 otherwise.
160 */ 160 */
161bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) 161bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
162{ 162{
163 u32 v; 163 u32 v;
164 164
@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
177 * Put a clockdomain referred to by (@inst, @cdoffs) into 177 * Put a clockdomain referred to by (@inst, @cdoffs) into
178 * hardware-supervised idle mode. No return value. 178 * hardware-supervised idle mode. No return value.
179 */ 179 */
180void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) 180void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
181{ 181{
182 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); 182 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
183} 183}
@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
191 * software-supervised idle mode, i.e., controlled manually by the 191 * software-supervised idle mode, i.e., controlled manually by the
192 * Linux OMAP clockdomain code. No return value. 192 * Linux OMAP clockdomain code. No return value.
193 */ 193 */
194void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) 194void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
195{ 195{
196 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); 196 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
197} 197}
@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
204 * Put a clockdomain referred to by (@inst, @cdoffs) into idle 204 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
205 * No return value. 205 * No return value.
206 */ 206 */
207void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) 207void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
208{ 208{
209 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); 209 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
210} 210}
@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
217 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, 217 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
218 * waking it up. No return value. 218 * waking it up. No return value.
219 */ 219 */
220void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) 220void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
221{ 221{
222 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); 222 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
223} 223}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 9d1f4fcdebbb..cfb8891b0c0e 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -377,13 +377,13 @@
377 377
378 378
379#ifndef __ASSEMBLER__ 379#ifndef __ASSEMBLER__
380extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); 380bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
381extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); 381void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
382extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); 382void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
383extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); 383void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
384extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); 384void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
385 385
386#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 386#ifdef CONFIG_SOC_AM33XX
387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, 387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
388 u16 clkctrl_offs); 388 u16 clkctrl_offs);
389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, 389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f0290f5566fe..731ca134348c 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
111/* Public functions */ 111/* Public functions */
112 112
113/* Read a register in a CM instance */ 113/* Read a register in a CM instance */
114u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) 114u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
115{ 115{
116 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 116 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
117 part == OMAP4430_INVALID_PRCM_PARTITION || 117 part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
120} 120}
121 121
122/* Write into a register in a CM instance */ 122/* Write into a register in a CM instance */
123void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) 123void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
124{ 124{
125 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 125 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
126 part == OMAP4430_INVALID_PRCM_PARTITION || 126 part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -129,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
129} 129}
130 130
131/* Read-modify-write a register in CM1. Caller must lock */ 131/* Read-modify-write a register in CM1. Caller must lock */
132u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 132u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
133 s16 idx) 133 s16 idx)
134{ 134{
135 u32 v; 135 u32 v;
@@ -142,12 +142,12 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
142 return v; 142 return v;
143} 143}
144 144
145u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 145u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
146{ 146{
147 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 147 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
148} 148}
149 149
150u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 150u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
151{ 151{
152 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 152 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
153} 153}
@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
177 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 177 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
178 * will handle the shift itself. 178 * will handle the shift itself.
179 */ 179 */
180static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) 180static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
181{ 181{
182 u32 v; 182 u32 v;
183 183
@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
196 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 196 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
197 * is in hardware-supervised idle mode, or 0 otherwise. 197 * is in hardware-supervised idle mode, or 0 otherwise.
198 */ 198 */
199bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) 199bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
200{ 200{
201 u32 v; 201 u32 v;
202 202
@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
216 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 216 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
217 * hardware-supervised idle mode. No return value. 217 * hardware-supervised idle mode. No return value.
218 */ 218 */
219void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) 219void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
220{ 220{
221 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 221 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
222} 222}
@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
231 * software-supervised idle mode, i.e., controlled manually by the 231 * software-supervised idle mode, i.e., controlled manually by the
232 * Linux OMAP clockdomain code. No return value. 232 * Linux OMAP clockdomain code. No return value.
233 */ 233 */
234void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) 234void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
235{ 235{
236 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 236 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
237} 237}
@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
245 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 245 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
246 * waking it up. No return value. 246 * waking it up. No return value.
247 */ 247 */
248void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) 248void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
249{ 249{
250 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 250 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
251} 251}
@@ -483,3 +483,12 @@ struct clkdm_ops omap4_clkdm_operations = {
483 .clkdm_clk_enable = omap4_clkdm_clk_enable, 483 .clkdm_clk_enable = omap4_clkdm_clk_enable,
484 .clkdm_clk_disable = omap4_clkdm_clk_disable, 484 .clkdm_clk_disable = omap4_clkdm_clk_disable,
485}; 485};
486
487struct clkdm_ops am43xx_clkdm_operations = {
488 .clkdm_sleep = omap4_clkdm_sleep,
489 .clkdm_wakeup = omap4_clkdm_wakeup,
490 .clkdm_allow_idle = omap4_clkdm_allow_idle,
491 .clkdm_deny_idle = omap4_clkdm_deny_idle,
492 .clkdm_clk_enable = omap4_clkdm_clk_enable,
493 .clkdm_clk_disable = omap4_clkdm_clk_disable,
494};
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index bd7bab889745..7f56ea444bc4 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -11,11 +11,11 @@
11#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H 11#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
12#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H 12#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
13 13
14extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); 14bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
15extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); 15void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
16extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); 16void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
17extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); 17void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
18extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); 18void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
19extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); 19extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
20extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, 20extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
21 u16 clkctrl_offs); 21 u16 clkctrl_offs);
@@ -27,14 +27,14 @@ extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
27 * In an ideal world, we would not export these low-level functions, 27 * In an ideal world, we would not export these low-level functions,
28 * but this will probably take some time to fix properly 28 * but this will probably take some time to fix properly
29 */ 29 */
30extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); 30u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
31extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); 31void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
32extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, 32u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
33 s16 inst, s16 idx); 33 u16 inst, s16 idx);
34extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, 34u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
35 s16 idx); 35 s16 idx);
36extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, 36u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
37 s16 idx); 37 s16 idx);
38extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, 38extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
39 u32 mask); 39 u32 mask);
40 40
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113ce4014..c90f64765a3d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -594,7 +594,13 @@ void __init am43xx_init_early(void)
594 NULL); 594 NULL);
595 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); 595 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
596 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); 596 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
597 omap_prm_base_init();
598 omap_cm_base_init();
597 omap3xxx_check_revision(); 599 omap3xxx_check_revision();
600 am43xx_powerdomains_init();
601 am43xx_clockdomains_init();
602 am43xx_hwmod_init();
603 omap_hwmod_init_postsetup();
598} 604}
599#endif 605#endif
600 606
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 1c217e89deb9..e3f0ecaf87dd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4144,6 +4144,14 @@ void __init omap_hwmod_init(void)
4144 soc_ops.init_clkdm = _init_clkdm; 4144 soc_ops.init_clkdm = _init_clkdm;
4145 soc_ops.update_context_lost = _omap4_update_context_lost; 4145 soc_ops.update_context_lost = _omap4_update_context_lost;
4146 soc_ops.get_context_lost = _omap4_get_context_lost; 4146 soc_ops.get_context_lost = _omap4_get_context_lost;
4147 } else if (soc_is_am43xx()) {
4148 soc_ops.enable_module = _omap4_enable_module;
4149 soc_ops.disable_module = _omap4_disable_module;
4150 soc_ops.wait_target_ready = _omap4_wait_target_ready;
4151 soc_ops.assert_hardreset = _omap4_assert_hardreset;
4152 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
4153 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
4154 soc_ops.init_clkdm = _init_clkdm;
4147 } else if (soc_is_am33xx()) { 4155 } else if (soc_is_am33xx()) {
4148 soc_ops.enable_module = _am33xx_enable_module; 4156 soc_ops.enable_module = _am33xx_enable_module;
4149 soc_ops.disable_module = _am33xx_disable_module; 4157 soc_ops.disable_module = _am33xx_disable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d02acf9308d3..0f97d635ff90 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -752,6 +752,7 @@ extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void); 752extern int omap54xx_hwmod_init(void);
753extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
754extern int dra7xx_hwmod_init(void); 754extern int dra7xx_hwmod_init(void);
755int am43xx_hwmod_init(void);
755 756
756extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 757extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
757 758
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
new file mode 100644
index 000000000000..130332c0534d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -0,0 +1,163 @@
1/*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Data common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
18#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
19
20extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main;
21extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s;
22extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls;
23extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup;
24extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
25extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
26extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
27extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
28extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
29extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
30extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
31extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
32extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
33extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio1;
34extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio2;
35extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3;
36extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
37extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
38extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
39extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0;
40extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0;
41extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0;
42extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
43extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1;
44extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1;
45extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1;
46extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
47extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2;
48extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2;
49extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2;
50extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
51extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2;
52extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3;
53extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
54extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
55extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
56extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
57extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0;
58extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1;
59extern struct omap_hwmod_ocp_if am33xx_l3_s__mmc2;
60extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
61extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
62extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
63extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3;
64extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4;
65extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5;
66extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6;
67extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7;
68extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
69extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
70extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
71extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
72extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart2;
73extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart3;
74extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart4;
75extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart5;
76extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6;
77extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
78extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
79extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
80
81extern struct omap_hwmod am33xx_l3_main_hwmod;
82extern struct omap_hwmod am33xx_l3_s_hwmod;
83extern struct omap_hwmod am33xx_l3_instr_hwmod;
84extern struct omap_hwmod am33xx_l4_ls_hwmod;
85extern struct omap_hwmod am33xx_l4_wkup_hwmod;
86extern struct omap_hwmod am33xx_mpu_hwmod;
87extern struct omap_hwmod am33xx_pruss_hwmod;
88extern struct omap_hwmod am33xx_gfx_hwmod;
89extern struct omap_hwmod am33xx_prcm_hwmod;
90extern struct omap_hwmod am33xx_aes0_hwmod;
91extern struct omap_hwmod am33xx_sha0_hwmod;
92extern struct omap_hwmod am33xx_ocmcram_hwmod;
93extern struct omap_hwmod am33xx_smartreflex0_hwmod;
94extern struct omap_hwmod am33xx_smartreflex1_hwmod;
95extern struct omap_hwmod am33xx_cpgmac0_hwmod;
96extern struct omap_hwmod am33xx_mdio_hwmod;
97extern struct omap_hwmod am33xx_dcan0_hwmod;
98extern struct omap_hwmod am33xx_dcan1_hwmod;
99extern struct omap_hwmod am33xx_elm_hwmod;
100extern struct omap_hwmod am33xx_epwmss0_hwmod;
101extern struct omap_hwmod am33xx_ecap0_hwmod;
102extern struct omap_hwmod am33xx_eqep0_hwmod;
103extern struct omap_hwmod am33xx_ehrpwm0_hwmod;
104extern struct omap_hwmod am33xx_epwmss1_hwmod;
105extern struct omap_hwmod am33xx_ecap1_hwmod;
106extern struct omap_hwmod am33xx_eqep1_hwmod;
107extern struct omap_hwmod am33xx_ehrpwm1_hwmod;
108extern struct omap_hwmod am33xx_epwmss2_hwmod;
109extern struct omap_hwmod am33xx_ecap2_hwmod;
110extern struct omap_hwmod am33xx_eqep2_hwmod;
111extern struct omap_hwmod am33xx_ehrpwm2_hwmod;
112extern struct omap_hwmod am33xx_gpio1_hwmod;
113extern struct omap_hwmod am33xx_gpio2_hwmod;
114extern struct omap_hwmod am33xx_gpio3_hwmod;
115extern struct omap_hwmod am33xx_gpmc_hwmod;
116extern struct omap_hwmod am33xx_i2c1_hwmod;
117extern struct omap_hwmod am33xx_i2c2_hwmod;
118extern struct omap_hwmod am33xx_i2c3_hwmod;
119extern struct omap_hwmod am33xx_mailbox_hwmod;
120extern struct omap_hwmod am33xx_mcasp0_hwmod;
121extern struct omap_hwmod am33xx_mcasp1_hwmod;
122extern struct omap_hwmod am33xx_mmc0_hwmod;
123extern struct omap_hwmod am33xx_mmc1_hwmod;
124extern struct omap_hwmod am33xx_mmc2_hwmod;
125extern struct omap_hwmod am33xx_rtc_hwmod;
126extern struct omap_hwmod am33xx_spi0_hwmod;
127extern struct omap_hwmod am33xx_spi1_hwmod;
128extern struct omap_hwmod am33xx_spinlock_hwmod;
129extern struct omap_hwmod am33xx_timer1_hwmod;
130extern struct omap_hwmod am33xx_timer2_hwmod;
131extern struct omap_hwmod am33xx_timer3_hwmod;
132extern struct omap_hwmod am33xx_timer4_hwmod;
133extern struct omap_hwmod am33xx_timer5_hwmod;
134extern struct omap_hwmod am33xx_timer6_hwmod;
135extern struct omap_hwmod am33xx_timer7_hwmod;
136extern struct omap_hwmod am33xx_tpcc_hwmod;
137extern struct omap_hwmod am33xx_tptc0_hwmod;
138extern struct omap_hwmod am33xx_tptc1_hwmod;
139extern struct omap_hwmod am33xx_tptc2_hwmod;
140extern struct omap_hwmod am33xx_uart1_hwmod;
141extern struct omap_hwmod am33xx_uart2_hwmod;
142extern struct omap_hwmod am33xx_uart3_hwmod;
143extern struct omap_hwmod am33xx_uart4_hwmod;
144extern struct omap_hwmod am33xx_uart5_hwmod;
145extern struct omap_hwmod am33xx_uart6_hwmod;
146extern struct omap_hwmod am33xx_wd_timer1_hwmod;
147
148extern struct omap_hwmod_class am33xx_l4_hwmod_class;
149extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
150extern struct omap_hwmod_class am33xx_control_hwmod_class;
151extern struct omap_hwmod_class am33xx_gpio_hwmod_class;
152extern struct omap_hwmod_class am33xx_timer_hwmod_class;
153extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
154extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
155extern struct omap_hwmod_class am33xx_spi_hwmod_class;
156
157extern struct omap_gpio_dev_attr gpio_dev_attr;
158extern struct omap2_mcspi_dev_attr mcspi_attrib;
159
160void omap_hwmod_am33xx_reg(void);
161void omap_hwmod_am43xx_reg(void);
162
163#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
new file mode 100644
index 000000000000..e2db378b849e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -0,0 +1,643 @@
1/*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Interconnects common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/sizes.h>
18#include "omap_hwmod.h"
19#include "omap_hwmod_33xx_43xx_common_data.h"
20
21/* mpu -> l3 main */
22struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
23 .master = &am33xx_mpu_hwmod,
24 .slave = &am33xx_l3_main_hwmod,
25 .clk = "dpll_mpu_m2_ck",
26 .user = OCP_USER_MPU,
27};
28
29/* l3 main -> l3 s */
30struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
31 .master = &am33xx_l3_main_hwmod,
32 .slave = &am33xx_l3_s_hwmod,
33 .clk = "l3s_gclk",
34 .user = OCP_USER_MPU | OCP_USER_SDMA,
35};
36
37/* l3 s -> l4 per/ls */
38struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
39 .master = &am33xx_l3_s_hwmod,
40 .slave = &am33xx_l4_ls_hwmod,
41 .clk = "l3s_gclk",
42 .user = OCP_USER_MPU | OCP_USER_SDMA,
43};
44
45/* l3 s -> l4 wkup */
46struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
47 .master = &am33xx_l3_s_hwmod,
48 .slave = &am33xx_l4_wkup_hwmod,
49 .clk = "l3s_gclk",
50 .user = OCP_USER_MPU | OCP_USER_SDMA,
51};
52
53/* l3 main -> l3 instr */
54struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
55 .master = &am33xx_l3_main_hwmod,
56 .slave = &am33xx_l3_instr_hwmod,
57 .clk = "l3s_gclk",
58 .user = OCP_USER_MPU | OCP_USER_SDMA,
59};
60
61/* mpu -> prcm */
62struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
63 .master = &am33xx_mpu_hwmod,
64 .slave = &am33xx_prcm_hwmod,
65 .clk = "dpll_mpu_m2_ck",
66 .user = OCP_USER_MPU | OCP_USER_SDMA,
67};
68
69/* l3 s -> l3 main*/
70struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
71 .master = &am33xx_l3_s_hwmod,
72 .slave = &am33xx_l3_main_hwmod,
73 .clk = "l3s_gclk",
74 .user = OCP_USER_MPU | OCP_USER_SDMA,
75};
76
77/* pru-icss -> l3 main */
78struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
79 .master = &am33xx_pruss_hwmod,
80 .slave = &am33xx_l3_main_hwmod,
81 .clk = "l3_gclk",
82 .user = OCP_USER_MPU | OCP_USER_SDMA,
83};
84
85/* gfx -> l3 main */
86struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
87 .master = &am33xx_gfx_hwmod,
88 .slave = &am33xx_l3_main_hwmod,
89 .clk = "dpll_core_m4_ck",
90 .user = OCP_USER_MPU | OCP_USER_SDMA,
91};
92
93/* l3 main -> gfx */
94struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
95 .master = &am33xx_l3_main_hwmod,
96 .slave = &am33xx_gfx_hwmod,
97 .clk = "dpll_core_m4_ck",
98 .user = OCP_USER_MPU | OCP_USER_SDMA,
99};
100
101/* l4 wkup -> rtc */
102struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
103 .master = &am33xx_l4_wkup_hwmod,
104 .slave = &am33xx_rtc_hwmod,
105 .clk = "clkdiv32k_ick",
106 .user = OCP_USER_MPU,
107};
108
109/* l4 per/ls -> DCAN0 */
110struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
111 .master = &am33xx_l4_ls_hwmod,
112 .slave = &am33xx_dcan0_hwmod,
113 .clk = "l4ls_gclk",
114 .user = OCP_USER_MPU | OCP_USER_SDMA,
115};
116
117/* l4 per/ls -> DCAN1 */
118struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
119 .master = &am33xx_l4_ls_hwmod,
120 .slave = &am33xx_dcan1_hwmod,
121 .clk = "l4ls_gclk",
122 .user = OCP_USER_MPU | OCP_USER_SDMA,
123};
124
125/* l4 per/ls -> GPIO2 */
126struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
127 .master = &am33xx_l4_ls_hwmod,
128 .slave = &am33xx_gpio1_hwmod,
129 .clk = "l4ls_gclk",
130 .user = OCP_USER_MPU | OCP_USER_SDMA,
131};
132
133/* l4 per/ls -> gpio3 */
134struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
135 .master = &am33xx_l4_ls_hwmod,
136 .slave = &am33xx_gpio2_hwmod,
137 .clk = "l4ls_gclk",
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139};
140
141/* l4 per/ls -> gpio4 */
142struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
143 .master = &am33xx_l4_ls_hwmod,
144 .slave = &am33xx_gpio3_hwmod,
145 .clk = "l4ls_gclk",
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
147};
148
149struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
150 .master = &am33xx_cpgmac0_hwmod,
151 .slave = &am33xx_mdio_hwmod,
152 .user = OCP_USER_MPU,
153};
154
155static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
156 {
157 .pa_start = 0x48080000,
158 .pa_end = 0x48080000 + SZ_8K - 1,
159 .flags = ADDR_TYPE_RT
160 },
161 { }
162};
163
164struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
165 .master = &am33xx_l4_ls_hwmod,
166 .slave = &am33xx_elm_hwmod,
167 .clk = "l4ls_gclk",
168 .addr = am33xx_elm_addr_space,
169 .user = OCP_USER_MPU,
170};
171
172static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
173 {
174 .pa_start = 0x48300000,
175 .pa_end = 0x48300000 + SZ_16 - 1,
176 .flags = ADDR_TYPE_RT
177 },
178 { }
179};
180
181struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
182 .master = &am33xx_l4_ls_hwmod,
183 .slave = &am33xx_epwmss0_hwmod,
184 .clk = "l4ls_gclk",
185 .addr = am33xx_epwmss0_addr_space,
186 .user = OCP_USER_MPU,
187};
188
189struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
190 .master = &am33xx_epwmss0_hwmod,
191 .slave = &am33xx_ecap0_hwmod,
192 .clk = "l4ls_gclk",
193 .user = OCP_USER_MPU,
194};
195
196struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
197 .master = &am33xx_epwmss0_hwmod,
198 .slave = &am33xx_eqep0_hwmod,
199 .clk = "l4ls_gclk",
200 .user = OCP_USER_MPU,
201};
202
203struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
204 .master = &am33xx_epwmss0_hwmod,
205 .slave = &am33xx_ehrpwm0_hwmod,
206 .clk = "l4ls_gclk",
207 .user = OCP_USER_MPU,
208};
209
210
211static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
212 {
213 .pa_start = 0x48302000,
214 .pa_end = 0x48302000 + SZ_16 - 1,
215 .flags = ADDR_TYPE_RT
216 },
217 { }
218};
219
220struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
221 .master = &am33xx_l4_ls_hwmod,
222 .slave = &am33xx_epwmss1_hwmod,
223 .clk = "l4ls_gclk",
224 .addr = am33xx_epwmss1_addr_space,
225 .user = OCP_USER_MPU,
226};
227
228struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
229 .master = &am33xx_epwmss1_hwmod,
230 .slave = &am33xx_ecap1_hwmod,
231 .clk = "l4ls_gclk",
232 .user = OCP_USER_MPU,
233};
234
235struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
236 .master = &am33xx_epwmss1_hwmod,
237 .slave = &am33xx_eqep1_hwmod,
238 .clk = "l4ls_gclk",
239 .user = OCP_USER_MPU,
240};
241
242struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
243 .master = &am33xx_epwmss1_hwmod,
244 .slave = &am33xx_ehrpwm1_hwmod,
245 .clk = "l4ls_gclk",
246 .user = OCP_USER_MPU,
247};
248
249static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
250 {
251 .pa_start = 0x48304000,
252 .pa_end = 0x48304000 + SZ_16 - 1,
253 .flags = ADDR_TYPE_RT
254 },
255 { }
256};
257
258struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
259 .master = &am33xx_l4_ls_hwmod,
260 .slave = &am33xx_epwmss2_hwmod,
261 .clk = "l4ls_gclk",
262 .addr = am33xx_epwmss2_addr_space,
263 .user = OCP_USER_MPU,
264};
265
266struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
267 .master = &am33xx_epwmss2_hwmod,
268 .slave = &am33xx_ecap2_hwmod,
269 .clk = "l4ls_gclk",
270 .user = OCP_USER_MPU,
271};
272
273struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
274 .master = &am33xx_epwmss2_hwmod,
275 .slave = &am33xx_eqep2_hwmod,
276 .clk = "l4ls_gclk",
277 .user = OCP_USER_MPU,
278};
279
280struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
281 .master = &am33xx_epwmss2_hwmod,
282 .slave = &am33xx_ehrpwm2_hwmod,
283 .clk = "l4ls_gclk",
284 .user = OCP_USER_MPU,
285};
286
287/* l3s cfg -> gpmc */
288static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
289 {
290 .pa_start = 0x50000000,
291 .pa_end = 0x50000000 + SZ_8K - 1,
292 .flags = ADDR_TYPE_RT,
293 },
294 { }
295};
296
297struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
298 .master = &am33xx_l3_s_hwmod,
299 .slave = &am33xx_gpmc_hwmod,
300 .clk = "l3s_gclk",
301 .addr = am33xx_gpmc_addr_space,
302 .user = OCP_USER_MPU,
303};
304
305/* i2c2 */
306struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
307 .master = &am33xx_l4_ls_hwmod,
308 .slave = &am33xx_i2c2_hwmod,
309 .clk = "l4ls_gclk",
310 .user = OCP_USER_MPU,
311};
312
313struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
314 .master = &am33xx_l4_ls_hwmod,
315 .slave = &am33xx_i2c3_hwmod,
316 .clk = "l4ls_gclk",
317 .user = OCP_USER_MPU,
318};
319
320static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
321 {
322 .pa_start = 0x480C8000,
323 .pa_end = 0x480C8000 + (SZ_4K - 1),
324 .flags = ADDR_TYPE_RT
325 },
326 { }
327};
328
329/* l4 ls -> mailbox */
330struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
331 .master = &am33xx_l4_ls_hwmod,
332 .slave = &am33xx_mailbox_hwmod,
333 .clk = "l4ls_gclk",
334 .addr = am33xx_mailbox_addrs,
335 .user = OCP_USER_MPU,
336};
337
338/* l4 ls -> spinlock */
339struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
340 .master = &am33xx_l4_ls_hwmod,
341 .slave = &am33xx_spinlock_hwmod,
342 .clk = "l4ls_gclk",
343 .user = OCP_USER_MPU,
344};
345
346/* l4 ls -> mcasp0 */
347static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
348 {
349 .pa_start = 0x48038000,
350 .pa_end = 0x48038000 + SZ_8K - 1,
351 .flags = ADDR_TYPE_RT
352 },
353 { }
354};
355
356struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
357 .master = &am33xx_l4_ls_hwmod,
358 .slave = &am33xx_mcasp0_hwmod,
359 .clk = "l4ls_gclk",
360 .addr = am33xx_mcasp0_addr_space,
361 .user = OCP_USER_MPU,
362};
363
364/* l4 ls -> mcasp1 */
365static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
366 {
367 .pa_start = 0x4803C000,
368 .pa_end = 0x4803C000 + SZ_8K - 1,
369 .flags = ADDR_TYPE_RT
370 },
371 { }
372};
373
374struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
375 .master = &am33xx_l4_ls_hwmod,
376 .slave = &am33xx_mcasp1_hwmod,
377 .clk = "l4ls_gclk",
378 .addr = am33xx_mcasp1_addr_space,
379 .user = OCP_USER_MPU,
380};
381
382/* l4 ls -> mmc0 */
383static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
384 {
385 .pa_start = 0x48060100,
386 .pa_end = 0x48060100 + SZ_4K - 1,
387 .flags = ADDR_TYPE_RT,
388 },
389 { }
390};
391
392struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
393 .master = &am33xx_l4_ls_hwmod,
394 .slave = &am33xx_mmc0_hwmod,
395 .clk = "l4ls_gclk",
396 .addr = am33xx_mmc0_addr_space,
397 .user = OCP_USER_MPU,
398};
399
400/* l4 ls -> mmc1 */
401static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
402 {
403 .pa_start = 0x481d8100,
404 .pa_end = 0x481d8100 + SZ_4K - 1,
405 .flags = ADDR_TYPE_RT,
406 },
407 { }
408};
409
410struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
411 .master = &am33xx_l4_ls_hwmod,
412 .slave = &am33xx_mmc1_hwmod,
413 .clk = "l4ls_gclk",
414 .addr = am33xx_mmc1_addr_space,
415 .user = OCP_USER_MPU,
416};
417
418/* l3 s -> mmc2 */
419static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
420 {
421 .pa_start = 0x47810100,
422 .pa_end = 0x47810100 + SZ_64K - 1,
423 .flags = ADDR_TYPE_RT,
424 },
425 { }
426};
427
428struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
429 .master = &am33xx_l3_s_hwmod,
430 .slave = &am33xx_mmc2_hwmod,
431 .clk = "l3s_gclk",
432 .addr = am33xx_mmc2_addr_space,
433 .user = OCP_USER_MPU,
434};
435
436/* l4 ls -> mcspi0 */
437struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
438 .master = &am33xx_l4_ls_hwmod,
439 .slave = &am33xx_spi0_hwmod,
440 .clk = "l4ls_gclk",
441 .user = OCP_USER_MPU,
442};
443
444/* l4 ls -> mcspi1 */
445struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
446 .master = &am33xx_l4_ls_hwmod,
447 .slave = &am33xx_spi1_hwmod,
448 .clk = "l4ls_gclk",
449 .user = OCP_USER_MPU,
450};
451
452/* l4 per -> timer2 */
453struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
454 .master = &am33xx_l4_ls_hwmod,
455 .slave = &am33xx_timer2_hwmod,
456 .clk = "l4ls_gclk",
457 .user = OCP_USER_MPU,
458};
459
460/* l4 per -> timer3 */
461struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
462 .master = &am33xx_l4_ls_hwmod,
463 .slave = &am33xx_timer3_hwmod,
464 .clk = "l4ls_gclk",
465 .user = OCP_USER_MPU,
466};
467
468/* l4 per -> timer4 */
469struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
470 .master = &am33xx_l4_ls_hwmod,
471 .slave = &am33xx_timer4_hwmod,
472 .clk = "l4ls_gclk",
473 .user = OCP_USER_MPU,
474};
475
476/* l4 per -> timer5 */
477struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
478 .master = &am33xx_l4_ls_hwmod,
479 .slave = &am33xx_timer5_hwmod,
480 .clk = "l4ls_gclk",
481 .user = OCP_USER_MPU,
482};
483
484/* l4 per -> timer6 */
485struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
486 .master = &am33xx_l4_ls_hwmod,
487 .slave = &am33xx_timer6_hwmod,
488 .clk = "l4ls_gclk",
489 .user = OCP_USER_MPU,
490};
491
492/* l4 per -> timer7 */
493struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
494 .master = &am33xx_l4_ls_hwmod,
495 .slave = &am33xx_timer7_hwmod,
496 .clk = "l4ls_gclk",
497 .user = OCP_USER_MPU,
498};
499
500/* l3 main -> tpcc */
501struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
502 .master = &am33xx_l3_main_hwmod,
503 .slave = &am33xx_tpcc_hwmod,
504 .clk = "l3_gclk",
505 .user = OCP_USER_MPU,
506};
507
508/* l3 main -> tpcc0 */
509static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
510 {
511 .pa_start = 0x49800000,
512 .pa_end = 0x49800000 + SZ_8K - 1,
513 .flags = ADDR_TYPE_RT,
514 },
515 { }
516};
517
518struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
519 .master = &am33xx_l3_main_hwmod,
520 .slave = &am33xx_tptc0_hwmod,
521 .clk = "l3_gclk",
522 .addr = am33xx_tptc0_addr_space,
523 .user = OCP_USER_MPU,
524};
525
526/* l3 main -> tpcc1 */
527static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
528 {
529 .pa_start = 0x49900000,
530 .pa_end = 0x49900000 + SZ_8K - 1,
531 .flags = ADDR_TYPE_RT,
532 },
533 { }
534};
535
536struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
537 .master = &am33xx_l3_main_hwmod,
538 .slave = &am33xx_tptc1_hwmod,
539 .clk = "l3_gclk",
540 .addr = am33xx_tptc1_addr_space,
541 .user = OCP_USER_MPU,
542};
543
544/* l3 main -> tpcc2 */
545static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
546 {
547 .pa_start = 0x49a00000,
548 .pa_end = 0x49a00000 + SZ_8K - 1,
549 .flags = ADDR_TYPE_RT,
550 },
551 { }
552};
553
554struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
555 .master = &am33xx_l3_main_hwmod,
556 .slave = &am33xx_tptc2_hwmod,
557 .clk = "l3_gclk",
558 .addr = am33xx_tptc2_addr_space,
559 .user = OCP_USER_MPU,
560};
561
562/* l4 ls -> uart2 */
563struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
564 .master = &am33xx_l4_ls_hwmod,
565 .slave = &am33xx_uart2_hwmod,
566 .clk = "l4ls_gclk",
567 .user = OCP_USER_MPU,
568};
569
570/* l4 ls -> uart3 */
571struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
572 .master = &am33xx_l4_ls_hwmod,
573 .slave = &am33xx_uart3_hwmod,
574 .clk = "l4ls_gclk",
575 .user = OCP_USER_MPU,
576};
577
578/* l4 ls -> uart4 */
579struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
580 .master = &am33xx_l4_ls_hwmod,
581 .slave = &am33xx_uart4_hwmod,
582 .clk = "l4ls_gclk",
583 .user = OCP_USER_MPU,
584};
585
586/* l4 ls -> uart5 */
587struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
588 .master = &am33xx_l4_ls_hwmod,
589 .slave = &am33xx_uart5_hwmod,
590 .clk = "l4ls_gclk",
591 .user = OCP_USER_MPU,
592};
593
594/* l4 ls -> uart6 */
595struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
596 .master = &am33xx_l4_ls_hwmod,
597 .slave = &am33xx_uart6_hwmod,
598 .clk = "l4ls_gclk",
599 .user = OCP_USER_MPU,
600};
601
602/* l3 main -> ocmc */
603struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
604 .master = &am33xx_l3_main_hwmod,
605 .slave = &am33xx_ocmcram_hwmod,
606 .user = OCP_USER_MPU | OCP_USER_SDMA,
607};
608
609/* l3 main -> sha0 HIB2 */
610static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
611 {
612 .pa_start = 0x53100000,
613 .pa_end = 0x53100000 + SZ_512 - 1,
614 .flags = ADDR_TYPE_RT
615 },
616 { }
617};
618
619struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
620 .master = &am33xx_l3_main_hwmod,
621 .slave = &am33xx_sha0_hwmod,
622 .clk = "sha0_fck",
623 .addr = am33xx_sha0_addrs,
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* l3 main -> AES0 HIB2 */
628static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
629 {
630 .pa_start = 0x53500000,
631 .pa_end = 0x53500000 + SZ_1M - 1,
632 .flags = ADDR_TYPE_RT
633 },
634 { }
635};
636
637struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
638 .master = &am33xx_l3_main_hwmod,
639 .slave = &am33xx_aes0_hwmod,
640 .clk = "aes0_fck",
641 .addr = am33xx_aes0_addrs,
642 .user = OCP_USER_MPU | OCP_USER_SDMA,
643};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
new file mode 100644
index 000000000000..0f178623e7da
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -0,0 +1,1469 @@
1/*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Hwmod common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "i2c.h"
21#include "mmc.h"
22#include "wd_timer.h"
23#include "cm33xx.h"
24#include "prm33xx.h"
25#include "omap_hwmod_33xx_43xx_common_data.h"
26#include "prcm43xx.h"
27
28#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
29#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
30#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
31
32/*
33 * 'l3' class
34 * instance(s): l3_main, l3_s, l3_instr
35 */
36static struct omap_hwmod_class am33xx_l3_hwmod_class = {
37 .name = "l3",
38};
39
40struct omap_hwmod am33xx_l3_main_hwmod = {
41 .name = "l3_main",
42 .class = &am33xx_l3_hwmod_class,
43 .clkdm_name = "l3_clkdm",
44 .flags = HWMOD_INIT_NO_IDLE,
45 .main_clk = "l3_gclk",
46 .prcm = {
47 .omap4 = {
48 .modulemode = MODULEMODE_SWCTRL,
49 },
50 },
51};
52
53/* l3_s */
54struct omap_hwmod am33xx_l3_s_hwmod = {
55 .name = "l3_s",
56 .class = &am33xx_l3_hwmod_class,
57 .clkdm_name = "l3s_clkdm",
58};
59
60/* l3_instr */
61struct omap_hwmod am33xx_l3_instr_hwmod = {
62 .name = "l3_instr",
63 .class = &am33xx_l3_hwmod_class,
64 .clkdm_name = "l3_clkdm",
65 .flags = HWMOD_INIT_NO_IDLE,
66 .main_clk = "l3_gclk",
67 .prcm = {
68 .omap4 = {
69 .modulemode = MODULEMODE_SWCTRL,
70 },
71 },
72};
73
74/*
75 * 'l4' class
76 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
77 */
78struct omap_hwmod_class am33xx_l4_hwmod_class = {
79 .name = "l4",
80};
81
82/* l4_ls */
83struct omap_hwmod am33xx_l4_ls_hwmod = {
84 .name = "l4_ls",
85 .class = &am33xx_l4_hwmod_class,
86 .clkdm_name = "l4ls_clkdm",
87 .flags = HWMOD_INIT_NO_IDLE,
88 .main_clk = "l4ls_gclk",
89 .prcm = {
90 .omap4 = {
91 .modulemode = MODULEMODE_SWCTRL,
92 },
93 },
94};
95
96/* l4_wkup */
97struct omap_hwmod am33xx_l4_wkup_hwmod = {
98 .name = "l4_wkup",
99 .class = &am33xx_l4_hwmod_class,
100 .clkdm_name = "l4_wkup_clkdm",
101 .flags = HWMOD_INIT_NO_IDLE,
102 .prcm = {
103 .omap4 = {
104 .modulemode = MODULEMODE_SWCTRL,
105 },
106 },
107};
108
109/*
110 * 'mpu' class
111 */
112static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
113 .name = "mpu",
114};
115
116struct omap_hwmod am33xx_mpu_hwmod = {
117 .name = "mpu",
118 .class = &am33xx_mpu_hwmod_class,
119 .clkdm_name = "mpu_clkdm",
120 .flags = HWMOD_INIT_NO_IDLE,
121 .main_clk = "dpll_mpu_m2_ck",
122 .prcm = {
123 .omap4 = {
124 .modulemode = MODULEMODE_SWCTRL,
125 },
126 },
127};
128
129/*
130 * 'wakeup m3' class
131 * Wakeup controller sub-system under wakeup domain
132 */
133struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
134 .name = "wkup_m3",
135};
136
137/*
138 * 'pru-icss' class
139 * Programmable Real-Time Unit and Industrial Communication Subsystem
140 */
141static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
142 .name = "pruss",
143};
144
145static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
146 { .name = "pruss", .rst_shift = 1 },
147};
148
149/* pru-icss */
150/* Pseudo hwmod for reset control purpose only */
151struct omap_hwmod am33xx_pruss_hwmod = {
152 .name = "pruss",
153 .class = &am33xx_pruss_hwmod_class,
154 .clkdm_name = "pruss_ocp_clkdm",
155 .main_clk = "pruss_ocp_gclk",
156 .prcm = {
157 .omap4 = {
158 .modulemode = MODULEMODE_SWCTRL,
159 },
160 },
161 .rst_lines = am33xx_pruss_resets,
162 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
163};
164
165/* gfx */
166/* Pseudo hwmod for reset control purpose only */
167static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
168 .name = "gfx",
169};
170
171static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
172 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
173};
174
175struct omap_hwmod am33xx_gfx_hwmod = {
176 .name = "gfx",
177 .class = &am33xx_gfx_hwmod_class,
178 .clkdm_name = "gfx_l3_clkdm",
179 .main_clk = "gfx_fck_div_ck",
180 .prcm = {
181 .omap4 = {
182 .modulemode = MODULEMODE_SWCTRL,
183 },
184 },
185 .rst_lines = am33xx_gfx_resets,
186 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
187};
188
189/*
190 * 'prcm' class
191 * power and reset manager (whole prcm infrastructure)
192 */
193static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
194 .name = "prcm",
195};
196
197/* prcm */
198struct omap_hwmod am33xx_prcm_hwmod = {
199 .name = "prcm",
200 .class = &am33xx_prcm_hwmod_class,
201 .clkdm_name = "l4_wkup_clkdm",
202};
203
204/*
205 * 'aes0' class
206 */
207static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
208 .rev_offs = 0x80,
209 .sysc_offs = 0x84,
210 .syss_offs = 0x88,
211 .sysc_flags = SYSS_HAS_RESET_STATUS,
212};
213
214static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
215 .name = "aes0",
216 .sysc = &am33xx_aes0_sysc,
217};
218
219struct omap_hwmod am33xx_aes0_hwmod = {
220 .name = "aes",
221 .class = &am33xx_aes0_hwmod_class,
222 .clkdm_name = "l3_clkdm",
223 .main_clk = "aes0_fck",
224 .prcm = {
225 .omap4 = {
226 .modulemode = MODULEMODE_SWCTRL,
227 },
228 },
229};
230
231/* sha0 HIB2 (the 'P' (public) device) */
232static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
233 .rev_offs = 0x100,
234 .sysc_offs = 0x110,
235 .syss_offs = 0x114,
236 .sysc_flags = SYSS_HAS_RESET_STATUS,
237};
238
239static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
240 .name = "sha0",
241 .sysc = &am33xx_sha0_sysc,
242};
243
244struct omap_hwmod am33xx_sha0_hwmod = {
245 .name = "sham",
246 .class = &am33xx_sha0_hwmod_class,
247 .clkdm_name = "l3_clkdm",
248 .main_clk = "l3_gclk",
249 .prcm = {
250 .omap4 = {
251 .modulemode = MODULEMODE_SWCTRL,
252 },
253 },
254};
255
256/* ocmcram */
257static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
258 .name = "ocmcram",
259};
260
261struct omap_hwmod am33xx_ocmcram_hwmod = {
262 .name = "ocmcram",
263 .class = &am33xx_ocmcram_hwmod_class,
264 .clkdm_name = "l3_clkdm",
265 .flags = HWMOD_INIT_NO_IDLE,
266 .main_clk = "l3_gclk",
267 .prcm = {
268 .omap4 = {
269 .modulemode = MODULEMODE_SWCTRL,
270 },
271 },
272};
273
274/* 'smartreflex' class */
275static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
276 .name = "smartreflex",
277};
278
279/* smartreflex0 */
280struct omap_hwmod am33xx_smartreflex0_hwmod = {
281 .name = "smartreflex0",
282 .class = &am33xx_smartreflex_hwmod_class,
283 .clkdm_name = "l4_wkup_clkdm",
284 .main_clk = "smartreflex0_fck",
285 .prcm = {
286 .omap4 = {
287 .modulemode = MODULEMODE_SWCTRL,
288 },
289 },
290};
291
292/* smartreflex1 */
293struct omap_hwmod am33xx_smartreflex1_hwmod = {
294 .name = "smartreflex1",
295 .class = &am33xx_smartreflex_hwmod_class,
296 .clkdm_name = "l4_wkup_clkdm",
297 .main_clk = "smartreflex1_fck",
298 .prcm = {
299 .omap4 = {
300 .modulemode = MODULEMODE_SWCTRL,
301 },
302 },
303};
304
305/*
306 * 'control' module class
307 */
308struct omap_hwmod_class am33xx_control_hwmod_class = {
309 .name = "control",
310};
311
312/*
313 * 'cpgmac' class
314 * cpsw/cpgmac sub system
315 */
316static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
317 .rev_offs = 0x0,
318 .sysc_offs = 0x8,
319 .syss_offs = 0x4,
320 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
321 SYSS_HAS_RESET_STATUS),
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
323 MSTANDBY_NO),
324 .sysc_fields = &omap_hwmod_sysc_type3,
325};
326
327static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
328 .name = "cpgmac0",
329 .sysc = &am33xx_cpgmac_sysc,
330};
331
332struct omap_hwmod am33xx_cpgmac0_hwmod = {
333 .name = "cpgmac0",
334 .class = &am33xx_cpgmac0_hwmod_class,
335 .clkdm_name = "cpsw_125mhz_clkdm",
336 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
337 .main_clk = "cpsw_125mhz_gclk",
338 .mpu_rt_idx = 1,
339 .prcm = {
340 .omap4 = {
341 .modulemode = MODULEMODE_SWCTRL,
342 },
343 },
344};
345
346/*
347 * mdio class
348 */
349static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
350 .name = "davinci_mdio",
351};
352
353struct omap_hwmod am33xx_mdio_hwmod = {
354 .name = "davinci_mdio",
355 .class = &am33xx_mdio_hwmod_class,
356 .clkdm_name = "cpsw_125mhz_clkdm",
357 .main_clk = "cpsw_125mhz_gclk",
358};
359
360/*
361 * dcan class
362 */
363static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
364 .name = "d_can",
365};
366
367/* dcan0 */
368struct omap_hwmod am33xx_dcan0_hwmod = {
369 .name = "d_can0",
370 .class = &am33xx_dcan_hwmod_class,
371 .clkdm_name = "l4ls_clkdm",
372 .main_clk = "dcan0_fck",
373 .prcm = {
374 .omap4 = {
375 .modulemode = MODULEMODE_SWCTRL,
376 },
377 },
378};
379
380/* dcan1 */
381struct omap_hwmod am33xx_dcan1_hwmod = {
382 .name = "d_can1",
383 .class = &am33xx_dcan_hwmod_class,
384 .clkdm_name = "l4ls_clkdm",
385 .main_clk = "dcan1_fck",
386 .prcm = {
387 .omap4 = {
388 .modulemode = MODULEMODE_SWCTRL,
389 },
390 },
391};
392
393/* elm */
394static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
395 .rev_offs = 0x0000,
396 .sysc_offs = 0x0010,
397 .syss_offs = 0x0014,
398 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
399 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
400 SYSS_HAS_RESET_STATUS),
401 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403};
404
405static struct omap_hwmod_class am33xx_elm_hwmod_class = {
406 .name = "elm",
407 .sysc = &am33xx_elm_sysc,
408};
409
410struct omap_hwmod am33xx_elm_hwmod = {
411 .name = "elm",
412 .class = &am33xx_elm_hwmod_class,
413 .clkdm_name = "l4ls_clkdm",
414 .main_clk = "l4ls_gclk",
415 .prcm = {
416 .omap4 = {
417 .modulemode = MODULEMODE_SWCTRL,
418 },
419 },
420};
421
422/* pwmss */
423static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
424 .rev_offs = 0x0,
425 .sysc_offs = 0x4,
426 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
427 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
428 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
429 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
430 .sysc_fields = &omap_hwmod_sysc_type2,
431};
432
433struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
434 .name = "epwmss",
435 .sysc = &am33xx_epwmss_sysc,
436};
437
438static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
439 .name = "ecap",
440};
441
442static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
443 .name = "eqep",
444};
445
446struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
447 .name = "ehrpwm",
448};
449
450/* epwmss0 */
451struct omap_hwmod am33xx_epwmss0_hwmod = {
452 .name = "epwmss0",
453 .class = &am33xx_epwmss_hwmod_class,
454 .clkdm_name = "l4ls_clkdm",
455 .main_clk = "l4ls_gclk",
456 .prcm = {
457 .omap4 = {
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461};
462
463/* ecap0 */
464struct omap_hwmod am33xx_ecap0_hwmod = {
465 .name = "ecap0",
466 .class = &am33xx_ecap_hwmod_class,
467 .clkdm_name = "l4ls_clkdm",
468 .main_clk = "l4ls_gclk",
469};
470
471/* eqep0 */
472struct omap_hwmod am33xx_eqep0_hwmod = {
473 .name = "eqep0",
474 .class = &am33xx_eqep_hwmod_class,
475 .clkdm_name = "l4ls_clkdm",
476 .main_clk = "l4ls_gclk",
477};
478
479/* ehrpwm0 */
480struct omap_hwmod am33xx_ehrpwm0_hwmod = {
481 .name = "ehrpwm0",
482 .class = &am33xx_ehrpwm_hwmod_class,
483 .clkdm_name = "l4ls_clkdm",
484 .main_clk = "l4ls_gclk",
485};
486
487/* epwmss1 */
488struct omap_hwmod am33xx_epwmss1_hwmod = {
489 .name = "epwmss1",
490 .class = &am33xx_epwmss_hwmod_class,
491 .clkdm_name = "l4ls_clkdm",
492 .main_clk = "l4ls_gclk",
493 .prcm = {
494 .omap4 = {
495 .modulemode = MODULEMODE_SWCTRL,
496 },
497 },
498};
499
500/* ecap1 */
501struct omap_hwmod am33xx_ecap1_hwmod = {
502 .name = "ecap1",
503 .class = &am33xx_ecap_hwmod_class,
504 .clkdm_name = "l4ls_clkdm",
505 .main_clk = "l4ls_gclk",
506};
507
508/* eqep1 */
509struct omap_hwmod am33xx_eqep1_hwmod = {
510 .name = "eqep1",
511 .class = &am33xx_eqep_hwmod_class,
512 .clkdm_name = "l4ls_clkdm",
513 .main_clk = "l4ls_gclk",
514};
515
516/* ehrpwm1 */
517struct omap_hwmod am33xx_ehrpwm1_hwmod = {
518 .name = "ehrpwm1",
519 .class = &am33xx_ehrpwm_hwmod_class,
520 .clkdm_name = "l4ls_clkdm",
521 .main_clk = "l4ls_gclk",
522};
523
524/* epwmss2 */
525struct omap_hwmod am33xx_epwmss2_hwmod = {
526 .name = "epwmss2",
527 .class = &am33xx_epwmss_hwmod_class,
528 .clkdm_name = "l4ls_clkdm",
529 .main_clk = "l4ls_gclk",
530 .prcm = {
531 .omap4 = {
532 .modulemode = MODULEMODE_SWCTRL,
533 },
534 },
535};
536
537/* ecap2 */
538struct omap_hwmod am33xx_ecap2_hwmod = {
539 .name = "ecap2",
540 .class = &am33xx_ecap_hwmod_class,
541 .clkdm_name = "l4ls_clkdm",
542 .main_clk = "l4ls_gclk",
543};
544
545/* eqep2 */
546struct omap_hwmod am33xx_eqep2_hwmod = {
547 .name = "eqep2",
548 .class = &am33xx_eqep_hwmod_class,
549 .clkdm_name = "l4ls_clkdm",
550 .main_clk = "l4ls_gclk",
551};
552
553/* ehrpwm2 */
554struct omap_hwmod am33xx_ehrpwm2_hwmod = {
555 .name = "ehrpwm2",
556 .class = &am33xx_ehrpwm_hwmod_class,
557 .clkdm_name = "l4ls_clkdm",
558 .main_clk = "l4ls_gclk",
559};
560
561/*
562 * 'gpio' class: for gpio 0,1,2,3
563 */
564static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
565 .rev_offs = 0x0000,
566 .sysc_offs = 0x0010,
567 .syss_offs = 0x0114,
568 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
569 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
570 SYSS_HAS_RESET_STATUS),
571 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
572 SIDLE_SMART_WKUP),
573 .sysc_fields = &omap_hwmod_sysc_type1,
574};
575
576struct omap_hwmod_class am33xx_gpio_hwmod_class = {
577 .name = "gpio",
578 .sysc = &am33xx_gpio_sysc,
579 .rev = 2,
580};
581
582struct omap_gpio_dev_attr gpio_dev_attr = {
583 .bank_width = 32,
584 .dbck_flag = true,
585};
586
587/* gpio1 */
588static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
589 { .role = "dbclk", .clk = "gpio1_dbclk" },
590};
591
592struct omap_hwmod am33xx_gpio1_hwmod = {
593 .name = "gpio2",
594 .class = &am33xx_gpio_hwmod_class,
595 .clkdm_name = "l4ls_clkdm",
596 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
597 .main_clk = "l4ls_gclk",
598 .prcm = {
599 .omap4 = {
600 .modulemode = MODULEMODE_SWCTRL,
601 },
602 },
603 .opt_clks = gpio1_opt_clks,
604 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
605 .dev_attr = &gpio_dev_attr,
606};
607
608/* gpio2 */
609static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
610 { .role = "dbclk", .clk = "gpio2_dbclk" },
611};
612
613struct omap_hwmod am33xx_gpio2_hwmod = {
614 .name = "gpio3",
615 .class = &am33xx_gpio_hwmod_class,
616 .clkdm_name = "l4ls_clkdm",
617 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
618 .main_clk = "l4ls_gclk",
619 .prcm = {
620 .omap4 = {
621 .modulemode = MODULEMODE_SWCTRL,
622 },
623 },
624 .opt_clks = gpio2_opt_clks,
625 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
626 .dev_attr = &gpio_dev_attr,
627};
628
629/* gpio3 */
630static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
631 { .role = "dbclk", .clk = "gpio3_dbclk" },
632};
633
634struct omap_hwmod am33xx_gpio3_hwmod = {
635 .name = "gpio4",
636 .class = &am33xx_gpio_hwmod_class,
637 .clkdm_name = "l4ls_clkdm",
638 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
639 .main_clk = "l4ls_gclk",
640 .prcm = {
641 .omap4 = {
642 .modulemode = MODULEMODE_SWCTRL,
643 },
644 },
645 .opt_clks = gpio3_opt_clks,
646 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
647 .dev_attr = &gpio_dev_attr,
648};
649
650/* gpmc */
651static struct omap_hwmod_class_sysconfig gpmc_sysc = {
652 .rev_offs = 0x0,
653 .sysc_offs = 0x10,
654 .syss_offs = 0x14,
655 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
656 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
657 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
658 .sysc_fields = &omap_hwmod_sysc_type1,
659};
660
661static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
662 .name = "gpmc",
663 .sysc = &gpmc_sysc,
664};
665
666struct omap_hwmod am33xx_gpmc_hwmod = {
667 .name = "gpmc",
668 .class = &am33xx_gpmc_hwmod_class,
669 .clkdm_name = "l3s_clkdm",
670 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
671 .main_clk = "l3s_gclk",
672 .prcm = {
673 .omap4 = {
674 .modulemode = MODULEMODE_SWCTRL,
675 },
676 },
677};
678
679/* 'i2c' class */
680static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
681 .sysc_offs = 0x0010,
682 .syss_offs = 0x0090,
683 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
684 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
685 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
686 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
687 SIDLE_SMART_WKUP),
688 .sysc_fields = &omap_hwmod_sysc_type1,
689};
690
691static struct omap_hwmod_class i2c_class = {
692 .name = "i2c",
693 .sysc = &am33xx_i2c_sysc,
694 .rev = OMAP_I2C_IP_VERSION_2,
695 .reset = &omap_i2c_reset,
696};
697
698static struct omap_i2c_dev_attr i2c_dev_attr = {
699 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
700};
701
702/* i2c1 */
703struct omap_hwmod am33xx_i2c1_hwmod = {
704 .name = "i2c1",
705 .class = &i2c_class,
706 .clkdm_name = "l4_wkup_clkdm",
707 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
708 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
709 .prcm = {
710 .omap4 = {
711 .modulemode = MODULEMODE_SWCTRL,
712 },
713 },
714 .dev_attr = &i2c_dev_attr,
715};
716
717/* i2c1 */
718struct omap_hwmod am33xx_i2c2_hwmod = {
719 .name = "i2c2",
720 .class = &i2c_class,
721 .clkdm_name = "l4ls_clkdm",
722 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
723 .main_clk = "dpll_per_m2_div4_ck",
724 .prcm = {
725 .omap4 = {
726 .modulemode = MODULEMODE_SWCTRL,
727 },
728 },
729 .dev_attr = &i2c_dev_attr,
730};
731
732/* i2c3 */
733struct omap_hwmod am33xx_i2c3_hwmod = {
734 .name = "i2c3",
735 .class = &i2c_class,
736 .clkdm_name = "l4ls_clkdm",
737 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
738 .main_clk = "dpll_per_m2_div4_ck",
739 .prcm = {
740 .omap4 = {
741 .modulemode = MODULEMODE_SWCTRL,
742 },
743 },
744 .dev_attr = &i2c_dev_attr,
745};
746
747/*
748 * 'mailbox' class
749 * mailbox module allowing communication between the on-chip processors using a
750 * queued mailbox-interrupt mechanism.
751 */
752static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
753 .rev_offs = 0x0000,
754 .sysc_offs = 0x0010,
755 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
756 SYSC_HAS_SOFTRESET),
757 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
758 .sysc_fields = &omap_hwmod_sysc_type2,
759};
760
761static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
762 .name = "mailbox",
763 .sysc = &am33xx_mailbox_sysc,
764};
765
766struct omap_hwmod am33xx_mailbox_hwmod = {
767 .name = "mailbox",
768 .class = &am33xx_mailbox_hwmod_class,
769 .clkdm_name = "l4ls_clkdm",
770 .main_clk = "l4ls_gclk",
771 .prcm = {
772 .omap4 = {
773 .modulemode = MODULEMODE_SWCTRL,
774 },
775 },
776};
777
778/*
779 * 'mcasp' class
780 */
781static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
782 .rev_offs = 0x0,
783 .sysc_offs = 0x4,
784 .sysc_flags = SYSC_HAS_SIDLEMODE,
785 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
786 .sysc_fields = &omap_hwmod_sysc_type3,
787};
788
789static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
790 .name = "mcasp",
791 .sysc = &am33xx_mcasp_sysc,
792};
793
794/* mcasp0 */
795struct omap_hwmod am33xx_mcasp0_hwmod = {
796 .name = "mcasp0",
797 .class = &am33xx_mcasp_hwmod_class,
798 .clkdm_name = "l3s_clkdm",
799 .main_clk = "mcasp0_fck",
800 .prcm = {
801 .omap4 = {
802 .modulemode = MODULEMODE_SWCTRL,
803 },
804 },
805};
806
807/* mcasp1 */
808struct omap_hwmod am33xx_mcasp1_hwmod = {
809 .name = "mcasp1",
810 .class = &am33xx_mcasp_hwmod_class,
811 .clkdm_name = "l3s_clkdm",
812 .main_clk = "mcasp1_fck",
813 .prcm = {
814 .omap4 = {
815 .modulemode = MODULEMODE_SWCTRL,
816 },
817 },
818};
819
820/* 'mmc' class */
821static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
822 .rev_offs = 0x1fc,
823 .sysc_offs = 0x10,
824 .syss_offs = 0x14,
825 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
826 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
827 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
828 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
829 .sysc_fields = &omap_hwmod_sysc_type1,
830};
831
832static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
833 .name = "mmc",
834 .sysc = &am33xx_mmc_sysc,
835};
836
837/* mmc0 */
838static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
839 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
840};
841
842struct omap_hwmod am33xx_mmc0_hwmod = {
843 .name = "mmc1",
844 .class = &am33xx_mmc_hwmod_class,
845 .clkdm_name = "l4ls_clkdm",
846 .main_clk = "mmc_clk",
847 .prcm = {
848 .omap4 = {
849 .modulemode = MODULEMODE_SWCTRL,
850 },
851 },
852 .dev_attr = &am33xx_mmc0_dev_attr,
853};
854
855/* mmc1 */
856static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
857 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
858};
859
860struct omap_hwmod am33xx_mmc1_hwmod = {
861 .name = "mmc2",
862 .class = &am33xx_mmc_hwmod_class,
863 .clkdm_name = "l4ls_clkdm",
864 .main_clk = "mmc_clk",
865 .prcm = {
866 .omap4 = {
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &am33xx_mmc1_dev_attr,
871};
872
873/* mmc2 */
874static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
875 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
876};
877struct omap_hwmod am33xx_mmc2_hwmod = {
878 .name = "mmc3",
879 .class = &am33xx_mmc_hwmod_class,
880 .clkdm_name = "l3s_clkdm",
881 .main_clk = "mmc_clk",
882 .prcm = {
883 .omap4 = {
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &am33xx_mmc2_dev_attr,
888};
889
890/*
891 * 'rtc' class
892 * rtc subsystem
893 */
894static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
895 .rev_offs = 0x0074,
896 .sysc_offs = 0x0078,
897 .sysc_flags = SYSC_HAS_SIDLEMODE,
898 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
899 SIDLE_SMART | SIDLE_SMART_WKUP),
900 .sysc_fields = &omap_hwmod_sysc_type3,
901};
902
903static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
904 .name = "rtc",
905 .sysc = &am33xx_rtc_sysc,
906};
907
908struct omap_hwmod am33xx_rtc_hwmod = {
909 .name = "rtc",
910 .class = &am33xx_rtc_hwmod_class,
911 .clkdm_name = "l4_rtc_clkdm",
912 .main_clk = "clk_32768_ck",
913 .prcm = {
914 .omap4 = {
915 .modulemode = MODULEMODE_SWCTRL,
916 },
917 },
918};
919
920/* 'spi' class */
921static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
922 .rev_offs = 0x0000,
923 .sysc_offs = 0x0110,
924 .syss_offs = 0x0114,
925 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
926 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
927 SYSS_HAS_RESET_STATUS),
928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
929 .sysc_fields = &omap_hwmod_sysc_type1,
930};
931
932struct omap_hwmod_class am33xx_spi_hwmod_class = {
933 .name = "mcspi",
934 .sysc = &am33xx_mcspi_sysc,
935 .rev = OMAP4_MCSPI_REV,
936};
937
938/* spi0 */
939struct omap2_mcspi_dev_attr mcspi_attrib = {
940 .num_chipselect = 2,
941};
942struct omap_hwmod am33xx_spi0_hwmod = {
943 .name = "spi0",
944 .class = &am33xx_spi_hwmod_class,
945 .clkdm_name = "l4ls_clkdm",
946 .main_clk = "dpll_per_m2_div4_ck",
947 .prcm = {
948 .omap4 = {
949 .modulemode = MODULEMODE_SWCTRL,
950 },
951 },
952 .dev_attr = &mcspi_attrib,
953};
954
955/* spi1 */
956struct omap_hwmod am33xx_spi1_hwmod = {
957 .name = "spi1",
958 .class = &am33xx_spi_hwmod_class,
959 .clkdm_name = "l4ls_clkdm",
960 .main_clk = "dpll_per_m2_div4_ck",
961 .prcm = {
962 .omap4 = {
963 .modulemode = MODULEMODE_SWCTRL,
964 },
965 },
966 .dev_attr = &mcspi_attrib,
967};
968
969/*
970 * 'spinlock' class
971 * spinlock provides hardware assistance for synchronizing the
972 * processes running on multiple processors
973 */
974
975static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
976 .rev_offs = 0x0000,
977 .sysc_offs = 0x0010,
978 .syss_offs = 0x0014,
979 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
980 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
981 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
982 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
983 .sysc_fields = &omap_hwmod_sysc_type1,
984};
985
986static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
987 .name = "spinlock",
988 .sysc = &am33xx_spinlock_sysc,
989};
990
991struct omap_hwmod am33xx_spinlock_hwmod = {
992 .name = "spinlock",
993 .class = &am33xx_spinlock_hwmod_class,
994 .clkdm_name = "l4ls_clkdm",
995 .main_clk = "l4ls_gclk",
996 .prcm = {
997 .omap4 = {
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001};
1002
1003/* 'timer 2-7' class */
1004static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1005 .rev_offs = 0x0000,
1006 .sysc_offs = 0x0010,
1007 .syss_offs = 0x0014,
1008 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1009 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1010 SIDLE_SMART_WKUP),
1011 .sysc_fields = &omap_hwmod_sysc_type2,
1012};
1013
1014struct omap_hwmod_class am33xx_timer_hwmod_class = {
1015 .name = "timer",
1016 .sysc = &am33xx_timer_sysc,
1017};
1018
1019/* timer1 1ms */
1020static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1021 .rev_offs = 0x0000,
1022 .sysc_offs = 0x0010,
1023 .syss_offs = 0x0014,
1024 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1025 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1026 SYSS_HAS_RESET_STATUS),
1027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1028 .sysc_fields = &omap_hwmod_sysc_type1,
1029};
1030
1031static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1032 .name = "timer",
1033 .sysc = &am33xx_timer1ms_sysc,
1034};
1035
1036struct omap_hwmod am33xx_timer1_hwmod = {
1037 .name = "timer1",
1038 .class = &am33xx_timer1ms_hwmod_class,
1039 .clkdm_name = "l4_wkup_clkdm",
1040 .main_clk = "timer1_fck",
1041 .prcm = {
1042 .omap4 = {
1043 .modulemode = MODULEMODE_SWCTRL,
1044 },
1045 },
1046};
1047
1048struct omap_hwmod am33xx_timer2_hwmod = {
1049 .name = "timer2",
1050 .class = &am33xx_timer_hwmod_class,
1051 .clkdm_name = "l4ls_clkdm",
1052 .main_clk = "timer2_fck",
1053 .prcm = {
1054 .omap4 = {
1055 .modulemode = MODULEMODE_SWCTRL,
1056 },
1057 },
1058};
1059
1060struct omap_hwmod am33xx_timer3_hwmod = {
1061 .name = "timer3",
1062 .class = &am33xx_timer_hwmod_class,
1063 .clkdm_name = "l4ls_clkdm",
1064 .main_clk = "timer3_fck",
1065 .prcm = {
1066 .omap4 = {
1067 .modulemode = MODULEMODE_SWCTRL,
1068 },
1069 },
1070};
1071
1072struct omap_hwmod am33xx_timer4_hwmod = {
1073 .name = "timer4",
1074 .class = &am33xx_timer_hwmod_class,
1075 .clkdm_name = "l4ls_clkdm",
1076 .main_clk = "timer4_fck",
1077 .prcm = {
1078 .omap4 = {
1079 .modulemode = MODULEMODE_SWCTRL,
1080 },
1081 },
1082};
1083
1084struct omap_hwmod am33xx_timer5_hwmod = {
1085 .name = "timer5",
1086 .class = &am33xx_timer_hwmod_class,
1087 .clkdm_name = "l4ls_clkdm",
1088 .main_clk = "timer5_fck",
1089 .prcm = {
1090 .omap4 = {
1091 .modulemode = MODULEMODE_SWCTRL,
1092 },
1093 },
1094};
1095
1096struct omap_hwmod am33xx_timer6_hwmod = {
1097 .name = "timer6",
1098 .class = &am33xx_timer_hwmod_class,
1099 .clkdm_name = "l4ls_clkdm",
1100 .main_clk = "timer6_fck",
1101 .prcm = {
1102 .omap4 = {
1103 .modulemode = MODULEMODE_SWCTRL,
1104 },
1105 },
1106};
1107
1108struct omap_hwmod am33xx_timer7_hwmod = {
1109 .name = "timer7",
1110 .class = &am33xx_timer_hwmod_class,
1111 .clkdm_name = "l4ls_clkdm",
1112 .main_clk = "timer7_fck",
1113 .prcm = {
1114 .omap4 = {
1115 .modulemode = MODULEMODE_SWCTRL,
1116 },
1117 },
1118};
1119
1120/* tpcc */
1121static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1122 .name = "tpcc",
1123};
1124
1125struct omap_hwmod am33xx_tpcc_hwmod = {
1126 .name = "tpcc",
1127 .class = &am33xx_tpcc_hwmod_class,
1128 .clkdm_name = "l3_clkdm",
1129 .main_clk = "l3_gclk",
1130 .prcm = {
1131 .omap4 = {
1132 .modulemode = MODULEMODE_SWCTRL,
1133 },
1134 },
1135};
1136
1137static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1138 .rev_offs = 0x0,
1139 .sysc_offs = 0x10,
1140 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1141 SYSC_HAS_MIDLEMODE),
1142 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1143 .sysc_fields = &omap_hwmod_sysc_type2,
1144};
1145
1146/* 'tptc' class */
1147static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1148 .name = "tptc",
1149 .sysc = &am33xx_tptc_sysc,
1150};
1151
1152/* tptc0 */
1153struct omap_hwmod am33xx_tptc0_hwmod = {
1154 .name = "tptc0",
1155 .class = &am33xx_tptc_hwmod_class,
1156 .clkdm_name = "l3_clkdm",
1157 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1158 .main_clk = "l3_gclk",
1159 .prcm = {
1160 .omap4 = {
1161 .modulemode = MODULEMODE_SWCTRL,
1162 },
1163 },
1164};
1165
1166/* tptc1 */
1167struct omap_hwmod am33xx_tptc1_hwmod = {
1168 .name = "tptc1",
1169 .class = &am33xx_tptc_hwmod_class,
1170 .clkdm_name = "l3_clkdm",
1171 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1172 .main_clk = "l3_gclk",
1173 .prcm = {
1174 .omap4 = {
1175 .modulemode = MODULEMODE_SWCTRL,
1176 },
1177 },
1178};
1179
1180/* tptc2 */
1181struct omap_hwmod am33xx_tptc2_hwmod = {
1182 .name = "tptc2",
1183 .class = &am33xx_tptc_hwmod_class,
1184 .clkdm_name = "l3_clkdm",
1185 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1186 .main_clk = "l3_gclk",
1187 .prcm = {
1188 .omap4 = {
1189 .modulemode = MODULEMODE_SWCTRL,
1190 },
1191 },
1192};
1193
1194/* 'uart' class */
1195static struct omap_hwmod_class_sysconfig uart_sysc = {
1196 .rev_offs = 0x50,
1197 .sysc_offs = 0x54,
1198 .syss_offs = 0x58,
1199 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1200 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1201 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1202 SIDLE_SMART_WKUP),
1203 .sysc_fields = &omap_hwmod_sysc_type1,
1204};
1205
1206static struct omap_hwmod_class uart_class = {
1207 .name = "uart",
1208 .sysc = &uart_sysc,
1209};
1210
1211struct omap_hwmod am33xx_uart1_hwmod = {
1212 .name = "uart1",
1213 .class = &uart_class,
1214 .clkdm_name = "l4_wkup_clkdm",
1215 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1216 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1217 .prcm = {
1218 .omap4 = {
1219 .modulemode = MODULEMODE_SWCTRL,
1220 },
1221 },
1222};
1223
1224struct omap_hwmod am33xx_uart2_hwmod = {
1225 .name = "uart2",
1226 .class = &uart_class,
1227 .clkdm_name = "l4ls_clkdm",
1228 .flags = HWMOD_SWSUP_SIDLE_ACT,
1229 .main_clk = "dpll_per_m2_div4_ck",
1230 .prcm = {
1231 .omap4 = {
1232 .modulemode = MODULEMODE_SWCTRL,
1233 },
1234 },
1235};
1236
1237/* uart3 */
1238struct omap_hwmod am33xx_uart3_hwmod = {
1239 .name = "uart3",
1240 .class = &uart_class,
1241 .clkdm_name = "l4ls_clkdm",
1242 .flags = HWMOD_SWSUP_SIDLE_ACT,
1243 .main_clk = "dpll_per_m2_div4_ck",
1244 .prcm = {
1245 .omap4 = {
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249};
1250
1251struct omap_hwmod am33xx_uart4_hwmod = {
1252 .name = "uart4",
1253 .class = &uart_class,
1254 .clkdm_name = "l4ls_clkdm",
1255 .flags = HWMOD_SWSUP_SIDLE_ACT,
1256 .main_clk = "dpll_per_m2_div4_ck",
1257 .prcm = {
1258 .omap4 = {
1259 .modulemode = MODULEMODE_SWCTRL,
1260 },
1261 },
1262};
1263
1264struct omap_hwmod am33xx_uart5_hwmod = {
1265 .name = "uart5",
1266 .class = &uart_class,
1267 .clkdm_name = "l4ls_clkdm",
1268 .flags = HWMOD_SWSUP_SIDLE_ACT,
1269 .main_clk = "dpll_per_m2_div4_ck",
1270 .prcm = {
1271 .omap4 = {
1272 .modulemode = MODULEMODE_SWCTRL,
1273 },
1274 },
1275};
1276
1277struct omap_hwmod am33xx_uart6_hwmod = {
1278 .name = "uart6",
1279 .class = &uart_class,
1280 .clkdm_name = "l4ls_clkdm",
1281 .flags = HWMOD_SWSUP_SIDLE_ACT,
1282 .main_clk = "dpll_per_m2_div4_ck",
1283 .prcm = {
1284 .omap4 = {
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288};
1289
1290/* 'wd_timer' class */
1291static struct omap_hwmod_class_sysconfig wdt_sysc = {
1292 .rev_offs = 0x0,
1293 .sysc_offs = 0x10,
1294 .syss_offs = 0x14,
1295 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1296 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1297 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1298 SIDLE_SMART_WKUP),
1299 .sysc_fields = &omap_hwmod_sysc_type1,
1300};
1301
1302static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1303 .name = "wd_timer",
1304 .sysc = &wdt_sysc,
1305 .pre_shutdown = &omap2_wd_timer_disable,
1306};
1307
1308/*
1309 * XXX: device.c file uses hardcoded name for watchdog timer
1310 * driver "wd_timer2, so we are also using same name as of now...
1311 */
1312struct omap_hwmod am33xx_wd_timer1_hwmod = {
1313 .name = "wd_timer2",
1314 .class = &am33xx_wd_timer_hwmod_class,
1315 .clkdm_name = "l4_wkup_clkdm",
1316 .flags = HWMOD_SWSUP_SIDLE,
1317 .main_clk = "wdt1_fck",
1318 .prcm = {
1319 .omap4 = {
1320 .modulemode = MODULEMODE_SWCTRL,
1321 },
1322 },
1323};
1324
1325static void omap_hwmod_am33xx_clkctrl(void)
1326{
1327 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1328 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1329 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1330 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1331 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1332 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1333 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1334 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1335 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1336 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1337 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1338 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1339 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1340 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1341 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1342 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1343 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_smartreflex0_hwmod,
1358 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1359 CLKCTRL(am33xx_smartreflex1_hwmod,
1360 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1361 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1383}
1384
1385static void omap_hwmod_am33xx_rst(void)
1386{
1387 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1388 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1389 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1390}
1391
1392void omap_hwmod_am33xx_reg(void)
1393{
1394 omap_hwmod_am33xx_clkctrl();
1395 omap_hwmod_am33xx_rst();
1396}
1397
1398static void omap_hwmod_am43xx_clkctrl(void)
1399{
1400 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1401 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1402 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1403 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1404 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1405 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1406 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1407 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1408 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1409 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1410 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1411 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1412 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1413 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1414 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1415 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1416 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1417 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1418 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1420 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1421 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1422 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1423 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1424 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1425 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1426 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1427 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1428 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1429 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1430 CLKCTRL(am33xx_smartreflex0_hwmod,
1431 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1432 CLKCTRL(am33xx_smartreflex1_hwmod,
1433 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1434 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1435 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1436 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1437 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1438 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1439 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1440 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1441 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1442 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1443 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1444 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1445 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1446 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1447 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1448 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1449 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1450 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1451 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1452 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1453 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1454 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1455 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1456}
1457
1458static void omap_hwmod_am43xx_rst(void)
1459{
1460 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1461 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1462 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1463}
1464
1465void omap_hwmod_am43xx_reg(void)
1466{
1467 omap_hwmod_am43xx_clkctrl();
1468 omap_hwmod_am43xx_rst();
1469}
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index a166e5394113..6b406ca4bd3b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -29,6 +29,7 @@
29#include "i2c.h" 29#include "i2c.h"
30#include "mmc.h" 30#include "mmc.h"
31#include "wd_timer.h" 31#include "wd_timer.h"
32#include "omap_hwmod_33xx_43xx_common_data.h"
32 33
33/* 34/*
34 * IP blocks 35 * IP blocks
@@ -62,73 +63,6 @@ static struct omap_hwmod am33xx_emif_hwmod = {
62 }, 63 },
63}; 64};
64 65
65/*
66 * 'l3' class
67 * instance(s): l3_main, l3_s, l3_instr
68 */
69static struct omap_hwmod_class am33xx_l3_hwmod_class = {
70 .name = "l3",
71};
72
73static struct omap_hwmod am33xx_l3_main_hwmod = {
74 .name = "l3_main",
75 .class = &am33xx_l3_hwmod_class,
76 .clkdm_name = "l3_clkdm",
77 .flags = HWMOD_INIT_NO_IDLE,
78 .main_clk = "l3_gclk",
79 .prcm = {
80 .omap4 = {
81 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
82 .modulemode = MODULEMODE_SWCTRL,
83 },
84 },
85};
86
87/* l3_s */
88static struct omap_hwmod am33xx_l3_s_hwmod = {
89 .name = "l3_s",
90 .class = &am33xx_l3_hwmod_class,
91 .clkdm_name = "l3s_clkdm",
92};
93
94/* l3_instr */
95static struct omap_hwmod am33xx_l3_instr_hwmod = {
96 .name = "l3_instr",
97 .class = &am33xx_l3_hwmod_class,
98 .clkdm_name = "l3_clkdm",
99 .flags = HWMOD_INIT_NO_IDLE,
100 .main_clk = "l3_gclk",
101 .prcm = {
102 .omap4 = {
103 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
104 .modulemode = MODULEMODE_SWCTRL,
105 },
106 },
107};
108
109/*
110 * 'l4' class
111 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
112 */
113static struct omap_hwmod_class am33xx_l4_hwmod_class = {
114 .name = "l4",
115};
116
117/* l4_ls */
118static struct omap_hwmod am33xx_l4_ls_hwmod = {
119 .name = "l4_ls",
120 .class = &am33xx_l4_hwmod_class,
121 .clkdm_name = "l4ls_clkdm",
122 .flags = HWMOD_INIT_NO_IDLE,
123 .main_clk = "l4ls_gclk",
124 .prcm = {
125 .omap4 = {
126 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
127 .modulemode = MODULEMODE_SWCTRL,
128 },
129 },
130};
131
132/* l4_hs */ 66/* l4_hs */
133static struct omap_hwmod am33xx_l4_hs_hwmod = { 67static struct omap_hwmod am33xx_l4_hs_hwmod = {
134 .name = "l4_hs", 68 .name = "l4_hs",
@@ -144,50 +78,6 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = {
144 }, 78 },
145}; 79};
146 80
147
148/* l4_wkup */
149static struct omap_hwmod am33xx_l4_wkup_hwmod = {
150 .name = "l4_wkup",
151 .class = &am33xx_l4_hwmod_class,
152 .clkdm_name = "l4_wkup_clkdm",
153 .flags = HWMOD_INIT_NO_IDLE,
154 .prcm = {
155 .omap4 = {
156 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
157 .modulemode = MODULEMODE_SWCTRL,
158 },
159 },
160};
161
162/*
163 * 'mpu' class
164 */
165static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
166 .name = "mpu",
167};
168
169static struct omap_hwmod am33xx_mpu_hwmod = {
170 .name = "mpu",
171 .class = &am33xx_mpu_hwmod_class,
172 .clkdm_name = "mpu_clkdm",
173 .flags = HWMOD_INIT_NO_IDLE,
174 .main_clk = "dpll_mpu_m2_ck",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181};
182
183/*
184 * 'wakeup m3' class
185 * Wakeup controller sub-system under wakeup domain
186 */
187static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
188 .name = "wkup_m3",
189};
190
191static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { 81static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
192 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, 82 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
193}; 83};
@@ -213,78 +103,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
213}; 103};
214 104
215/* 105/*
216 * 'pru-icss' class
217 * Programmable Real-Time Unit and Industrial Communication Subsystem
218 */
219static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
220 .name = "pruss",
221};
222
223static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
224 { .name = "pruss", .rst_shift = 1 },
225};
226
227/* pru-icss */
228/* Pseudo hwmod for reset control purpose only */
229static struct omap_hwmod am33xx_pruss_hwmod = {
230 .name = "pruss",
231 .class = &am33xx_pruss_hwmod_class,
232 .clkdm_name = "pruss_ocp_clkdm",
233 .main_clk = "pruss_ocp_gclk",
234 .prcm = {
235 .omap4 = {
236 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
237 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
239 },
240 },
241 .rst_lines = am33xx_pruss_resets,
242 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
243};
244
245/* gfx */
246/* Pseudo hwmod for reset control purpose only */
247static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
248 .name = "gfx",
249};
250
251static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
252 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
253};
254
255static struct omap_hwmod am33xx_gfx_hwmod = {
256 .name = "gfx",
257 .class = &am33xx_gfx_hwmod_class,
258 .clkdm_name = "gfx_l3_clkdm",
259 .main_clk = "gfx_fck_div_ck",
260 .prcm = {
261 .omap4 = {
262 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
263 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
264 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
265 .modulemode = MODULEMODE_SWCTRL,
266 },
267 },
268 .rst_lines = am33xx_gfx_resets,
269 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
270};
271
272/*
273 * 'prcm' class
274 * power and reset manager (whole prcm infrastructure)
275 */
276static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
277 .name = "prcm",
278};
279
280/* prcm */
281static struct omap_hwmod am33xx_prcm_hwmod = {
282 .name = "prcm",
283 .class = &am33xx_prcm_hwmod_class,
284 .clkdm_name = "l4_wkup_clkdm",
285};
286
287/*
288 * 'adc/tsc' class 106 * 'adc/tsc' class
289 * TouchScreen Controller (Anolog-To-Digital Converter) 107 * TouchScreen Controller (Anolog-To-Digital Converter)
290 */ 108 */
@@ -388,79 +206,6 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
388#endif 206#endif
389 207
390/* 208/*
391 * 'aes0' class
392 */
393static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
394 .rev_offs = 0x80,
395 .sysc_offs = 0x84,
396 .syss_offs = 0x88,
397 .sysc_flags = SYSS_HAS_RESET_STATUS,
398};
399
400static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
401 .name = "aes0",
402 .sysc = &am33xx_aes0_sysc,
403};
404
405static struct omap_hwmod am33xx_aes0_hwmod = {
406 .name = "aes",
407 .class = &am33xx_aes0_hwmod_class,
408 .clkdm_name = "l3_clkdm",
409 .main_clk = "aes0_fck",
410 .prcm = {
411 .omap4 = {
412 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
413 .modulemode = MODULEMODE_SWCTRL,
414 },
415 },
416};
417
418/* sha0 HIB2 (the 'P' (public) device) */
419static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
420 .rev_offs = 0x100,
421 .sysc_offs = 0x110,
422 .syss_offs = 0x114,
423 .sysc_flags = SYSS_HAS_RESET_STATUS,
424};
425
426static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
427 .name = "sha0",
428 .sysc = &am33xx_sha0_sysc,
429};
430
431static struct omap_hwmod am33xx_sha0_hwmod = {
432 .name = "sham",
433 .class = &am33xx_sha0_hwmod_class,
434 .clkdm_name = "l3_clkdm",
435 .main_clk = "l3_gclk",
436 .prcm = {
437 .omap4 = {
438 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
439 .modulemode = MODULEMODE_SWCTRL,
440 },
441 },
442};
443
444/* ocmcram */
445static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
446 .name = "ocmcram",
447};
448
449static struct omap_hwmod am33xx_ocmcram_hwmod = {
450 .name = "ocmcram",
451 .class = &am33xx_ocmcram_hwmod_class,
452 .clkdm_name = "l3_clkdm",
453 .flags = HWMOD_INIT_NO_IDLE,
454 .main_clk = "l3_gclk",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461};
462
463/*
464 * 'debugss' class 209 * 'debugss' class
465 * debug sub system 210 * debug sub system
466 */ 211 */
@@ -488,46 +233,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
488 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), 233 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
489}; 234};
490 235
491/* 'smartreflex' class */
492static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
493 .name = "smartreflex",
494};
495
496/* smartreflex0 */
497static struct omap_hwmod am33xx_smartreflex0_hwmod = {
498 .name = "smartreflex0",
499 .class = &am33xx_smartreflex_hwmod_class,
500 .clkdm_name = "l4_wkup_clkdm",
501 .main_clk = "smartreflex0_fck",
502 .prcm = {
503 .omap4 = {
504 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
505 .modulemode = MODULEMODE_SWCTRL,
506 },
507 },
508};
509
510/* smartreflex1 */
511static struct omap_hwmod am33xx_smartreflex1_hwmod = {
512 .name = "smartreflex1",
513 .class = &am33xx_smartreflex_hwmod_class,
514 .clkdm_name = "l4_wkup_clkdm",
515 .main_clk = "smartreflex1_fck",
516 .prcm = {
517 .omap4 = {
518 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
519 .modulemode = MODULEMODE_SWCTRL,
520 },
521 },
522};
523
524/*
525 * 'control' module class
526 */
527static struct omap_hwmod_class am33xx_control_hwmod_class = {
528 .name = "control",
529};
530
531static struct omap_hwmod am33xx_control_hwmod = { 236static struct omap_hwmod am33xx_control_hwmod = {
532 .name = "control", 237 .name = "control",
533 .class = &am33xx_control_hwmod_class, 238 .class = &am33xx_control_hwmod_class,
@@ -542,288 +247,6 @@ static struct omap_hwmod am33xx_control_hwmod = {
542 }, 247 },
543}; 248};
544 249
545/*
546 * 'cpgmac' class
547 * cpsw/cpgmac sub system
548 */
549static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
550 .rev_offs = 0x0,
551 .sysc_offs = 0x8,
552 .syss_offs = 0x4,
553 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
554 SYSS_HAS_RESET_STATUS),
555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
556 MSTANDBY_NO),
557 .sysc_fields = &omap_hwmod_sysc_type3,
558};
559
560static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
561 .name = "cpgmac0",
562 .sysc = &am33xx_cpgmac_sysc,
563};
564
565static struct omap_hwmod am33xx_cpgmac0_hwmod = {
566 .name = "cpgmac0",
567 .class = &am33xx_cpgmac0_hwmod_class,
568 .clkdm_name = "cpsw_125mhz_clkdm",
569 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
570 .main_clk = "cpsw_125mhz_gclk",
571 .mpu_rt_idx = 1,
572 .prcm = {
573 .omap4 = {
574 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
575 .modulemode = MODULEMODE_SWCTRL,
576 },
577 },
578};
579
580/*
581 * mdio class
582 */
583static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
584 .name = "davinci_mdio",
585};
586
587static struct omap_hwmod am33xx_mdio_hwmod = {
588 .name = "davinci_mdio",
589 .class = &am33xx_mdio_hwmod_class,
590 .clkdm_name = "cpsw_125mhz_clkdm",
591 .main_clk = "cpsw_125mhz_gclk",
592};
593
594/*
595 * dcan class
596 */
597static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
598 .name = "d_can",
599};
600
601/* dcan0 */
602static struct omap_hwmod am33xx_dcan0_hwmod = {
603 .name = "d_can0",
604 .class = &am33xx_dcan_hwmod_class,
605 .clkdm_name = "l4ls_clkdm",
606 .main_clk = "dcan0_fck",
607 .prcm = {
608 .omap4 = {
609 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
610 .modulemode = MODULEMODE_SWCTRL,
611 },
612 },
613};
614
615/* dcan1 */
616static struct omap_hwmod am33xx_dcan1_hwmod = {
617 .name = "d_can1",
618 .class = &am33xx_dcan_hwmod_class,
619 .clkdm_name = "l4ls_clkdm",
620 .main_clk = "dcan1_fck",
621 .prcm = {
622 .omap4 = {
623 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
624 .modulemode = MODULEMODE_SWCTRL,
625 },
626 },
627};
628
629/* elm */
630static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
631 .rev_offs = 0x0000,
632 .sysc_offs = 0x0010,
633 .syss_offs = 0x0014,
634 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
635 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
636 SYSS_HAS_RESET_STATUS),
637 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
638 .sysc_fields = &omap_hwmod_sysc_type1,
639};
640
641static struct omap_hwmod_class am33xx_elm_hwmod_class = {
642 .name = "elm",
643 .sysc = &am33xx_elm_sysc,
644};
645
646static struct omap_hwmod am33xx_elm_hwmod = {
647 .name = "elm",
648 .class = &am33xx_elm_hwmod_class,
649 .clkdm_name = "l4ls_clkdm",
650 .main_clk = "l4ls_gclk",
651 .prcm = {
652 .omap4 = {
653 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
654 .modulemode = MODULEMODE_SWCTRL,
655 },
656 },
657};
658
659/* pwmss */
660static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
661 .rev_offs = 0x0,
662 .sysc_offs = 0x4,
663 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
664 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
665 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
666 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
667 .sysc_fields = &omap_hwmod_sysc_type2,
668};
669
670static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
671 .name = "epwmss",
672 .sysc = &am33xx_epwmss_sysc,
673};
674
675static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
676 .name = "ecap",
677};
678
679static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
680 .name = "eqep",
681};
682
683static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
684 .name = "ehrpwm",
685};
686
687/* epwmss0 */
688static struct omap_hwmod am33xx_epwmss0_hwmod = {
689 .name = "epwmss0",
690 .class = &am33xx_epwmss_hwmod_class,
691 .clkdm_name = "l4ls_clkdm",
692 .main_clk = "l4ls_gclk",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
696 .modulemode = MODULEMODE_SWCTRL,
697 },
698 },
699};
700
701/* ecap0 */
702static struct omap_hwmod am33xx_ecap0_hwmod = {
703 .name = "ecap0",
704 .class = &am33xx_ecap_hwmod_class,
705 .clkdm_name = "l4ls_clkdm",
706 .main_clk = "l4ls_gclk",
707};
708
709/* eqep0 */
710static struct omap_hwmod am33xx_eqep0_hwmod = {
711 .name = "eqep0",
712 .class = &am33xx_eqep_hwmod_class,
713 .clkdm_name = "l4ls_clkdm",
714 .main_clk = "l4ls_gclk",
715};
716
717/* ehrpwm0 */
718static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
719 .name = "ehrpwm0",
720 .class = &am33xx_ehrpwm_hwmod_class,
721 .clkdm_name = "l4ls_clkdm",
722 .main_clk = "l4ls_gclk",
723};
724
725/* epwmss1 */
726static struct omap_hwmod am33xx_epwmss1_hwmod = {
727 .name = "epwmss1",
728 .class = &am33xx_epwmss_hwmod_class,
729 .clkdm_name = "l4ls_clkdm",
730 .main_clk = "l4ls_gclk",
731 .prcm = {
732 .omap4 = {
733 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
734 .modulemode = MODULEMODE_SWCTRL,
735 },
736 },
737};
738
739/* ecap1 */
740static struct omap_hwmod am33xx_ecap1_hwmod = {
741 .name = "ecap1",
742 .class = &am33xx_ecap_hwmod_class,
743 .clkdm_name = "l4ls_clkdm",
744 .main_clk = "l4ls_gclk",
745};
746
747/* eqep1 */
748static struct omap_hwmod am33xx_eqep1_hwmod = {
749 .name = "eqep1",
750 .class = &am33xx_eqep_hwmod_class,
751 .clkdm_name = "l4ls_clkdm",
752 .main_clk = "l4ls_gclk",
753};
754
755/* ehrpwm1 */
756static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
757 .name = "ehrpwm1",
758 .class = &am33xx_ehrpwm_hwmod_class,
759 .clkdm_name = "l4ls_clkdm",
760 .main_clk = "l4ls_gclk",
761};
762
763/* epwmss2 */
764static struct omap_hwmod am33xx_epwmss2_hwmod = {
765 .name = "epwmss2",
766 .class = &am33xx_epwmss_hwmod_class,
767 .clkdm_name = "l4ls_clkdm",
768 .main_clk = "l4ls_gclk",
769 .prcm = {
770 .omap4 = {
771 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
772 .modulemode = MODULEMODE_SWCTRL,
773 },
774 },
775};
776
777/* ecap2 */
778static struct omap_hwmod am33xx_ecap2_hwmod = {
779 .name = "ecap2",
780 .class = &am33xx_ecap_hwmod_class,
781 .clkdm_name = "l4ls_clkdm",
782 .main_clk = "l4ls_gclk",
783};
784
785/* eqep2 */
786static struct omap_hwmod am33xx_eqep2_hwmod = {
787 .name = "eqep2",
788 .class = &am33xx_eqep_hwmod_class,
789 .clkdm_name = "l4ls_clkdm",
790 .main_clk = "l4ls_gclk",
791};
792
793/* ehrpwm2 */
794static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
795 .name = "ehrpwm2",
796 .class = &am33xx_ehrpwm_hwmod_class,
797 .clkdm_name = "l4ls_clkdm",
798 .main_clk = "l4ls_gclk",
799};
800
801/*
802 * 'gpio' class: for gpio 0,1,2,3
803 */
804static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
805 .rev_offs = 0x0000,
806 .sysc_offs = 0x0010,
807 .syss_offs = 0x0114,
808 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
809 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
810 SYSS_HAS_RESET_STATUS),
811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
812 SIDLE_SMART_WKUP),
813 .sysc_fields = &omap_hwmod_sysc_type1,
814};
815
816static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
817 .name = "gpio",
818 .sysc = &am33xx_gpio_sysc,
819 .rev = 2,
820};
821
822static struct omap_gpio_dev_attr gpio_dev_attr = {
823 .bank_width = 32,
824 .dbck_flag = true,
825};
826
827/* gpio0 */ 250/* gpio0 */
828static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { 251static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
829 { .role = "dbclk", .clk = "gpio0_dbclk" }, 252 { .role = "dbclk", .clk = "gpio0_dbclk" },
@@ -846,174 +269,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
846 .dev_attr = &gpio_dev_attr, 269 .dev_attr = &gpio_dev_attr,
847}; 270};
848 271
849/* gpio1 */
850static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
851 { .role = "dbclk", .clk = "gpio1_dbclk" },
852};
853
854static struct omap_hwmod am33xx_gpio1_hwmod = {
855 .name = "gpio2",
856 .class = &am33xx_gpio_hwmod_class,
857 .clkdm_name = "l4ls_clkdm",
858 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
859 .main_clk = "l4ls_gclk",
860 .prcm = {
861 .omap4 = {
862 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866 .opt_clks = gpio1_opt_clks,
867 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
868 .dev_attr = &gpio_dev_attr,
869};
870
871/* gpio2 */
872static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
873 { .role = "dbclk", .clk = "gpio2_dbclk" },
874};
875
876static struct omap_hwmod am33xx_gpio2_hwmod = {
877 .name = "gpio3",
878 .class = &am33xx_gpio_hwmod_class,
879 .clkdm_name = "l4ls_clkdm",
880 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
881 .main_clk = "l4ls_gclk",
882 .prcm = {
883 .omap4 = {
884 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
885 .modulemode = MODULEMODE_SWCTRL,
886 },
887 },
888 .opt_clks = gpio2_opt_clks,
889 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
890 .dev_attr = &gpio_dev_attr,
891};
892
893/* gpio3 */
894static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
895 { .role = "dbclk", .clk = "gpio3_dbclk" },
896};
897
898static struct omap_hwmod am33xx_gpio3_hwmod = {
899 .name = "gpio4",
900 .class = &am33xx_gpio_hwmod_class,
901 .clkdm_name = "l4ls_clkdm",
902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903 .main_clk = "l4ls_gclk",
904 .prcm = {
905 .omap4 = {
906 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
907 .modulemode = MODULEMODE_SWCTRL,
908 },
909 },
910 .opt_clks = gpio3_opt_clks,
911 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
912 .dev_attr = &gpio_dev_attr,
913};
914
915/* gpmc */
916static struct omap_hwmod_class_sysconfig gpmc_sysc = {
917 .rev_offs = 0x0,
918 .sysc_offs = 0x10,
919 .syss_offs = 0x14,
920 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
921 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
922 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
923 .sysc_fields = &omap_hwmod_sysc_type1,
924};
925
926static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
927 .name = "gpmc",
928 .sysc = &gpmc_sysc,
929};
930
931static struct omap_hwmod am33xx_gpmc_hwmod = {
932 .name = "gpmc",
933 .class = &am33xx_gpmc_hwmod_class,
934 .clkdm_name = "l3s_clkdm",
935 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
936 .main_clk = "l3s_gclk",
937 .prcm = {
938 .omap4 = {
939 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
940 .modulemode = MODULEMODE_SWCTRL,
941 },
942 },
943};
944
945/* 'i2c' class */
946static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
947 .sysc_offs = 0x0010,
948 .syss_offs = 0x0090,
949 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
950 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
951 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
952 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
953 SIDLE_SMART_WKUP),
954 .sysc_fields = &omap_hwmod_sysc_type1,
955};
956
957static struct omap_hwmod_class i2c_class = {
958 .name = "i2c",
959 .sysc = &am33xx_i2c_sysc,
960 .rev = OMAP_I2C_IP_VERSION_2,
961 .reset = &omap_i2c_reset,
962};
963
964static struct omap_i2c_dev_attr i2c_dev_attr = {
965 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
966};
967
968/* i2c1 */
969static struct omap_hwmod am33xx_i2c1_hwmod = {
970 .name = "i2c1",
971 .class = &i2c_class,
972 .clkdm_name = "l4_wkup_clkdm",
973 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
974 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
975 .prcm = {
976 .omap4 = {
977 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
978 .modulemode = MODULEMODE_SWCTRL,
979 },
980 },
981 .dev_attr = &i2c_dev_attr,
982};
983
984/* i2c1 */
985static struct omap_hwmod am33xx_i2c2_hwmod = {
986 .name = "i2c2",
987 .class = &i2c_class,
988 .clkdm_name = "l4ls_clkdm",
989 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
990 .main_clk = "dpll_per_m2_div4_ck",
991 .prcm = {
992 .omap4 = {
993 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL,
995 },
996 },
997 .dev_attr = &i2c_dev_attr,
998};
999
1000/* i2c3 */
1001static struct omap_hwmod am33xx_i2c3_hwmod = {
1002 .name = "i2c3",
1003 .class = &i2c_class,
1004 .clkdm_name = "l4ls_clkdm",
1005 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1006 .main_clk = "dpll_per_m2_div4_ck",
1007 .prcm = {
1008 .omap4 = {
1009 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1010 .modulemode = MODULEMODE_SWCTRL,
1011 },
1012 },
1013 .dev_attr = &i2c_dev_attr,
1014};
1015
1016
1017/* lcdc */ 272/* lcdc */
1018static struct omap_hwmod_class_sysconfig lcdc_sysc = { 273static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1019 .rev_offs = 0x0, 274 .rev_offs = 0x0,
@@ -1043,613 +298,6 @@ static struct omap_hwmod am33xx_lcdc_hwmod = {
1043}; 298};
1044 299
1045/* 300/*
1046 * 'mailbox' class
1047 * mailbox module allowing communication between the on-chip processors using a
1048 * queued mailbox-interrupt mechanism.
1049 */
1050static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1051 .rev_offs = 0x0000,
1052 .sysc_offs = 0x0010,
1053 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1054 SYSC_HAS_SOFTRESET),
1055 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1056 .sysc_fields = &omap_hwmod_sysc_type2,
1057};
1058
1059static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1060 .name = "mailbox",
1061 .sysc = &am33xx_mailbox_sysc,
1062};
1063
1064static struct omap_hwmod am33xx_mailbox_hwmod = {
1065 .name = "mailbox",
1066 .class = &am33xx_mailbox_hwmod_class,
1067 .clkdm_name = "l4ls_clkdm",
1068 .main_clk = "l4ls_gclk",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1072 .modulemode = MODULEMODE_SWCTRL,
1073 },
1074 },
1075};
1076
1077/*
1078 * 'mcasp' class
1079 */
1080static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1081 .rev_offs = 0x0,
1082 .sysc_offs = 0x4,
1083 .sysc_flags = SYSC_HAS_SIDLEMODE,
1084 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1085 .sysc_fields = &omap_hwmod_sysc_type3,
1086};
1087
1088static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1089 .name = "mcasp",
1090 .sysc = &am33xx_mcasp_sysc,
1091};
1092
1093/* mcasp0 */
1094static struct omap_hwmod am33xx_mcasp0_hwmod = {
1095 .name = "mcasp0",
1096 .class = &am33xx_mcasp_hwmod_class,
1097 .clkdm_name = "l3s_clkdm",
1098 .main_clk = "mcasp0_fck",
1099 .prcm = {
1100 .omap4 = {
1101 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1102 .modulemode = MODULEMODE_SWCTRL,
1103 },
1104 },
1105};
1106
1107/* mcasp1 */
1108static struct omap_hwmod am33xx_mcasp1_hwmod = {
1109 .name = "mcasp1",
1110 .class = &am33xx_mcasp_hwmod_class,
1111 .clkdm_name = "l3s_clkdm",
1112 .main_clk = "mcasp1_fck",
1113 .prcm = {
1114 .omap4 = {
1115 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1116 .modulemode = MODULEMODE_SWCTRL,
1117 },
1118 },
1119};
1120
1121/* 'mmc' class */
1122static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1123 .rev_offs = 0x1fc,
1124 .sysc_offs = 0x10,
1125 .syss_offs = 0x14,
1126 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1127 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1128 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1129 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1130 .sysc_fields = &omap_hwmod_sysc_type1,
1131};
1132
1133static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1134 .name = "mmc",
1135 .sysc = &am33xx_mmc_sysc,
1136};
1137
1138/* mmc0 */
1139static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1140 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1141};
1142
1143static struct omap_hwmod am33xx_mmc0_hwmod = {
1144 .name = "mmc1",
1145 .class = &am33xx_mmc_hwmod_class,
1146 .clkdm_name = "l4ls_clkdm",
1147 .main_clk = "mmc_clk",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .dev_attr = &am33xx_mmc0_dev_attr,
1155};
1156
1157/* mmc1 */
1158static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1159 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1160};
1161
1162static struct omap_hwmod am33xx_mmc1_hwmod = {
1163 .name = "mmc2",
1164 .class = &am33xx_mmc_hwmod_class,
1165 .clkdm_name = "l4ls_clkdm",
1166 .main_clk = "mmc_clk",
1167 .prcm = {
1168 .omap4 = {
1169 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1170 .modulemode = MODULEMODE_SWCTRL,
1171 },
1172 },
1173 .dev_attr = &am33xx_mmc1_dev_attr,
1174};
1175
1176/* mmc2 */
1177static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1178 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1179};
1180static struct omap_hwmod am33xx_mmc2_hwmod = {
1181 .name = "mmc3",
1182 .class = &am33xx_mmc_hwmod_class,
1183 .clkdm_name = "l3s_clkdm",
1184 .main_clk = "mmc_clk",
1185 .prcm = {
1186 .omap4 = {
1187 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1188 .modulemode = MODULEMODE_SWCTRL,
1189 },
1190 },
1191 .dev_attr = &am33xx_mmc2_dev_attr,
1192};
1193
1194/*
1195 * 'rtc' class
1196 * rtc subsystem
1197 */
1198static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1199 .rev_offs = 0x0074,
1200 .sysc_offs = 0x0078,
1201 .sysc_flags = SYSC_HAS_SIDLEMODE,
1202 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1203 SIDLE_SMART | SIDLE_SMART_WKUP),
1204 .sysc_fields = &omap_hwmod_sysc_type3,
1205};
1206
1207static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1208 .name = "rtc",
1209 .sysc = &am33xx_rtc_sysc,
1210};
1211
1212static struct omap_hwmod am33xx_rtc_hwmod = {
1213 .name = "rtc",
1214 .class = &am33xx_rtc_hwmod_class,
1215 .clkdm_name = "l4_rtc_clkdm",
1216 .main_clk = "clk_32768_ck",
1217 .prcm = {
1218 .omap4 = {
1219 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1220 .modulemode = MODULEMODE_SWCTRL,
1221 },
1222 },
1223};
1224
1225/* 'spi' class */
1226static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1227 .rev_offs = 0x0000,
1228 .sysc_offs = 0x0110,
1229 .syss_offs = 0x0114,
1230 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1231 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1232 SYSS_HAS_RESET_STATUS),
1233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1234 .sysc_fields = &omap_hwmod_sysc_type1,
1235};
1236
1237static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1238 .name = "mcspi",
1239 .sysc = &am33xx_mcspi_sysc,
1240 .rev = OMAP4_MCSPI_REV,
1241};
1242
1243/* spi0 */
1244static struct omap2_mcspi_dev_attr mcspi_attrib = {
1245 .num_chipselect = 2,
1246};
1247static struct omap_hwmod am33xx_spi0_hwmod = {
1248 .name = "spi0",
1249 .class = &am33xx_spi_hwmod_class,
1250 .clkdm_name = "l4ls_clkdm",
1251 .main_clk = "dpll_per_m2_div4_ck",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1255 .modulemode = MODULEMODE_SWCTRL,
1256 },
1257 },
1258 .dev_attr = &mcspi_attrib,
1259};
1260
1261/* spi1 */
1262static struct omap_hwmod am33xx_spi1_hwmod = {
1263 .name = "spi1",
1264 .class = &am33xx_spi_hwmod_class,
1265 .clkdm_name = "l4ls_clkdm",
1266 .main_clk = "dpll_per_m2_div4_ck",
1267 .prcm = {
1268 .omap4 = {
1269 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1270 .modulemode = MODULEMODE_SWCTRL,
1271 },
1272 },
1273 .dev_attr = &mcspi_attrib,
1274};
1275
1276/*
1277 * 'spinlock' class
1278 * spinlock provides hardware assistance for synchronizing the
1279 * processes running on multiple processors
1280 */
1281
1282static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
1283 .rev_offs = 0x0000,
1284 .sysc_offs = 0x0010,
1285 .syss_offs = 0x0014,
1286 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1287 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1288 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1289 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1290 .sysc_fields = &omap_hwmod_sysc_type1,
1291};
1292
1293static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1294 .name = "spinlock",
1295 .sysc = &am33xx_spinlock_sysc,
1296};
1297
1298static struct omap_hwmod am33xx_spinlock_hwmod = {
1299 .name = "spinlock",
1300 .class = &am33xx_spinlock_hwmod_class,
1301 .clkdm_name = "l4ls_clkdm",
1302 .main_clk = "l4ls_gclk",
1303 .prcm = {
1304 .omap4 = {
1305 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1306 .modulemode = MODULEMODE_SWCTRL,
1307 },
1308 },
1309};
1310
1311/* 'timer 2-7' class */
1312static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1313 .rev_offs = 0x0000,
1314 .sysc_offs = 0x0010,
1315 .syss_offs = 0x0014,
1316 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1318 SIDLE_SMART_WKUP),
1319 .sysc_fields = &omap_hwmod_sysc_type2,
1320};
1321
1322static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1323 .name = "timer",
1324 .sysc = &am33xx_timer_sysc,
1325};
1326
1327/* timer1 1ms */
1328static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1329 .rev_offs = 0x0000,
1330 .sysc_offs = 0x0010,
1331 .syss_offs = 0x0014,
1332 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1333 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1334 SYSS_HAS_RESET_STATUS),
1335 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1336 .sysc_fields = &omap_hwmod_sysc_type1,
1337};
1338
1339static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1340 .name = "timer",
1341 .sysc = &am33xx_timer1ms_sysc,
1342};
1343
1344static struct omap_hwmod am33xx_timer1_hwmod = {
1345 .name = "timer1",
1346 .class = &am33xx_timer1ms_hwmod_class,
1347 .clkdm_name = "l4_wkup_clkdm",
1348 .main_clk = "timer1_fck",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1352 .modulemode = MODULEMODE_SWCTRL,
1353 },
1354 },
1355};
1356
1357static struct omap_hwmod am33xx_timer2_hwmod = {
1358 .name = "timer2",
1359 .class = &am33xx_timer_hwmod_class,
1360 .clkdm_name = "l4ls_clkdm",
1361 .main_clk = "timer2_fck",
1362 .prcm = {
1363 .omap4 = {
1364 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1365 .modulemode = MODULEMODE_SWCTRL,
1366 },
1367 },
1368};
1369
1370static struct omap_hwmod am33xx_timer3_hwmod = {
1371 .name = "timer3",
1372 .class = &am33xx_timer_hwmod_class,
1373 .clkdm_name = "l4ls_clkdm",
1374 .main_clk = "timer3_fck",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1378 .modulemode = MODULEMODE_SWCTRL,
1379 },
1380 },
1381};
1382
1383static struct omap_hwmod am33xx_timer4_hwmod = {
1384 .name = "timer4",
1385 .class = &am33xx_timer_hwmod_class,
1386 .clkdm_name = "l4ls_clkdm",
1387 .main_clk = "timer4_fck",
1388 .prcm = {
1389 .omap4 = {
1390 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1391 .modulemode = MODULEMODE_SWCTRL,
1392 },
1393 },
1394};
1395
1396static struct omap_hwmod am33xx_timer5_hwmod = {
1397 .name = "timer5",
1398 .class = &am33xx_timer_hwmod_class,
1399 .clkdm_name = "l4ls_clkdm",
1400 .main_clk = "timer5_fck",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407};
1408
1409static struct omap_hwmod am33xx_timer6_hwmod = {
1410 .name = "timer6",
1411 .class = &am33xx_timer_hwmod_class,
1412 .clkdm_name = "l4ls_clkdm",
1413 .main_clk = "timer6_fck",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420};
1421
1422static struct omap_hwmod am33xx_timer7_hwmod = {
1423 .name = "timer7",
1424 .class = &am33xx_timer_hwmod_class,
1425 .clkdm_name = "l4ls_clkdm",
1426 .main_clk = "timer7_fck",
1427 .prcm = {
1428 .omap4 = {
1429 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1430 .modulemode = MODULEMODE_SWCTRL,
1431 },
1432 },
1433};
1434
1435/* tpcc */
1436static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1437 .name = "tpcc",
1438};
1439
1440static struct omap_hwmod am33xx_tpcc_hwmod = {
1441 .name = "tpcc",
1442 .class = &am33xx_tpcc_hwmod_class,
1443 .clkdm_name = "l3_clkdm",
1444 .main_clk = "l3_gclk",
1445 .prcm = {
1446 .omap4 = {
1447 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1448 .modulemode = MODULEMODE_SWCTRL,
1449 },
1450 },
1451};
1452
1453static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1454 .rev_offs = 0x0,
1455 .sysc_offs = 0x10,
1456 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1457 SYSC_HAS_MIDLEMODE),
1458 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1459 .sysc_fields = &omap_hwmod_sysc_type2,
1460};
1461
1462/* 'tptc' class */
1463static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1464 .name = "tptc",
1465 .sysc = &am33xx_tptc_sysc,
1466};
1467
1468/* tptc0 */
1469static struct omap_hwmod am33xx_tptc0_hwmod = {
1470 .name = "tptc0",
1471 .class = &am33xx_tptc_hwmod_class,
1472 .clkdm_name = "l3_clkdm",
1473 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1474 .main_clk = "l3_gclk",
1475 .prcm = {
1476 .omap4 = {
1477 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1479 },
1480 },
1481};
1482
1483/* tptc1 */
1484static struct omap_hwmod am33xx_tptc1_hwmod = {
1485 .name = "tptc1",
1486 .class = &am33xx_tptc_hwmod_class,
1487 .clkdm_name = "l3_clkdm",
1488 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1489 .main_clk = "l3_gclk",
1490 .prcm = {
1491 .omap4 = {
1492 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1493 .modulemode = MODULEMODE_SWCTRL,
1494 },
1495 },
1496};
1497
1498/* tptc2 */
1499static struct omap_hwmod am33xx_tptc2_hwmod = {
1500 .name = "tptc2",
1501 .class = &am33xx_tptc_hwmod_class,
1502 .clkdm_name = "l3_clkdm",
1503 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1504 .main_clk = "l3_gclk",
1505 .prcm = {
1506 .omap4 = {
1507 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1508 .modulemode = MODULEMODE_SWCTRL,
1509 },
1510 },
1511};
1512
1513/* 'uart' class */
1514static struct omap_hwmod_class_sysconfig uart_sysc = {
1515 .rev_offs = 0x50,
1516 .sysc_offs = 0x54,
1517 .syss_offs = 0x58,
1518 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1519 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1520 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1521 SIDLE_SMART_WKUP),
1522 .sysc_fields = &omap_hwmod_sysc_type1,
1523};
1524
1525static struct omap_hwmod_class uart_class = {
1526 .name = "uart",
1527 .sysc = &uart_sysc,
1528};
1529
1530/* uart1 */
1531static struct omap_hwmod am33xx_uart1_hwmod = {
1532 .name = "uart1",
1533 .class = &uart_class,
1534 .clkdm_name = "l4_wkup_clkdm",
1535 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1536 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1537 .prcm = {
1538 .omap4 = {
1539 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1540 .modulemode = MODULEMODE_SWCTRL,
1541 },
1542 },
1543};
1544
1545static struct omap_hwmod am33xx_uart2_hwmod = {
1546 .name = "uart2",
1547 .class = &uart_class,
1548 .clkdm_name = "l4ls_clkdm",
1549 .flags = HWMOD_SWSUP_SIDLE_ACT,
1550 .main_clk = "dpll_per_m2_div4_ck",
1551 .prcm = {
1552 .omap4 = {
1553 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1554 .modulemode = MODULEMODE_SWCTRL,
1555 },
1556 },
1557};
1558
1559/* uart3 */
1560static struct omap_hwmod am33xx_uart3_hwmod = {
1561 .name = "uart3",
1562 .class = &uart_class,
1563 .clkdm_name = "l4ls_clkdm",
1564 .flags = HWMOD_SWSUP_SIDLE_ACT,
1565 .main_clk = "dpll_per_m2_div4_ck",
1566 .prcm = {
1567 .omap4 = {
1568 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1569 .modulemode = MODULEMODE_SWCTRL,
1570 },
1571 },
1572};
1573
1574static struct omap_hwmod am33xx_uart4_hwmod = {
1575 .name = "uart4",
1576 .class = &uart_class,
1577 .clkdm_name = "l4ls_clkdm",
1578 .flags = HWMOD_SWSUP_SIDLE_ACT,
1579 .main_clk = "dpll_per_m2_div4_ck",
1580 .prcm = {
1581 .omap4 = {
1582 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1583 .modulemode = MODULEMODE_SWCTRL,
1584 },
1585 },
1586};
1587
1588static struct omap_hwmod am33xx_uart5_hwmod = {
1589 .name = "uart5",
1590 .class = &uart_class,
1591 .clkdm_name = "l4ls_clkdm",
1592 .flags = HWMOD_SWSUP_SIDLE_ACT,
1593 .main_clk = "dpll_per_m2_div4_ck",
1594 .prcm = {
1595 .omap4 = {
1596 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1597 .modulemode = MODULEMODE_SWCTRL,
1598 },
1599 },
1600};
1601
1602static struct omap_hwmod am33xx_uart6_hwmod = {
1603 .name = "uart6",
1604 .class = &uart_class,
1605 .clkdm_name = "l4ls_clkdm",
1606 .flags = HWMOD_SWSUP_SIDLE_ACT,
1607 .main_clk = "dpll_per_m2_div4_ck",
1608 .prcm = {
1609 .omap4 = {
1610 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
1611 .modulemode = MODULEMODE_SWCTRL,
1612 },
1613 },
1614};
1615
1616/* 'wd_timer' class */
1617static struct omap_hwmod_class_sysconfig wdt_sysc = {
1618 .rev_offs = 0x0,
1619 .sysc_offs = 0x10,
1620 .syss_offs = 0x14,
1621 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1622 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1623 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1624 SIDLE_SMART_WKUP),
1625 .sysc_fields = &omap_hwmod_sysc_type1,
1626};
1627
1628static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1629 .name = "wd_timer",
1630 .sysc = &wdt_sysc,
1631 .pre_shutdown = &omap2_wd_timer_disable,
1632};
1633
1634/*
1635 * XXX: device.c file uses hardcoded name for watchdog timer
1636 * driver "wd_timer2, so we are also using same name as of now...
1637 */
1638static struct omap_hwmod am33xx_wd_timer1_hwmod = {
1639 .name = "wd_timer2",
1640 .class = &am33xx_wd_timer_hwmod_class,
1641 .clkdm_name = "l4_wkup_clkdm",
1642 .flags = HWMOD_SWSUP_SIDLE,
1643 .main_clk = "wdt1_fck",
1644 .prcm = {
1645 .omap4 = {
1646 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
1647 .modulemode = MODULEMODE_SWCTRL,
1648 },
1649 },
1650};
1651
1652/*
1653 * 'usb_otg' class 301 * 'usb_otg' class
1654 * high-speed on-the-go universal serial bus (usb_otg) controller 302 * high-speed on-the-go universal serial bus (usb_otg) controller
1655 */ 303 */
@@ -1703,14 +351,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
1703 .user = OCP_USER_MPU | OCP_USER_SDMA, 351 .user = OCP_USER_MPU | OCP_USER_SDMA,
1704}; 352};
1705 353
1706/* mpu -> l3 main */
1707static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
1708 .master = &am33xx_mpu_hwmod,
1709 .slave = &am33xx_l3_main_hwmod,
1710 .clk = "dpll_mpu_m2_ck",
1711 .user = OCP_USER_MPU,
1712};
1713
1714/* l3 main -> l4 hs */ 354/* l3 main -> l4 hs */
1715static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { 355static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
1716 .master = &am33xx_l3_main_hwmod, 356 .master = &am33xx_l3_main_hwmod,
@@ -1719,62 +359,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
1719 .user = OCP_USER_MPU | OCP_USER_SDMA, 359 .user = OCP_USER_MPU | OCP_USER_SDMA,
1720}; 360};
1721 361
1722/* l3 main -> l3 s */
1723static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
1724 .master = &am33xx_l3_main_hwmod,
1725 .slave = &am33xx_l3_s_hwmod,
1726 .clk = "l3s_gclk",
1727 .user = OCP_USER_MPU | OCP_USER_SDMA,
1728};
1729
1730/* l3 s -> l4 per/ls */
1731static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
1732 .master = &am33xx_l3_s_hwmod,
1733 .slave = &am33xx_l4_ls_hwmod,
1734 .clk = "l3s_gclk",
1735 .user = OCP_USER_MPU | OCP_USER_SDMA,
1736};
1737
1738/* l3 s -> l4 wkup */
1739static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
1740 .master = &am33xx_l3_s_hwmod,
1741 .slave = &am33xx_l4_wkup_hwmod,
1742 .clk = "l3s_gclk",
1743 .user = OCP_USER_MPU | OCP_USER_SDMA,
1744};
1745
1746/* l3 main -> l3 instr */
1747static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
1748 .master = &am33xx_l3_main_hwmod,
1749 .slave = &am33xx_l3_instr_hwmod,
1750 .clk = "l3s_gclk",
1751 .user = OCP_USER_MPU | OCP_USER_SDMA,
1752};
1753
1754/* mpu -> prcm */
1755static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
1756 .master = &am33xx_mpu_hwmod,
1757 .slave = &am33xx_prcm_hwmod,
1758 .clk = "dpll_mpu_m2_ck",
1759 .user = OCP_USER_MPU | OCP_USER_SDMA,
1760};
1761
1762/* l3 s -> l3 main*/
1763static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
1764 .master = &am33xx_l3_s_hwmod,
1765 .slave = &am33xx_l3_main_hwmod,
1766 .clk = "l3s_gclk",
1767 .user = OCP_USER_MPU | OCP_USER_SDMA,
1768};
1769
1770/* pru-icss -> l3 main */
1771static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
1772 .master = &am33xx_pruss_hwmod,
1773 .slave = &am33xx_l3_main_hwmod,
1774 .clk = "l3_gclk",
1775 .user = OCP_USER_MPU | OCP_USER_SDMA,
1776};
1777
1778/* wkup m3 -> l4 wkup */ 362/* wkup m3 -> l4 wkup */
1779static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { 363static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
1780 .master = &am33xx_wkup_m3_hwmod, 364 .master = &am33xx_wkup_m3_hwmod,
@@ -1783,14 +367,6 @@ static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
1783 .user = OCP_USER_MPU | OCP_USER_SDMA, 367 .user = OCP_USER_MPU | OCP_USER_SDMA,
1784}; 368};
1785 369
1786/* gfx -> l3 main */
1787static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
1788 .master = &am33xx_gfx_hwmod,
1789 .slave = &am33xx_l3_main_hwmod,
1790 .clk = "dpll_core_m4_ck",
1791 .user = OCP_USER_MPU | OCP_USER_SDMA,
1792};
1793
1794/* l4 wkup -> wkup m3 */ 370/* l4 wkup -> wkup m3 */
1795static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { 371static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
1796 .master = &am33xx_l4_wkup_hwmod, 372 .master = &am33xx_l4_wkup_hwmod,
@@ -1807,14 +383,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
1807 .user = OCP_USER_MPU | OCP_USER_SDMA, 383 .user = OCP_USER_MPU | OCP_USER_SDMA,
1808}; 384};
1809 385
1810/* l3 main -> gfx */
1811static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1812 .master = &am33xx_l3_main_hwmod,
1813 .slave = &am33xx_gfx_hwmod,
1814 .clk = "dpll_core_m4_ck",
1815 .user = OCP_USER_MPU | OCP_USER_SDMA,
1816};
1817
1818/* l3_main -> debugss */ 386/* l3_main -> debugss */
1819static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { 387static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
1820 { 388 {
@@ -1857,54 +425,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
1857 .user = OCP_USER_MPU, 425 .user = OCP_USER_MPU,
1858}; 426};
1859 427
1860/* l4 wkup -> rtc */
1861static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
1862 .master = &am33xx_l4_wkup_hwmod,
1863 .slave = &am33xx_rtc_hwmod,
1864 .clk = "clkdiv32k_ick",
1865 .user = OCP_USER_MPU,
1866};
1867
1868/* l4 per/ls -> DCAN0 */
1869static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
1870 .master = &am33xx_l4_ls_hwmod,
1871 .slave = &am33xx_dcan0_hwmod,
1872 .clk = "l4ls_gclk",
1873 .user = OCP_USER_MPU | OCP_USER_SDMA,
1874};
1875
1876/* l4 per/ls -> DCAN1 */
1877static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
1878 .master = &am33xx_l4_ls_hwmod,
1879 .slave = &am33xx_dcan1_hwmod,
1880 .clk = "l4ls_gclk",
1881 .user = OCP_USER_MPU | OCP_USER_SDMA,
1882};
1883
1884/* l4 per/ls -> GPIO2 */
1885static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
1886 .master = &am33xx_l4_ls_hwmod,
1887 .slave = &am33xx_gpio1_hwmod,
1888 .clk = "l4ls_gclk",
1889 .user = OCP_USER_MPU | OCP_USER_SDMA,
1890};
1891
1892/* l4 per/ls -> gpio3 */
1893static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
1894 .master = &am33xx_l4_ls_hwmod,
1895 .slave = &am33xx_gpio2_hwmod,
1896 .clk = "l4ls_gclk",
1897 .user = OCP_USER_MPU | OCP_USER_SDMA,
1898};
1899
1900/* l4 per/ls -> gpio4 */
1901static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
1902 .master = &am33xx_l4_ls_hwmod,
1903 .slave = &am33xx_gpio3_hwmod,
1904 .clk = "l4ls_gclk",
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
1908/* L4 WKUP -> I2C1 */ 428/* L4 WKUP -> I2C1 */
1909static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { 429static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
1910 .master = &am33xx_l4_wkup_hwmod, 430 .master = &am33xx_l4_wkup_hwmod,
@@ -1946,177 +466,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
1946 .user = OCP_USER_MPU, 466 .user = OCP_USER_MPU,
1947}; 467};
1948 468
1949static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
1950 .master = &am33xx_cpgmac0_hwmod,
1951 .slave = &am33xx_mdio_hwmod,
1952 .user = OCP_USER_MPU,
1953};
1954
1955static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
1956 {
1957 .pa_start = 0x48080000,
1958 .pa_end = 0x48080000 + SZ_8K - 1,
1959 .flags = ADDR_TYPE_RT
1960 },
1961 { }
1962};
1963
1964static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
1965 .master = &am33xx_l4_ls_hwmod,
1966 .slave = &am33xx_elm_hwmod,
1967 .clk = "l4ls_gclk",
1968 .addr = am33xx_elm_addr_space,
1969 .user = OCP_USER_MPU,
1970};
1971
1972static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
1973 {
1974 .pa_start = 0x48300000,
1975 .pa_end = 0x48300000 + SZ_16 - 1,
1976 .flags = ADDR_TYPE_RT
1977 },
1978 { }
1979};
1980
1981static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
1982 .master = &am33xx_l4_ls_hwmod,
1983 .slave = &am33xx_epwmss0_hwmod,
1984 .clk = "l4ls_gclk",
1985 .addr = am33xx_epwmss0_addr_space,
1986 .user = OCP_USER_MPU,
1987};
1988
1989static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
1990 .master = &am33xx_epwmss0_hwmod,
1991 .slave = &am33xx_ecap0_hwmod,
1992 .clk = "l4ls_gclk",
1993 .user = OCP_USER_MPU,
1994};
1995
1996static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
1997 .master = &am33xx_epwmss0_hwmod,
1998 .slave = &am33xx_eqep0_hwmod,
1999 .clk = "l4ls_gclk",
2000 .user = OCP_USER_MPU,
2001};
2002
2003static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2004 .master = &am33xx_epwmss0_hwmod,
2005 .slave = &am33xx_ehrpwm0_hwmod,
2006 .clk = "l4ls_gclk",
2007 .user = OCP_USER_MPU,
2008};
2009
2010
2011static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2012 {
2013 .pa_start = 0x48302000,
2014 .pa_end = 0x48302000 + SZ_16 - 1,
2015 .flags = ADDR_TYPE_RT
2016 },
2017 { }
2018};
2019
2020static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2021 .master = &am33xx_l4_ls_hwmod,
2022 .slave = &am33xx_epwmss1_hwmod,
2023 .clk = "l4ls_gclk",
2024 .addr = am33xx_epwmss1_addr_space,
2025 .user = OCP_USER_MPU,
2026};
2027
2028static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2029 .master = &am33xx_epwmss1_hwmod,
2030 .slave = &am33xx_ecap1_hwmod,
2031 .clk = "l4ls_gclk",
2032 .user = OCP_USER_MPU,
2033};
2034
2035static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2036 .master = &am33xx_epwmss1_hwmod,
2037 .slave = &am33xx_eqep1_hwmod,
2038 .clk = "l4ls_gclk",
2039 .user = OCP_USER_MPU,
2040};
2041
2042static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2043 .master = &am33xx_epwmss1_hwmod,
2044 .slave = &am33xx_ehrpwm1_hwmod,
2045 .clk = "l4ls_gclk",
2046 .user = OCP_USER_MPU,
2047};
2048
2049static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2050 {
2051 .pa_start = 0x48304000,
2052 .pa_end = 0x48304000 + SZ_16 - 1,
2053 .flags = ADDR_TYPE_RT
2054 },
2055 { }
2056};
2057
2058static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2059 .master = &am33xx_l4_ls_hwmod,
2060 .slave = &am33xx_epwmss2_hwmod,
2061 .clk = "l4ls_gclk",
2062 .addr = am33xx_epwmss2_addr_space,
2063 .user = OCP_USER_MPU,
2064};
2065
2066static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2067 .master = &am33xx_epwmss2_hwmod,
2068 .slave = &am33xx_ecap2_hwmod,
2069 .clk = "l4ls_gclk",
2070 .user = OCP_USER_MPU,
2071};
2072
2073static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2074 .master = &am33xx_epwmss2_hwmod,
2075 .slave = &am33xx_eqep2_hwmod,
2076 .clk = "l4ls_gclk",
2077 .user = OCP_USER_MPU,
2078};
2079
2080static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2081 .master = &am33xx_epwmss2_hwmod,
2082 .slave = &am33xx_ehrpwm2_hwmod,
2083 .clk = "l4ls_gclk",
2084 .user = OCP_USER_MPU,
2085};
2086
2087/* l3s cfg -> gpmc */
2088static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2089 {
2090 .pa_start = 0x50000000,
2091 .pa_end = 0x50000000 + SZ_8K - 1,
2092 .flags = ADDR_TYPE_RT,
2093 },
2094 { }
2095};
2096
2097static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2098 .master = &am33xx_l3_s_hwmod,
2099 .slave = &am33xx_gpmc_hwmod,
2100 .clk = "l3s_gclk",
2101 .addr = am33xx_gpmc_addr_space,
2102 .user = OCP_USER_MPU,
2103};
2104
2105/* i2c2 */
2106static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2107 .master = &am33xx_l4_ls_hwmod,
2108 .slave = &am33xx_i2c2_hwmod,
2109 .clk = "l4ls_gclk",
2110 .user = OCP_USER_MPU,
2111};
2112
2113static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2114 .master = &am33xx_l4_ls_hwmod,
2115 .slave = &am33xx_i2c3_hwmod,
2116 .clk = "l4ls_gclk",
2117 .user = OCP_USER_MPU,
2118};
2119
2120static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { 469static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2121 { 470 {
2122 .pa_start = 0x4830E000, 471 .pa_start = 0x4830E000,
@@ -2134,138 +483,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2134 .user = OCP_USER_MPU, 483 .user = OCP_USER_MPU,
2135}; 484};
2136 485
2137static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2138 {
2139 .pa_start = 0x480C8000,
2140 .pa_end = 0x480C8000 + (SZ_4K - 1),
2141 .flags = ADDR_TYPE_RT
2142 },
2143 { }
2144};
2145
2146/* l4 ls -> mailbox */
2147static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2148 .master = &am33xx_l4_ls_hwmod,
2149 .slave = &am33xx_mailbox_hwmod,
2150 .clk = "l4ls_gclk",
2151 .addr = am33xx_mailbox_addrs,
2152 .user = OCP_USER_MPU,
2153};
2154
2155/* l4 ls -> spinlock */
2156static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2157 .master = &am33xx_l4_ls_hwmod,
2158 .slave = &am33xx_spinlock_hwmod,
2159 .clk = "l4ls_gclk",
2160 .user = OCP_USER_MPU,
2161};
2162
2163/* l4 ls -> mcasp0 */
2164static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2165 {
2166 .pa_start = 0x48038000,
2167 .pa_end = 0x48038000 + SZ_8K - 1,
2168 .flags = ADDR_TYPE_RT
2169 },
2170 { }
2171};
2172
2173static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2174 .master = &am33xx_l4_ls_hwmod,
2175 .slave = &am33xx_mcasp0_hwmod,
2176 .clk = "l4ls_gclk",
2177 .addr = am33xx_mcasp0_addr_space,
2178 .user = OCP_USER_MPU,
2179};
2180
2181/* l4 ls -> mcasp1 */
2182static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2183 {
2184 .pa_start = 0x4803C000,
2185 .pa_end = 0x4803C000 + SZ_8K - 1,
2186 .flags = ADDR_TYPE_RT
2187 },
2188 { }
2189};
2190
2191static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2192 .master = &am33xx_l4_ls_hwmod,
2193 .slave = &am33xx_mcasp1_hwmod,
2194 .clk = "l4ls_gclk",
2195 .addr = am33xx_mcasp1_addr_space,
2196 .user = OCP_USER_MPU,
2197};
2198
2199/* l4 ls -> mmc0 */
2200static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2201 {
2202 .pa_start = 0x48060100,
2203 .pa_end = 0x48060100 + SZ_4K - 1,
2204 .flags = ADDR_TYPE_RT,
2205 },
2206 { }
2207};
2208
2209static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2210 .master = &am33xx_l4_ls_hwmod,
2211 .slave = &am33xx_mmc0_hwmod,
2212 .clk = "l4ls_gclk",
2213 .addr = am33xx_mmc0_addr_space,
2214 .user = OCP_USER_MPU,
2215};
2216
2217/* l4 ls -> mmc1 */
2218static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2219 {
2220 .pa_start = 0x481d8100,
2221 .pa_end = 0x481d8100 + SZ_4K - 1,
2222 .flags = ADDR_TYPE_RT,
2223 },
2224 { }
2225};
2226
2227static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2228 .master = &am33xx_l4_ls_hwmod,
2229 .slave = &am33xx_mmc1_hwmod,
2230 .clk = "l4ls_gclk",
2231 .addr = am33xx_mmc1_addr_space,
2232 .user = OCP_USER_MPU,
2233};
2234
2235/* l3 s -> mmc2 */
2236static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2237 {
2238 .pa_start = 0x47810100,
2239 .pa_end = 0x47810100 + SZ_64K - 1,
2240 .flags = ADDR_TYPE_RT,
2241 },
2242 { }
2243};
2244
2245static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2246 .master = &am33xx_l3_s_hwmod,
2247 .slave = &am33xx_mmc2_hwmod,
2248 .clk = "l3s_gclk",
2249 .addr = am33xx_mmc2_addr_space,
2250 .user = OCP_USER_MPU,
2251};
2252
2253/* l4 ls -> mcspi0 */
2254static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2255 .master = &am33xx_l4_ls_hwmod,
2256 .slave = &am33xx_spi0_hwmod,
2257 .clk = "l4ls_gclk",
2258 .user = OCP_USER_MPU,
2259};
2260
2261/* l4 ls -> mcspi1 */
2262static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2263 .master = &am33xx_l4_ls_hwmod,
2264 .slave = &am33xx_spi1_hwmod,
2265 .clk = "l4ls_gclk",
2266 .user = OCP_USER_MPU,
2267};
2268
2269/* l4 wkup -> timer1 */ 486/* l4 wkup -> timer1 */
2270static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { 487static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2271 .master = &am33xx_l4_wkup_hwmod, 488 .master = &am33xx_l4_wkup_hwmod,
@@ -2274,116 +491,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2274 .user = OCP_USER_MPU, 491 .user = OCP_USER_MPU,
2275}; 492};
2276 493
2277/* l4 per -> timer2 */
2278static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
2279 .master = &am33xx_l4_ls_hwmod,
2280 .slave = &am33xx_timer2_hwmod,
2281 .clk = "l4ls_gclk",
2282 .user = OCP_USER_MPU,
2283};
2284
2285/* l4 per -> timer3 */
2286static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
2287 .master = &am33xx_l4_ls_hwmod,
2288 .slave = &am33xx_timer3_hwmod,
2289 .clk = "l4ls_gclk",
2290 .user = OCP_USER_MPU,
2291};
2292
2293/* l4 per -> timer4 */
2294static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
2295 .master = &am33xx_l4_ls_hwmod,
2296 .slave = &am33xx_timer4_hwmod,
2297 .clk = "l4ls_gclk",
2298 .user = OCP_USER_MPU,
2299};
2300
2301/* l4 per -> timer5 */
2302static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
2303 .master = &am33xx_l4_ls_hwmod,
2304 .slave = &am33xx_timer5_hwmod,
2305 .clk = "l4ls_gclk",
2306 .user = OCP_USER_MPU,
2307};
2308
2309/* l4 per -> timer6 */
2310static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
2311 .master = &am33xx_l4_ls_hwmod,
2312 .slave = &am33xx_timer6_hwmod,
2313 .clk = "l4ls_gclk",
2314 .user = OCP_USER_MPU,
2315};
2316
2317/* l4 per -> timer7 */
2318static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
2319 .master = &am33xx_l4_ls_hwmod,
2320 .slave = &am33xx_timer7_hwmod,
2321 .clk = "l4ls_gclk",
2322 .user = OCP_USER_MPU,
2323};
2324
2325/* l3 main -> tpcc */
2326static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
2327 .master = &am33xx_l3_main_hwmod,
2328 .slave = &am33xx_tpcc_hwmod,
2329 .clk = "l3_gclk",
2330 .user = OCP_USER_MPU,
2331};
2332
2333/* l3 main -> tpcc0 */
2334static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2335 {
2336 .pa_start = 0x49800000,
2337 .pa_end = 0x49800000 + SZ_8K - 1,
2338 .flags = ADDR_TYPE_RT,
2339 },
2340 { }
2341};
2342
2343static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2344 .master = &am33xx_l3_main_hwmod,
2345 .slave = &am33xx_tptc0_hwmod,
2346 .clk = "l3_gclk",
2347 .addr = am33xx_tptc0_addr_space,
2348 .user = OCP_USER_MPU,
2349};
2350
2351/* l3 main -> tpcc1 */
2352static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2353 {
2354 .pa_start = 0x49900000,
2355 .pa_end = 0x49900000 + SZ_8K - 1,
2356 .flags = ADDR_TYPE_RT,
2357 },
2358 { }
2359};
2360
2361static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2362 .master = &am33xx_l3_main_hwmod,
2363 .slave = &am33xx_tptc1_hwmod,
2364 .clk = "l3_gclk",
2365 .addr = am33xx_tptc1_addr_space,
2366 .user = OCP_USER_MPU,
2367};
2368
2369/* l3 main -> tpcc2 */
2370static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2371 {
2372 .pa_start = 0x49a00000,
2373 .pa_end = 0x49a00000 + SZ_8K - 1,
2374 .flags = ADDR_TYPE_RT,
2375 },
2376 { }
2377};
2378
2379static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2380 .master = &am33xx_l3_main_hwmod,
2381 .slave = &am33xx_tptc2_hwmod,
2382 .clk = "l3_gclk",
2383 .addr = am33xx_tptc2_addr_space,
2384 .user = OCP_USER_MPU,
2385};
2386
2387/* l4 wkup -> uart1 */ 494/* l4 wkup -> uart1 */
2388static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { 495static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2389 .master = &am33xx_l4_wkup_hwmod, 496 .master = &am33xx_l4_wkup_hwmod,
@@ -2392,46 +499,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2392 .user = OCP_USER_MPU, 499 .user = OCP_USER_MPU,
2393}; 500};
2394 501
2395/* l4 ls -> uart2 */
2396static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2397 .master = &am33xx_l4_ls_hwmod,
2398 .slave = &am33xx_uart2_hwmod,
2399 .clk = "l4ls_gclk",
2400 .user = OCP_USER_MPU,
2401};
2402
2403/* l4 ls -> uart3 */
2404static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2405 .master = &am33xx_l4_ls_hwmod,
2406 .slave = &am33xx_uart3_hwmod,
2407 .clk = "l4ls_gclk",
2408 .user = OCP_USER_MPU,
2409};
2410
2411/* l4 ls -> uart4 */
2412static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2413 .master = &am33xx_l4_ls_hwmod,
2414 .slave = &am33xx_uart4_hwmod,
2415 .clk = "l4ls_gclk",
2416 .user = OCP_USER_MPU,
2417};
2418
2419/* l4 ls -> uart5 */
2420static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2421 .master = &am33xx_l4_ls_hwmod,
2422 .slave = &am33xx_uart5_hwmod,
2423 .clk = "l4ls_gclk",
2424 .user = OCP_USER_MPU,
2425};
2426
2427/* l4 ls -> uart6 */
2428static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2429 .master = &am33xx_l4_ls_hwmod,
2430 .slave = &am33xx_uart6_hwmod,
2431 .clk = "l4ls_gclk",
2432 .user = OCP_USER_MPU,
2433};
2434
2435/* l4 wkup -> wd_timer1 */ 502/* l4 wkup -> wd_timer1 */
2436static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { 503static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
2437 .master = &am33xx_l4_wkup_hwmod, 504 .master = &am33xx_l4_wkup_hwmod,
@@ -2450,49 +517,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
2450 .flags = OCPIF_SWSUP_IDLE, 517 .flags = OCPIF_SWSUP_IDLE,
2451}; 518};
2452 519
2453/* l3 main -> ocmc */
2454static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
2455 .master = &am33xx_l3_main_hwmod,
2456 .slave = &am33xx_ocmcram_hwmod,
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2458};
2459
2460/* l3 main -> sha0 HIB2 */
2461static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
2462 {
2463 .pa_start = 0x53100000,
2464 .pa_end = 0x53100000 + SZ_512 - 1,
2465 .flags = ADDR_TYPE_RT
2466 },
2467 { }
2468};
2469
2470static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
2471 .master = &am33xx_l3_main_hwmod,
2472 .slave = &am33xx_sha0_hwmod,
2473 .clk = "sha0_fck",
2474 .addr = am33xx_sha0_addrs,
2475 .user = OCP_USER_MPU | OCP_USER_SDMA,
2476};
2477
2478/* l3 main -> AES0 HIB2 */
2479static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
2480 {
2481 .pa_start = 0x53500000,
2482 .pa_end = 0x53500000 + SZ_1M - 1,
2483 .flags = ADDR_TYPE_RT
2484 },
2485 { }
2486};
2487
2488static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
2489 .master = &am33xx_l3_main_hwmod,
2490 .slave = &am33xx_aes0_hwmod,
2491 .clk = "aes0_fck",
2492 .addr = am33xx_aes0_addrs,
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494};
2495
2496/* rng */ 520/* rng */
2497static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { 521static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
2498 .rev_offs = 0x1fe0, 522 .rev_offs = 0x1fe0,
@@ -2613,6 +637,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2613 637
2614int __init am33xx_hwmod_init(void) 638int __init am33xx_hwmod_init(void)
2615{ 639{
640 omap_hwmod_am33xx_reg();
2616 omap_hwmod_init(); 641 omap_hwmod_init();
2617 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); 642 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
2618} 643}
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
new file mode 100644
index 000000000000..9002fca76699
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -0,0 +1,758 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h"
22
23/* IP blocks */
24static struct omap_hwmod am43xx_l4_hs_hwmod = {
25 .name = "l4_hs",
26 .class = &am33xx_l4_hwmod_class,
27 .clkdm_name = "l3_clkdm",
28 .flags = HWMOD_INIT_NO_IDLE,
29 .main_clk = "l4hs_gclk",
30 .prcm = {
31 .omap4 = {
32 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
33 .modulemode = MODULEMODE_SWCTRL,
34 },
35 },
36};
37
38static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
39 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
40};
41
42static struct omap_hwmod am43xx_wkup_m3_hwmod = {
43 .name = "wkup_m3",
44 .class = &am33xx_wkup_m3_hwmod_class,
45 .clkdm_name = "l4_wkup_aon_clkdm",
46 /* Keep hardreset asserted */
47 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
48 .main_clk = "sys_clkin_ck",
49 .prcm = {
50 .omap4 = {
51 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
52 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
53 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 .rst_lines = am33xx_wkup_m3_resets,
58 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
59};
60
61static struct omap_hwmod am43xx_control_hwmod = {
62 .name = "control",
63 .class = &am33xx_control_hwmod_class,
64 .clkdm_name = "l4_wkup_clkdm",
65 .flags = HWMOD_INIT_NO_IDLE,
66 .main_clk = "sys_clkin_ck",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
70 .modulemode = MODULEMODE_SWCTRL,
71 },
72 },
73};
74
75static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
76 { .role = "dbclk", .clk = "gpio0_dbclk" },
77};
78
79static struct omap_hwmod am43xx_gpio0_hwmod = {
80 .name = "gpio1",
81 .class = &am33xx_gpio_hwmod_class,
82 .clkdm_name = "l4_wkup_clkdm",
83 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
84 .main_clk = "sys_clkin_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 .opt_clks = gpio0_opt_clks,
92 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
93 .dev_attr = &gpio_dev_attr,
94};
95
96static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
97 .rev_offs = 0x0,
98 .sysc_offs = 0x4,
99 .sysc_flags = SYSC_HAS_SIDLEMODE,
100 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
101 .sysc_fields = &omap_hwmod_sysc_type1,
102};
103
104static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
105 .name = "synctimer",
106 .sysc = &am43xx_synctimer_sysc,
107};
108
109static struct omap_hwmod am43xx_synctimer_hwmod = {
110 .name = "counter_32k",
111 .class = &am43xx_synctimer_hwmod_class,
112 .clkdm_name = "l4_wkup_aon_clkdm",
113 .flags = HWMOD_SWSUP_SIDLE,
114 .main_clk = "synctimer_32kclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121};
122
123static struct omap_hwmod am43xx_timer8_hwmod = {
124 .name = "timer8",
125 .class = &am33xx_timer_hwmod_class,
126 .clkdm_name = "l4ls_clkdm",
127 .main_clk = "timer8_fck",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
131 .modulemode = MODULEMODE_SWCTRL,
132 },
133 },
134};
135
136static struct omap_hwmod am43xx_timer9_hwmod = {
137 .name = "timer9",
138 .class = &am33xx_timer_hwmod_class,
139 .clkdm_name = "l4ls_clkdm",
140 .main_clk = "timer9_fck",
141 .prcm = {
142 .omap4 = {
143 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
144 .modulemode = MODULEMODE_SWCTRL,
145 },
146 },
147};
148
149static struct omap_hwmod am43xx_timer10_hwmod = {
150 .name = "timer10",
151 .class = &am33xx_timer_hwmod_class,
152 .clkdm_name = "l4ls_clkdm",
153 .main_clk = "timer10_fck",
154 .prcm = {
155 .omap4 = {
156 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
157 .modulemode = MODULEMODE_SWCTRL,
158 },
159 },
160};
161
162static struct omap_hwmod am43xx_timer11_hwmod = {
163 .name = "timer11",
164 .class = &am33xx_timer_hwmod_class,
165 .clkdm_name = "l4ls_clkdm",
166 .main_clk = "timer11_fck",
167 .prcm = {
168 .omap4 = {
169 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
170 .modulemode = MODULEMODE_SWCTRL,
171 },
172 },
173};
174
175static struct omap_hwmod am43xx_epwmss3_hwmod = {
176 .name = "epwmss3",
177 .class = &am33xx_epwmss_hwmod_class,
178 .clkdm_name = "l4ls_clkdm",
179 .main_clk = "l4ls_gclk",
180 .prcm = {
181 .omap4 = {
182 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
183 .modulemode = MODULEMODE_SWCTRL,
184 },
185 },
186};
187
188static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
189 .name = "ehrpwm3",
190 .class = &am33xx_ehrpwm_hwmod_class,
191 .clkdm_name = "l4ls_clkdm",
192 .main_clk = "l4ls_gclk",
193};
194
195static struct omap_hwmod am43xx_epwmss4_hwmod = {
196 .name = "epwmss4",
197 .class = &am33xx_epwmss_hwmod_class,
198 .clkdm_name = "l4ls_clkdm",
199 .main_clk = "l4ls_gclk",
200 .prcm = {
201 .omap4 = {
202 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
203 .modulemode = MODULEMODE_SWCTRL,
204 },
205 },
206};
207
208static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
209 .name = "ehrpwm4",
210 .class = &am33xx_ehrpwm_hwmod_class,
211 .clkdm_name = "l4ls_clkdm",
212 .main_clk = "l4ls_gclk",
213};
214
215static struct omap_hwmod am43xx_epwmss5_hwmod = {
216 .name = "epwmss5",
217 .class = &am33xx_epwmss_hwmod_class,
218 .clkdm_name = "l4ls_clkdm",
219 .main_clk = "l4ls_gclk",
220 .prcm = {
221 .omap4 = {
222 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
223 .modulemode = MODULEMODE_SWCTRL,
224 },
225 },
226};
227
228static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
229 .name = "ehrpwm5",
230 .class = &am33xx_ehrpwm_hwmod_class,
231 .clkdm_name = "l4ls_clkdm",
232 .main_clk = "l4ls_gclk",
233};
234
235static struct omap_hwmod am43xx_spi2_hwmod = {
236 .name = "spi2",
237 .class = &am33xx_spi_hwmod_class,
238 .clkdm_name = "l4ls_clkdm",
239 .main_clk = "dpll_per_m2_div4_ck",
240 .prcm = {
241 .omap4 = {
242 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
243 .modulemode = MODULEMODE_SWCTRL,
244 },
245 },
246 .dev_attr = &mcspi_attrib,
247};
248
249static struct omap_hwmod am43xx_spi3_hwmod = {
250 .name = "spi3",
251 .class = &am33xx_spi_hwmod_class,
252 .clkdm_name = "l4ls_clkdm",
253 .main_clk = "dpll_per_m2_div4_ck",
254 .prcm = {
255 .omap4 = {
256 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
257 .modulemode = MODULEMODE_SWCTRL,
258 },
259 },
260 .dev_attr = &mcspi_attrib,
261};
262
263static struct omap_hwmod am43xx_spi4_hwmod = {
264 .name = "spi4",
265 .class = &am33xx_spi_hwmod_class,
266 .clkdm_name = "l4ls_clkdm",
267 .main_clk = "dpll_per_m2_div4_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
271 .modulemode = MODULEMODE_SWCTRL,
272 },
273 },
274 .dev_attr = &mcspi_attrib,
275};
276
277static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
278 { .role = "dbclk", .clk = "gpio4_dbclk" },
279};
280
281static struct omap_hwmod am43xx_gpio4_hwmod = {
282 .name = "gpio5",
283 .class = &am33xx_gpio_hwmod_class,
284 .clkdm_name = "l4ls_clkdm",
285 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
286 .main_clk = "l4ls_gclk",
287 .prcm = {
288 .omap4 = {
289 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
290 .modulemode = MODULEMODE_SWCTRL,
291 },
292 },
293 .opt_clks = gpio4_opt_clks,
294 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
295 .dev_attr = &gpio_dev_attr,
296};
297
298static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
299 { .role = "dbclk", .clk = "gpio5_dbclk" },
300};
301
302static struct omap_hwmod am43xx_gpio5_hwmod = {
303 .name = "gpio6",
304 .class = &am33xx_gpio_hwmod_class,
305 .clkdm_name = "l4ls_clkdm",
306 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
307 .main_clk = "l4ls_gclk",
308 .prcm = {
309 .omap4 = {
310 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 .opt_clks = gpio5_opt_clks,
315 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
316 .dev_attr = &gpio_dev_attr,
317};
318
319static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
320 .name = "ocp2scp",
321};
322
323static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
324 .name = "ocp2scp0",
325 .class = &am43xx_ocp2scp_hwmod_class,
326 .clkdm_name = "l4ls_clkdm",
327 .main_clk = "l4ls_gclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
332 },
333 },
334};
335
336static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
337 .name = "ocp2scp1",
338 .class = &am43xx_ocp2scp_hwmod_class,
339 .clkdm_name = "l4ls_clkdm",
340 .main_clk = "l4ls_gclk",
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
344 .modulemode = MODULEMODE_SWCTRL,
345 },
346 },
347};
348
349static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
350 .rev_offs = 0x0000,
351 .sysc_offs = 0x0010,
352 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
353 SYSC_HAS_SIDLEMODE),
354 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
355 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
356 MSTANDBY_NO | MSTANDBY_SMART |
357 MSTANDBY_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359};
360
361static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
362 .name = "usb_otg_ss",
363 .sysc = &am43xx_usb_otg_ss_sysc,
364};
365
366static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
367 .name = "usb_otg_ss0",
368 .class = &am43xx_usb_otg_ss_hwmod_class,
369 .clkdm_name = "l3s_clkdm",
370 .main_clk = "l3s_gclk",
371 .prcm = {
372 .omap4 = {
373 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
374 .modulemode = MODULEMODE_SWCTRL,
375 },
376 },
377};
378
379static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
380 .name = "usb_otg_ss1",
381 .class = &am43xx_usb_otg_ss_hwmod_class,
382 .clkdm_name = "l3s_clkdm",
383 .main_clk = "l3s_gclk",
384 .prcm = {
385 .omap4 = {
386 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
387 .modulemode = MODULEMODE_SWCTRL,
388 },
389 },
390};
391
392static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
393 .sysc_offs = 0x0010,
394 .sysc_flags = SYSC_HAS_SIDLEMODE,
395 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 SIDLE_SMART_WKUP),
397 .sysc_fields = &omap_hwmod_sysc_type2,
398};
399
400static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
401 .name = "qspi",
402 .sysc = &am43xx_qspi_sysc,
403};
404
405static struct omap_hwmod am43xx_qspi_hwmod = {
406 .name = "qspi",
407 .class = &am43xx_qspi_hwmod_class,
408 .clkdm_name = "l3s_clkdm",
409 .main_clk = "l3s_gclk",
410 .prcm = {
411 .omap4 = {
412 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
413 .modulemode = MODULEMODE_SWCTRL,
414 },
415 },
416};
417
418/* Interfaces */
419static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
420 .master = &am33xx_l3_main_hwmod,
421 .slave = &am43xx_l4_hs_hwmod,
422 .clk = "l3s_gclk",
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424};
425
426static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
427 .master = &am43xx_wkup_m3_hwmod,
428 .slave = &am33xx_l4_wkup_hwmod,
429 .clk = "sys_clkin_ck",
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
433static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
434 .master = &am33xx_l4_wkup_hwmod,
435 .slave = &am43xx_wkup_m3_hwmod,
436 .clk = "sys_clkin_ck",
437 .user = OCP_USER_MPU | OCP_USER_SDMA,
438};
439
440static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
441 .master = &am33xx_l3_main_hwmod,
442 .slave = &am33xx_pruss_hwmod,
443 .clk = "dpll_core_m4_ck",
444 .user = OCP_USER_MPU,
445};
446
447static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
448 .master = &am33xx_l4_wkup_hwmod,
449 .slave = &am33xx_smartreflex0_hwmod,
450 .clk = "sys_clkin_ck",
451 .user = OCP_USER_MPU,
452};
453
454static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
455 .master = &am33xx_l4_wkup_hwmod,
456 .slave = &am33xx_smartreflex1_hwmod,
457 .clk = "sys_clkin_ck",
458 .user = OCP_USER_MPU,
459};
460
461static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
462 .master = &am33xx_l4_wkup_hwmod,
463 .slave = &am43xx_control_hwmod,
464 .clk = "sys_clkin_ck",
465 .user = OCP_USER_MPU,
466};
467
468static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
469 .master = &am33xx_l4_wkup_hwmod,
470 .slave = &am33xx_i2c1_hwmod,
471 .clk = "sys_clkin_ck",
472 .user = OCP_USER_MPU,
473};
474
475static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
476 .master = &am33xx_l4_wkup_hwmod,
477 .slave = &am43xx_gpio0_hwmod,
478 .clk = "sys_clkin_ck",
479 .user = OCP_USER_MPU | OCP_USER_SDMA,
480};
481
482static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
483 .master = &am43xx_l4_hs_hwmod,
484 .slave = &am33xx_cpgmac0_hwmod,
485 .clk = "cpsw_125mhz_gclk",
486 .user = OCP_USER_MPU,
487};
488
489static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
490 .master = &am33xx_l4_wkup_hwmod,
491 .slave = &am33xx_timer1_hwmod,
492 .clk = "sys_clkin_ck",
493 .user = OCP_USER_MPU,
494};
495
496static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
497 .master = &am33xx_l4_wkup_hwmod,
498 .slave = &am33xx_uart1_hwmod,
499 .clk = "sys_clkin_ck",
500 .user = OCP_USER_MPU,
501};
502
503static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
504 .master = &am33xx_l4_wkup_hwmod,
505 .slave = &am33xx_wd_timer1_hwmod,
506 .clk = "sys_clkin_ck",
507 .user = OCP_USER_MPU,
508};
509
510static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
511 .master = &am33xx_l4_wkup_hwmod,
512 .slave = &am43xx_synctimer_hwmod,
513 .clk = "sys_clkin_ck",
514 .user = OCP_USER_MPU,
515};
516
517static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
518 .master = &am33xx_l4_ls_hwmod,
519 .slave = &am43xx_timer8_hwmod,
520 .clk = "l4ls_gclk",
521 .user = OCP_USER_MPU,
522};
523
524static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
525 .master = &am33xx_l4_ls_hwmod,
526 .slave = &am43xx_timer9_hwmod,
527 .clk = "l4ls_gclk",
528 .user = OCP_USER_MPU,
529};
530
531static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
532 .master = &am33xx_l4_ls_hwmod,
533 .slave = &am43xx_timer10_hwmod,
534 .clk = "l4ls_gclk",
535 .user = OCP_USER_MPU,
536};
537
538static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
539 .master = &am33xx_l4_ls_hwmod,
540 .slave = &am43xx_timer11_hwmod,
541 .clk = "l4ls_gclk",
542 .user = OCP_USER_MPU,
543};
544
545static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
546 .master = &am33xx_l4_ls_hwmod,
547 .slave = &am43xx_epwmss3_hwmod,
548 .clk = "l4ls_gclk",
549 .user = OCP_USER_MPU,
550};
551
552static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
553 .master = &am43xx_epwmss3_hwmod,
554 .slave = &am43xx_ehrpwm3_hwmod,
555 .clk = "l4ls_gclk",
556 .user = OCP_USER_MPU,
557};
558
559static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
560 .master = &am33xx_l4_ls_hwmod,
561 .slave = &am43xx_epwmss4_hwmod,
562 .clk = "l4ls_gclk",
563 .user = OCP_USER_MPU,
564};
565
566static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
567 .master = &am43xx_epwmss4_hwmod,
568 .slave = &am43xx_ehrpwm4_hwmod,
569 .clk = "l4ls_gclk",
570 .user = OCP_USER_MPU,
571};
572
573static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
574 .master = &am33xx_l4_ls_hwmod,
575 .slave = &am43xx_epwmss5_hwmod,
576 .clk = "l4ls_gclk",
577 .user = OCP_USER_MPU,
578};
579
580static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
581 .master = &am43xx_epwmss5_hwmod,
582 .slave = &am43xx_ehrpwm5_hwmod,
583 .clk = "l4ls_gclk",
584 .user = OCP_USER_MPU,
585};
586
587static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
588 .master = &am33xx_l4_ls_hwmod,
589 .slave = &am43xx_spi2_hwmod,
590 .clk = "l4ls_gclk",
591 .user = OCP_USER_MPU,
592};
593
594static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
595 .master = &am33xx_l4_ls_hwmod,
596 .slave = &am43xx_spi3_hwmod,
597 .clk = "l4ls_gclk",
598 .user = OCP_USER_MPU,
599};
600
601static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
602 .master = &am33xx_l4_ls_hwmod,
603 .slave = &am43xx_spi4_hwmod,
604 .clk = "l4ls_gclk",
605 .user = OCP_USER_MPU,
606};
607
608static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
609 .master = &am33xx_l4_ls_hwmod,
610 .slave = &am43xx_gpio4_hwmod,
611 .clk = "l4ls_gclk",
612 .user = OCP_USER_MPU | OCP_USER_SDMA,
613};
614
615static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
616 .master = &am33xx_l4_ls_hwmod,
617 .slave = &am43xx_gpio5_hwmod,
618 .clk = "l4ls_gclk",
619 .user = OCP_USER_MPU | OCP_USER_SDMA,
620};
621
622static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
623 .master = &am33xx_l4_ls_hwmod,
624 .slave = &am43xx_ocp2scp0_hwmod,
625 .clk = "l4ls_gclk",
626 .user = OCP_USER_MPU,
627};
628
629static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
630 .master = &am33xx_l4_ls_hwmod,
631 .slave = &am43xx_ocp2scp1_hwmod,
632 .clk = "l4ls_gclk",
633 .user = OCP_USER_MPU,
634};
635
636static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
637 .master = &am33xx_l3_s_hwmod,
638 .slave = &am43xx_usb_otg_ss0_hwmod,
639 .clk = "l3s_gclk",
640 .user = OCP_USER_MPU | OCP_USER_SDMA,
641};
642
643static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
644 .master = &am33xx_l3_s_hwmod,
645 .slave = &am43xx_usb_otg_ss1_hwmod,
646 .clk = "l3s_gclk",
647 .user = OCP_USER_MPU | OCP_USER_SDMA,
648};
649
650static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
651 .master = &am33xx_l3_s_hwmod,
652 .slave = &am43xx_qspi_hwmod,
653 .clk = "l3s_gclk",
654 .user = OCP_USER_MPU | OCP_USER_SDMA,
655};
656
657static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
658 &am33xx_l4_wkup__synctimer,
659 &am43xx_l4_ls__timer8,
660 &am43xx_l4_ls__timer9,
661 &am43xx_l4_ls__timer10,
662 &am43xx_l4_ls__timer11,
663 &am43xx_l4_ls__epwmss3,
664 &am43xx_epwmss3__ehrpwm3,
665 &am43xx_l4_ls__epwmss4,
666 &am43xx_epwmss4__ehrpwm4,
667 &am43xx_l4_ls__epwmss5,
668 &am43xx_epwmss5__ehrpwm5,
669 &am43xx_l4_ls__mcspi2,
670 &am43xx_l4_ls__mcspi3,
671 &am43xx_l4_ls__mcspi4,
672 &am43xx_l4_ls__gpio4,
673 &am43xx_l4_ls__gpio5,
674 &am43xx_l3_main__pruss,
675 &am33xx_mpu__l3_main,
676 &am33xx_mpu__prcm,
677 &am33xx_l3_s__l4_ls,
678 &am33xx_l3_s__l4_wkup,
679 &am43xx_l3_main__l4_hs,
680 &am33xx_l3_main__l3_s,
681 &am33xx_l3_main__l3_instr,
682 &am33xx_l3_main__gfx,
683 &am33xx_l3_s__l3_main,
684 &am33xx_pruss__l3_main,
685 &am43xx_wkup_m3__l4_wkup,
686 &am33xx_gfx__l3_main,
687 &am43xx_l4_wkup__wkup_m3,
688 &am43xx_l4_wkup__control,
689 &am43xx_l4_wkup__smartreflex0,
690 &am43xx_l4_wkup__smartreflex1,
691 &am43xx_l4_wkup__uart1,
692 &am43xx_l4_wkup__timer1,
693 &am43xx_l4_wkup__i2c1,
694 &am43xx_l4_wkup__gpio0,
695 &am43xx_l4_wkup__wd_timer1,
696 &am43xx_l3_s__qspi,
697 &am33xx_l4_per__dcan0,
698 &am33xx_l4_per__dcan1,
699 &am33xx_l4_per__gpio1,
700 &am33xx_l4_per__gpio2,
701 &am33xx_l4_per__gpio3,
702 &am33xx_l4_per__i2c2,
703 &am33xx_l4_per__i2c3,
704 &am33xx_l4_per__mailbox,
705 &am33xx_l4_ls__mcasp0,
706 &am33xx_l4_ls__mcasp1,
707 &am33xx_l4_ls__mmc0,
708 &am33xx_l4_ls__mmc1,
709 &am33xx_l3_s__mmc2,
710 &am33xx_l4_ls__timer2,
711 &am33xx_l4_ls__timer3,
712 &am33xx_l4_ls__timer4,
713 &am33xx_l4_ls__timer5,
714 &am33xx_l4_ls__timer6,
715 &am33xx_l4_ls__timer7,
716 &am33xx_l3_main__tpcc,
717 &am33xx_l4_ls__uart2,
718 &am33xx_l4_ls__uart3,
719 &am33xx_l4_ls__uart4,
720 &am33xx_l4_ls__uart5,
721 &am33xx_l4_ls__uart6,
722 &am33xx_l4_ls__elm,
723 &am33xx_l4_ls__epwmss0,
724 &am33xx_epwmss0__ecap0,
725 &am33xx_epwmss0__eqep0,
726 &am33xx_epwmss0__ehrpwm0,
727 &am33xx_l4_ls__epwmss1,
728 &am33xx_epwmss1__ecap1,
729 &am33xx_epwmss1__eqep1,
730 &am33xx_epwmss1__ehrpwm1,
731 &am33xx_l4_ls__epwmss2,
732 &am33xx_epwmss2__ecap2,
733 &am33xx_epwmss2__eqep2,
734 &am33xx_epwmss2__ehrpwm2,
735 &am33xx_l3_s__gpmc,
736 &am33xx_l4_ls__mcspi0,
737 &am33xx_l4_ls__mcspi1,
738 &am33xx_l3_main__tptc0,
739 &am33xx_l3_main__tptc1,
740 &am33xx_l3_main__tptc2,
741 &am33xx_l3_main__ocmc,
742 &am43xx_l4_hs__cpgmac0,
743 &am33xx_cpgmac0__mdio,
744 &am33xx_l3_main__sha0,
745 &am33xx_l3_main__aes0,
746 &am43xx_l4_ls__ocp2scp0,
747 &am43xx_l4_ls__ocp2scp1,
748 &am43xx_l3_s__usbotgss0,
749 &am43xx_l3_s__usbotgss1,
750 NULL,
751};
752
753int __init am43xx_hwmod_init(void)
754{
755 omap_hwmod_am43xx_reg();
756 omap_hwmod_init();
757 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
758}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index baf3d8bf6bea..da5a59ae77b6 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -257,6 +257,7 @@ extern void am33xx_powerdomains_init(void);
257extern void omap44xx_powerdomains_init(void); 257extern void omap44xx_powerdomains_init(void);
258extern void omap54xx_powerdomains_init(void); 258extern void omap54xx_powerdomains_init(void);
259extern void dra7xx_powerdomains_init(void); 259extern void dra7xx_powerdomains_init(void);
260void am43xx_powerdomains_init(void);
260 261
261extern struct pwrdm_ops omap2_pwrdm_operations; 262extern struct pwrdm_ops omap2_pwrdm_operations;
262extern struct pwrdm_ops omap3_pwrdm_operations; 263extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
new file mode 100644
index 000000000000..95fee54c38ab
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -0,0 +1,136 @@
1/*
2 * AM43xx Power domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include "powerdomain.h"
15
16#include "prcm-common.h"
17#include "prcm44xx.h"
18#include "prcm43xx.h"
19
20static struct powerdomain gfx_43xx_pwrdm = {
21 .name = "gfx_pwrdm",
22 .voltdm = { .name = "core" },
23 .prcm_offs = AM43XX_PRM_GFX_INST,
24 .prcm_partition = AM43XX_PRM_PARTITION,
25 .pwrsts = PWRSTS_OFF_ON,
26 .banks = 1,
27 .pwrsts_mem_on = {
28 [0] = PWRSTS_ON, /* gfx_mem */
29 },
30 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
31};
32
33static struct powerdomain mpu_43xx_pwrdm = {
34 .name = "mpu_pwrdm",
35 .voltdm = { .name = "mpu" },
36 .prcm_offs = AM43XX_PRM_MPU_INST,
37 .prcm_partition = AM43XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF_RET,
40 .banks = 3,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
43 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
44 [2] = PWRSTS_OFF_RET, /* mpu_ram */
45 },
46 .pwrsts_mem_on = {
47 [0] = PWRSTS_ON, /* mpu_l1 */
48 [1] = PWRSTS_ON, /* mpu_l2 */
49 [2] = PWRSTS_ON, /* mpu_ram */
50 },
51 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
52};
53
54static struct powerdomain rtc_43xx_pwrdm = {
55 .name = "rtc_pwrdm",
56 .voltdm = { .name = "rtc" },
57 .prcm_offs = AM43XX_PRM_RTC_INST,
58 .prcm_partition = AM43XX_PRM_PARTITION,
59 .pwrsts = PWRSTS_ON,
60};
61
62static struct powerdomain wkup_43xx_pwrdm = {
63 .name = "wkup_pwrdm",
64 .voltdm = { .name = "core" },
65 .prcm_offs = AM43XX_PRM_WKUP_INST,
66 .prcm_partition = AM43XX_PRM_PARTITION,
67 .pwrsts = PWRSTS_ON,
68 .banks = 1,
69 .pwrsts_mem_on = {
70 [0] = PWRSTS_ON, /* debugss_mem */
71 },
72};
73
74static struct powerdomain tamper_43xx_pwrdm = {
75 .name = "tamper_pwrdm",
76 .voltdm = { .name = "tamper" },
77 .prcm_offs = AM43XX_PRM_TAMPER_INST,
78 .prcm_partition = AM43XX_PRM_PARTITION,
79 .pwrsts = PWRSTS_ON,
80};
81
82static struct powerdomain cefuse_43xx_pwrdm = {
83 .name = "cefuse_pwrdm",
84 .voltdm = { .name = "core" },
85 .prcm_offs = AM43XX_PRM_CEFUSE_INST,
86 .prcm_partition = AM43XX_PRM_PARTITION,
87 .pwrsts = PWRSTS_OFF_ON,
88 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
89};
90
91static struct powerdomain per_43xx_pwrdm = {
92 .name = "per_pwrdm",
93 .voltdm = { .name = "core" },
94 .prcm_offs = AM43XX_PRM_PER_INST,
95 .prcm_partition = AM43XX_PRM_PARTITION,
96 .pwrsts = PWRSTS_OFF_RET_ON,
97 .pwrsts_logic_ret = PWRSTS_OFF_RET,
98 .banks = 4,
99 .pwrsts_mem_ret = {
100 [0] = PWRSTS_OFF_RET, /* icss_mem */
101 [1] = PWRSTS_OFF_RET, /* per_mem */
102 [2] = PWRSTS_OFF_RET, /* ram1_mem */
103 [3] = PWRSTS_OFF_RET, /* ram2_mem */
104 },
105 .pwrsts_mem_on = {
106 [0] = PWRSTS_ON, /* icss_mem */
107 [1] = PWRSTS_ON, /* per_mem */
108 [2] = PWRSTS_ON, /* ram1_mem */
109 [3] = PWRSTS_ON, /* ram2_mem */
110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112};
113
114static struct powerdomain *powerdomains_am43xx[] __initdata = {
115 &gfx_43xx_pwrdm,
116 &mpu_43xx_pwrdm,
117 &rtc_43xx_pwrdm,
118 &wkup_43xx_pwrdm,
119 &tamper_43xx_pwrdm,
120 &cefuse_43xx_pwrdm,
121 &per_43xx_pwrdm,
122 NULL
123};
124
125static int am43xx_check_vcvp(void)
126{
127 return 0;
128}
129
130void __init am43xx_powerdomains_init(void)
131{
132 omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp;
133 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
134 pwrdm_register_pwrdms(powerdomains_am43xx);
135 pwrdm_complete_init();
136}
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
new file mode 100644
index 000000000000..7785be984edd
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -0,0 +1,146 @@
1/*
2 * AM43x PRCM defines
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
12#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
13
14#define AM43XX_PRM_PARTITION 1
15#define AM43XX_CM_PARTITION 1
16
17/* PRM instances */
18#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
19#define AM43XX_PRM_MPU_INST 0x0300
20#define AM43XX_PRM_GFX_INST 0x0400
21#define AM43XX_PRM_RTC_INST 0x0500
22#define AM43XX_PRM_TAMPER_INST 0x0600
23#define AM43XX_PRM_CEFUSE_INST 0x0700
24#define AM43XX_PRM_PER_INST 0x0800
25#define AM43XX_PRM_WKUP_INST 0x2000
26#define AM43XX_PRM_DEVICE_INST 0x4000
27
28/* RM RSTCTRL offsets */
29#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
30#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
31#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010
32
33/* RM RSTST offsets */
34#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014
35#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014
36
37/* CM instances */
38#define AM43XX_CM_WKUP_INST 0x2800
39#define AM43XX_CM_DEVICE_INST 0x4100
40#define AM43XX_CM_DPLL_INST 0x4200
41#define AM43XX_CM_MPU_INST 0x8300
42#define AM43XX_CM_GFX_INST 0x8400
43#define AM43XX_CM_RTC_INST 0x8500
44#define AM43XX_CM_TAMPER_INST 0x8600
45#define AM43XX_CM_CEFUSE_INST 0x8700
46#define AM43XX_CM_PER_INST 0x8800
47
48/* CD offsets */
49#define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000
50#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100
51#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200
52#define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300
53#define AM43XX_CM_MPU_MPU_CDOFFS 0x0000
54#define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000
55#define AM43XX_CM_RTC_RTC_CDOFFS 0x0000
56#define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000
57#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000
58#define AM43XX_CM_PER_L3_CDOFFS 0x0000
59#define AM43XX_CM_PER_L3S_CDOFFS 0x0200
60#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
61#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
62#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
63#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
64#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
65#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
66
67/* CLK CTRL offsets */
68#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580
69#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588
70#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590
71#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598
72#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0
73#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428
74#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430
75#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468
76#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438
77#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440
78#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448
79#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478
80#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480
81#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488
82#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8
83#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0
84#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
85#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
86#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
87#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
88#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
89#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
90#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530
91#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538
92#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540
93#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548
94#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550
95#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558
96#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228
97#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360
98#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350
99#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358
100#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348
101#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328
102#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340
103#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368
104#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120
105#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338
106#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220
107#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020
108#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248
109#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258
110#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220
111#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238
112#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240
113#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420
114#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020
115#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078
116#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080
117#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088
118#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090
119#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20
120#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320
121#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
122#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0
123#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
124#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040
125#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
126#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
127#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
128#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
129#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
130#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570
131#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578
132#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230
133#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450
134#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458
135#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460
136#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510
137#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518
138#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520
139#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490
140#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498
141#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260
142#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
143#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
145
146#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 19:11:59 -0400