Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A week's worth of fixes for various ARM platforms.  Diff wise, the
  largest fix is for OMAP to deal with how GIC now registers interrupts
  (irq_domain_add_legacy() -> irq_domain_add_linear() changes).

  Besides this, a few more renesas platforms needed the GIC instatiation
  done for legacy boards.  There's also a fix that disables coherency of
  mvebu due to issues, and a few other smaller fixes"

* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: dts: add baud rate to Juno stdout-path
  ARM: dts: imx25: Fix PWM "per" clocks
  bus: mvebu-mbus: fix support of MBus window 13
  Merge tag 'mvebu-fixes-3.19-3' of git://git.infradead.org/linux-mvebu into fixes
  ARM: mvebu: completely disable hardware I/O coherency
  ARM: OMAP: Work around hardcoded interrupts
  ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds
  ARM: shmobile: r8a7778: Instantiate GIC from C board code in legacy builds
  arm: boot: dts: dra7: enable dwc3 suspend PHY quirk

17 files changed, 117 insertions, 14 deletions

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc1643a..63f8b007bdc5 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1257,6 +1257,8 @@
                                 tx-fifo-resize;
                                 maximum-speed = "super-speed";
                                 dr_mode = "otg";
+                                snps,dis_u3_susphy_quirk;
+                                snps,dis_u2_susphy_quirk;
                         };
                 };
 
@@ -1278,6 +1280,8 @@
                                 tx-fifo-resize;
                                 maximum-speed = "high-speed";
                                 dr_mode = "otg";
+                                snps,dis_u3_susphy_quirk;
+                                snps,dis_u2_susphy_quirk;
                         };
                 };
 
@@ -1299,6 +1303,8 @@
                                 tx-fifo-resize;
                                 maximum-speed = "high-speed";
                                 dr_mode = "otg";
+                                snps,dis_u3_susphy_quirk;
+                                snps,dis_u2_susphy_quirk;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index d238676a9107..e4d3aecc4ed2 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -369,7 +369,7 @@
                                 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
                                 #pwm-cells = <2>;
                                 reg = <0x53fa0000 0x4000>;
-                                clocks = <&clks 106>, <&clks 36>;
+                                clocks = <&clks 106>, <&clks 52>;
                                 clock-names = "ipg", "per";
                                 interrupts = <36>;
                         };
@@ -388,7 +388,7 @@
                                 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
                                 #pwm-cells = <2>;
                                 reg = <0x53fa8000 0x4000>;
-                                clocks = <&clks 107>, <&clks 36>;
+                                clocks = <&clks 107>, <&clks 52>;
                                 clock-names = "ipg", "per";
                                 interrupts = <41>;
                         };
@@ -429,7 +429,7 @@
                         pwm4: pwm@53fc8000 {
                                 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
                                 reg = <0x53fc8000 0x4000>;
-                                clocks = <&clks 108>, <&clks 36>;
+                                clocks = <&clks 108>, <&clks 52>;
                                 clock-names = "ipg", "per";
                                 interrupts = <42>;
                         };
@@ -476,7 +476,7 @@
                                 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
                                 #pwm-cells = <2>;
                                 reg = <0x53fe0000 0x4000>;
-                                clocks = <&clks 105>, <&clks 36>;
+                                clocks = <&clks 105>, <&clks 52>;
                                 clock-names = "ipg", "per";
                                 interrupts = <26>;
                         };
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 3585cb394e9b..caa21e9b8cd9 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -246,9 +246,14 @@ static int coherency_type(void)
         return type;
 }
 
+/*
+ * As a precaution, we currently completely disable hardware I/O
+ * coherency, until enough testing is done with automatic I/O
+ * synchronization barriers to validate that it is a proper solution.
+ */
 int coherency_available(void)
 {
-        return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
+        return false;
 }
 
 int __init coherency_init(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index db57741c9c8a..64e44d6d07c0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 
+unsigned int omap4_xlate_irq(unsigned int hwirq);
 void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..cc30e49a4cc2 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
 }
 omap_early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id gic_match[] = {
+        { .compatible = "arm,cortex-a9-gic", },
+        { .compatible = "arm,cortex-a15-gic", },
+        { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+        struct of_phandle_args irq_data;
+        unsigned int irq;
+
+        if (!gic_node)
+                gic_node = of_find_matching_node(NULL, gic_match);
+
+        if (WARN_ON(!gic_node))
+                return hwirq;
+
+        irq_data.np = gic_node;
+        irq_data.args_count = 3;
+        irq_data.args[0] = 0;
+        irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+        irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+        irq = irq_create_of_mapping(&irq_data);
+        if (WARN_ON(!irq))
+                irq = hwirq;
+
+        return irq;
+}
+
 void __init omap_gic_of_init(void)
 {
         struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908dc5cf0..9025ffffd2dc 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 
         mpu_irqs_cnt = _count_mpu_irqs(oh);
         for (i = 0; i < mpu_irqs_cnt; i++) {
+                unsigned int irq;
+
+                if (oh->xlate_irq)
+                        irq = oh->xlate_irq((oh->mpu_irqs + i)->irq);
+                else
+                        irq = (oh->mpu_irqs + i)->irq;
                 (res + r)->name = (oh->mpu_irqs + i)->name;
-                (res + r)->start = (oh->mpu_irqs + i)->irq;
-                (res + r)->end = (oh->mpu_irqs + i)->irq;
+                (res + r)->start = irq;
+                (res + r)->end = irq;
                 (res + r)->flags = IORESOURCE_IRQ;
                 r++;
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 35ca6efbec31..5b42fafcaf55 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@ struct omap_hwmod {
         spinlock_t                      _lock;
         struct list_head                node;
         struct omap_hwmod_ocp_if        *_mpu_port;
+        unsigned int                    (*xlate_irq)(unsigned int);
         u16                             flags;
         u8                              mpu_rt_idx;
         u8                              response_lat;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c314b3c31117..f5e68a782025 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -479,6 +479,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
         .class          = &omap44xx_dma_hwmod_class,
         .clkdm_name     = "l3_dma_clkdm",
         .mpu_irqs       = omap44xx_dma_system_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .main_clk       = "l3_div_ck",
         .prcm = {
                 .omap4 = {
@@ -640,6 +641,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
         .class          = &omap44xx_dispc_hwmod_class,
         .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dispc_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
         .main_clk       = "dss_dss_clk",
         .prcm = {
@@ -693,6 +695,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
         .class          = &omap44xx_dsi_hwmod_class,
         .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
         .main_clk       = "dss_dss_clk",
         .prcm = {
@@ -726,6 +729,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
         .class          = &omap44xx_dsi_hwmod_class,
         .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
         .main_clk       = "dss_dss_clk",
         .prcm = {
@@ -784,6 +788,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
          */
         .flags          = HWMOD_SWSUP_SIDLE,
         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
         .main_clk       = "dss_48mhz_clk",
         .prcm = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3e9523084b2a..7c3fac035e93 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -288,6 +288,7 @@ static struct omap_hwmod omap54xx_dma_system_hwmod = {
         .class          = &omap54xx_dma_hwmod_class,
         .clkdm_name     = "dma_clkdm",
         .mpu_irqs       = omap54xx_dma_system_irqs,
+        .xlate_irq      = omap4_xlate_irq,
         .main_clk       = "l3_iclk_div",
         .prcm = {
                 .omap4 = {
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index a8e4b582c527..6163d66102a3 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -498,6 +498,7 @@ struct omap_prcm_irq_setup {
         u8 nr_irqs;
         const struct omap_prcm_irq *irqs;
         int irq;
+        unsigned int (*xlate_irq)(unsigned int);
         void (*read_pending_irqs)(unsigned long *events);
         void (*ocp_barrier)(void);
         void (*save_and_clear_irqen)(u32 *saved_mask);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index cc170fb81ff7..408c64efb807 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -49,6 +49,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
         .irqs                   = omap4_prcm_irqs,
         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
         .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
+        .xlate_irq              = omap4_xlate_irq,
         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
@@ -751,8 +752,10 @@ static int omap44xx_prm_late_init(void)
                 }
 
                 /* Once OMAP4 DT is filled as well */
-                if (irq_num >= 0)
+                if (irq_num >= 0) {
                         omap4_prcm_irq_setup.irq = irq_num;
+                        omap4_prcm_irq_setup.xlate_irq = NULL;
+                }
         }
 
         omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 779940cb6e56..dea2833ca627 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -187,6 +187,7 @@ int omap_prcm_event_to_irq(const char *name)
  */
 void omap_prcm_irq_cleanup(void)
 {
+        unsigned int irq;
         int i;
 
         if (!prcm_irq_setup) {
@@ -211,7 +212,11 @@ void omap_prcm_irq_cleanup(void)
         kfree(prcm_irq_setup->priority_mask);
         prcm_irq_setup->priority_mask = NULL;
 
-        irq_set_chained_handler(prcm_irq_setup->irq, NULL);
+        if (prcm_irq_setup->xlate_irq)
+                irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
+        else
+                irq = prcm_irq_setup->irq;
+        irq_set_chained_handler(irq, NULL);
 
         if (prcm_irq_setup->base_irq > 0)
                 irq_free_descs(prcm_irq_setup->base_irq,
@@ -259,6 +264,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
         int offset, i;
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
+        unsigned int irq;
 
         if (!irq_setup)
                 return -EINVAL;
@@ -298,7 +304,11 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
                                 1 << (offset & 0x1f);
         }
 
-        irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
+        if (irq_setup->xlate_irq)
+                irq = irq_setup->xlate_irq(irq_setup->irq);
+        else
+                irq = irq_setup->irq;
+        irq_set_chained_handler(irq, omap_prcm_irq_handler);
 
         irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
                 0);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 4457e731f7a4..292eca0e78ed 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -66,19 +66,24 @@ void __init omap_pmic_init(int bus, u32 clkrate,
         omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
 }
 
+#ifdef CONFIG_ARCH_OMAP4
 void __init omap4_pmic_init(const char *pmic_type,
                     struct twl4030_platform_data *pmic_data,
                     struct i2c_board_info *devices, int nr_devices)
 {
         /* PMIC part*/
+        unsigned int irq;
+
         omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
         omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
-        omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
+        irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
+        omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
 
         /* Register additional devices on i2c1 bus if needed */
         if (devices)
                 i2c_register_board_info(1, devices, nr_devices);
 }
+#endif
 
 void __init omap_pmic_late_init(void)
 {
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 170bd146ba17..cef8895a9b82 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -576,11 +576,18 @@ void __init r8a7778_init_irq_extpin(int irlm)
 void __init r8a7778_init_irq_dt(void)
 {
         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+        void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
+        void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
+#endif
 
         BUG_ON(!base);
 
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+#else
         irqchip_init();
-
+#endif
         /* route all interrupts to ARM */
         __raw_writel(0x73ffffff, base + INT2NTSR0);
         __raw_writel(0xffffffff, base + INT2NTSR1);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d172cf31..27dceaf9e688 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -720,10 +720,17 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 
 void __init r8a7779_init_irq_dt(void)
 {
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+        void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
+        void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
+#endif
         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
+#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+#else
         irqchip_init();
-
+#endif
         /* route all interrupts to ARM */
         __raw_writel(0xffffffff, INT2NTSR0);
         __raw_writel(0x3fffffff, INT2NTSR1);
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index cb3073e4e7a8..d429129ecb3d 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -22,7 +22,7 @@
         };
 
         chosen {
-                stdout-path = &soc_uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         psci {
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index eb7682dc123b..81bf297f1034 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -210,12 +210,25 @@ static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
 }
 
 /* Checks whether the given window number is available */
+
+/* On Armada XP, 375 and 38x the MBus window 13 has the remap
+ * capability, like windows 0 to 7. However, the mvebu-mbus driver
+ * isn't currently taking into account this special case, which means
+ * that when window 13 is actually used, the remap registers are left
+ * to 0, making the device using this MBus window unavailable. The
+ * quick fix for stable is to not use window 13. A follow up patch
+ * will correctly handle this window.
+*/
 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
                                      const int win)
 {
         void __iomem *addr = mbus->mbuswins_base +
                 mbus->soc->win_cfg_offset(win);
         u32 ctrl = readl(addr + WIN_CTRL_OFF);
+
+        if (win == 13)
+                return false;
+
         return !(ctrl & WIN_CTRL_ENABLE);
 }