aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2013-04-08 12:03:08 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-08 12:03:08 -0400
commit6fa6183aefcdefe0db26a0ceeaaf11c149acd449 (patch)
treea7c8fc974e8731c4ad60fb28c31734a24093dc92
parent321ae6fa03688ba901b1e3043961a44ed6333014 (diff)
parentc309f7f46167e85d1aae2fd31f23e7d2b5cdfbe0 (diff)
Merge tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren <tony@atomide.com>: Clean up related changes for v3.10 merge window. Mostly clock and PM related with removal of now unused DMA channel definitions. The clock change to use SoC specific lists will make it a little bit easier to add support for new SoCs variants without having to patch all over the place. * tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4: Fix the init code to have OMAP4460 errata available in DT build ARM: OMAP4: PM: Now remove L4 per clockdomain static depedency with MPU ARM: OMAP4: PM: Remove L4 wakeup depedency with MPU since errata fix exist now ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus() ARM: OMAP4+: Remove out of placed smp_wmb() in secondary wakeup code ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path ARM: OMAP4+: Remove the un-necessary cache flush from hotplug code ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable] tuple ARM: OMAP4+: Use common scratchpad SAR RAM offsets for all architectures ARM: OMAP2+: Remove unused DMA channel definitions ARM: OMAP1: Remove unused DMA channel definitions ARM: OMAP2+: clock data: Remove CK_* flags Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/mach-omap1/dma.h41
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c283
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c311
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c165
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c685
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c515
-rw-r--r--arch/arm/mach-omap2/clock.c17
-rw-r--r--arch/arm/mach-omap2/clock.h20
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c3
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c7
-rw-r--r--arch/arm/mach-omap2/dma.h70
-rw-r--r--arch/arm/mach-omap2/omap-hotplug.c6
-rw-r--r--arch/arm/mach-omap2/omap-smp.c57
-rw-r--r--arch/arm/mach-omap2/omap4-common.c16
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h14
-rw-r--r--arch/arm/mach-omap2/pm24xx.c11
-rw-r--r--arch/arm/mach-omap2/pm34xx.c9
-rw-r--r--arch/arm/mach-omap2/pm44xx.c20
18 files changed, 1059 insertions, 1191 deletions
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
index da6345dab03f..d05909c96715 100644
--- a/arch/arm/mach-omap1/dma.h
+++ b/arch/arm/mach-omap1/dma.h
@@ -21,21 +21,10 @@
21 21
22/* DMA channels for omap1 */ 22/* DMA channels for omap1 */
23#define OMAP_DMA_NO_DEVICE 0 23#define OMAP_DMA_NO_DEVICE 0
24#define OMAP_DMA_MCSI1_TX 1
25#define OMAP_DMA_MCSI1_RX 2
26#define OMAP_DMA_I2C_RX 3
27#define OMAP_DMA_I2C_TX 4
28#define OMAP_DMA_EXT_NDMA_REQ 5
29#define OMAP_DMA_EXT_NDMA_REQ2 6
30#define OMAP_DMA_UWIRE_TX 7
31#define OMAP_DMA_MCBSP1_TX 8 24#define OMAP_DMA_MCBSP1_TX 8
32#define OMAP_DMA_MCBSP1_RX 9 25#define OMAP_DMA_MCBSP1_RX 9
33#define OMAP_DMA_MCBSP3_TX 10 26#define OMAP_DMA_MCBSP3_TX 10
34#define OMAP_DMA_MCBSP3_RX 11 27#define OMAP_DMA_MCBSP3_RX 11
35#define OMAP_DMA_UART1_TX 12
36#define OMAP_DMA_UART1_RX 13
37#define OMAP_DMA_UART2_TX 14
38#define OMAP_DMA_UART2_RX 15
39#define OMAP_DMA_MCBSP2_TX 16 28#define OMAP_DMA_MCBSP2_TX 16
40#define OMAP_DMA_MCBSP2_RX 17 29#define OMAP_DMA_MCBSP2_RX 17
41#define OMAP_DMA_UART3_TX 18 30#define OMAP_DMA_UART3_TX 18
@@ -43,41 +32,11 @@
43#define OMAP_DMA_CAMERA_IF_RX 20 32#define OMAP_DMA_CAMERA_IF_RX 20
44#define OMAP_DMA_MMC_TX 21 33#define OMAP_DMA_MMC_TX 21
45#define OMAP_DMA_MMC_RX 22 34#define OMAP_DMA_MMC_RX 22
46#define OMAP_DMA_NAND 23
47#define OMAP_DMA_IRQ_LCD_LINE 24
48#define OMAP_DMA_MEMORY_STICK 25
49#define OMAP_DMA_USB_W2FC_RX0 26 35#define OMAP_DMA_USB_W2FC_RX0 26
50#define OMAP_DMA_USB_W2FC_RX1 27
51#define OMAP_DMA_USB_W2FC_RX2 28
52#define OMAP_DMA_USB_W2FC_TX0 29 36#define OMAP_DMA_USB_W2FC_TX0 29
53#define OMAP_DMA_USB_W2FC_TX1 30
54#define OMAP_DMA_USB_W2FC_TX2 31
55 37
56/* These are only for 1610 */ 38/* These are only for 1610 */
57#define OMAP_DMA_CRYPTO_DES_IN 32
58#define OMAP_DMA_SPI_TX 33
59#define OMAP_DMA_SPI_RX 34
60#define OMAP_DMA_CRYPTO_HASH 35
61#define OMAP_DMA_CCP_ATTN 36
62#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
63#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
64#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
65#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
66#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
67#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
68#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
69#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
70#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
71#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
72#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
73#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
74#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
75#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
76#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
77#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
78#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
79#define OMAP_DMA_MMC2_TX 54 39#define OMAP_DMA_MMC2_TX 54
80#define OMAP_DMA_MMC2_RX 55 40#define OMAP_DMA_MMC2_RX 55
81#define OMAP_DMA_CRYPTO_DES_OUT 56
82 41
83#endif /* __OMAP1_DMA_CHANNEL_H */ 42#endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 0f0a97c1fcc0..3662f4d4c8ea 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1739 1739
1740static struct omap_clk omap2420_clks[] = { 1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */ 1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), 1742 CLK(NULL, "func_32k_ck", &func_32k_ck),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), 1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1744 CLK(NULL, "osc_ck", &osc_ck, CK_242X), 1744 CLK(NULL, "osc_ck", &osc_ck),
1745 CLK(NULL, "sys_ck", &sys_ck, CK_242X), 1745 CLK(NULL, "sys_ck", &sys_ck),
1746 CLK(NULL, "alt_ck", &alt_ck, CK_242X), 1746 CLK(NULL, "alt_ck", &alt_ck),
1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), 1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1748 /* internal analog sources */ 1748 /* internal analog sources */
1749 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), 1749 CLK(NULL, "dpll_ck", &dpll_ck),
1750 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), 1750 CLK(NULL, "apll96_ck", &apll96_ck),
1751 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), 1751 CLK(NULL, "apll54_ck", &apll54_ck),
1752 /* internal prcm root sources */ 1752 /* internal prcm root sources */
1753 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), 1753 CLK(NULL, "func_54m_ck", &func_54m_ck),
1754 CLK(NULL, "core_ck", &core_ck, CK_242X), 1754 CLK(NULL, "core_ck", &core_ck),
1755 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), 1755 CLK(NULL, "func_96m_ck", &func_96m_ck),
1756 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), 1756 CLK(NULL, "func_48m_ck", &func_48m_ck),
1757 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), 1757 CLK(NULL, "func_12m_ck", &func_12m_ck),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), 1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1759 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), 1759 CLK(NULL, "sys_clkout", &sys_clkout),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), 1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), 1761 CLK(NULL, "sys_clkout2", &sys_clkout2),
1762 CLK(NULL, "emul_ck", &emul_ck, CK_242X), 1762 CLK(NULL, "emul_ck", &emul_ck),
1763 /* mpu domain clocks */ 1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), 1764 CLK(NULL, "mpu_ck", &mpu_ck),
1765 /* dsp domain clocks */ 1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), 1766 CLK(NULL, "dsp_fck", &dsp_fck),
1767 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), 1767 CLK(NULL, "dsp_ick", &dsp_ick),
1768 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), 1768 CLK(NULL, "iva1_ifck", &iva1_ifck),
1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), 1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
1770 /* GFX domain clocks */ 1770 /* GFX domain clocks */
1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), 1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), 1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1773 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), 1773 CLK(NULL, "gfx_ick", &gfx_ick),
1774 /* DSS domain clocks */ 1774 /* DSS domain clocks */
1775 CLK("omapdss_dss", "ick", &dss_ick, CK_242X), 1775 CLK("omapdss_dss", "ick", &dss_ick),
1776 CLK(NULL, "dss_ick", &dss_ick, CK_242X), 1776 CLK(NULL, "dss_ick", &dss_ick),
1777 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), 1777 CLK(NULL, "dss1_fck", &dss1_fck),
1778 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), 1778 CLK(NULL, "dss2_fck", &dss2_fck),
1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), 1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1780 /* L3 domain clocks */ 1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), 1781 CLK(NULL, "core_l3_ck", &core_l3_ck),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), 1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), 1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1784 /* L4 domain clocks */ 1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck, CK_242X), 1785 CLK(NULL, "l4_ck", &l4_ck),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), 1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1787 /* virtual meta-group clock */ 1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), 1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1789 /* general l4 interface ck, multi-parent functional clk */ 1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), 1790 CLK(NULL, "gpt1_ick", &gpt1_ick),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), 1791 CLK(NULL, "gpt1_fck", &gpt1_fck),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), 1792 CLK(NULL, "gpt2_ick", &gpt2_ick),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), 1793 CLK(NULL, "gpt2_fck", &gpt2_fck),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), 1794 CLK(NULL, "gpt3_ick", &gpt3_ick),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), 1795 CLK(NULL, "gpt3_fck", &gpt3_fck),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), 1796 CLK(NULL, "gpt4_ick", &gpt4_ick),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), 1797 CLK(NULL, "gpt4_fck", &gpt4_fck),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), 1798 CLK(NULL, "gpt5_ick", &gpt5_ick),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), 1799 CLK(NULL, "gpt5_fck", &gpt5_fck),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), 1800 CLK(NULL, "gpt6_ick", &gpt6_ick),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), 1801 CLK(NULL, "gpt6_fck", &gpt6_fck),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), 1802 CLK(NULL, "gpt7_ick", &gpt7_ick),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), 1803 CLK(NULL, "gpt7_fck", &gpt7_fck),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), 1804 CLK(NULL, "gpt8_ick", &gpt8_ick),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), 1805 CLK(NULL, "gpt8_fck", &gpt8_fck),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), 1806 CLK(NULL, "gpt9_ick", &gpt9_ick),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), 1807 CLK(NULL, "gpt9_fck", &gpt9_fck),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), 1808 CLK(NULL, "gpt10_ick", &gpt10_ick),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), 1809 CLK(NULL, "gpt10_fck", &gpt10_fck),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), 1810 CLK(NULL, "gpt11_ick", &gpt11_ick),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), 1811 CLK(NULL, "gpt11_fck", &gpt11_fck),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), 1812 CLK(NULL, "gpt12_ick", &gpt12_ick),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), 1813 CLK(NULL, "gpt12_fck", &gpt12_fck),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), 1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), 1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), 1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), 1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), 1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), 1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), 1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), 1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), 1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), 1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), 1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), 1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1826 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), 1826 CLK(NULL, "uart1_ick", &uart1_ick),
1827 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), 1827 CLK(NULL, "uart1_fck", &uart1_fck),
1828 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), 1828 CLK(NULL, "uart2_ick", &uart2_ick),
1829 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), 1829 CLK(NULL, "uart2_fck", &uart2_fck),
1830 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), 1830 CLK(NULL, "uart3_ick", &uart3_ick),
1831 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), 1831 CLK(NULL, "uart3_fck", &uart3_fck),
1832 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), 1832 CLK(NULL, "gpios_ick", &gpios_ick),
1833 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), 1833 CLK(NULL, "gpios_fck", &gpios_fck),
1834 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), 1834 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), 1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), 1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), 1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1838 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), 1838 CLK(NULL, "wdt1_ick", &wdt1_ick),
1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), 1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1840 CLK("omap24xxcam", "fck", &cam_fck, CK_242X), 1840 CLK("omap24xxcam", "fck", &cam_fck),
1841 CLK(NULL, "cam_fck", &cam_fck, CK_242X), 1841 CLK(NULL, "cam_fck", &cam_fck),
1842 CLK("omap24xxcam", "ick", &cam_ick, CK_242X), 1842 CLK("omap24xxcam", "ick", &cam_ick),
1843 CLK(NULL, "cam_ick", &cam_ick, CK_242X), 1843 CLK(NULL, "cam_ick", &cam_ick),
1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), 1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1845 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), 1845 CLK(NULL, "wdt4_ick", &wdt4_ick),
1846 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), 1846 CLK(NULL, "wdt4_fck", &wdt4_fck),
1847 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), 1847 CLK(NULL, "wdt3_ick", &wdt3_ick),
1848 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), 1848 CLK(NULL, "wdt3_fck", &wdt3_fck),
1849 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), 1849 CLK(NULL, "mspro_ick", &mspro_ick),
1850 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), 1850 CLK(NULL, "mspro_fck", &mspro_fck),
1851 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), 1851 CLK("mmci-omap.0", "ick", &mmc_ick),
1852 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), 1852 CLK(NULL, "mmc_ick", &mmc_ick),
1853 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), 1853 CLK("mmci-omap.0", "fck", &mmc_fck),
1854 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), 1854 CLK(NULL, "mmc_fck", &mmc_fck),
1855 CLK(NULL, "fac_ick", &fac_ick, CK_242X), 1855 CLK(NULL, "fac_ick", &fac_ick),
1856 CLK(NULL, "fac_fck", &fac_fck, CK_242X), 1856 CLK(NULL, "fac_fck", &fac_fck),
1857 CLK(NULL, "eac_ick", &eac_ick, CK_242X), 1857 CLK(NULL, "eac_ick", &eac_ick),
1858 CLK(NULL, "eac_fck", &eac_fck, CK_242X), 1858 CLK(NULL, "eac_fck", &eac_fck),
1859 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), 1859 CLK("omap_hdq.0", "ick", &hdq_ick),
1860 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), 1860 CLK(NULL, "hdq_ick", &hdq_ick),
1861 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), 1861 CLK("omap_hdq.0", "fck", &hdq_fck),
1862 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), 1862 CLK(NULL, "hdq_fck", &hdq_fck),
1863 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), 1863 CLK("omap_i2c.1", "ick", &i2c1_ick),
1864 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), 1864 CLK(NULL, "i2c1_ick", &i2c1_ick),
1865 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), 1865 CLK(NULL, "i2c1_fck", &i2c1_fck),
1866 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), 1866 CLK("omap_i2c.2", "ick", &i2c2_ick),
1867 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), 1867 CLK(NULL, "i2c2_ick", &i2c2_ick),
1868 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), 1868 CLK(NULL, "i2c2_fck", &i2c2_fck),
1869 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), 1869 CLK(NULL, "gpmc_fck", &gpmc_fck),
1870 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), 1870 CLK(NULL, "sdma_fck", &sdma_fck),
1871 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), 1871 CLK(NULL, "sdma_ick", &sdma_ick),
1872 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), 1872 CLK(NULL, "sdrc_ick", &sdrc_ick),
1873 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), 1873 CLK(NULL, "vlynq_ick", &vlynq_ick),
1874 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), 1874 CLK(NULL, "vlynq_fck", &vlynq_fck),
1875 CLK(NULL, "des_ick", &des_ick, CK_242X), 1875 CLK(NULL, "des_ick", &des_ick),
1876 CLK("omap-sham", "ick", &sha_ick, CK_242X), 1876 CLK("omap-sham", "ick", &sha_ick),
1877 CLK(NULL, "sha_ick", &sha_ick, CK_242X), 1877 CLK(NULL, "sha_ick", &sha_ick),
1878 CLK("omap_rng", "ick", &rng_ick, CK_242X), 1878 CLK("omap_rng", "ick", &rng_ick),
1879 CLK(NULL, "rng_ick", &rng_ick, CK_242X), 1879 CLK(NULL, "rng_ick", &rng_ick),
1880 CLK("omap-aes", "ick", &aes_ick, CK_242X), 1880 CLK("omap-aes", "ick", &aes_ick),
1881 CLK(NULL, "aes_ick", &aes_ick, CK_242X), 1881 CLK(NULL, "aes_ick", &aes_ick),
1882 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1882 CLK(NULL, "pka_ick", &pka_ick),
1883 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1883 CLK(NULL, "usb_fck", &usb_fck),
1884 CLK("musb-hdrc", "fck", &osc_ck, CK_242X), 1884 CLK("musb-hdrc", "fck", &osc_ck),
1885 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), 1885 CLK(NULL, "timer_32k_ck", &func_32k_ck),
1886 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), 1886 CLK(NULL, "timer_sys_ck", &sys_ck),
1887 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), 1887 CLK(NULL, "timer_ext_ck", &alt_ck),
1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), 1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
1889}; 1889};
1890 1890
1891 1891
@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
1904 1904
1905int __init omap2420_clk_init(void) 1905int __init omap2420_clk_init(void)
1906{ 1906{
1907 struct omap_clk *c;
1908
1909 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; 1907 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1910 cpu_mask = RATE_IN_242X; 1908 cpu_mask = RATE_IN_242X;
1911 rate_table = omap2420_rate_table; 1909 rate_table = omap2420_rate_table;
@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
1914 1912
1915 omap2xxx_clkt_vps_check_bootloader_rates(); 1913 omap2xxx_clkt_vps_check_bootloader_rates();
1916 1914
1917 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); 1915 omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
1918 c++) {
1919 clkdev_add(&c->lk);
1920 if (!__clk_init(NULL, c->lk.clk))
1921 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1922 }
1923 1916
1924 omap2xxx_clkt_vps_late_init(); 1917 omap2xxx_clkt_vps_late_init();
1925 1918
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index aed8f74ca076..bda353b2f7d9 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1840,168 +1840,168 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1840 1840
1841static struct omap_clk omap2430_clks[] = { 1841static struct omap_clk omap2430_clks[] = {
1842 /* external root sources */ 1842 /* external root sources */
1843 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), 1843 CLK(NULL, "func_32k_ck", &func_32k_ck),
1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), 1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1845 CLK(NULL, "osc_ck", &osc_ck, CK_243X), 1845 CLK(NULL, "osc_ck", &osc_ck),
1846 CLK("twl", "fck", &osc_ck, CK_243X), 1846 CLK("twl", "fck", &osc_ck),
1847 CLK(NULL, "sys_ck", &sys_ck, CK_243X), 1847 CLK(NULL, "sys_ck", &sys_ck),
1848 CLK(NULL, "alt_ck", &alt_ck, CK_243X), 1848 CLK(NULL, "alt_ck", &alt_ck),
1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), 1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1850 /* internal analog sources */ 1850 /* internal analog sources */
1851 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), 1851 CLK(NULL, "dpll_ck", &dpll_ck),
1852 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), 1852 CLK(NULL, "apll96_ck", &apll96_ck),
1853 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), 1853 CLK(NULL, "apll54_ck", &apll54_ck),
1854 /* internal prcm root sources */ 1854 /* internal prcm root sources */
1855 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), 1855 CLK(NULL, "func_54m_ck", &func_54m_ck),
1856 CLK(NULL, "core_ck", &core_ck, CK_243X), 1856 CLK(NULL, "core_ck", &core_ck),
1857 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), 1857 CLK(NULL, "func_96m_ck", &func_96m_ck),
1858 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), 1858 CLK(NULL, "func_48m_ck", &func_48m_ck),
1859 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), 1859 CLK(NULL, "func_12m_ck", &func_12m_ck),
1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), 1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1861 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), 1861 CLK(NULL, "sys_clkout", &sys_clkout),
1862 CLK(NULL, "emul_ck", &emul_ck, CK_243X), 1862 CLK(NULL, "emul_ck", &emul_ck),
1863 /* mpu domain clocks */ 1863 /* mpu domain clocks */
1864 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), 1864 CLK(NULL, "mpu_ck", &mpu_ck),
1865 /* dsp domain clocks */ 1865 /* dsp domain clocks */
1866 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), 1866 CLK(NULL, "dsp_fck", &dsp_fck),
1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), 1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick),
1868 /* GFX domain clocks */ 1868 /* GFX domain clocks */
1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), 1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), 1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1871 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), 1871 CLK(NULL, "gfx_ick", &gfx_ick),
1872 /* Modem domain clocks */ 1872 /* Modem domain clocks */
1873 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), 1873 CLK(NULL, "mdm_ick", &mdm_ick),
1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), 1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
1875 /* DSS domain clocks */ 1875 /* DSS domain clocks */
1876 CLK("omapdss_dss", "ick", &dss_ick, CK_243X), 1876 CLK("omapdss_dss", "ick", &dss_ick),
1877 CLK(NULL, "dss_ick", &dss_ick, CK_243X), 1877 CLK(NULL, "dss_ick", &dss_ick),
1878 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), 1878 CLK(NULL, "dss1_fck", &dss1_fck),
1879 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), 1879 CLK(NULL, "dss2_fck", &dss2_fck),
1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), 1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1881 /* L3 domain clocks */ 1881 /* L3 domain clocks */
1882 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), 1882 CLK(NULL, "core_l3_ck", &core_l3_ck),
1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), 1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), 1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1885 /* L4 domain clocks */ 1885 /* L4 domain clocks */
1886 CLK(NULL, "l4_ck", &l4_ck, CK_243X), 1886 CLK(NULL, "l4_ck", &l4_ck),
1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), 1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1888 /* virtual meta-group clock */ 1888 /* virtual meta-group clock */
1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), 1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1890 /* general l4 interface ck, multi-parent functional clk */ 1890 /* general l4 interface ck, multi-parent functional clk */
1891 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), 1891 CLK(NULL, "gpt1_ick", &gpt1_ick),
1892 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), 1892 CLK(NULL, "gpt1_fck", &gpt1_fck),
1893 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), 1893 CLK(NULL, "gpt2_ick", &gpt2_ick),
1894 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), 1894 CLK(NULL, "gpt2_fck", &gpt2_fck),
1895 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), 1895 CLK(NULL, "gpt3_ick", &gpt3_ick),
1896 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), 1896 CLK(NULL, "gpt3_fck", &gpt3_fck),
1897 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), 1897 CLK(NULL, "gpt4_ick", &gpt4_ick),
1898 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), 1898 CLK(NULL, "gpt4_fck", &gpt4_fck),
1899 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), 1899 CLK(NULL, "gpt5_ick", &gpt5_ick),
1900 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), 1900 CLK(NULL, "gpt5_fck", &gpt5_fck),
1901 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), 1901 CLK(NULL, "gpt6_ick", &gpt6_ick),
1902 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), 1902 CLK(NULL, "gpt6_fck", &gpt6_fck),
1903 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), 1903 CLK(NULL, "gpt7_ick", &gpt7_ick),
1904 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), 1904 CLK(NULL, "gpt7_fck", &gpt7_fck),
1905 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), 1905 CLK(NULL, "gpt8_ick", &gpt8_ick),
1906 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), 1906 CLK(NULL, "gpt8_fck", &gpt8_fck),
1907 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), 1907 CLK(NULL, "gpt9_ick", &gpt9_ick),
1908 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), 1908 CLK(NULL, "gpt9_fck", &gpt9_fck),
1909 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), 1909 CLK(NULL, "gpt10_ick", &gpt10_ick),
1910 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), 1910 CLK(NULL, "gpt10_fck", &gpt10_fck),
1911 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), 1911 CLK(NULL, "gpt11_ick", &gpt11_ick),
1912 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), 1912 CLK(NULL, "gpt11_fck", &gpt11_fck),
1913 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), 1913 CLK(NULL, "gpt12_ick", &gpt12_ick),
1914 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), 1914 CLK(NULL, "gpt12_fck", &gpt12_fck),
1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), 1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), 1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), 1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), 1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), 1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), 1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), 1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), 1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), 1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), 1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), 1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), 1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), 1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), 1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), 1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), 1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), 1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), 1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), 1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), 1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), 1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), 1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), 1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), 1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
1939 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), 1939 CLK(NULL, "uart1_ick", &uart1_ick),
1940 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), 1940 CLK(NULL, "uart1_fck", &uart1_fck),
1941 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), 1941 CLK(NULL, "uart2_ick", &uart2_ick),
1942 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), 1942 CLK(NULL, "uart2_fck", &uart2_fck),
1943 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), 1943 CLK(NULL, "uart3_ick", &uart3_ick),
1944 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), 1944 CLK(NULL, "uart3_fck", &uart3_fck),
1945 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), 1945 CLK(NULL, "gpios_ick", &gpios_ick),
1946 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), 1946 CLK(NULL, "gpios_fck", &gpios_fck),
1947 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), 1947 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), 1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), 1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), 1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1951 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), 1951 CLK(NULL, "wdt1_ick", &wdt1_ick),
1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), 1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1953 CLK(NULL, "icr_ick", &icr_ick, CK_243X), 1953 CLK(NULL, "icr_ick", &icr_ick),
1954 CLK("omap24xxcam", "fck", &cam_fck, CK_243X), 1954 CLK("omap24xxcam", "fck", &cam_fck),
1955 CLK(NULL, "cam_fck", &cam_fck, CK_243X), 1955 CLK(NULL, "cam_fck", &cam_fck),
1956 CLK("omap24xxcam", "ick", &cam_ick, CK_243X), 1956 CLK("omap24xxcam", "ick", &cam_ick),
1957 CLK(NULL, "cam_ick", &cam_ick, CK_243X), 1957 CLK(NULL, "cam_ick", &cam_ick),
1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), 1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1959 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), 1959 CLK(NULL, "wdt4_ick", &wdt4_ick),
1960 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), 1960 CLK(NULL, "wdt4_fck", &wdt4_fck),
1961 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), 1961 CLK(NULL, "mspro_ick", &mspro_ick),
1962 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), 1962 CLK(NULL, "mspro_fck", &mspro_fck),
1963 CLK(NULL, "fac_ick", &fac_ick, CK_243X), 1963 CLK(NULL, "fac_ick", &fac_ick),
1964 CLK(NULL, "fac_fck", &fac_fck, CK_243X), 1964 CLK(NULL, "fac_fck", &fac_fck),
1965 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), 1965 CLK("omap_hdq.0", "ick", &hdq_ick),
1966 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), 1966 CLK(NULL, "hdq_ick", &hdq_ick),
1967 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), 1967 CLK("omap_hdq.1", "fck", &hdq_fck),
1968 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), 1968 CLK(NULL, "hdq_fck", &hdq_fck),
1969 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), 1969 CLK("omap_i2c.1", "ick", &i2c1_ick),
1970 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), 1970 CLK(NULL, "i2c1_ick", &i2c1_ick),
1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), 1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck),
1972 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), 1972 CLK("omap_i2c.2", "ick", &i2c2_ick),
1973 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), 1973 CLK(NULL, "i2c2_ick", &i2c2_ick),
1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), 1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck),
1975 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), 1975 CLK(NULL, "gpmc_fck", &gpmc_fck),
1976 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), 1976 CLK(NULL, "sdma_fck", &sdma_fck),
1977 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), 1977 CLK(NULL, "sdma_ick", &sdma_ick),
1978 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), 1978 CLK(NULL, "sdrc_ick", &sdrc_ick),
1979 CLK(NULL, "des_ick", &des_ick, CK_243X), 1979 CLK(NULL, "des_ick", &des_ick),
1980 CLK("omap-sham", "ick", &sha_ick, CK_243X), 1980 CLK("omap-sham", "ick", &sha_ick),
1981 CLK("omap_rng", "ick", &rng_ick, CK_243X), 1981 CLK("omap_rng", "ick", &rng_ick),
1982 CLK(NULL, "rng_ick", &rng_ick, CK_243X), 1982 CLK(NULL, "rng_ick", &rng_ick),
1983 CLK("omap-aes", "ick", &aes_ick, CK_243X), 1983 CLK("omap-aes", "ick", &aes_ick),
1984 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1984 CLK(NULL, "pka_ick", &pka_ick),
1985 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1985 CLK(NULL, "usb_fck", &usb_fck),
1986 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 1986 CLK("musb-omap2430", "ick", &usbhs_ick),
1987 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), 1987 CLK(NULL, "usbhs_ick", &usbhs_ick),
1988 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), 1988 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
1989 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), 1989 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
1990 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), 1990 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
1991 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), 1991 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
1992 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), 1992 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
1993 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), 1993 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
1994 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 1994 CLK(NULL, "gpio5_ick", &gpio5_ick),
1995 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 1995 CLK(NULL, "gpio5_fck", &gpio5_fck),
1996 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1996 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
1997 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1997 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
1998 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), 1998 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
1999 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 1999 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
2000 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), 2000 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
2001 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), 2001 CLK(NULL, "timer_32k_ck", &func_32k_ck),
2002 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), 2002 CLK(NULL, "timer_sys_ck", &sys_ck),
2003 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), 2003 CLK(NULL, "timer_ext_ck", &alt_ck),
2004 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), 2004 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
2005}; 2005};
2006 2006
2007static const char *enable_init_clks[] = { 2007static const char *enable_init_clks[] = {
@@ -2019,8 +2019,6 @@ static const char *enable_init_clks[] = {
2019 2019
2020int __init omap2430_clk_init(void) 2020int __init omap2430_clk_init(void)
2021{ 2021{
2022 struct omap_clk *c;
2023
2024 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; 2022 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2025 cpu_mask = RATE_IN_243X; 2023 cpu_mask = RATE_IN_243X;
2026 rate_table = omap2430_rate_table; 2024 rate_table = omap2430_rate_table;
@@ -2029,12 +2027,7 @@ int __init omap2430_clk_init(void)
2029 2027
2030 omap2xxx_clkt_vps_check_bootloader_rates(); 2028 omap2xxx_clkt_vps_check_bootloader_rates();
2031 2029
2032 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); 2030 omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
2033 c++) {
2034 clkdev_add(&c->lk);
2035 if (!__clk_init(NULL, c->lk.clk))
2036 omap2_init_clk_hw_omap_clocks(c->lk.clk);
2037 }
2038 2031
2039 omap2xxx_clkt_vps_late_init(); 2032 omap2xxx_clkt_vps_late_init();
2040 2033
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..dcc5bf57a263 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -838,80 +838,80 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
838 * clkdev 838 * clkdev
839 */ 839 */
840static struct omap_clk am33xx_clks[] = { 840static struct omap_clk am33xx_clks[] = {
841 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), 841 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
842 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), 842 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
843 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), 843 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
844 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), 844 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
845 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), 845 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
846 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), 846 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
847 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), 847 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
848 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), 848 CLK(NULL, "tclkin_ck", &tclkin_ck),
849 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), 849 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
850 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), 850 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
851 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), 851 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
852 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), 852 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
853 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), 853 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
854 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), 854 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
855 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), 855 CLK("cpu0", NULL, &dpll_mpu_ck),
856 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), 856 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
857 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), 857 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
858 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), 858 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
859 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), 859 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
860 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), 860 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
861 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), 861 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
862 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), 862 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
863 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), 863 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
864 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), 864 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
865 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), 865 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
866 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), 866 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
867 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), 867 CLK(NULL, "cefuse_fck", &cefuse_fck),
868 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), 868 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
869 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), 869 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
870 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), 870 CLK(NULL, "dcan0_fck", &dcan0_fck),
871 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), 871 CLK("481cc000.d_can", NULL, &dcan0_fck),
872 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), 872 CLK(NULL, "dcan1_fck", &dcan1_fck),
873 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), 873 CLK("481d0000.d_can", NULL, &dcan1_fck),
874 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), 874 CLK(NULL, "debugss_ick", &debugss_ick),
875 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), 875 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
876 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), 876 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
877 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), 877 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
878 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), 878 CLK(NULL, "mmu_fck", &mmu_fck),
879 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), 879 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
880 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), 880 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
881 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), 881 CLK(NULL, "timer1_fck", &timer1_fck),
882 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), 882 CLK(NULL, "timer2_fck", &timer2_fck),
883 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), 883 CLK(NULL, "timer3_fck", &timer3_fck),
884 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), 884 CLK(NULL, "timer4_fck", &timer4_fck),
885 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), 885 CLK(NULL, "timer5_fck", &timer5_fck),
886 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), 886 CLK(NULL, "timer6_fck", &timer6_fck),
887 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), 887 CLK(NULL, "timer7_fck", &timer7_fck),
888 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), 888 CLK(NULL, "usbotg_fck", &usbotg_fck),
889 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), 889 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
890 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), 890 CLK(NULL, "wdt1_fck", &wdt1_fck),
891 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), 891 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
892 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), 892 CLK(NULL, "l3_gclk", &l3_gclk),
893 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), 893 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
894 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), 894 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
895 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), 895 CLK(NULL, "l3s_gclk", &l3s_gclk),
896 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), 896 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
897 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), 897 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
898 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), 898 CLK(NULL, "clk_24mhz", &clk_24mhz),
899 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), 899 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
900 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), 900 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
901 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), 901 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
902 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), 902 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
903 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), 903 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
904 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), 904 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
905 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), 905 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
906 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), 906 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
907 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), 907 CLK(NULL, "lcd_gclk", &lcd_gclk),
908 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), 908 CLK(NULL, "mmc_clk", &mmc_clk),
909 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), 909 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
910 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), 910 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
911 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), 911 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
912 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), 912 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
913 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), 913 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
914 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), 914 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
915}; 915};
916 916
917 917
@@ -926,21 +926,10 @@ static const char *enable_init_clks[] = {
926 926
927int __init am33xx_clk_init(void) 927int __init am33xx_clk_init(void)
928{ 928{
929 struct omap_clk *c; 929 if (soc_is_am33xx())
930 u32 cpu_clkflg;
931
932 if (soc_is_am33xx()) {
933 cpu_mask = RATE_IN_AM33XX; 930 cpu_mask = RATE_IN_AM33XX;
934 cpu_clkflg = CK_AM33XX; 931
935 } 932 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
936
937 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
938 if (c->cpu & cpu_clkflg) {
939 clkdev_add(&c->lk);
940 if (!__clk_init(NULL, c->lk.clk))
941 omap2_init_clk_hw_omap_clocks(c->lk.clk);
942 }
943 }
944 933
945 omap2_clk_disable_autoidle_all(); 934 omap2_clk_disable_autoidle_all();
946 935
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 4579c3c5338f..438d13341e23 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3219,289 +3219,325 @@ static struct clk_hw_omap wdt3_ick_hw = {
3219DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); 3219DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3220 3220
3221/* 3221/*
3222 * clkdev 3222 * clocks specific to omap3430es1
3223 */
3224static struct omap_clk omap3430es1_clks[] = {
3225 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3226 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3227 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3228 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3229 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3230 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3231 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3232 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3233 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3234 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3235 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3236 CLK(NULL, "fac_ick", &fac_ick),
3237 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3238 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3239 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3240 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3241 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3242};
3243
3244/*
3245 * clocks specific to am35xx
3246 */
3247static struct omap_clk am35xx_clks[] = {
3248 CLK(NULL, "ipss_ick", &ipss_ick),
3249 CLK(NULL, "rmii_ck", &rmii_ck),
3250 CLK(NULL, "pclk_ck", &pclk_ck),
3251 CLK(NULL, "emac_ick", &emac_ick),
3252 CLK(NULL, "emac_fck", &emac_fck),
3253 CLK("davinci_emac.0", NULL, &emac_ick),
3254 CLK("davinci_mdio.0", NULL, &emac_fck),
3255 CLK("vpfe-capture", "master", &vpfe_ick),
3256 CLK("vpfe-capture", "slave", &vpfe_fck),
3257 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3258 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3259 CLK(NULL, "hecc_ck", &hecc_ck),
3260 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3261 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3262};
3263
3264/*
3265 * clocks specific to omap36xx
3266 */
3267static struct omap_clk omap36xx_clks[] = {
3268 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3269 CLK(NULL, "uart4_fck", &uart4_fck),
3270};
3271
3272/*
3273 * clocks common to omap36xx omap34xx
3274 */
3275static struct omap_clk omap34xx_omap36xx_clks[] = {
3276 CLK(NULL, "aes1_ick", &aes1_ick),
3277 CLK("omap_rng", "ick", &rng_ick),
3278 CLK(NULL, "sha11_ick", &sha11_ick),
3279 CLK(NULL, "des1_ick", &des1_ick),
3280 CLK(NULL, "cam_mclk", &cam_mclk),
3281 CLK(NULL, "cam_ick", &cam_ick),
3282 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3283 CLK(NULL, "security_l3_ick", &security_l3_ick),
3284 CLK(NULL, "pka_ick", &pka_ick),
3285 CLK(NULL, "icr_ick", &icr_ick),
3286 CLK("omap-aes", "ick", &aes2_ick),
3287 CLK("omap-sham", "ick", &sha12_ick),
3288 CLK(NULL, "des2_ick", &des2_ick),
3289 CLK(NULL, "mspro_ick", &mspro_ick),
3290 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3291 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3292 CLK(NULL, "sr1_fck", &sr1_fck),
3293 CLK(NULL, "sr2_fck", &sr2_fck),
3294 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3295 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3296 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3297 CLK(NULL, "dpll2_fck", &dpll2_fck),
3298 CLK(NULL, "iva2_ck", &iva2_ck),
3299 CLK(NULL, "modem_fck", &modem_fck),
3300 CLK(NULL, "sad2d_ick", &sad2d_ick),
3301 CLK(NULL, "mad2d_ick", &mad2d_ick),
3302 CLK(NULL, "mspro_fck", &mspro_fck),
3303 CLK(NULL, "dpll2_ck", &dpll2_ck),
3304 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3305};
3306
3307/*
3308 * clocks common to omap36xx and omap3430es2plus
3309 */
3310static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3312 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3313 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3314 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3315 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3316 CLK(NULL, "usim_fck", &usim_fck),
3317 CLK(NULL, "usim_ick", &usim_ick),
3318};
3319
3320/*
3321 * clocks common to am35xx omap36xx and omap3430es2plus
3322 */
3323static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3324 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3325 CLK(NULL, "dpll5_ck", &dpll5_ck),
3326 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3327 CLK(NULL, "sgx_fck", &sgx_fck),
3328 CLK(NULL, "sgx_ick", &sgx_ick),
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3330 CLK(NULL, "ts_fck", &ts_fck),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck),
3332 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
3333 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
3334 CLK(NULL, "usbtll_ick", &usbtll_ick),
3335 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
3336 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
3337 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3338 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3339 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3340 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3341 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3342 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3343 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3344 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3345 CLK(NULL, "usbhost_ick", &usbhost_ick),
3346 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
3347};
3348
3349/*
3350 * common clocks
3223 */ 3351 */
3224static struct omap_clk omap3xxx_clks[] = { 3352static struct omap_clk omap3xxx_clks[] = {
3225 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), 3353 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3226 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3354 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3227 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3355 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3228 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3356 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3229 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3357 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3230 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), 3358 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3231 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), 3359 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3232 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3360 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3233 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3361 CLK("twl", "fck", &osc_sys_ck),
3234 CLK("twl", "fck", &osc_sys_ck, CK_3XXX), 3362 CLK(NULL, "sys_ck", &sys_ck),
3235 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3363 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3236 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3364 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3237 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3365 CLK(NULL, "sys_altclk", &sys_altclk),
3238 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3366 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3239 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3367 CLK(NULL, "sys_clkout1", &sys_clkout1),
3240 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), 3368 CLK(NULL, "dpll1_ck", &dpll1_ck),
3241 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), 3369 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3242 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), 3370 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3243 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), 3371 CLK(NULL, "dpll3_ck", &dpll3_ck),
3244 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), 3372 CLK(NULL, "core_ck", &core_ck),
3245 CLK(NULL, "core_ck", &core_ck, CK_3XXX), 3373 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3246 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), 3374 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3247 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), 3375 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3248 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), 3376 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3249 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), 3377 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3250 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), 3378 CLK(NULL, "dpll4_ck", &dpll4_ck),
3251 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), 3379 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3252 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), 3380 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3253 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), 3381 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3254 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), 3382 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3255 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), 3383 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3256 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), 3384 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3257 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), 3385 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3258 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), 3386 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3259 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), 3387 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3260 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), 3388 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3261 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), 3389 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3262 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), 3390 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3263 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), 3391 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3264 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), 3392 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3265 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), 3393 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3266 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), 3394 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3267 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), 3395 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3268 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), 3396 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3269 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3397 CLK(NULL, "sys_clkout2", &sys_clkout2),
3270 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3398 CLK(NULL, "corex2_fck", &corex2_fck),
3271 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3399 CLK(NULL, "dpll1_fck", &dpll1_fck),
3272 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3400 CLK(NULL, "mpu_ck", &mpu_ck),
3273 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3401 CLK(NULL, "arm_fck", &arm_fck),
3274 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), 3402 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3275 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), 3403 CLK(NULL, "l3_ick", &l3_ick),
3276 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), 3404 CLK(NULL, "l4_ick", &l4_ick),
3277 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), 3405 CLK(NULL, "rm_ick", &rm_ick),
3278 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3406 CLK(NULL, "gpt10_fck", &gpt10_fck),
3279 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3407 CLK(NULL, "gpt11_fck", &gpt11_fck),
3280 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3408 CLK(NULL, "core_96m_fck", &core_96m_fck),
3281 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), 3409 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3282 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), 3410 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3283 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), 3411 CLK(NULL, "i2c3_fck", &i2c3_fck),
3284 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), 3412 CLK(NULL, "i2c2_fck", &i2c2_fck),
3285 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), 3413 CLK(NULL, "i2c1_fck", &i2c1_fck),
3286 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), 3414 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3287 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), 3415 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3288 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3416 CLK(NULL, "core_48m_fck", &core_48m_fck),
3289 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3417 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3290 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3418 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3291 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3419 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3292 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3420 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3293 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3421 CLK(NULL, "uart2_fck", &uart2_fck),
3294 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), 3422 CLK(NULL, "uart1_fck", &uart1_fck),
3295 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), 3423 CLK(NULL, "core_12m_fck", &core_12m_fck),
3296 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), 3424 CLK("omap_hdq.0", "fck", &hdq_fck),
3297 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), 3425 CLK(NULL, "hdq_fck", &hdq_fck),
3298 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), 3426 CLK(NULL, "core_l3_ick", &core_l3_ick),
3299 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3427 CLK(NULL, "sdrc_ick", &sdrc_ick),
3300 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3428 CLK(NULL, "gpmc_fck", &gpmc_fck),
3301 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3429 CLK(NULL, "core_l4_ick", &core_l4_ick),
3302 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3430 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3303 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3431 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3304 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3432 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3305 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3433 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3306 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3434 CLK("omap_hdq.0", "ick", &hdq_ick),
3307 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3435 CLK(NULL, "hdq_ick", &hdq_ick),
3308 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), 3436 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3309 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), 3437 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3310 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), 3438 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3311 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), 3439 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3312 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), 3440 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3313 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), 3441 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3314 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), 3442 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3315 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), 3443 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3316 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), 3444 CLK("omap_i2c.3", "ick", &i2c3_ick),
3317 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), 3445 CLK("omap_i2c.2", "ick", &i2c2_ick),
3318 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), 3446 CLK("omap_i2c.1", "ick", &i2c1_ick),
3319 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), 3447 CLK(NULL, "i2c3_ick", &i2c3_ick),
3320 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), 3448 CLK(NULL, "i2c2_ick", &i2c2_ick),
3321 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), 3449 CLK(NULL, "i2c1_ick", &i2c1_ick),
3322 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3450 CLK(NULL, "uart2_ick", &uart2_ick),
3323 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3451 CLK(NULL, "uart1_ick", &uart1_ick),
3324 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), 3452 CLK(NULL, "gpt11_ick", &gpt11_ick),
3325 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3453 CLK(NULL, "gpt10_ick", &gpt10_ick),
3326 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3454 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3327 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3455 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3328 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3456 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3329 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3457 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3330 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3458 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3331 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3459 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3332 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3460 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3333 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3461 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3334 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3462 CLK(NULL, "utmi_p1_gfclk", &dummy_ck),
3335 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3463 CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
3336 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), 3464 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
3337 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), 3465 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
3338 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3466 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
3339 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3467 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
3340 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3468 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3341 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3469 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3342 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3470 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3343 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3471 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3344 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3472 CLK(NULL, "init_60m_fclk", &dummy_ck),
3345 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3473 CLK(NULL, "gpt1_fck", &gpt1_fck),
3346 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3474 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3347 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3475 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3348 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), 3476 CLK(NULL, "wdt2_fck", &wdt2_fck),
3349 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), 3477 CLK("omap_wdt", "ick", &wdt2_ick),
3350 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), 3478 CLK(NULL, "wdt2_ick", &wdt2_ick),
3351 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), 3479 CLK(NULL, "wdt1_ick", &wdt1_ick),
3352 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3480 CLK(NULL, "gpio1_ick", &gpio1_ick),
3353 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3481 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3354 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), 3482 CLK(NULL, "gpt12_ick", &gpt12_ick),
3355 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3483 CLK(NULL, "gpt1_ick", &gpt1_ick),
3356 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3484 CLK(NULL, "per_96m_fck", &per_96m_fck),
3357 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), 3485 CLK(NULL, "per_48m_fck", &per_48m_fck),
3358 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), 3486 CLK(NULL, "uart3_fck", &uart3_fck),
3359 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), 3487 CLK(NULL, "gpt2_fck", &gpt2_fck),
3360 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), 3488 CLK(NULL, "gpt3_fck", &gpt3_fck),
3361 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), 3489 CLK(NULL, "gpt4_fck", &gpt4_fck),
3362 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), 3490 CLK(NULL, "gpt5_fck", &gpt5_fck),
3363 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), 3491 CLK(NULL, "gpt6_fck", &gpt6_fck),
3364 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), 3492 CLK(NULL, "gpt7_fck", &gpt7_fck),
3365 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), 3493 CLK(NULL, "gpt8_fck", &gpt8_fck),
3366 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), 3494 CLK(NULL, "gpt9_fck", &gpt9_fck),
3367 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), 3495 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3368 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), 3496 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3369 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), 3497 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3370 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), 3498 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3371 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), 3499 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3372 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), 3500 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3373 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3501 CLK(NULL, "wdt3_fck", &wdt3_fck),
3374 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3502 CLK(NULL, "per_l4_ick", &per_l4_ick),
3375 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), 3503 CLK(NULL, "gpio6_ick", &gpio6_ick),
3376 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), 3504 CLK(NULL, "gpio5_ick", &gpio5_ick),
3377 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3505 CLK(NULL, "gpio4_ick", &gpio4_ick),
3378 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), 3506 CLK(NULL, "gpio3_ick", &gpio3_ick),
3379 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3507 CLK(NULL, "gpio2_ick", &gpio2_ick),
3380 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), 3508 CLK(NULL, "wdt3_ick", &wdt3_ick),
3381 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), 3509 CLK(NULL, "uart3_ick", &uart3_ick),
3382 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3510 CLK(NULL, "uart4_ick", &uart4_ick),
3383 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 3511 CLK(NULL, "gpt9_ick", &gpt9_ick),
3384 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), 3512 CLK(NULL, "gpt8_ick", &gpt8_ick),
3385 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), 3513 CLK(NULL, "gpt7_ick", &gpt7_ick),
3386 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), 3514 CLK(NULL, "gpt6_ick", &gpt6_ick),
3387 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), 3515 CLK(NULL, "gpt5_ick", &gpt5_ick),
3388 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), 3516 CLK(NULL, "gpt4_ick", &gpt4_ick),
3389 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3517 CLK(NULL, "gpt3_ick", &gpt3_ick),
3390 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3518 CLK(NULL, "gpt2_ick", &gpt2_ick),
3391 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), 3519 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3392 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), 3520 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3393 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), 3521 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3394 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), 3522 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3395 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), 3523 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3396 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3524 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3397 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3525 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3398 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), 3526 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3399 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), 3527 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3400 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), 3528 CLK("etb", "emu_src_ck", &emu_src_ck),
3401 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3529 CLK(NULL, "emu_src_ck", &emu_src_ck),
3402 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3530 CLK(NULL, "pclk_fck", &pclk_fck),
3403 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3531 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3404 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3532 CLK(NULL, "atclk_fck", &atclk_fck),
3405 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), 3533 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3406 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), 3534 CLK(NULL, "traceclk_fck", &traceclk_fck),
3407 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), 3535 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3408 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), 3536 CLK(NULL, "gpt12_fck", &gpt12_fck),
3409 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), 3537 CLK(NULL, "wdt1_fck", &wdt1_fck),
3410 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), 3538 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3411 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), 3539 CLK(NULL, "timer_sys_ck", &sys_ck),
3412 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), 3540 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3413 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3414 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3415 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3416 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3417 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3418 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3419 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3420 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3421 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3422 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3423 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3424 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3425 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3426 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3427 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3428 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3429 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3430 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3431 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3432 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3433 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3434 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3435 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3436 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3437 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3438 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3439 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3440 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3441 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3442 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3443 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3444 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3445 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3446 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3447 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3448 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3449 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3450 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3451 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3452 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3453 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3454 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3455 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3456 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3457 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3458 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3459 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3460 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3461 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3462 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3463 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3464 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3465 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3466 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3467 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3468 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3469 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3470 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3471 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3472 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3473 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3474 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3475 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3476 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3477 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3478 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3479 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3480 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3481 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3482 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3483 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3484 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3485 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3486 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3487 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3488 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3489 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3490 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3491 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3492 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3493 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3494 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3495 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3496 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3497 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3498 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3499 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3500 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3501 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3502 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3503 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3504 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3505}; 3541};
3506 3542
3507static const char *enable_init_clks[] = { 3543static const char *enable_init_clks[] = {
@@ -3512,8 +3548,27 @@ static const char *enable_init_clks[] = {
3512 3548
3513int __init omap3xxx_clk_init(void) 3549int __init omap3xxx_clk_init(void)
3514{ 3550{
3515 struct omap_clk *c; 3551 if (omap3_has_192mhz_clk())
3516 u32 cpu_clkflg = 0; 3552 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3553
3554 if (cpu_is_omap3630()) {
3555 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3556 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3557 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3558 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3559 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3560 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3561 }
3562
3563 /*
3564 * XXX This type of dynamic rewriting of the clock tree is
3565 * deprecated and should be revised soon.
3566 */
3567 if (cpu_is_omap3630())
3568 dpll4_dd = dpll4_dd_3630;
3569 else
3570 dpll4_dd = dpll4_dd_34xx;
3571
3517 3572
3518 /* 3573 /*
3519 * 3505 must be tested before 3517, since 3517 returns true 3574 * 3505 must be tested before 3517, since 3517 returns true
@@ -3523,13 +3578,20 @@ int __init omap3xxx_clk_init(void)
3523 */ 3578 */
3524 if (soc_is_am35xx()) { 3579 if (soc_is_am35xx()) {
3525 cpu_mask = RATE_IN_34XX; 3580 cpu_mask = RATE_IN_34XX;
3526 cpu_clkflg = CK_AM35XX; 3581 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3582 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3583 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3584 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3527 } else if (cpu_is_omap3630()) { 3585 } else if (cpu_is_omap3630()) {
3528 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); 3586 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3529 cpu_clkflg = CK_36XX; 3587 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3530 } else if (cpu_is_ti816x()) { 3588 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3531 cpu_mask = RATE_IN_TI816X; 3589 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3532 cpu_clkflg = CK_TI816X; 3590 omap_clocks_register(omap34xx_omap36xx_clks,
3591 ARRAY_SIZE(omap34xx_omap36xx_clks));
3592 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3593 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3594 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3533 } else if (soc_is_am33xx()) { 3595 } else if (soc_is_am33xx()) {
3534 cpu_mask = RATE_IN_AM33XX; 3596 cpu_mask = RATE_IN_AM33XX;
3535 } else if (cpu_is_ti814x()) { 3597 } else if (cpu_is_ti814x()) {
@@ -3537,49 +3599,32 @@ int __init omap3xxx_clk_init(void)
3537 } else if (cpu_is_omap34xx()) { 3599 } else if (cpu_is_omap34xx()) {
3538 if (omap_rev() == OMAP3430_REV_ES1_0) { 3600 if (omap_rev() == OMAP3430_REV_ES1_0) {
3539 cpu_mask = RATE_IN_3430ES1; 3601 cpu_mask = RATE_IN_3430ES1;
3540 cpu_clkflg = CK_3430ES1; 3602 omap_clocks_register(omap3430es1_clks,
3603 ARRAY_SIZE(omap3430es1_clks));
3604 omap_clocks_register(omap34xx_omap36xx_clks,
3605 ARRAY_SIZE(omap34xx_omap36xx_clks));
3606 omap_clocks_register(omap3xxx_clks,
3607 ARRAY_SIZE(omap3xxx_clks));
3541 } else { 3608 } else {
3542 /* 3609 /*
3543 * Assume that anything that we haven't matched yet 3610 * Assume that anything that we haven't matched yet
3544 * has 3430ES2-type clocks. 3611 * has 3430ES2-type clocks.
3545 */ 3612 */
3546 cpu_mask = RATE_IN_3430ES2PLUS; 3613 cpu_mask = RATE_IN_3430ES2PLUS;
3547 cpu_clkflg = CK_3430ES2PLUS; 3614 omap_clocks_register(omap34xx_omap36xx_clks,
3615 ARRAY_SIZE(omap34xx_omap36xx_clks));
3616 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3617 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3618 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3619 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3620 omap_clocks_register(omap3xxx_clks,
3621 ARRAY_SIZE(omap3xxx_clks));
3548 } 3622 }
3549 } else { 3623 } else {
3550 WARN(1, "clock: could not identify OMAP3 variant\n"); 3624 WARN(1, "clock: could not identify OMAP3 variant\n");
3551 } 3625 }
3552 3626
3553 if (omap3_has_192mhz_clk()) 3627 omap2_clk_disable_autoidle_all();
3554 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3555
3556 if (cpu_is_omap3630()) {
3557 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3558 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3559 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3560 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3561 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3562 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3563 }
3564
3565 /*
3566 * XXX This type of dynamic rewriting of the clock tree is
3567 * deprecated and should be revised soon.
3568 */
3569 if (cpu_is_omap3630())
3570 dpll4_dd = dpll4_dd_3630;
3571 else
3572 dpll4_dd = dpll4_dd_34xx;
3573
3574 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3575 c++)
3576 if (c->cpu & cpu_clkflg) {
3577 clkdev_add(&c->lk);
3578 if (!__clk_init(NULL, c->lk.clk))
3579 omap2_init_clk_hw_omap_clocks(c->lk.clk);
3580 }
3581
3582 omap2_clk_disable_autoidle_all();
3583 3628
3584 omap2_clk_enable_init_clocks(enable_init_clks, 3629 omap2_clk_enable_init_clocks(enable_init_clks,
3585 ARRAY_SIZE(enable_init_clks)); 3630 ARRAY_SIZE(enable_init_clks));
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 3d58f335f173..b1e77ef968fa 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1413,283 +1413,284 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1413 0x0, NULL); 1413 0x0, NULL);
1414 1414
1415/* 1415/*
1416 * clkdev 1416 * clocks specific to omap4460
1417 */ 1417 */
1418static struct omap_clk omap446x_clks[] = {
1419 CLK(NULL, "div_ts_ck", &div_ts_ck),
1420 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
1421};
1422
1423/*
1424 * clocks specific to omap4430
1425 */
1426static struct omap_clk omap443x_clks[] = {
1427 CLK(NULL, "bandgap_fclk", &bandgap_fclk),
1428};
1418 1429
1430/*
1431 * clocks common to omap44xx
1432 */
1419static struct omap_clk omap44xx_clks[] = { 1433static struct omap_clk omap44xx_clks[] = {
1420 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), 1434 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
1421 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), 1435 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
1422 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), 1436 CLK(NULL, "pad_clks_ck", &pad_clks_ck),
1423 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), 1437 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
1424 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), 1438 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
1425 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), 1439 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
1426 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), 1440 CLK(NULL, "slimbus_clk", &slimbus_clk),
1427 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), 1441 CLK(NULL, "sys_32k_ck", &sys_32k_ck),
1428 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), 1442 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
1429 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), 1443 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
1430 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), 1444 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
1431 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), 1445 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
1432 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), 1446 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
1433 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 1447 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
1434 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 1448 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
1435 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 1449 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
1436 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), 1450 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
1437 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 1451 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
1438 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 1452 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
1439 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 1453 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
1440 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 1454 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
1441 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), 1455 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
1442 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 1456 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
1443 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 1457 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
1444 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), 1458 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
1445 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 1459 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
1446 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), 1460 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
1447 CLK(NULL, "abe_clk", &abe_clk, CK_443X), 1461 CLK(NULL, "abe_clk", &abe_clk),
1448 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), 1462 CLK(NULL, "aess_fclk", &aess_fclk),
1449 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), 1463 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
1450 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), 1464 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
1451 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), 1465 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
1452 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), 1466 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
1453 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), 1467 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
1454 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), 1468 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
1455 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), 1469 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
1456 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), 1470 CLK(NULL, "ddrphy_ck", &ddrphy_ck),
1457 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), 1471 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
1458 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), 1472 CLK(NULL, "div_core_ck", &div_core_ck),
1459 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), 1473 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
1460 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), 1474 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
1461 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), 1475 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
1462 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), 1476 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
1463 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), 1477 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
1464 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), 1478 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
1465 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), 1479 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
1466 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), 1480 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
1467 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), 1481 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
1468 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), 1482 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
1469 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), 1483 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
1470 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), 1484 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
1471 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), 1485 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
1472 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), 1486 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
1473 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), 1487 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
1474 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), 1488 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
1475 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), 1489 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
1476 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), 1490 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
1477 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), 1491 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
1478 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), 1492 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
1479 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), 1493 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
1480 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), 1494 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
1481 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), 1495 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
1482 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), 1496 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
1483 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), 1497 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
1484 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 1498 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
1485 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 1499 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
1486 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), 1500 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
1487 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), 1501 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
1488 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), 1502 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
1489 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), 1503 CLK(NULL, "func_12m_fclk", &func_12m_fclk),
1490 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), 1504 CLK(NULL, "func_24m_clk", &func_24m_clk),
1491 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), 1505 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
1492 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), 1506 CLK(NULL, "func_48m_fclk", &func_48m_fclk),
1493 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 1507 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
1494 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 1508 CLK(NULL, "func_64m_fclk", &func_64m_fclk),
1495 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 1509 CLK(NULL, "func_96m_fclk", &func_96m_fclk),
1496 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 1510 CLK(NULL, "init_60m_fclk", &init_60m_fclk),
1497 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 1511 CLK(NULL, "l3_div_ck", &l3_div_ck),
1498 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 1512 CLK(NULL, "l4_div_ck", &l4_div_ck),
1499 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 1513 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
1500 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 1514 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
1501 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), 1515 CLK("smp_twd", NULL, &mpu_periphclk),
1502 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 1516 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
1503 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 1517 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
1504 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), 1518 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
1505 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 1519 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
1506 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 1520 CLK(NULL, "aes1_fck", &aes1_fck),
1507 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 1521 CLK(NULL, "aes2_fck", &aes2_fck),
1508 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 1522 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
1509 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), 1523 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
1510 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), 1524 CLK(NULL, "dss_sys_clk", &dss_sys_clk),
1511 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 1525 CLK(NULL, "dss_tv_clk", &dss_tv_clk),
1512 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X), 1526 CLK(NULL, "dss_dss_clk", &dss_dss_clk),
1513 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), 1527 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
1514 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 1528 CLK(NULL, "dss_fck", &dss_fck),
1515 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 1529 CLK("omapdss_dss", "ick", &dss_fck),
1516 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 1530 CLK(NULL, "fdif_fck", &fdif_fck),
1517 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 1531 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
1518 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 1532 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
1519 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 1533 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1520 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 1534 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
1521 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 1535 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
1522 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 1536 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
1523 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 1537 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
1524 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 1538 CLK(NULL, "hsi_fck", &hsi_fck),
1525 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 1539 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
1526 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X), 1540 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
1527 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 1541 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
1528 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 1542 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
1529 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 1543 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
1530 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X), 1544 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
1531 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 1545 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
1532 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X), 1546 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
1533 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 1547 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
1534 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X), 1548 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
1535 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 1549 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
1536 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X), 1550 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
1537 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 1551 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
1538 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), 1552 CLK(NULL, "sha2md5_fck", &sha2md5_fck),
1539 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), 1553 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
1540 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), 1554 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
1541 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1555 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
1542 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1556 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
1543 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1557 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
1544 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 1558 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
1545 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 1559 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
1546 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 1560 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
1547 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 1561 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
1548 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 1562 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
1549 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 1563 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
1550 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 1564 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
1551 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 1565 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
1552 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X), 1566 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
1553 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X), 1567 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
1554 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X), 1568 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
1555 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X), 1569 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
1556 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X), 1570 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
1557 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X), 1571 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
1558 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X), 1572 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
1559 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X), 1573 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
1560 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X), 1574 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
1561 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X), 1575 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
1562 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X), 1576 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
1563 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 1577 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
1564 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 1578 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
1565 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 1579 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
1566 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 1580 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
1567 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), 1581 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
1568 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), 1582 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
1569 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), 1583 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
1570 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), 1584 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
1571 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), 1585 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
1572 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 1586 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
1573 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 1587 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
1574 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 1588 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
1575 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), 1589 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
1576 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), 1590 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
1577 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 1591 CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
1578 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 1592 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
1579 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), 1593 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
1580 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 1594 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
1581 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), 1595 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
1582 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 1596 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
1583 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 1597 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
1584 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 1598 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
1585 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), 1599 CLK(NULL, "usim_ck", &usim_ck),
1586 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1600 CLK(NULL, "usim_fclk", &usim_fclk),
1587 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1601 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
1588 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 1602 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
1589 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 1603 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1590 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 1604 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1591 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 1605 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
1592 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 1606 CLK(NULL, "auxclk0_ck", &auxclk0_ck),
1593 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 1607 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
1594 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), 1608 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
1595 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), 1609 CLK(NULL, "auxclk1_ck", &auxclk1_ck),
1596 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), 1610 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
1597 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), 1611 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
1598 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), 1612 CLK(NULL, "auxclk2_ck", &auxclk2_ck),
1599 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), 1613 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
1600 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), 1614 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
1601 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), 1615 CLK(NULL, "auxclk3_ck", &auxclk3_ck),
1602 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), 1616 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
1603 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), 1617 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
1604 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), 1618 CLK(NULL, "auxclk4_ck", &auxclk4_ck),
1605 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), 1619 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
1606 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), 1620 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1607 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), 1621 CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1608 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), 1622 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1609 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), 1623 CLK("omap-gpmc", "fck", &dummy_ck),
1610 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), 1624 CLK("omap_i2c.1", "ick", &dummy_ck),
1611 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 1625 CLK("omap_i2c.2", "ick", &dummy_ck),
1612 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), 1626 CLK("omap_i2c.3", "ick", &dummy_ck),
1613 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), 1627 CLK("omap_i2c.4", "ick", &dummy_ck),
1614 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 1628 CLK(NULL, "mailboxes_ick", &dummy_ck),
1615 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 1629 CLK("omap_hsmmc.0", "ick", &dummy_ck),
1616 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 1630 CLK("omap_hsmmc.1", "ick", &dummy_ck),
1617 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), 1631 CLK("omap_hsmmc.2", "ick", &dummy_ck),
1618 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), 1632 CLK("omap_hsmmc.3", "ick", &dummy_ck),
1619 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), 1633 CLK("omap_hsmmc.4", "ick", &dummy_ck),
1620 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), 1634 CLK("omap-mcbsp.1", "ick", &dummy_ck),
1621 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), 1635 CLK("omap-mcbsp.2", "ick", &dummy_ck),
1622 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), 1636 CLK("omap-mcbsp.3", "ick", &dummy_ck),
1623 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 1637 CLK("omap-mcbsp.4", "ick", &dummy_ck),
1624 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 1638 CLK("omap2_mcspi.1", "ick", &dummy_ck),
1625 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 1639 CLK("omap2_mcspi.2", "ick", &dummy_ck),
1626 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 1640 CLK("omap2_mcspi.3", "ick", &dummy_ck),
1627 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 1641 CLK("omap2_mcspi.4", "ick", &dummy_ck),
1628 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 1642 CLK(NULL, "uart1_ick", &dummy_ck),
1629 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 1643 CLK(NULL, "uart2_ick", &dummy_ck),
1630 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 1644 CLK(NULL, "uart3_ick", &dummy_ck),
1631 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 1645 CLK(NULL, "uart4_ick", &dummy_ck),
1632 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 1646 CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
1633 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 1647 CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
1634 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 1648 CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
1635 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), 1649 CLK("omap_wdt", "ick", &dummy_ck),
1636 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), 1650 CLK(NULL, "timer_32k_ck", &sys_32k_ck),
1637 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
1638 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
1639 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
1640 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ 1651 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1641 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1652 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
1642 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1653 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
1643 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1654 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
1644 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1655 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
1645 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1656 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
1646 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1657 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
1647 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1658 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
1648 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1659 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
1649 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1660 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
1650 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1661 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
1651 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1662 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
1652 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1663 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
1653 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1664 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
1654 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1665 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
1655 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1666 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
1656 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1667 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
1657 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1668 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
1658 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), 1669 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
1659 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1670 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
1660 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1671 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
1661 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1672 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
1662 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 1673 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
1663 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1674 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
1664}; 1675};
1665 1676
1666int __init omap4xxx_clk_init(void) 1677int __init omap4xxx_clk_init(void)
1667{ 1678{
1668 u32 cpu_clkflg;
1669 struct omap_clk *c;
1670 int rc; 1679 int rc;
1671 1680
1672 if (cpu_is_omap443x()) { 1681 if (cpu_is_omap443x()) {
1673 cpu_mask = RATE_IN_4430; 1682 cpu_mask = RATE_IN_4430;
1674 cpu_clkflg = CK_443X; 1683 omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
1675 } else if (cpu_is_omap446x() || cpu_is_omap447x()) { 1684 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1676 cpu_mask = RATE_IN_4460 | RATE_IN_4430; 1685 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1677 cpu_clkflg = CK_446X | CK_443X; 1686 omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
1678
1679 if (cpu_is_omap447x()) 1687 if (cpu_is_omap447x())
1680 pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); 1688 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1681 } else { 1689 } else {
1682 return 0; 1690 return 0;
1683 } 1691 }
1684 1692
1685 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); 1693 omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
1686 c++) {
1687 if (c->cpu & cpu_clkflg) {
1688 clkdev_add(&c->lk);
1689 if (!__clk_init(NULL, c->lk.clk))
1690 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1691 }
1692 }
1693 1694
1694 omap2_clk_disable_autoidle_all(); 1695 omap2_clk_disable_autoidle_all();
1695 1696
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e4ec3a69ee2e..8474c7d228ee 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,7 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26#include <linux/clk-private.h>
27#include <asm/cpu.h> 27#include <asm/cpu.h>
28 28
29 29
@@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
569}; 569};
570 570
571/** 571/**
572 * omap_clocks_register - register an array of omap_clk
573 * @ocs: pointer to an array of omap_clk to register
574 */
575void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
576{
577 struct omap_clk *c;
578
579 for (c = oclks; c < oclks + cnt; c++) {
580 clkdev_add(&c->lk);
581 if (!__clk_init(NULL, c->lk.clk))
582 omap2_init_clk_hw_omap_clocks(c->lk.clk);
583 }
584}
585
586/**
572 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 587 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
573 * @mpurate_ck_name: clk name of the clock to change rate 588 * @mpurate_ck_name: clk name of the clock to change rate
574 * 589 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 60ddd8612b4d..7aa32cd292f9 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -27,9 +27,8 @@ struct omap_clk {
27 struct clk_lookup lk; 27 struct clk_lookup lk;
28}; 28};
29 29
30#define CLK(dev, con, ck, cp) \ 30#define CLK(dev, con, ck) \
31 { \ 31 { \
32 .cpu = cp, \
33 .lk = { \ 32 .lk = { \
34 .dev_id = dev, \ 33 .dev_id = dev, \
35 .con_id = con, \ 34 .con_id = con, \
@@ -37,22 +36,6 @@ struct omap_clk {
37 }, \ 36 }, \
38 } 37 }
39 38
40/* Platform flags for the clkdev-OMAP integration code */
41#define CK_242X (1 << 0)
42#define CK_243X (1 << 1) /* 243x, 253x */
43#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
44#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
45#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
46#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
47#define CK_443X (1 << 6)
48#define CK_TI816X (1 << 7)
49#define CK_446X (1 << 8)
50#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
51
52
53#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
54#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
55
56struct clockdomain; 39struct clockdomain;
57#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 40#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
58 41
@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
480extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 463extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
481extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 464extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
482 465
466extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
483#endif 467#endif
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 80392fca86c6..06f567faf993 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -107,8 +107,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
107{ 107{
108 struct omap3_idle_statedata *cx = &omap3_idle_data[index]; 108 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
109 109
110 local_fiq_disable();
111
112 if (omap_irq_pending() || need_resched()) 110 if (omap_irq_pending() || need_resched())
113 goto return_sleep_time; 111 goto return_sleep_time;
114 112
@@ -143,7 +141,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
143 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); 141 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
144 142
145return_sleep_time: 143return_sleep_time:
146 local_fiq_enable();
147 144
148 return index; 145 return index;
149} 146}
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index d639aef0deda..944e64aad7e5 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -70,10 +70,7 @@ static int omap4_enter_idle_simple(struct cpuidle_device *dev,
70 struct cpuidle_driver *drv, 70 struct cpuidle_driver *drv,
71 int index) 71 int index)
72{ 72{
73 local_fiq_disable();
74 omap_do_wfi(); 73 omap_do_wfi();
75 local_fiq_enable();
76
77 return index; 74 return index;
78} 75}
79 76
@@ -84,8 +81,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
84 struct omap4_idle_statedata *cx = &omap4_idle_data[index]; 81 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
85 int cpu_id = smp_processor_id(); 82 int cpu_id = smp_processor_id();
86 83
87 local_fiq_disable();
88
89 /* 84 /*
90 * CPU0 has to wait and stay ON until CPU1 is OFF state. 85 * CPU0 has to wait and stay ON until CPU1 is OFF state.
91 * This is necessary to honour hardware recommondation 86 * This is necessary to honour hardware recommondation
@@ -158,8 +153,6 @@ fail:
158 cpuidle_coupled_parallel_barrier(dev, &abort_barrier); 153 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
159 cpu_done[dev->cpu] = false; 154 cpu_done[dev->cpu] = false;
160 155
161 local_fiq_enable();
162
163 return index; 156 return index;
164} 157}
165 158
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
index eba80dbc5218..65f80cacf178 100644
--- a/arch/arm/mach-omap2/dma.h
+++ b/arch/arm/mach-omap2/dma.h
@@ -22,69 +22,20 @@
22 22
23/* DMA channels for 24xx */ 23/* DMA channels for 24xx */
24#define OMAP24XX_DMA_NO_DEVICE 0 24#define OMAP24XX_DMA_NO_DEVICE 0
25#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
26#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ 25#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
27#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ 26#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
28#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 27#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
29#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
30#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
31#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
32#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
33#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
34#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ 28#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
35#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ 29#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
36#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
37#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
38#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
39#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
40#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ 30#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
41#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ 31#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
42#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ 32#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
43#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
44#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
45#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
46#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
47#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
48#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
49#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
50#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
51#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
52#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
53#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
54#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
55#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
56#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
57#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
58#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
59#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
60#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
61#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
62#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
63#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
64#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
65#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
66#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ 33#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
67#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ 34#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
68#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ 35#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
69#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ 36#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
70#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ 37#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
71#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ 38#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
72#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
73#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
74#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
75#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
76#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
77#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
78#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
79#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
80#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
81#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
82#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
83#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
84#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
85#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
86#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
87#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
88#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ 39#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
89#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ 40#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
90#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ 41#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
@@ -93,33 +44,12 @@
93#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ 44#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
94#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ 45#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
95#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ 46#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
96#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
97#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
98#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
99#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
100#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
101#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
102#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ 47#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
103#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ 48#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
104#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
105#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ 49#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
106#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
107#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
108#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ 50#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
109#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ 51#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
110#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
111#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
112#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ 52#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
113#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
114#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
115#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
116#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
117#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
118#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
119#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
120#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
121#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
122#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
123 53
124#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ 54#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
125#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ 55#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index e712d1725a8b..458f72f9dc8f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,11 +19,8 @@
19#include <linux/smp.h> 19#include <linux/smp.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/cacheflush.h>
23#include "omap-wakeupgen.h" 22#include "omap-wakeupgen.h"
24
25#include "common.h" 23#include "common.h"
26
27#include "powerdomain.h" 24#include "powerdomain.h"
28 25
29/* 26/*
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
35 unsigned int boot_cpu = 0; 32 unsigned int boot_cpu = 0;
36 void __iomem *base = omap_get_wakeupgen_base(); 33 void __iomem *base = omap_get_wakeupgen_base();
37 34
38 flush_cache_all();
39 dsb();
40
41 /* 35 /*
42 * we're ready for shutdown now, so do it 36 * we're ready for shutdown now, so do it
43 */ 37 */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index e7a449758ab5..f76f94fb8473 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irqchip/arm-gic.h> 22#include <linux/irqchip/arm-gic.h>
23 23
24#include <asm/cacheflush.h>
25#include <asm/smp_scu.h> 24#include <asm/smp_scu.h>
26 25
27#include "omap-secure.h" 26#include "omap-secure.h"
@@ -96,9 +95,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
96 else 95 else
97 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); 96 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
98 97
99 flush_cache_all();
100 smp_wmb();
101
102 if (!cpu1_clkdm) 98 if (!cpu1_clkdm)
103 cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); 99 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
104 100
@@ -161,38 +157,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
161 return 0; 157 return 0;
162} 158}
163 159
164static void __init wakeup_secondary(void)
165{
166 void *startup_addr = omap_secondary_startup;
167 void __iomem *base = omap_get_wakeupgen_base();
168
169 if (cpu_is_omap446x()) {
170 startup_addr = omap_secondary_startup_4460;
171 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
172 }
173
174 /*
175 * Write the address of secondary startup routine into the
176 * AuxCoreBoot1 where ROM code will jump and start executing
177 * on secondary core once out of WFE
178 * A barrier is added to ensure that write buffer is drained
179 */
180 if (omap_secure_apis_support())
181 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
182 else
183 __raw_writel(virt_to_phys(omap5_secondary_startup),
184 base + OMAP_AUX_CORE_BOOT_1);
185
186 smp_wmb();
187
188 /*
189 * Send a 'sev' to wake the secondary core from WFE.
190 * Drain the outstanding writes to memory
191 */
192 dsb_sev();
193 mb();
194}
195
196/* 160/*
197 * Initialise the CPU possible map early - this describes the CPUs 161 * Initialise the CPU possible map early - this describes the CPUs
198 * which may be present or become present in the system. 162 * which may be present or become present in the system.
@@ -228,6 +192,8 @@ static void __init omap4_smp_init_cpus(void)
228 192
229static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 193static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
230{ 194{
195 void *startup_addr = omap_secondary_startup;
196 void __iomem *base = omap_get_wakeupgen_base();
231 197
232 /* 198 /*
233 * Initialise the SCU and wake up the secondary core using 199 * Initialise the SCU and wake up the secondary core using
@@ -235,7 +201,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
235 */ 201 */
236 if (scu_base) 202 if (scu_base)
237 scu_enable(scu_base); 203 scu_enable(scu_base);
238 wakeup_secondary(); 204
205 if (cpu_is_omap446x()) {
206 startup_addr = omap_secondary_startup_4460;
207 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
208 }
209
210 /*
211 * Write the address of secondary startup routine into the
212 * AuxCoreBoot1 where ROM code will jump and start executing
213 * on secondary core once out of WFE
214 * A barrier is added to ensure that write buffer is drained
215 */
216 if (omap_secure_apis_support())
217 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
218 else
219 __raw_writel(virt_to_phys(omap5_secondary_startup),
220 base + OMAP_AUX_CORE_BOOT_1);
221
239} 222}
240 223
241struct smp_operations omap4_smp_ops __initdata = { 224struct smp_operations omap4_smp_ops __initdata = {
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb115a27f..20bf3c754bfd 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <linux/export.h> 23#include <linux/export.h>
24#include <linux/irqchip/arm-gic.h> 24#include <linux/irqchip/arm-gic.h>
25#include <linux/of_address.h>
25 26
26#include <asm/hardware/cache-l2x0.h> 27#include <asm/hardware/cache-l2x0.h>
27#include <asm/mach/map.h> 28#include <asm/mach/map.h>
@@ -258,6 +259,21 @@ omap_early_initcall(omap4_sar_ram_init);
258 259
259void __init omap_gic_of_init(void) 260void __init omap_gic_of_init(void)
260{ 261{
262 struct device_node *np;
263
264 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
265 if (!cpu_is_omap446x())
266 goto skip_errata_init;
267
268 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
269 gic_dist_base_addr = of_iomap(np, 0);
270 WARN_ON(!gic_dist_base_addr);
271
272 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
273 twd_base = of_iomap(np, 0);
274 WARN_ON(!twd_base);
275
276skip_errata_init:
261 omap_wakeupgen_init(); 277 omap_wakeupgen_init();
262 irqchip_init(); 278 irqchip_init();
263} 279}
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe803b04..6822d0a7324f 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -20,13 +20,13 @@
20#define SAR_BANK4_OFFSET 0x3000 20#define SAR_BANK4_OFFSET 0x3000
21 21
22/* Scratch pad memory offsets from SAR_BANK1 */ 22/* Scratch pad memory offsets from SAR_BANK1 */
23#define SCU_OFFSET0 0xd00 23#define SCU_OFFSET0 0xfe4
24#define SCU_OFFSET1 0xd04 24#define SCU_OFFSET1 0xfe8
25#define OMAP_TYPE_OFFSET 0xd10 25#define OMAP_TYPE_OFFSET 0xfec
26#define L2X0_SAVE_OFFSET0 0xd14 26#define L2X0_SAVE_OFFSET0 0xff0
27#define L2X0_SAVE_OFFSET1 0xd18 27#define L2X0_SAVE_OFFSET1 0xff4
28#define L2X0_AUXCTRL_OFFSET 0xd1c 28#define L2X0_AUXCTRL_OFFSET 0xff8
29#define L2X0_PREFETCH_CTRL_OFFSET 0xd20 29#define L2X0_PREFETCH_CTRL_OFFSET 0xffc
30 30
31/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ 31/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
32#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 32#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b59d93908341..ce956b0a7ba4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -200,22 +200,17 @@ static int omap2_can_sleep(void)
200 200
201static void omap2_pm_idle(void) 201static void omap2_pm_idle(void)
202{ 202{
203 local_fiq_disable();
204
205 if (!omap2_can_sleep()) { 203 if (!omap2_can_sleep()) {
206 if (omap_irq_pending()) 204 if (omap_irq_pending())
207 goto out; 205 return;
208 omap2_enter_mpu_retention(); 206 omap2_enter_mpu_retention();
209 goto out; 207 return;
210 } 208 }
211 209
212 if (omap_irq_pending()) 210 if (omap_irq_pending())
213 goto out; 211 return;
214 212
215 omap2_enter_full_retention(); 213 omap2_enter_full_retention();
216
217out:
218 local_fiq_enable();
219} 214}
220 215
221static void __init prcm_setup_regs(void) 216static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2d93d8b23835..c01859398b54 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -346,19 +346,14 @@ void omap_sram_idle(void)
346 346
347static void omap3_pm_idle(void) 347static void omap3_pm_idle(void)
348{ 348{
349 local_fiq_disable();
350
351 if (omap_irq_pending()) 349 if (omap_irq_pending())
352 goto out; 350 return;
353 351
354 trace_cpu_idle(1, smp_processor_id()); 352 trace_cpu_idle(1, smp_processor_id());
355 353
356 omap_sram_idle(); 354 omap_sram_idle();
357 355
358 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 356 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
359
360out:
361 local_fiq_enable();
362} 357}
363 358
364#ifdef CONFIG_SUSPEND 359#ifdef CONFIG_SUSPEND
@@ -757,14 +752,12 @@ int __init omap3_pm_init(void)
757 pr_err("Memory allocation failed when allocating for secure sram context\n"); 752 pr_err("Memory allocation failed when allocating for secure sram context\n");
758 753
759 local_irq_disable(); 754 local_irq_disable();
760 local_fiq_disable();
761 755
762 omap_dma_global_context_save(); 756 omap_dma_global_context_save();
763 omap3_save_secure_ram_context(); 757 omap3_save_secure_ram_context();
764 omap_dma_global_context_restore(); 758 omap_dma_global_context_restore();
765 759
766 local_irq_enable(); 760 local_irq_enable();
767 local_fiq_enable();
768 } 761 }
769 762
770 omap3_save_scratchpad_contents(); 763 omap3_save_scratchpad_contents();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea62e75ef21d..5ba6d888d6ff 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -131,11 +131,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
131 */ 131 */
132static void omap_default_idle(void) 132static void omap_default_idle(void)
133{ 133{
134 local_fiq_disable();
135
136 omap_do_wfi(); 134 omap_do_wfi();
137
138 local_fiq_enable();
139} 135}
140 136
141/** 137/**
@@ -147,8 +143,8 @@ static void omap_default_idle(void)
147int __init omap4_pm_init(void) 143int __init omap4_pm_init(void)
148{ 144{
149 int ret; 145 int ret;
150 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup; 146 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
151 struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; 147 struct clockdomain *ducati_clkdm, *l3_2_clkdm;
152 148
153 if (omap_rev() == OMAP4430_REV_ES1_0) { 149 if (omap_rev() == OMAP4430_REV_ES1_0) {
154 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 150 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -175,27 +171,19 @@ int __init omap4_pm_init(void)
175 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as 171 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
176 * expected. The hardware recommendation is to enable static 172 * expected. The hardware recommendation is to enable static
177 * dependencies for these to avoid system lock ups or random crashes. 173 * dependencies for these to avoid system lock ups or random crashes.
178 * The L4 wakeup depedency is added to workaround the OCP sync hardware
179 * BUG with 32K synctimer which lead to incorrect timer value read
180 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
181 * are part of L4 wakeup clockdomain.
182 */ 174 */
183 mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); 175 mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
184 emif_clkdm = clkdm_lookup("l3_emif_clkdm"); 176 emif_clkdm = clkdm_lookup("l3_emif_clkdm");
185 l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); 177 l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
186 l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); 178 l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
187 l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
188 l4wkup = clkdm_lookup("l4_wkup_clkdm");
189 ducati_clkdm = clkdm_lookup("ducati_clkdm"); 179 ducati_clkdm = clkdm_lookup("ducati_clkdm");
190 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) || 180 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
191 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) 181 (!l3_2_clkdm) || (!ducati_clkdm))
192 goto err2; 182 goto err2;
193 183
194 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); 184 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
195 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); 185 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
196 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); 186 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
197 ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
198 ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
199 ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); 187 ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
200 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); 188 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
201 if (ret) { 189 if (ret) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 00:21:57 -0400