Merge branch 'for_3.10/omap_generic_cleanup_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux into omap-for-v3.10/cleanup-v2

9 files changed, 51 insertions, 92 deletions

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 80392fca86c6..06f567faf993 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -107,8 +107,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 {
         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 
-        local_fiq_disable();
-
         if (omap_irq_pending() || need_resched())
                 goto return_sleep_time;
 
@@ -143,7 +141,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
                 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
 
 return_sleep_time:
-        local_fiq_enable();
 
         return index;
 }
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index d639aef0deda..944e64aad7e5 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -70,10 +70,7 @@ static int omap4_enter_idle_simple(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
-        local_fiq_disable();
         omap_do_wfi();
-        local_fiq_enable();
-
         return index;
 }
 
@@ -84,8 +81,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
         struct omap4_idle_statedata *cx = &omap4_idle_data[index];
         int cpu_id = smp_processor_id();
 
-        local_fiq_disable();
-
         /*
          * CPU0 has to wait and stay ON until CPU1 is OFF state.
          * This is necessary to honour hardware recommondation
@@ -158,8 +153,6 @@ fail:
         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
         cpu_done[dev->cpu] = false;
 
-        local_fiq_enable();
-
         return index;
 }
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index e712d1725a8b..458f72f9dc8f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,11 +19,8 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include "omap-wakeupgen.h"
-
 #include "common.h"
-
 #include "powerdomain.h"
 
 /*
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
         unsigned int boot_cpu = 0;
         void __iomem *base = omap_get_wakeupgen_base();
 
-        flush_cache_all();
-        dsb();
-
         /*
          * we're ready for shutdown now, so do it
          */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a..0cbb677c4df4 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 
 #include "omap-secure.h"
@@ -103,9 +102,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         else
                 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
-        flush_cache_all();
-        smp_wmb();
-
         if (!cpu1_clkdm)
                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 
@@ -168,38 +164,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         return 0;
 }
 
-static void __init wakeup_secondary(void)
-{
-        void *startup_addr = omap_secondary_startup;
-        void __iomem *base = omap_get_wakeupgen_base();
-
-        if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
-                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
-        }
-
-        /*
-         * Write the address of secondary startup routine into the
-         * AuxCoreBoot1 where ROM code will jump and start executing
-         * on secondary core once out of WFE
-         * A barrier is added to ensure that write buffer is drained
-         */
-        if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
-        else
-                __raw_writel(virt_to_phys(omap5_secondary_startup),
-                                                base + OMAP_AUX_CORE_BOOT_1);
-
-        smp_wmb();
-
-        /*
-         * Send a 'sev' to wake the secondary core from WFE.
-         * Drain the outstanding writes to memory
-         */
-        dsb_sev();
-        mb();
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
@@ -235,6 +199,8 @@ static void __init omap4_smp_init_cpus(void)
 
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void *startup_addr = omap_secondary_startup;
+        void __iomem *base = omap_get_wakeupgen_base();
 
         /*
          * Initialise the SCU and wake up the secondary core using
@@ -242,7 +208,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
          */
         if (scu_base)
                 scu_enable(scu_base);
-        wakeup_secondary();
+
+        if (cpu_is_omap446x()) {
+                startup_addr = omap_secondary_startup_4460;
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+        }
+
+        /*
+         * Write the address of secondary startup routine into the
+         * AuxCoreBoot1 where ROM code will jump and start executing
+         * on secondary core once out of WFE
+         * A barrier is added to ensure that write buffer is drained
+         */
+        if (omap_secure_apis_support())
+                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
+        else
+                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                                base + OMAP_AUX_CORE_BOOT_1);
+
 }
 
 struct smp_operations omap4_smp_ops __initdata = {
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb115a27f..20bf3c754bfd 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/of_address.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -258,6 +259,21 @@ omap_early_initcall(omap4_sar_ram_init);
 
 void __init omap_gic_of_init(void)
 {
+        struct device_node *np;
+
+        /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
+        if (!cpu_is_omap446x())
+                goto skip_errata_init;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+        gic_dist_base_addr = of_iomap(np, 0);
+        WARN_ON(!gic_dist_base_addr);
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
+        twd_base = of_iomap(np, 0);
+        WARN_ON(!twd_base);
+
+skip_errata_init:
         omap_wakeupgen_init();
         irqchip_init();
 }
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe803b04..6822d0a7324f 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -20,13 +20,13 @@
 #define SAR_BANK4_OFFSET                0x3000
 
 /* Scratch pad memory offsets from SAR_BANK1 */
-#define SCU_OFFSET0                             0xd00
-#define SCU_OFFSET1                             0xd04
-#define OMAP_TYPE_OFFSET                        0xd10
-#define L2X0_SAVE_OFFSET0                       0xd14
-#define L2X0_SAVE_OFFSET1                       0xd18
-#define L2X0_AUXCTRL_OFFSET                     0xd1c
-#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+#define SCU_OFFSET0                             0xfe4
+#define SCU_OFFSET1                             0xfe8
+#define OMAP_TYPE_OFFSET                        0xfec
+#define L2X0_SAVE_OFFSET0                       0xff0
+#define L2X0_SAVE_OFFSET1                       0xff4
+#define L2X0_AUXCTRL_OFFSET                     0xff8
+#define L2X0_PREFETCH_CTRL_OFFSET               0xffc
 
 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b59d93908341..ce956b0a7ba4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -200,22 +200,17 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (!omap2_can_sleep()) {
                 if (omap_irq_pending())
-                        goto out;
+                        return;
                 omap2_enter_mpu_retention();
-                goto out;
+                return;
         }
 
         if (omap_irq_pending())
-                goto out;
+                return;
 
         omap2_enter_full_retention();
-
-out:
-        local_fiq_enable();
 }
 
 static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2d93d8b23835..c01859398b54 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -346,19 +346,14 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (omap_irq_pending())
-                goto out;
+                return;
 
         trace_cpu_idle(1, smp_processor_id());
 
         omap_sram_idle();
 
         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
-
-out:
-        local_fiq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
@@ -757,14 +752,12 @@ int __init omap3_pm_init(void)
                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 
                 local_irq_disable();
-                local_fiq_disable();
 
                 omap_dma_global_context_save();
                 omap3_save_secure_ram_context();
                 omap_dma_global_context_restore();
 
                 local_irq_enable();
-                local_fiq_enable();
         }
 
         omap3_save_scratchpad_contents();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea62e75ef21d..5ba6d888d6ff 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -131,11 +131,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static void omap_default_idle(void)
 {
-        local_fiq_disable();
-
         omap_do_wfi();
-
-        local_fiq_enable();
 }
 
 /**
@@ -147,8 +143,8 @@ static void omap_default_idle(void)
 int __init omap4_pm_init(void)
 {
         int ret;
-        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
-        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm;
 
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -175,27 +171,19 @@ int __init omap4_pm_init(void)
          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
          * expected. The hardware recommendation is to enable static
          * dependencies for these to avoid system lock ups or random crashes.
-         * The L4 wakeup depedency is added to workaround the OCP sync hardware
-         * BUG with 32K synctimer which lead to incorrect timer value read
-         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
-         * are part of L4 wakeup clockdomain.
          */
         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
-        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
-        l4wkup = clkdm_lookup("l4_wkup_clkdm");
         ducati_clkdm = clkdm_lookup("ducati_clkdm");
-        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
-                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm))
                 goto err2;
 
         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {