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authorLiviu Dudau <Liviu.Dudau@arm.com>2014-11-27 09:36:45 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-28 16:38:14 -0500
commit6bc474de366155c19d69966b45a7c06b8e2a9837 (patch)
treedd7e8c6f0daba4b2a71d8cb81965f162f506ac8f
parent419043609689d0aba9f727a6faf1ff406e269ecf (diff)
arm64: ARM: Fix the Generic Timers interrupt active level description
The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional description" that generic timers provide an active-LOW interrupt output. Fix the device trees to correctly describe this. While doing this update the CPU mask to match the number of described CPUs as well. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dts8
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts8
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts8
3 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 4a060906809d..27f32962e55c 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -78,10 +78,10 @@
78 78
79 timer { 79 timer {
80 compatible = "arm,armv8-timer"; 80 compatible = "arm,armv8-timer";
81 interrupts = <1 13 0xff01>, 81 interrupts = <1 13 0xf08>,
82 <1 14 0xff01>, 82 <1 14 0xf08>,
83 <1 11 0xff01>, 83 <1 11 0xf08>,
84 <1 10 0xff01>; 84 <1 10 0xf08>;
85 clock-frequency = <100000000>; 85 clock-frequency = <100000000>;
86 }; 86 };
87 87
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index 097ecc4d0f5d..cb3073e4e7a8 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -98,10 +98,10 @@
98 98
99 timer { 99 timer {
100 compatible = "arm,armv8-timer"; 100 compatible = "arm,armv8-timer";
101 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>, 101 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>, 102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>, 103 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>; 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
105 }; 105 };
106 106
107 pmu { 107 pmu {
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 572005ea2217..efc59b3baf63 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -81,10 +81,10 @@
81 81
82 timer { 82 timer {
83 compatible = "arm,armv8-timer"; 83 compatible = "arm,armv8-timer";
84 interrupts = <1 13 0xff01>, 84 interrupts = <1 13 0xf08>,
85 <1 14 0xff01>, 85 <1 14 0xf08>,
86 <1 11 0xff01>, 86 <1 11 0xf08>,
87 <1 10 0xff01>; 87 <1 10 0xf08>;
88 clock-frequency = <100000000>; 88 clock-frequency = <100000000>;
89 }; 89 };
90 90