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authorSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>2014-11-25 23:51:09 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-28 10:09:05 -0500
commit419043609689d0aba9f727a6faf1ff406e269ecf (patch)
tree36e56fa463d1e9837783517be8fd509e9eee2da5
parent71f867ec130e3cc8e692366fdf8941ded27c727e (diff)
arm64: amd-seattle: Adding device tree for AMD Seattle platform
Initial revision of device tree for AMD Seattle Development platform. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com> Signed-off-by: Joel Schopp <Joel.Schopp@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm64/Kconfig5
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/amd/Makefile5
-rw-r--r--arch/arm64/boot/dts/amd/amd-overdrive.dts66
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi54
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi172
6 files changed, 303 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9532f8d5857e..ddc01961a0da 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -142,6 +142,11 @@ source "kernel/Kconfig.freezer"
142 142
143menu "Platform selection" 143menu "Platform selection"
144 144
145config ARCH_SEATTLE
146 bool "AMD Seattle SoC Family"
147 help
148 This enables support for AMD Seattle SOC Family
149
145config ARCH_THUNDER 150config ARCH_THUNDER
146 bool "Cavium Inc. Thunder SoC Family" 151 bool "Cavium Inc. Thunder SoC Family"
147 help 152 help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8ff3d58..3b8d427c3985 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
1dts-dirs += amd
1dts-dirs += apm 2dts-dirs += apm
2dts-dirs += arm 3dts-dirs += arm
3dts-dirs += cavium 4dts-dirs += cavium
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
new file mode 100644
index 000000000000..cfdf701e05df
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive.dts b/arch/arm64/boot/dts/amd/amd-overdrive.dts
new file mode 100644
index 000000000000..564a3f7df71d
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-overdrive.dts
@@ -0,0 +1,66 @@
1/*
2 * DTS file for AMD Seattle Overdrive Development Board
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7/dts-v1/;
8
9/include/ "amd-seattle-soc.dtsi"
10
11/ {
12 model = "AMD Seattle Development Board (Overdrive)";
13 compatible = "amd,seattle-overdrive", "amd,seattle";
14
15 chosen {
16 stdout-path = &serial0;
17 linux,pci-probe-only;
18 };
19};
20
21&ccp0 {
22 status = "ok";
23};
24
25&gpio0 {
26 status = "ok";
27};
28
29&gpio1 {
30 status = "ok";
31};
32
33&i2c0 {
34 status = "ok";
35};
36
37&pcie0 {
38 status = "ok";
39};
40
41&spi0 {
42 status = "ok";
43};
44
45&spi1 {
46 status = "ok";
47 sdcard0: sdcard@0 {
48 compatible = "mmc-spi-slot";
49 reg = <0>;
50 spi-max-frequency = <20000000>;
51 voltage-ranges = <3200 3400>;
52 gpios = <&gpio0 7 0>;
53 interrupt-parent = <&gpio0>;
54 interrupts = <7 3>;
55 pl022,hierarchy = <0>;
56 pl022,interface = <0>;
57 pl022,com-mode = <0x0>;
58 pl022,rx-level-trig = <0>;
59 pl022,tx-level-trig = <0>;
60 };
61};
62
63&v2m0 {
64 arm,msi-base-spi = <64>;
65 arm,msi-num-spis = <256>;
66};
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
new file mode 100644
index 000000000000..f623c46525a6
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
@@ -0,0 +1,54 @@
1/*
2 * DTS file for AMD Seattle Clocks
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7 adl3clk_100mhz: clk100mhz_0 {
8 compatible = "fixed-clock";
9 #clock-cells = <0>;
10 clock-frequency = <100000000>;
11 clock-output-names = "adl3clk_100mhz";
12 };
13
14 ccpclk_375mhz: clk375mhz {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <375000000>;
18 clock-output-names = "ccpclk_375mhz";
19 };
20
21 sataclk_333mhz: clk333mhz {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <333000000>;
25 clock-output-names = "sataclk_333mhz";
26 };
27
28 pcieclk_500mhz: clk500mhz_0 {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <500000000>;
32 clock-output-names = "pcieclk_500mhz";
33 };
34
35 dmaclk_500mhz: clk500mhz_1 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <500000000>;
39 clock-output-names = "dmaclk_500mhz";
40 };
41
42 miscclk_250mhz: clk250mhz_4 {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <250000000>;
46 clock-output-names = "miscclk_250mhz";
47 };
48
49 uartspiclk_100mhz: clk100mhz_1 {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <100000000>;
53 clock-output-names = "uartspiclk_100mhz";
54 };
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
new file mode 100644
index 000000000000..0c8e7ae96fed
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -0,0 +1,172 @@
1/*
2 * DTS file for AMD Seattle SoC
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7/ {
8 compatible = "amd,seattle";
9 interrupt-parent = <&gic0>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 gic0: interrupt-controller@e1101000 {
14 compatible = "arm,gic-400", "arm,cortex-a15-gic";
15 interrupt-controller;
16 #interrupt-cells = <3>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19 reg = <0x0 0xe1110000 0 0x1000>,
20 <0x0 0xe112f000 0 0x2000>,
21 <0x0 0xe1140000 0 0x10000>,
22 <0x0 0xe1160000 0 0x10000>;
23 interrupts = <1 9 0xf04>;
24 ranges = <0 0 0 0xe1100000 0 0x100000>;
25 v2m0: v2m@e0080000 {
26 compatible = "arm,gic-v2m-frame";
27 msi-controller;
28 reg = <0x0 0x00080000 0 0x1000>;
29 };
30 };
31
32 timer {
33 compatible = "arm,armv8-timer";
34 interrupts = <1 13 0xff04>,
35 <1 14 0xff04>,
36 <1 11 0xff04>,
37 <1 10 0xff04>;
38 };
39
40 pmu {
41 compatible = "arm,armv8-pmuv3";
42 interrupts = <0 7 4>,
43 <0 8 4>,
44 <0 9 4>,
45 <0 10 4>,
46 <0 11 4>,
47 <0 12 4>,
48 <0 13 4>,
49 <0 14 4>;
50 };
51
52 smb0: smb {
53 compatible = "simple-bus";
54 #address-cells = <2>;
55 #size-cells = <2>;
56 ranges;
57
58 /* DDR range is 40-bit addressing */
59 dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
60
61 /include/ "amd-seattle-clks.dtsi"
62
63 sata0: sata@e0300000 {
64 compatible = "snps,dwc-ahci";
65 reg = <0 0xe0300000 0 0x800>;
66 interrupts = <0 355 4>;
67 clocks = <&sataclk_333mhz>;
68 dma-coherent;
69 };
70
71 i2c0: i2c@e1000000 {
72 status = "disabled";
73 compatible = "snps,designware-i2c";
74 reg = <0 0xe1000000 0 0x1000>;
75 interrupts = <0 357 4>;
76 clocks = <&uartspiclk_100mhz>;
77 };
78
79 serial0: serial@e1010000 {
80 compatible = "arm,pl011", "arm,primecell";
81 reg = <0 0xe1010000 0 0x1000>;
82 interrupts = <0 328 4>;
83 clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
84 clock-names = "uartclk", "apb_pclk";
85 };
86
87 spi0: ssp@e1020000 {
88 status = "disabled";
89 compatible = "arm,pl022", "arm,primecell";
90 #gpio-cells = <2>;
91 reg = <0 0xe1020000 0 0x1000>;
92 spi-controller;
93 interrupts = <0 330 4>;
94 clocks = <&uartspiclk_100mhz>;
95 clock-names = "apb_pclk";
96 };
97
98 spi1: ssp@e1030000 {
99 status = "disabled";
100 compatible = "arm,pl022", "arm,primecell";
101 #gpio-cells = <2>;
102 reg = <0 0xe1030000 0 0x1000>;
103 spi-controller;
104 interrupts = <0 329 4>;
105 clocks = <&uartspiclk_100mhz>;
106 clock-names = "apb_pclk";
107 num-cs = <1>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 };
111
112 gpio0: gpio@e1040000 {
113 status = "disabled";
114 compatible = "arm,pl061", "arm,primecell";
115 #gpio-cells = <2>;
116 reg = <0 0xe1040000 0 0x1000>;
117 gpio-controller;
118 interrupts = <0 359 4>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 clocks = <&uartspiclk_100mhz>;
122 clock-names = "apb_pclk";
123 };
124
125 gpio1: gpio@e1050000 {
126 status = "disabled";
127 compatible = "arm,pl061", "arm,primecell";
128 #gpio-cells = <2>;
129 reg = <0 0xe1050000 0 0x1000>;
130 gpio-controller;
131 interrupts = <0 358 4>;
132 clocks = <&uartspiclk_100mhz>;
133 clock-names = "apb_pclk";
134 };
135
136 ccp0: ccp@e0100000 {
137 status = "disabled";
138 compatible = "amd,ccp-seattle-v1a";
139 reg = <0 0xe0100000 0 0x10000>;
140 interrupts = <0 3 4>;
141 dma-coherent;
142 };
143
144 pcie0: pcie@f0000000 {
145 compatible = "pci-host-ecam-generic";
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 device_type = "pci";
150 bus-range = <0 0xff>;
151 msi-parent = <&v2m0>;
152 reg = <0 0xf0000000 0 0x10000000>;
153
154 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
155 interrupt-map =
156 <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
157 <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
158 <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
159 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
160
161 dma-coherent;
162 dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
163 ranges =
164 /* I/O Memory (size=64K) */
165 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
166 /* 32-bit MMIO (size=2G) */
167 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
168 /* 64-bit MMIO (size= 124G) */
169 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
170 };
171 };
172};
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-07 21:43:54 -0400