m68knommu: clean up use of MBAR for DRAM registers on ColdFire start

In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
author: Greg Ungerer <gerg@uclinux.org> 2011-03-06 08:01:46 -0500
committer: Greg Ungerer <gerg@uclinux.org> 2011-03-15 07:01:55 -0400
commit: 6a92e1982d5c538d1cfafbe4b0cb16d49306854f (patch)
tree: 700847577d3cd3385125fe46822e8759a76607da
parent: 58f0ac98f386d2b335e5852e8feec828c43a0e13 (diff)
8 files changed, 49 insertions, 49 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7b58da5050a0..dfd6d3f73584 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -48,14 +48,14 @@
 #define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
 #define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
-#define MCFSIM_DCRR             0x46            /* DRAM Refresh reg (r/w) */
+#define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
-#define MCFSIM_DCTR             0x4a            /* DRAM Timing reg (r/w) */
+#define MCFSIM_DCTR             (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
-#define MCFSIM_DAR0             0x4c            /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DAR0             (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DMR0             0x50            /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCR0             0x57            /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DCR0             (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DAR1             0x58            /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DAR1             (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DMR1             0x5c            /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCR1             0x63            /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_DCR1             (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 #define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
 #define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 89067bd04150..3f3dbf01a109 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -40,11 +40,11 @@
 /*
 *      SDRAM configuration registers.
 */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x44)     /* Control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x48)     /* Base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x4c)     /* Address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x50)     /* Base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x54)     /* Address mask 1 */
 /*
 *  Reset Controll Unit (relative to IPSBAR).
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index c318ce786f93..33b0b4df07ca 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -60,11 +60,11 @@
 #define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
 #define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
 /*
 *      Timer module.
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 04b8c103095d..838fb2b1e88b 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -43,21 +43,21 @@
 *      SDRAM configuration registers.
 */
 #ifdef CONFIG_M5271
-#define MCFSIM_DCR              0x40            /* SDRAM control */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x40)     /* Control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x48)     /* Base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x4c)     /* Address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x50)     /* Base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x54)     /* Address mask 1 */
 #endif
 #ifdef CONFIG_M5275
-#define MCFSIM_DMR              0x40            /* SDRAM mode */
+#define MCFSIM_DMR              (MCF_IPSBAR + 0x40)     /* Mode */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x44)     /* Control */
-#define MCFSIM_DCFG1            0x48            /* SDRAM configuration 1 */
+#define MCFSIM_DCFG1            (MCF_IPSBAR + 0x48)     /* Configuration 1 */
-#define MCFSIM_DCFG2            0x4c            /* SDRAM configuration 2 */
+#define MCFSIM_DCFG2            (MCF_IPSBAR + 0x4c)     /* Configuration 2 */
-#define MCFSIM_DBAR0            0x50            /* SDRAM base address 0 */
+#define MCFSIM_DBAR0            (MCF_IPSBAR + 0x50)     /* Base address 0 */
-#define MCFSIM_DMR0             0x54            /* SDRAM address mask 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x54)     /* Address mask 0 */
-#define MCFSIM_DBAR1            0x58            /* SDRAM base address 1 */
+#define MCFSIM_DBAR1            (MCF_IPSBAR + 0x58)     /* Base address 1 */
-#define MCFSIM_DMR1             0x5c            /* SDRAM address mask 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x5c)     /* Address mask 1 */
 #endif
 /*
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 87c0cce59057..47324f2258a7 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -40,11 +40,11 @@
 /*
 *      SDRAM configuration registers.
 */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x00000044) /* Control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x00000048) /* Base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x00000050) /* Base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
 /*
 *      DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index c3846fcfa5d1..e4365f2e5c29 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -89,11 +89,11 @@
 #define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
 #endif /* CONFIG_OLDMASK */
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM Addr/Ctrl 0 */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM Mask 0 */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM Addr/Ctrl 1 */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM Mask 1 */
 /*
 *  Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 43272584dc09..c1eba01d26b0 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -72,11 +72,11 @@
 #define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
 #define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
 /*
 *      Timer module.
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index 7967e8ab9fae..129bff4956b5 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -41,17 +41,17 @@
 *      DRAM controller is quite different.
 */
 .macro GET_MEM_SIZE
-        movel   MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
+        movel   MCFSIM_DMR0,%d0         /* get mask for 1st bank */
        btst    #0,%d0                  /* check if region enabled */
        beq     1f
        andl    #0xfffc0000,%d0
        beq     1f
        addl    #0x00040000,%d0         /* convert mask to size */
 1:
-        movel   MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
+        movel   MCFSIM_DMR1,%d1         /* get mask for 2nd bank */
        btst    #0,%d1                  /* check if region enabled */
        beq     2f
-        andl    #0xfffc0000, %d1
+        andl    #0xfffc0000,%d1
        beq     2f
        addl    #0x00040000,%d1
        addl    %d1,%d0                 /* total mem size in d0 */
author	Greg Ungerer <gerg@uclinux.org>	2011-03-06 08:01:46 -0500
committer	Greg Ungerer <gerg@uclinux.org>	2011-03-15 07:01:55 -0400
commit	6a92e1982d5c538d1cfafbe4b0cb16d49306854f (patch)
tree	700847577d3cd3385125fe46822e8759a76607da
parent	58f0ac98f386d2b335e5852e8feec828c43a0e13 (diff)

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 7b58da5050a0..dfd6d3f73584 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h
@@ -48,14 +48,14 @@
48	#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */	48	#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
49	#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */	49	#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
50		50
51	#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */	51	#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
52	#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */	52	#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
53	#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */	53	#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
54	#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */	54	#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
55	#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */	55	#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
56	#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */	56	#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
57	#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */	57	#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
58	#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */	58	#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
59		59
60	#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */	60	#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
61	#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */	61	#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */


diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 89067bd04150..3f3dbf01a109 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h
@@ -40,11 +40,11 @@
40	/*	40	/*
41	* SDRAM configuration registers.	41	* SDRAM configuration registers.
42	*/	42	*/
43	#define MCFSIM_DCR 0x44 /* SDRAM control */	43	#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
44	#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */	44	#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
45	#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */	45	#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
46	#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */	46	#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
47	#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */	47	#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
48		48
49	/*	49	/*
50	* Reset Controll Unit (relative to IPSBAR).	50	* Reset Controll Unit (relative to IPSBAR).


diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index c318ce786f93..33b0b4df07ca 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h
@@ -60,11 +60,11 @@
60	#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */	60	#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
61	#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */	61	#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
62		62
63	#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */	63	#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
64	#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */	64	#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
65	#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */	65	#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
66	#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */	66	#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
67	#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */	67	#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
68		68
69	/*	69	/*
70	* Timer module.	70	* Timer module.


diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 04b8c103095d..838fb2b1e88b 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h
@@ -43,21 +43,21 @@
43	* SDRAM configuration registers.	43	* SDRAM configuration registers.
44	*/	44	*/
45	#ifdef CONFIG_M5271	45	#ifdef CONFIG_M5271
46	#define MCFSIM_DCR 0x40 /* SDRAM control */	46	#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
47	#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */	47	#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
48	#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */	48	#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
49	#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */	49	#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
50	#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */	50	#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
51	#endif	51	#endif
52	#ifdef CONFIG_M5275	52	#ifdef CONFIG_M5275
53	#define MCFSIM_DMR 0x40 /* SDRAM mode */	53	#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
54	#define MCFSIM_DCR 0x44 /* SDRAM control */	54	#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
55	#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */	55	#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
56	#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */	56	#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
57	#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */	57	#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
58	#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */	58	#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
59	#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */	59	#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
60	#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */	60	#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
61	#endif	61	#endif
62		62
63	/*	63	/*


diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 87c0cce59057..47324f2258a7 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h
@@ -40,11 +40,11 @@
40	/*	40	/*
41	* SDRAM configuration registers.	41	* SDRAM configuration registers.
42	*/	42	*/
43	#define MCFSIM_DCR 0x44 /* SDRAM control */	43	#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
44	#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */	44	#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
45	#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */	45	#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
46	#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */	46	#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
47	#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */	47	#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
48		48
49	/*	49	/*
50	* DMA unit base addresses.	50	* DMA unit base addresses.


diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index c3846fcfa5d1..e4365f2e5c29 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h
@@ -89,11 +89,11 @@
89	#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */	89	#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
90	#endif /* CONFIG_OLDMASK */	90	#endif /* CONFIG_OLDMASK */
91		91
92	#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */	92	#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
93	#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */	93	#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
94	#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */	94	#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
95	#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */	95	#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
96	#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */	96	#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
97		97
98	/*	98	/*
99	* Timer module.	99	* Timer module.


diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 43272584dc09..c1eba01d26b0 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h
@@ -72,11 +72,11 @@
72	#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */	72	#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
73	#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */	73	#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
74		74
75	#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */	75	#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
76	#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */	76	#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
77	#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */	77	#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
78	#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */	78	#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
79	#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */	79	#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
80		80
81	/*	81	/*
82	* Timer module.	82	* Timer module.


diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 7967e8ab9fae..129bff4956b5 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S
@@ -41,17 +41,17 @@
41	* DRAM controller is quite different.	41	* DRAM controller is quite different.
42	*/	42	*/
43	.macro GET_MEM_SIZE	43	.macro GET_MEM_SIZE
44	movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */	44	movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
45	btst #0,%d0 /* check if region enabled */	45	btst #0,%d0 /* check if region enabled */
46	beq 1f	46	beq 1f
47	andl #0xfffc0000,%d0	47	andl #0xfffc0000,%d0
48	beq 1f	48	beq 1f
49	addl #0x00040000,%d0 /* convert mask to size */	49	addl #0x00040000,%d0 /* convert mask to size */
50	1:	50	1:
51	movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */	51	movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
52	btst #0,%d1 /* check if region enabled */	52	btst #0,%d1 /* check if region enabled */
53	beq 2f	53	beq 2f
54	andl #0xfffc0000, %d1	54	andl #0xfffc0000,%d1
55	beq 2f	55	beq 2f
56	addl #0x00040000,%d1	56	addl #0x00040000,%d1
57	addl %d1,%d0 /* total mem size in d0 */	57	addl %d1,%d0 /* total mem size in d0 */