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authorRyan Mallon <ryan@bluewatersys.com>2011-05-20 03:34:21 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-20 17:34:24 -0400
commit61e72bca04be2dc11a637185f2bbe6dba32ecaf3 (patch)
tree997d0912e7f1483bdc913fae32e2c3b61481238e
parentf6558bf92aed978a81514131e408326f25046137 (diff)
ARM: 6935/1: SPEAR3xx: Rename register/irq defines to remove naming conflicts
Prefix register and irq defintions to remove naming conflicts between the three SPEAr3xx platforms. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h4
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h206
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h26
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h44
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h48
-rw-r--r--arch/arm/mach-spear3xx/spear300.c66
-rw-r--r--arch/arm/mach-spear3xx/spear310.c92
-rw-r--r--arch/arm/mach-spear3xx/spear320.c134
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c6
9 files changed, 314 insertions, 312 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 115d3cbf7420..af4cb5b8aa40 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,8 +27,8 @@
27 * Following GPT channels will be used as clock source and clockevent 27 * Following GPT channels will be used as clock source and clockevent
28 */ 28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE 29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device gpio_device; 34extern struct amba_device gpio_device;
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index a1a7f481866d..6e265442808e 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,140 @@
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* SPEAr3xx IRQ definitions */
18#define IRQ_HW_ACCEL_MOD_0 0 18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define IRQ_INTRCOMM_RAS_ARM 1 19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define IRQ_CPU_GPT1_1 2 20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define IRQ_CPU_GPT1_2 3 21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define IRQ_BASIC_GPT1_1 4 22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define IRQ_BASIC_GPT1_2 5 23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define IRQ_BASIC_GPT2_1 6 24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define IRQ_BASIC_GPT2_2 7 25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define IRQ_BASIC_DMA 8 26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define IRQ_BASIC_SMI 9 27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define IRQ_BASIC_RTC 10 28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define IRQ_BASIC_GPIO 11 29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define IRQ_BASIC_WDT 12 30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define IRQ_DDR_CONTROLLER 13 31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define IRQ_SYS_ERROR 14 32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define IRQ_WAKEUP_RCV 15 33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define IRQ_JPEG 16 34#define SPEAR3XX_IRQ_JPEG 16
35#define IRQ_IRDA 17 35#define SPEAR3XX_IRQ_IRDA 17
36#define IRQ_ADC 18 36#define SPEAR3XX_IRQ_ADC 18
37#define IRQ_UART 19 37#define SPEAR3XX_IRQ_UART 19
38#define IRQ_SSP 20 38#define SPEAR3XX_IRQ_SSP 20
39#define IRQ_I2C 21 39#define SPEAR3XX_IRQ_I2C 21
40#define IRQ_MAC_1 22 40#define SPEAR3XX_IRQ_MAC_1 22
41#define IRQ_MAC_2 23 41#define SPEAR3XX_IRQ_MAC_2 23
42#define IRQ_USB_DEV 24 42#define SPEAR3XX_IRQ_USB_DEV 24
43#define IRQ_USB_H_OHCI_0 25 43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define IRQ_USB_H_EHCI_0 26 44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define IRQ_USB_H_OHCI_1 27 46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define IRQ_GEN_RAS_1 28 47#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define IRQ_GEN_RAS_2 29 48#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define IRQ_GEN_RAS_3 30 49#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define IRQ_HW_ACCEL_MOD_1 31 50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define IRQ_VIC_END 32 51#define SPEAR3XX_IRQ_VIC_END 32
52 52
53#define VIRQ_START IRQ_VIC_END 53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 54
55/* SPEAr300 Virtual irq definitions */ 55/* SPEAr300 Virtual irq definitions */
56#ifdef CONFIG_MACH_SPEAR300
57/* IRQs sharing IRQ_GEN_RAS_1 */ 56/* IRQs sharing IRQ_GEN_RAS_1 */
58#define VIRQ_IT_PERS_S (VIRQ_START + 0) 57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
59#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) 58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
60#define VIRQ_I2S (VIRQ_START + 2) 59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
61#define VIRQ_TDM (VIRQ_START + 3) 60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
62#define VIRQ_CAMERA_L (VIRQ_START + 4) 61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
63#define VIRQ_CAMERA_F (VIRQ_START + 5) 62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
64#define VIRQ_CAMERA_V (VIRQ_START + 6) 63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
65#define VIRQ_KEYBOARD (VIRQ_START + 7) 64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
66#define VIRQ_GPIO1 (VIRQ_START + 8) 65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
67 66
68/* IRQs sharing IRQ_GEN_RAS_3 */ 67/* IRQs sharing IRQ_GEN_RAS_3 */
69#define IRQ_CLCD IRQ_GEN_RAS_3 68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
70 69
71/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
72#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM 71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
73
74/* GPIO pins virtual irqs */
75#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
76#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
77#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
78 72
79/* SPEAr310 Virtual irq definitions */ 73/* SPEAr310 Virtual irq definitions */
80#elif defined(CONFIG_MACH_SPEAR310)
81/* IRQs sharing IRQ_GEN_RAS_1 */ 74/* IRQs sharing IRQ_GEN_RAS_1 */
82#define VIRQ_SMII0 (VIRQ_START + 0) 75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
83#define VIRQ_SMII1 (VIRQ_START + 1) 76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
84#define VIRQ_SMII2 (VIRQ_START + 2) 77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
85#define VIRQ_SMII3 (VIRQ_START + 3) 78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
86#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) 79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
87#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) 80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
88#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) 81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
89#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) 82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
90 83
91/* IRQs sharing IRQ_GEN_RAS_2 */ 84/* IRQs sharing IRQ_GEN_RAS_2 */
92#define VIRQ_UART1 (VIRQ_START + 8) 85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
93#define VIRQ_UART2 (VIRQ_START + 9) 86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
94#define VIRQ_UART3 (VIRQ_START + 10) 87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
95#define VIRQ_UART4 (VIRQ_START + 11) 88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
96#define VIRQ_UART5 (VIRQ_START + 12) 89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
97 90
98/* IRQs sharing IRQ_GEN_RAS_3 */ 91/* IRQs sharing IRQ_GEN_RAS_3 */
99#define VIRQ_EMI (VIRQ_START + 13) 92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
100#define VIRQ_PLGPIO (VIRQ_START + 14) 93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
101 94
102/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
103#define VIRQ_TDM_HDLC (VIRQ_START + 15) 96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
104#define VIRQ_RS485_0 (VIRQ_START + 16) 97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
105#define VIRQ_RS485_1 (VIRQ_START + 17) 98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
106
107/* GPIO pins virtual irqs */
108#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
109 99
110/* SPEAr320 Virtual irq definitions */ 100/* SPEAr320 Virtual irq definitions */
111#else
112/* IRQs sharing IRQ_GEN_RAS_1 */ 101/* IRQs sharing IRQ_GEN_RAS_1 */
113#define VIRQ_EMI (VIRQ_START + 0) 102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
114#define VIRQ_CLCD (VIRQ_START + 1) 103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
115#define VIRQ_SPP (VIRQ_START + 2) 104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
116 105
117/* IRQs sharing IRQ_GEN_RAS_2 */ 106/* IRQs sharing IRQ_GEN_RAS_2 */
118#define IRQ_SDHCI IRQ_GEN_RAS_2 107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
119 108
120/* IRQs sharing IRQ_GEN_RAS_3 */ 109/* IRQs sharing IRQ_GEN_RAS_3 */
121#define VIRQ_PLGPIO (VIRQ_START + 3) 110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
122#define VIRQ_I2S_PLAY (VIRQ_START + 4) 111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
123#define VIRQ_I2S_REC (VIRQ_START + 5) 112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
124 113
125/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
126#define VIRQ_CANU (VIRQ_START + 6) 115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
127#define VIRQ_CANL (VIRQ_START + 7) 116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
128#define VIRQ_UART1 (VIRQ_START + 8) 117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
129#define VIRQ_UART2 (VIRQ_START + 9) 118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
130#define VIRQ_SSP1 (VIRQ_START + 10) 119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
131#define VIRQ_SSP2 (VIRQ_START + 11) 120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
132#define VIRQ_SMII0 (VIRQ_START + 12) 121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
133#define VIRQ_MII1_SMII1 (VIRQ_START + 13) 122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
134#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) 123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
135#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) 124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
136#define VIRQ_I2C (VIRQ_START + 16) 125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
137
138/* GPIO pins virtual irqs */
139#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
140 126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
141#endif 138#endif
142 139
143/* PLGPIO Virtual IRQs */ 140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
144#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
145#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) 144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
146#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) 145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
147#endif 149#endif
148 150
149#define VIRQ_END SPEAR_GPIO_INT_END 151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
150#define NR_IRQS VIRQ_END 152#define NR_IRQS SPEAR3XX_VIRQ_END
151 153
152#endif /* __MACH_IRQS_H */ 154#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index c723515f8853..3b6ea0729040 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
20#define SPEAR300_TELECOM_BASE UL(0x50000000) 20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21 21
22/* Interrupt registers offsets and masks */ 22/* Interrupt registers offsets and masks */
23#define INT_ENB_MASK_REG 0x54 23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define INT_STS_MASK_REG 0x58 24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define IT_PERS_S_IRQ_MASK (1 << 0) 25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define IT_CHANGE_S_IRQ_MASK (1 << 1) 26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define I2S_IRQ_MASK (1 << 2) 27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define TDM_IRQ_MASK (1 << 3) 28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define CAMERA_L_IRQ_MASK (1 << 4) 29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define CAMERA_F_IRQ_MASK (1 << 5) 30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define CAMERA_V_IRQ_MASK (1 << 6) 31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define KEYBOARD_IRQ_MASK (1 << 7) 32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define GPIO1_IRQ_MASK (1 << 8) 33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34 34
35#define SHIRQ_RAS1_MASK 0x1FF 35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36 36
37#define SPEAR300_CLCD_BASE UL(0x60000000) 37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000) 38#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e853479b8cd..1567d0da725f 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -29,29 +29,29 @@
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) 29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30 30
31/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
32#define INT_STS_MASK_REG 0x04 32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SMII0_IRQ_MASK (1 << 0) 33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SMII1_IRQ_MASK (1 << 1) 34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SMII2_IRQ_MASK (1 << 2) 35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SMII3_IRQ_MASK (1 << 3) 36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define WAKEUP_SMII0_IRQ_MASK (1 << 4) 37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define WAKEUP_SMII1_IRQ_MASK (1 << 5) 38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define WAKEUP_SMII2_IRQ_MASK (1 << 6) 39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define WAKEUP_SMII3_IRQ_MASK (1 << 7) 40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define UART1_IRQ_MASK (1 << 8) 41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define UART2_IRQ_MASK (1 << 9) 42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define UART3_IRQ_MASK (1 << 10) 43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define UART4_IRQ_MASK (1 << 11) 44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define UART5_IRQ_MASK (1 << 12) 45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define EMI_IRQ_MASK (1 << 13) 46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define TDM_HDLC_IRQ_MASK (1 << 14) 47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define RS485_0_IRQ_MASK (1 << 15) 48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define RS485_1_IRQ_MASK (1 << 16) 49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50 50
51#define SHIRQ_RAS1_MASK 0x000FF 51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SHIRQ_RAS2_MASK 0x01F00 52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SHIRQ_RAS3_MASK 0x02000 53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55 55
56#endif /* __MACH_SPEAR310_H */ 56#endif /* __MACH_SPEAR310_H */
57 57
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d85d959..8cfa83fa1296 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) 36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37 37
38/* Interrupt registers offsets and masks */ 38/* Interrupt registers offsets and masks */
39#define INT_STS_MASK_REG 0x04 39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define INT_CLR_MASK_REG 0x04 40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define INT_ENB_MASK_REG 0x08 41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define GPIO_IRQ_MASK (1 << 0) 42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define I2S_PLAY_IRQ_MASK (1 << 1) 43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define I2S_REC_IRQ_MASK (1 << 2) 44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define EMI_IRQ_MASK (1 << 7) 45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define CLCD_IRQ_MASK (1 << 8) 46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPP_IRQ_MASK (1 << 9) 47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SDHCI_IRQ_MASK (1 << 10) 48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define CAN_U_IRQ_MASK (1 << 11) 49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define CAN_L_IRQ_MASK (1 << 12) 50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define UART1_IRQ_MASK (1 << 13) 51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define UART2_IRQ_MASK (1 << 14) 52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SSP1_IRQ_MASK (1 << 15) 53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SSP2_IRQ_MASK (1 << 16) 54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SMII0_IRQ_MASK (1 << 17) 55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define MII1_SMII1_IRQ_MASK (1 << 18) 56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define WAKEUP_SMII0_IRQ_MASK (1 << 19) 57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) 58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define I2C1_IRQ_MASK (1 << 21) 59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60 60
61#define SHIRQ_RAS1_MASK 0x000380 61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SHIRQ_RAS3_MASK 0x000007 62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64 64
65#endif /* __MACH_SPEAR320_H */ 65#endif /* __MACH_SPEAR320_H */
66 66
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 3d749da0b826..81a57ce67176 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -373,52 +373,52 @@ struct pmx_driver pmx_driver = {
373/* spear3xx shared irq */ 373/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 374static struct shirq_dev_config shirq_ras1_config[] = {
375 { 375 {
376 .virq = VIRQ_IT_PERS_S, 376 .virq = SPEAR300_VIRQ_IT_PERS_S,
377 .enb_mask = IT_PERS_S_IRQ_MASK, 377 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
378 .status_mask = IT_PERS_S_IRQ_MASK, 378 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
379 }, { 379 }, {
380 .virq = VIRQ_IT_CHANGE_S, 380 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
381 .enb_mask = IT_CHANGE_S_IRQ_MASK, 381 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
382 .status_mask = IT_CHANGE_S_IRQ_MASK, 382 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
383 }, { 383 }, {
384 .virq = VIRQ_I2S, 384 .virq = SPEAR300_VIRQ_I2S,
385 .enb_mask = I2S_IRQ_MASK, 385 .enb_mask = SPEAR300_I2S_IRQ_MASK,
386 .status_mask = I2S_IRQ_MASK, 386 .status_mask = SPEAR300_I2S_IRQ_MASK,
387 }, { 387 }, {
388 .virq = VIRQ_TDM, 388 .virq = SPEAR300_VIRQ_TDM,
389 .enb_mask = TDM_IRQ_MASK, 389 .enb_mask = SPEAR300_TDM_IRQ_MASK,
390 .status_mask = TDM_IRQ_MASK, 390 .status_mask = SPEAR300_TDM_IRQ_MASK,
391 }, { 391 }, {
392 .virq = VIRQ_CAMERA_L, 392 .virq = SPEAR300_VIRQ_CAMERA_L,
393 .enb_mask = CAMERA_L_IRQ_MASK, 393 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
394 .status_mask = CAMERA_L_IRQ_MASK, 394 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
395 }, { 395 }, {
396 .virq = VIRQ_CAMERA_F, 396 .virq = SPEAR300_VIRQ_CAMERA_F,
397 .enb_mask = CAMERA_F_IRQ_MASK, 397 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
398 .status_mask = CAMERA_F_IRQ_MASK, 398 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
399 }, { 399 }, {
400 .virq = VIRQ_CAMERA_V, 400 .virq = SPEAR300_VIRQ_CAMERA_V,
401 .enb_mask = CAMERA_V_IRQ_MASK, 401 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
402 .status_mask = CAMERA_V_IRQ_MASK, 402 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
403 }, { 403 }, {
404 .virq = VIRQ_KEYBOARD, 404 .virq = SPEAR300_VIRQ_KEYBOARD,
405 .enb_mask = KEYBOARD_IRQ_MASK, 405 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
406 .status_mask = KEYBOARD_IRQ_MASK, 406 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
407 }, { 407 }, {
408 .virq = VIRQ_GPIO1, 408 .virq = SPEAR300_VIRQ_GPIO1,
409 .enb_mask = GPIO1_IRQ_MASK, 409 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
410 .status_mask = GPIO1_IRQ_MASK, 410 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
411 }, 411 },
412}; 412};
413 413
414static struct spear_shirq shirq_ras1 = { 414static struct spear_shirq shirq_ras1 = {
415 .irq = IRQ_GEN_RAS_1, 415 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
416 .dev_config = shirq_ras1_config, 416 .dev_config = shirq_ras1_config,
417 .dev_count = ARRAY_SIZE(shirq_ras1_config), 417 .dev_count = ARRAY_SIZE(shirq_ras1_config),
418 .regs = { 418 .regs = {
419 .enb_reg = INT_ENB_MASK_REG, 419 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
420 .status_reg = INT_STS_MASK_REG, 420 .status_reg = SPEAR300_INT_STS_MASK_REG,
421 .status_reg_mask = SHIRQ_RAS1_MASK, 421 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
422 .clear_reg = -1, 422 .clear_reg = -1,
423 }, 423 },
424}; 424};
@@ -427,7 +427,7 @@ static struct spear_shirq shirq_ras1 = {
427/* arm gpio1 device registration */ 427/* arm gpio1 device registration */
428static struct pl061_platform_data gpio1_plat_data = { 428static struct pl061_platform_data gpio1_plat_data = {
429 .gpio_base = 8, 429 .gpio_base = 8,
430 .irq_base = SPEAR_GPIO1_INT_BASE, 430 .irq_base = SPEAR300_GPIO1_INT_BASE,
431}; 431};
432 432
433struct amba_device gpio1_device = { 433struct amba_device gpio1_device = {
@@ -440,7 +440,7 @@ struct amba_device gpio1_device = {
440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1, 440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
442 }, 442 },
443 .irq = {VIRQ_GPIO1, NO_IRQ}, 443 .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
444}; 444};
445 445
446/* spear300 routines */ 446/* spear300 routines */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index e4fce3f1042c..826c166a76a5 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -142,115 +142,115 @@ struct pmx_driver pmx_driver = {
142/* spear3xx shared irq */ 142/* spear3xx shared irq */
143static struct shirq_dev_config shirq_ras1_config[] = { 143static struct shirq_dev_config shirq_ras1_config[] = {
144 { 144 {
145 .virq = VIRQ_SMII0, 145 .virq = SPEAR310_VIRQ_SMII0,
146 .status_mask = SMII0_IRQ_MASK, 146 .status_mask = SPEAR310_SMII0_IRQ_MASK,
147 }, { 147 }, {
148 .virq = VIRQ_SMII1, 148 .virq = SPEAR310_VIRQ_SMII1,
149 .status_mask = SMII1_IRQ_MASK, 149 .status_mask = SPEAR310_SMII1_IRQ_MASK,
150 }, { 150 }, {
151 .virq = VIRQ_SMII2, 151 .virq = SPEAR310_VIRQ_SMII2,
152 .status_mask = SMII2_IRQ_MASK, 152 .status_mask = SPEAR310_SMII2_IRQ_MASK,
153 }, { 153 }, {
154 .virq = VIRQ_SMII3, 154 .virq = SPEAR310_VIRQ_SMII3,
155 .status_mask = SMII3_IRQ_MASK, 155 .status_mask = SPEAR310_SMII3_IRQ_MASK,
156 }, { 156 }, {
157 .virq = VIRQ_WAKEUP_SMII0, 157 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
158 .status_mask = WAKEUP_SMII0_IRQ_MASK, 158 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
159 }, { 159 }, {
160 .virq = VIRQ_WAKEUP_SMII1, 160 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
161 .status_mask = WAKEUP_SMII1_IRQ_MASK, 161 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
162 }, { 162 }, {
163 .virq = VIRQ_WAKEUP_SMII2, 163 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
164 .status_mask = WAKEUP_SMII2_IRQ_MASK, 164 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
165 }, { 165 }, {
166 .virq = VIRQ_WAKEUP_SMII3, 166 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
167 .status_mask = WAKEUP_SMII3_IRQ_MASK, 167 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
168 }, 168 },
169}; 169};
170 170
171static struct spear_shirq shirq_ras1 = { 171static struct spear_shirq shirq_ras1 = {
172 .irq = IRQ_GEN_RAS_1, 172 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
173 .dev_config = shirq_ras1_config, 173 .dev_config = shirq_ras1_config,
174 .dev_count = ARRAY_SIZE(shirq_ras1_config), 174 .dev_count = ARRAY_SIZE(shirq_ras1_config),
175 .regs = { 175 .regs = {
176 .enb_reg = -1, 176 .enb_reg = -1,
177 .status_reg = INT_STS_MASK_REG, 177 .status_reg = SPEAR310_INT_STS_MASK_REG,
178 .status_reg_mask = SHIRQ_RAS1_MASK, 178 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
179 .clear_reg = -1, 179 .clear_reg = -1,
180 }, 180 },
181}; 181};
182 182
183static struct shirq_dev_config shirq_ras2_config[] = { 183static struct shirq_dev_config shirq_ras2_config[] = {
184 { 184 {
185 .virq = VIRQ_UART1, 185 .virq = SPEAR310_VIRQ_UART1,
186 .status_mask = UART1_IRQ_MASK, 186 .status_mask = SPEAR310_UART1_IRQ_MASK,
187 }, { 187 }, {
188 .virq = VIRQ_UART2, 188 .virq = SPEAR310_VIRQ_UART2,
189 .status_mask = UART2_IRQ_MASK, 189 .status_mask = SPEAR310_UART2_IRQ_MASK,
190 }, { 190 }, {
191 .virq = VIRQ_UART3, 191 .virq = SPEAR310_VIRQ_UART3,
192 .status_mask = UART3_IRQ_MASK, 192 .status_mask = SPEAR310_UART3_IRQ_MASK,
193 }, { 193 }, {
194 .virq = VIRQ_UART4, 194 .virq = SPEAR310_VIRQ_UART4,
195 .status_mask = UART4_IRQ_MASK, 195 .status_mask = SPEAR310_UART4_IRQ_MASK,
196 }, { 196 }, {
197 .virq = VIRQ_UART5, 197 .virq = SPEAR310_VIRQ_UART5,
198 .status_mask = UART5_IRQ_MASK, 198 .status_mask = SPEAR310_UART5_IRQ_MASK,
199 }, 199 },
200}; 200};
201 201
202static struct spear_shirq shirq_ras2 = { 202static struct spear_shirq shirq_ras2 = {
203 .irq = IRQ_GEN_RAS_2, 203 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
204 .dev_config = shirq_ras2_config, 204 .dev_config = shirq_ras2_config,
205 .dev_count = ARRAY_SIZE(shirq_ras2_config), 205 .dev_count = ARRAY_SIZE(shirq_ras2_config),
206 .regs = { 206 .regs = {
207 .enb_reg = -1, 207 .enb_reg = -1,
208 .status_reg = INT_STS_MASK_REG, 208 .status_reg = SPEAR310_INT_STS_MASK_REG,
209 .status_reg_mask = SHIRQ_RAS2_MASK, 209 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
210 .clear_reg = -1, 210 .clear_reg = -1,
211 }, 211 },
212}; 212};
213 213
214static struct shirq_dev_config shirq_ras3_config[] = { 214static struct shirq_dev_config shirq_ras3_config[] = {
215 { 215 {
216 .virq = VIRQ_EMI, 216 .virq = SPEAR310_VIRQ_EMI,
217 .status_mask = EMI_IRQ_MASK, 217 .status_mask = SPEAR310_EMI_IRQ_MASK,
218 }, 218 },
219}; 219};
220 220
221static struct spear_shirq shirq_ras3 = { 221static struct spear_shirq shirq_ras3 = {
222 .irq = IRQ_GEN_RAS_3, 222 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
223 .dev_config = shirq_ras3_config, 223 .dev_config = shirq_ras3_config,
224 .dev_count = ARRAY_SIZE(shirq_ras3_config), 224 .dev_count = ARRAY_SIZE(shirq_ras3_config),
225 .regs = { 225 .regs = {
226 .enb_reg = -1, 226 .enb_reg = -1,
227 .status_reg = INT_STS_MASK_REG, 227 .status_reg = SPEAR310_INT_STS_MASK_REG,
228 .status_reg_mask = SHIRQ_RAS3_MASK, 228 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
229 .clear_reg = -1, 229 .clear_reg = -1,
230 }, 230 },
231}; 231};
232 232
233static struct shirq_dev_config shirq_intrcomm_ras_config[] = { 233static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
234 { 234 {
235 .virq = VIRQ_TDM_HDLC, 235 .virq = SPEAR310_VIRQ_TDM_HDLC,
236 .status_mask = TDM_HDLC_IRQ_MASK, 236 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
237 }, { 237 }, {
238 .virq = VIRQ_RS485_0, 238 .virq = SPEAR310_VIRQ_RS485_0,
239 .status_mask = RS485_0_IRQ_MASK, 239 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
240 }, { 240 }, {
241 .virq = VIRQ_RS485_1, 241 .virq = SPEAR310_VIRQ_RS485_1,
242 .status_mask = RS485_1_IRQ_MASK, 242 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
243 }, 243 },
244}; 244};
245 245
246static struct spear_shirq shirq_intrcomm_ras = { 246static struct spear_shirq shirq_intrcomm_ras = {
247 .irq = IRQ_INTRCOMM_RAS_ARM, 247 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
248 .dev_config = shirq_intrcomm_ras_config, 248 .dev_config = shirq_intrcomm_ras_config,
249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
250 .regs = { 250 .regs = {
251 .enb_reg = -1, 251 .enb_reg = -1,
252 .status_reg = INT_STS_MASK_REG, 252 .status_reg = SPEAR310_INT_STS_MASK_REG,
253 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 253 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
254 .clear_reg = -1, 254 .clear_reg = -1,
255 }, 255 },
256}; 256};
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fc4598a46f5e..ccb745b60106 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -387,123 +387,123 @@ struct pmx_driver pmx_driver = {
387/* spear3xx shared irq */ 387/* spear3xx shared irq */
388static struct shirq_dev_config shirq_ras1_config[] = { 388static struct shirq_dev_config shirq_ras1_config[] = {
389 { 389 {
390 .virq = VIRQ_EMI, 390 .virq = SPEAR320_VIRQ_EMI,
391 .status_mask = EMI_IRQ_MASK, 391 .status_mask = SPEAR320_EMI_IRQ_MASK,
392 .clear_mask = EMI_IRQ_MASK, 392 .clear_mask = SPEAR320_EMI_IRQ_MASK,
393 }, { 393 }, {
394 .virq = VIRQ_CLCD, 394 .virq = SPEAR320_VIRQ_CLCD,
395 .status_mask = CLCD_IRQ_MASK, 395 .status_mask = SPEAR320_CLCD_IRQ_MASK,
396 .clear_mask = CLCD_IRQ_MASK, 396 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
397 }, { 397 }, {
398 .virq = VIRQ_SPP, 398 .virq = SPEAR320_VIRQ_SPP,
399 .status_mask = SPP_IRQ_MASK, 399 .status_mask = SPEAR320_SPP_IRQ_MASK,
400 .clear_mask = SPP_IRQ_MASK, 400 .clear_mask = SPEAR320_SPP_IRQ_MASK,
401 }, 401 },
402}; 402};
403 403
404static struct spear_shirq shirq_ras1 = { 404static struct spear_shirq shirq_ras1 = {
405 .irq = IRQ_GEN_RAS_1, 405 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
406 .dev_config = shirq_ras1_config, 406 .dev_config = shirq_ras1_config,
407 .dev_count = ARRAY_SIZE(shirq_ras1_config), 407 .dev_count = ARRAY_SIZE(shirq_ras1_config),
408 .regs = { 408 .regs = {
409 .enb_reg = -1, 409 .enb_reg = -1,
410 .status_reg = INT_STS_MASK_REG, 410 .status_reg = SPEAR320_INT_STS_MASK_REG,
411 .status_reg_mask = SHIRQ_RAS1_MASK, 411 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
412 .clear_reg = INT_CLR_MASK_REG, 412 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
413 .reset_to_clear = 1, 413 .reset_to_clear = 1,
414 }, 414 },
415}; 415};
416 416
417static struct shirq_dev_config shirq_ras3_config[] = { 417static struct shirq_dev_config shirq_ras3_config[] = {
418 { 418 {
419 .virq = VIRQ_PLGPIO, 419 .virq = SPEAR320_VIRQ_PLGPIO,
420 .enb_mask = GPIO_IRQ_MASK, 420 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
421 .status_mask = GPIO_IRQ_MASK, 421 .status_mask = SPEAR320_GPIO_IRQ_MASK,
422 .clear_mask = GPIO_IRQ_MASK, 422 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
423 }, { 423 }, {
424 .virq = VIRQ_I2S_PLAY, 424 .virq = SPEAR320_VIRQ_I2S_PLAY,
425 .enb_mask = I2S_PLAY_IRQ_MASK, 425 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
426 .status_mask = I2S_PLAY_IRQ_MASK, 426 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
427 .clear_mask = I2S_PLAY_IRQ_MASK, 427 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
428 }, { 428 }, {
429 .virq = VIRQ_I2S_REC, 429 .virq = SPEAR320_VIRQ_I2S_REC,
430 .enb_mask = I2S_REC_IRQ_MASK, 430 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
431 .status_mask = I2S_REC_IRQ_MASK, 431 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
432 .clear_mask = I2S_REC_IRQ_MASK, 432 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
433 }, 433 },
434}; 434};
435 435
436static struct spear_shirq shirq_ras3 = { 436static struct spear_shirq shirq_ras3 = {
437 .irq = IRQ_GEN_RAS_3, 437 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
438 .dev_config = shirq_ras3_config, 438 .dev_config = shirq_ras3_config,
439 .dev_count = ARRAY_SIZE(shirq_ras3_config), 439 .dev_count = ARRAY_SIZE(shirq_ras3_config),
440 .regs = { 440 .regs = {
441 .enb_reg = INT_ENB_MASK_REG, 441 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
442 .reset_to_enb = 1, 442 .reset_to_enb = 1,
443 .status_reg = INT_STS_MASK_REG, 443 .status_reg = SPEAR320_INT_STS_MASK_REG,
444 .status_reg_mask = SHIRQ_RAS3_MASK, 444 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
445 .clear_reg = INT_CLR_MASK_REG, 445 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
446 .reset_to_clear = 1, 446 .reset_to_clear = 1,
447 }, 447 },
448}; 448};
449 449
450static struct shirq_dev_config shirq_intrcomm_ras_config[] = { 450static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
451 { 451 {
452 .virq = VIRQ_CANU, 452 .virq = SPEAR320_VIRQ_CANU,
453 .status_mask = CAN_U_IRQ_MASK, 453 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
454 .clear_mask = CAN_U_IRQ_MASK, 454 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
455 }, { 455 }, {
456 .virq = VIRQ_CANL, 456 .virq = SPEAR320_VIRQ_CANL,
457 .status_mask = CAN_L_IRQ_MASK, 457 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
458 .clear_mask = CAN_L_IRQ_MASK, 458 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
459 }, { 459 }, {
460 .virq = VIRQ_UART1, 460 .virq = SPEAR320_VIRQ_UART1,
461 .status_mask = UART1_IRQ_MASK, 461 .status_mask = SPEAR320_UART1_IRQ_MASK,
462 .clear_mask = UART1_IRQ_MASK, 462 .clear_mask = SPEAR320_UART1_IRQ_MASK,
463 }, { 463 }, {
464 .virq = VIRQ_UART2, 464 .virq = SPEAR320_VIRQ_UART2,
465 .status_mask = UART2_IRQ_MASK, 465 .status_mask = SPEAR320_UART2_IRQ_MASK,
466 .clear_mask = UART2_IRQ_MASK, 466 .clear_mask = SPEAR320_UART2_IRQ_MASK,
467 }, { 467 }, {
468 .virq = VIRQ_SSP1, 468 .virq = SPEAR320_VIRQ_SSP1,
469 .status_mask = SSP1_IRQ_MASK, 469 .status_mask = SPEAR320_SSP1_IRQ_MASK,
470 .clear_mask = SSP1_IRQ_MASK, 470 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
471 }, { 471 }, {
472 .virq = VIRQ_SSP2, 472 .virq = SPEAR320_VIRQ_SSP2,
473 .status_mask = SSP2_IRQ_MASK, 473 .status_mask = SPEAR320_SSP2_IRQ_MASK,
474 .clear_mask = SSP2_IRQ_MASK, 474 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
475 }, { 475 }, {
476 .virq = VIRQ_SMII0, 476 .virq = SPEAR320_VIRQ_SMII0,
477 .status_mask = SMII0_IRQ_MASK, 477 .status_mask = SPEAR320_SMII0_IRQ_MASK,
478 .clear_mask = SMII0_IRQ_MASK, 478 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
479 }, { 479 }, {
480 .virq = VIRQ_MII1_SMII1, 480 .virq = SPEAR320_VIRQ_MII1_SMII1,
481 .status_mask = MII1_SMII1_IRQ_MASK, 481 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
482 .clear_mask = MII1_SMII1_IRQ_MASK, 482 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
483 }, { 483 }, {
484 .virq = VIRQ_WAKEUP_SMII0, 484 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
485 .status_mask = WAKEUP_SMII0_IRQ_MASK, 485 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
486 .clear_mask = WAKEUP_SMII0_IRQ_MASK, 486 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
487 }, { 487 }, {
488 .virq = VIRQ_WAKEUP_MII1_SMII1, 488 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
489 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 489 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
490 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 490 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
491 }, { 491 }, {
492 .virq = VIRQ_I2C, 492 .virq = SPEAR320_VIRQ_I2C1,
493 .status_mask = I2C1_IRQ_MASK, 493 .status_mask = SPEAR320_I2C1_IRQ_MASK,
494 .clear_mask = I2C1_IRQ_MASK, 494 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
495 }, 495 },
496}; 496};
497 497
498static struct spear_shirq shirq_intrcomm_ras = { 498static struct spear_shirq shirq_intrcomm_ras = {
499 .irq = IRQ_INTRCOMM_RAS_ARM, 499 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
500 .dev_config = shirq_intrcomm_ras_config, 500 .dev_config = shirq_intrcomm_ras_config,
501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
502 .regs = { 502 .regs = {
503 .enb_reg = -1, 503 .enb_reg = -1,
504 .status_reg = INT_STS_MASK_REG, 504 .status_reg = SPEAR320_INT_STS_MASK_REG,
505 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 505 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
506 .clear_reg = INT_CLR_MASK_REG, 506 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
507 .reset_to_clear = 1, 507 .reset_to_clear = 1,
508 }, 508 },
509}; 509};
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 1316eaa14822..35cb8c72d899 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -25,7 +25,7 @@
25/* gpio device registration */ 25/* gpio device registration */
26static struct pl061_platform_data gpio_plat_data = { 26static struct pl061_platform_data gpio_plat_data = {
27 .gpio_base = 0, 27 .gpio_base = 0,
28 .irq_base = SPEAR_GPIO_INT_BASE, 28 .irq_base = SPEAR3XX_GPIO_INT_BASE,
29}; 29};
30 30
31struct amba_device gpio_device = { 31struct amba_device gpio_device = {
@@ -38,7 +38,7 @@ struct amba_device gpio_device = {
38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, 38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
39 .flags = IORESOURCE_MEM, 39 .flags = IORESOURCE_MEM,
40 }, 40 },
41 .irq = {IRQ_BASIC_GPIO, NO_IRQ}, 41 .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
42}; 42};
43 43
44/* uart device registration */ 44/* uart device registration */
@@ -51,7 +51,7 @@ struct amba_device uart_device = {
51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, 51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
52 .flags = IORESOURCE_MEM, 52 .flags = IORESOURCE_MEM,
53 }, 53 },
54 .irq = {IRQ_UART, NO_IRQ}, 54 .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
55}; 55};
56 56
57/* Do spear3xx familiy common initialization part here */ 57/* Do spear3xx familiy common initialization part here */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 21:38:32 -0400