diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/spear310.c')
-rw-r--r-- | arch/arm/mach-spear3xx/spear310.c | 92 |
1 files changed, 46 insertions, 46 deletions
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index e4fce3f1042c..826c166a76a5 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c | |||
@@ -142,115 +142,115 @@ struct pmx_driver pmx_driver = { | |||
142 | /* spear3xx shared irq */ | 142 | /* spear3xx shared irq */ |
143 | static struct shirq_dev_config shirq_ras1_config[] = { | 143 | static struct shirq_dev_config shirq_ras1_config[] = { |
144 | { | 144 | { |
145 | .virq = VIRQ_SMII0, | 145 | .virq = SPEAR310_VIRQ_SMII0, |
146 | .status_mask = SMII0_IRQ_MASK, | 146 | .status_mask = SPEAR310_SMII0_IRQ_MASK, |
147 | }, { | 147 | }, { |
148 | .virq = VIRQ_SMII1, | 148 | .virq = SPEAR310_VIRQ_SMII1, |
149 | .status_mask = SMII1_IRQ_MASK, | 149 | .status_mask = SPEAR310_SMII1_IRQ_MASK, |
150 | }, { | 150 | }, { |
151 | .virq = VIRQ_SMII2, | 151 | .virq = SPEAR310_VIRQ_SMII2, |
152 | .status_mask = SMII2_IRQ_MASK, | 152 | .status_mask = SPEAR310_SMII2_IRQ_MASK, |
153 | }, { | 153 | }, { |
154 | .virq = VIRQ_SMII3, | 154 | .virq = SPEAR310_VIRQ_SMII3, |
155 | .status_mask = SMII3_IRQ_MASK, | 155 | .status_mask = SPEAR310_SMII3_IRQ_MASK, |
156 | }, { | 156 | }, { |
157 | .virq = VIRQ_WAKEUP_SMII0, | 157 | .virq = SPEAR310_VIRQ_WAKEUP_SMII0, |
158 | .status_mask = WAKEUP_SMII0_IRQ_MASK, | 158 | .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, |
159 | }, { | 159 | }, { |
160 | .virq = VIRQ_WAKEUP_SMII1, | 160 | .virq = SPEAR310_VIRQ_WAKEUP_SMII1, |
161 | .status_mask = WAKEUP_SMII1_IRQ_MASK, | 161 | .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, |
162 | }, { | 162 | }, { |
163 | .virq = VIRQ_WAKEUP_SMII2, | 163 | .virq = SPEAR310_VIRQ_WAKEUP_SMII2, |
164 | .status_mask = WAKEUP_SMII2_IRQ_MASK, | 164 | .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, |
165 | }, { | 165 | }, { |
166 | .virq = VIRQ_WAKEUP_SMII3, | 166 | .virq = SPEAR310_VIRQ_WAKEUP_SMII3, |
167 | .status_mask = WAKEUP_SMII3_IRQ_MASK, | 167 | .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, |
168 | }, | 168 | }, |
169 | }; | 169 | }; |
170 | 170 | ||
171 | static struct spear_shirq shirq_ras1 = { | 171 | static struct spear_shirq shirq_ras1 = { |
172 | .irq = IRQ_GEN_RAS_1, | 172 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
173 | .dev_config = shirq_ras1_config, | 173 | .dev_config = shirq_ras1_config, |
174 | .dev_count = ARRAY_SIZE(shirq_ras1_config), | 174 | .dev_count = ARRAY_SIZE(shirq_ras1_config), |
175 | .regs = { | 175 | .regs = { |
176 | .enb_reg = -1, | 176 | .enb_reg = -1, |
177 | .status_reg = INT_STS_MASK_REG, | 177 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
178 | .status_reg_mask = SHIRQ_RAS1_MASK, | 178 | .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, |
179 | .clear_reg = -1, | 179 | .clear_reg = -1, |
180 | }, | 180 | }, |
181 | }; | 181 | }; |
182 | 182 | ||
183 | static struct shirq_dev_config shirq_ras2_config[] = { | 183 | static struct shirq_dev_config shirq_ras2_config[] = { |
184 | { | 184 | { |
185 | .virq = VIRQ_UART1, | 185 | .virq = SPEAR310_VIRQ_UART1, |
186 | .status_mask = UART1_IRQ_MASK, | 186 | .status_mask = SPEAR310_UART1_IRQ_MASK, |
187 | }, { | 187 | }, { |
188 | .virq = VIRQ_UART2, | 188 | .virq = SPEAR310_VIRQ_UART2, |
189 | .status_mask = UART2_IRQ_MASK, | 189 | .status_mask = SPEAR310_UART2_IRQ_MASK, |
190 | }, { | 190 | }, { |
191 | .virq = VIRQ_UART3, | 191 | .virq = SPEAR310_VIRQ_UART3, |
192 | .status_mask = UART3_IRQ_MASK, | 192 | .status_mask = SPEAR310_UART3_IRQ_MASK, |
193 | }, { | 193 | }, { |
194 | .virq = VIRQ_UART4, | 194 | .virq = SPEAR310_VIRQ_UART4, |
195 | .status_mask = UART4_IRQ_MASK, | 195 | .status_mask = SPEAR310_UART4_IRQ_MASK, |
196 | }, { | 196 | }, { |
197 | .virq = VIRQ_UART5, | 197 | .virq = SPEAR310_VIRQ_UART5, |
198 | .status_mask = UART5_IRQ_MASK, | 198 | .status_mask = SPEAR310_UART5_IRQ_MASK, |
199 | }, | 199 | }, |
200 | }; | 200 | }; |
201 | 201 | ||
202 | static struct spear_shirq shirq_ras2 = { | 202 | static struct spear_shirq shirq_ras2 = { |
203 | .irq = IRQ_GEN_RAS_2, | 203 | .irq = SPEAR3XX_IRQ_GEN_RAS_2, |
204 | .dev_config = shirq_ras2_config, | 204 | .dev_config = shirq_ras2_config, |
205 | .dev_count = ARRAY_SIZE(shirq_ras2_config), | 205 | .dev_count = ARRAY_SIZE(shirq_ras2_config), |
206 | .regs = { | 206 | .regs = { |
207 | .enb_reg = -1, | 207 | .enb_reg = -1, |
208 | .status_reg = INT_STS_MASK_REG, | 208 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
209 | .status_reg_mask = SHIRQ_RAS2_MASK, | 209 | .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, |
210 | .clear_reg = -1, | 210 | .clear_reg = -1, |
211 | }, | 211 | }, |
212 | }; | 212 | }; |
213 | 213 | ||
214 | static struct shirq_dev_config shirq_ras3_config[] = { | 214 | static struct shirq_dev_config shirq_ras3_config[] = { |
215 | { | 215 | { |
216 | .virq = VIRQ_EMI, | 216 | .virq = SPEAR310_VIRQ_EMI, |
217 | .status_mask = EMI_IRQ_MASK, | 217 | .status_mask = SPEAR310_EMI_IRQ_MASK, |
218 | }, | 218 | }, |
219 | }; | 219 | }; |
220 | 220 | ||
221 | static struct spear_shirq shirq_ras3 = { | 221 | static struct spear_shirq shirq_ras3 = { |
222 | .irq = IRQ_GEN_RAS_3, | 222 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
223 | .dev_config = shirq_ras3_config, | 223 | .dev_config = shirq_ras3_config, |
224 | .dev_count = ARRAY_SIZE(shirq_ras3_config), | 224 | .dev_count = ARRAY_SIZE(shirq_ras3_config), |
225 | .regs = { | 225 | .regs = { |
226 | .enb_reg = -1, | 226 | .enb_reg = -1, |
227 | .status_reg = INT_STS_MASK_REG, | 227 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
228 | .status_reg_mask = SHIRQ_RAS3_MASK, | 228 | .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, |
229 | .clear_reg = -1, | 229 | .clear_reg = -1, |
230 | }, | 230 | }, |
231 | }; | 231 | }; |
232 | 232 | ||
233 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { | 233 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
234 | { | 234 | { |
235 | .virq = VIRQ_TDM_HDLC, | 235 | .virq = SPEAR310_VIRQ_TDM_HDLC, |
236 | .status_mask = TDM_HDLC_IRQ_MASK, | 236 | .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, |
237 | }, { | 237 | }, { |
238 | .virq = VIRQ_RS485_0, | 238 | .virq = SPEAR310_VIRQ_RS485_0, |
239 | .status_mask = RS485_0_IRQ_MASK, | 239 | .status_mask = SPEAR310_RS485_0_IRQ_MASK, |
240 | }, { | 240 | }, { |
241 | .virq = VIRQ_RS485_1, | 241 | .virq = SPEAR310_VIRQ_RS485_1, |
242 | .status_mask = RS485_1_IRQ_MASK, | 242 | .status_mask = SPEAR310_RS485_1_IRQ_MASK, |
243 | }, | 243 | }, |
244 | }; | 244 | }; |
245 | 245 | ||
246 | static struct spear_shirq shirq_intrcomm_ras = { | 246 | static struct spear_shirq shirq_intrcomm_ras = { |
247 | .irq = IRQ_INTRCOMM_RAS_ARM, | 247 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
248 | .dev_config = shirq_intrcomm_ras_config, | 248 | .dev_config = shirq_intrcomm_ras_config, |
249 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), | 249 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), |
250 | .regs = { | 250 | .regs = { |
251 | .enb_reg = -1, | 251 | .enb_reg = -1, |
252 | .status_reg = INT_STS_MASK_REG, | 252 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
253 | .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, | 253 | .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, |
254 | .clear_reg = -1, | 254 | .clear_reg = -1, |
255 | }, | 255 | }, |
256 | }; | 256 | }; |