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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 20:09:31 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 20:09:31 -0400
commit4b30b6f23a1a59cda29cc12566eb4f32a22a8069 (patch)
tree69e262a5065ce8be21c919febd29d5d9660f3e97
parent38da590bef19f23d4b610aecaad4f32de483890d (diff)
parent6c59c115b0f295434cc4f917d180fecd84d39f81 (diff)
Merge branch 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: MAINTAINERS: add maintainer of CSR SiRFprimaII machine ARM: CSR: initializing L2 cache ARM: CSR: mapping early DEBUG_LL uart ARM: CSR: Adding CSR SiRFprimaII board support OMAP4: clocks: Update the clock tree with 4460 clock nodes OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts OMAP4: ID: add omap_has_feature for max freq supported OMAP: ID: introduce chip detection for OMAP4460 ARM: Xilinx: merge board file into main platform code ARM: Xilinx: Adding Xilinx board support Fix up conflicts in arch/arm/mach-omap2/cm-regbits-44xx.h
-rw-r--r--Documentation/devicetree/bindings/arm/sirf.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/xilinx.txt7
-rw-r--r--MAINTAINERS6
-rw-r--r--arch/arm/Kconfig26
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts416
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts52
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c39
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h36
-rw-r--r--arch/arm/mach-omap2/id.c53
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h8
-rw-r--r--arch/arm/mach-prima2/Makefile7
-rw-r--r--arch/arm/mach-prima2/Makefile.boot3
-rw-r--r--arch/arm/mach-prima2/clock.c509
-rw-r--r--arch/arm/mach-prima2/common.h26
-rw-r--r--arch/arm/mach-prima2/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/debug-macro.S29
-rw-r--r--arch/arm/mach-prima2/include/mach/entry-macro.S29
-rw-r--r--arch/arm/mach-prima2/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/io.h16
-rw-r--r--arch/arm/mach-prima2/include/mach/irqs.h17
-rw-r--r--arch/arm/mach-prima2/include/mach/map.h16
-rw-r--r--arch/arm/mach-prima2/include/mach/memory.h21
-rw-r--r--arch/arm/mach-prima2/include/mach/system.h29
-rw-r--r--arch/arm/mach-prima2/include/mach/timex.h14
-rw-r--r--arch/arm/mach-prima2/include/mach/uart.h23
-rw-r--r--arch/arm/mach-prima2/include/mach/uncompress.h40
-rw-r--r--arch/arm/mach-prima2/include/mach/vmalloc.h16
-rw-r--r--arch/arm/mach-prima2/irq.c71
-rw-r--r--arch/arm/mach-prima2/l2x0.c59
-rw-r--r--arch/arm/mach-prima2/lluart.c25
-rw-r--r--arch/arm/mach-prima2/prima2.c41
-rw-r--r--arch/arm/mach-prima2/rstc.c69
-rw-r--r--arch/arm/mach-prima2/timer.c217
-rw-r--r--arch/arm/mach-zynq/Makefile6
-rw-r--r--arch/arm/mach-zynq/Makefile.boot3
-rw-r--r--arch/arm/mach-zynq/board_dt.c0
-rw-r--r--arch/arm/mach-zynq/common.c118
-rw-r--r--arch/arm/mach-zynq/common.h24
-rw-r--r--arch/arm/mach-zynq/include/mach/clkdev.h32
-rw-r--r--arch/arm/mach-zynq/include/mach/debug-macro.S36
-rw-r--r--arch/arm/mach-zynq/include/mach/entry-macro.S30
-rw-r--r--arch/arm/mach-zynq/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-zynq/include/mach/io.h33
-rw-r--r--arch/arm/mach-zynq/include/mach/irqs.h21
-rw-r--r--arch/arm/mach-zynq/include/mach/memory.h22
-rw-r--r--arch/arm/mach-zynq/include/mach/system.h28
-rw-r--r--arch/arm/mach-zynq/include/mach/timex.h23
-rw-r--r--arch/arm/mach-zynq/include/mach/uart.h25
-rw-r--r--arch/arm/mach-zynq/include/mach/uncompress.h51
-rw-r--r--arch/arm/mach-zynq/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-zynq/include/mach/zynq_soc.h48
-rw-r--r--arch/arm/mach-zynq/timer.c298
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h35
57 files changed, 2820 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt
new file mode 100644
index 000000000000..6b07f65b32de
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sirf.txt
@@ -0,0 +1,3 @@
1prima2 "cb" evalutation board
2Required root node properties:
3 - compatible = "sirf,prima2-cb", "sirf,prima2";
diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt
new file mode 100644
index 000000000000..6f1ed830b4f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/xilinx.txt
@@ -0,0 +1,7 @@
1Xilinx Zynq EP107 Emulation Platform board
2
3This board is an emulation platform for the Zynq product which is
4based on an ARM Cortex A9 processor.
5
6Required root node properties:
7 - compatible = "xlnx,zynq-ep107";
diff --git a/MAINTAINERS b/MAINTAINERS
index bf99d93c6366..7b2e9e85e427 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -734,6 +734,12 @@ T: git git://git.berlios.de/gemini-board
734S: Maintained 734S: Maintained
735F: arch/arm/mach-gemini/ 735F: arch/arm/mach-gemini/
736 736
737ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
738M: Barry Song <baohua.song@csr.com>
739L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
740S: Maintained
741F: arch/arm/mach-prima2/
742
737ARM/EBSA110 MACHINE SUPPORT 743ARM/EBSA110 MACHINE SUPPORT
738M: Russell King <linux@arm.linux.org.uk> 744M: Russell King <linux@arm.linux.org.uk>
739L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 745L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9cb1f4bd7618..1f6921172b1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -340,6 +340,19 @@ config ARCH_GEMINI
340 help 340 help
341 Support for the Cortina Systems Gemini family SoCs 341 Support for the Cortina Systems Gemini family SoCs
342 342
343config ARCH_PRIMA2
344 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
345 select CPU_V7
346 select GENERIC_TIME
347 select NO_IOPORT
348 select GENERIC_CLOCKEVENTS
349 select CLKDEV_LOOKUP
350 select GENERIC_IRQ_CHIP
351 select USE_OF
352 select ZONE_DMA
353 help
354 Support for CSR SiRFSoC ARM Cortex A9 Platform
355
343config ARCH_EBSA110 356config ARCH_EBSA110
344 bool "EBSA-110" 357 bool "EBSA-110"
345 select CPU_SA110 358 select CPU_SA110
@@ -884,6 +897,19 @@ config ARCH_VT8500
884 select HAVE_PWM 897 select HAVE_PWM
885 help 898 help
886 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 899 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
900
901config ARCH_ZYNQ
902 bool "Xilinx Zynq ARM Cortex A9 Platform"
903 select CPU_V7
904 select GENERIC_TIME
905 select GENERIC_CLOCKEVENTS
906 select CLKDEV_LOOKUP
907 select ARM_GIC
908 select ARM_AMBA
909 select ICST
910 select USE_OF
911 help
912 Support for Xilinx Zynq ARM Cortex A9 Platform
887endchoice 913endchoice
888 914
889# 915#
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 206c34ecb9e3..3a4a04b33d0f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -168,6 +168,7 @@ machine-$(CONFIG_ARCH_OMAP3) := omap2
168machine-$(CONFIG_ARCH_OMAP4) := omap2 168machine-$(CONFIG_ARCH_OMAP4) := omap2
169machine-$(CONFIG_ARCH_ORION5X) := orion5x 169machine-$(CONFIG_ARCH_ORION5X) := orion5x
170machine-$(CONFIG_ARCH_PNX4008) := pnx4008 170machine-$(CONFIG_ARCH_PNX4008) := pnx4008
171machine-$(CONFIG_ARCH_PRIMA2) := prima2
171machine-$(CONFIG_ARCH_PXA) := pxa 172machine-$(CONFIG_ARCH_PXA) := pxa
172machine-$(CONFIG_ARCH_REALVIEW) := realview 173machine-$(CONFIG_ARCH_REALVIEW) := realview
173machine-$(CONFIG_ARCH_RPC) := rpc 174machine-$(CONFIG_ARCH_RPC) := rpc
@@ -194,6 +195,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx
194machine-$(CONFIG_MACH_SPEAR310) := spear3xx 195machine-$(CONFIG_MACH_SPEAR310) := spear3xx
195machine-$(CONFIG_MACH_SPEAR320) := spear3xx 196machine-$(CONFIG_MACH_SPEAR320) := spear3xx
196machine-$(CONFIG_MACH_SPEAR600) := spear6xx 197machine-$(CONFIG_MACH_SPEAR600) := spear6xx
198machine-$(CONFIG_ARCH_ZYNQ) := zynq
197 199
198# Platform directory name. This list is sorted alphanumerically 200# Platform directory name. This list is sorted alphanumerically
199# by CONFIG_* macro name. 201# by CONFIG_* macro name.
@@ -201,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc
201plat-$(CONFIG_ARCH_OMAP) := omap 203plat-$(CONFIG_ARCH_OMAP) := omap
202plat-$(CONFIG_ARCH_S3C64XX) := samsung 204plat-$(CONFIG_ARCH_S3C64XX) := samsung
203plat-$(CONFIG_ARCH_TCC_926) := tcc 205plat-$(CONFIG_ARCH_TCC_926) := tcc
206plat-$(CONFIG_ARCH_ZYNQ) := versatile
204plat-$(CONFIG_PLAT_IOP) := iop 207plat-$(CONFIG_PLAT_IOP) := iop
205plat-$(CONFIG_PLAT_NOMADIK) := nomadik 208plat-$(CONFIG_PLAT_NOMADIK) := nomadik
206plat-$(CONFIG_PLAT_ORION) := orion 209plat-$(CONFIG_PLAT_ORION) := orion
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
new file mode 100644
index 000000000000..6fecc88065b2
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -0,0 +1,416 @@
1/dts-v1/;
2/ {
3 model = "SiRF Prima2 eVB";
4 compatible = "sirf,prima2-cb", "sirf,prima2";
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&intc>;
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 chosen {
14 bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
15 linux,stdout-path = &uart1;
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 axi {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
40
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache";
43 reg = <0x80040000 0x1000>;
44 interrupts = <59>;
45 };
46
47 intc: interrupt-controller@80020000 {
48 #interrupt-cells = <1>;
49 interrupt-controller;
50 compatible = "sirf,prima2-intc";
51 reg = <0x80020000 0x1000>;
52 };
53
54 sys-iobg {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges = <0x88000000 0x88000000 0x40000>;
59
60 clock-controller@88000000 {
61 compatible = "sirf,prima2-clkc";
62 reg = <0x88000000 0x1000>;
63 interrupts = <3>;
64 };
65
66 reset-controller@88010000 {
67 compatible = "sirf,prima2-rstc";
68 reg = <0x88010000 0x1000>;
69 };
70 };
71
72 mem-iobg {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges = <0x90000000 0x90000000 0x10000>;
77
78 memory-controller@90000000 {
79 compatible = "sirf,prima2-memc";
80 reg = <0x90000000 0x10000>;
81 interrupts = <27>;
82 };
83 };
84
85 disp-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x90010000 0x90010000 0x30000>;
90
91 display@90010000 {
92 compatible = "sirf,prima2-lcd";
93 reg = <0x90010000 0x20000>;
94 interrupts = <30>;
95 };
96
97 vpp@90020000 {
98 compatible = "sirf,prima2-vpp";
99 reg = <0x90020000 0x10000>;
100 interrupts = <31>;
101 };
102 };
103
104 graphics-iobg {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0x98000000 0x98000000 0x8000000>;
109
110 graphics@98000000 {
111 compatible = "powervr,sgx531";
112 reg = <0x98000000 0x8000000>;
113 interrupts = <6>;
114 };
115 };
116
117 multimedia-iobg {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges = <0xa0000000 0xa0000000 0x8000000>;
122
123 multimedia@a0000000 {
124 compatible = "sirf,prima2-video-codec";
125 reg = <0xa0000000 0x8000000>;
126 interrupts = <5>;
127 };
128 };
129
130 dsp-iobg {
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0xa8000000 0xa8000000 0x2000000>;
135
136 dspif@a8000000 {
137 compatible = "sirf,prima2-dspif";
138 reg = <0xa8000000 0x10000>;
139 interrupts = <9>;
140 };
141
142 gps@a8010000 {
143 compatible = "sirf,prima2-gps";
144 reg = <0xa8010000 0x10000>;
145 interrupts = <7>;
146 };
147
148 dsp@a9000000 {
149 compatible = "sirf,prima2-dsp";
150 reg = <0xa9000000 0x1000000>;
151 interrupts = <8>;
152 };
153 };
154
155 peri-iobg {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0xb0000000 0xb0000000 0x180000>;
160
161 timer@b0020000 {
162 compatible = "sirf,prima2-tick";
163 reg = <0xb0020000 0x1000>;
164 interrupts = <0>;
165 };
166
167 nand@b0030000 {
168 compatible = "sirf,prima2-nand";
169 reg = <0xb0030000 0x10000>;
170 interrupts = <41>;
171 };
172
173 audio@b0040000 {
174 compatible = "sirf,prima2-audio";
175 reg = <0xb0040000 0x10000>;
176 interrupts = <35>;
177 };
178
179 uart0: uart@b0050000 {
180 cell-index = <0>;
181 compatible = "sirf,prima2-uart";
182 reg = <0xb0050000 0x10000>;
183 interrupts = <17>;
184 };
185
186 uart1: uart@b0060000 {
187 cell-index = <1>;
188 compatible = "sirf,prima2-uart";
189 reg = <0xb0060000 0x10000>;
190 interrupts = <18>;
191 };
192
193 uart2: uart@b0070000 {
194 cell-index = <2>;
195 compatible = "sirf,prima2-uart";
196 reg = <0xb0070000 0x10000>;
197 interrupts = <19>;
198 };
199
200 usp0: usp@b0080000 {
201 cell-index = <0>;
202 compatible = "sirf,prima2-usp";
203 reg = <0xb0080000 0x10000>;
204 interrupts = <20>;
205 };
206
207 usp1: usp@b0090000 {
208 cell-index = <1>;
209 compatible = "sirf,prima2-usp";
210 reg = <0xb0090000 0x10000>;
211 interrupts = <21>;
212 };
213
214 usp2: usp@b00a0000 {
215 cell-index = <2>;
216 compatible = "sirf,prima2-usp";
217 reg = <0xb00a0000 0x10000>;
218 interrupts = <22>;
219 };
220
221 dmac0: dma-controller@b00b0000 {
222 cell-index = <0>;
223 compatible = "sirf,prima2-dmac";
224 reg = <0xb00b0000 0x10000>;
225 interrupts = <12>;
226 };
227
228 dmac1: dma-controller@b0160000 {
229 cell-index = <1>;
230 compatible = "sirf,prima2-dmac";
231 reg = <0xb0160000 0x10000>;
232 interrupts = <13>;
233 };
234
235 vip@b00C0000 {
236 compatible = "sirf,prima2-vip";
237 reg = <0xb00C0000 0x10000>;
238 };
239
240 spi0: spi@b00d0000 {
241 cell-index = <0>;
242 compatible = "sirf,prima2-spi";
243 reg = <0xb00d0000 0x10000>;
244 interrupts = <15>;
245 };
246
247 spi1: spi@b0170000 {
248 cell-index = <1>;
249 compatible = "sirf,prima2-spi";
250 reg = <0xb0170000 0x10000>;
251 interrupts = <16>;
252 };
253
254 i2c0: i2c@b00e0000 {
255 cell-index = <0>;
256 compatible = "sirf,prima2-i2c";
257 reg = <0xb00e0000 0x10000>;
258 interrupts = <24>;
259 };
260
261 i2c1: i2c@b00f0000 {
262 cell-index = <1>;
263 compatible = "sirf,prima2-i2c";
264 reg = <0xb00f0000 0x10000>;
265 interrupts = <25>;
266 };
267
268 tsc@b0110000 {
269 compatible = "sirf,prima2-tsc";
270 reg = <0xb0110000 0x10000>;
271 interrupts = <33>;
272 };
273
274 gpio: gpio-controller@b0120000 {
275 #gpio-cells = <2>;
276 #interrupt-cells = <2>;
277 compatible = "sirf,prima2-gpio";
278 reg = <0xb0120000 0x10000>;
279 gpio-controller;
280 interrupt-controller;
281 };
282
283 pwm@b0130000 {
284 compatible = "sirf,prima2-pwm";
285 reg = <0xb0130000 0x10000>;
286 };
287
288 efusesys@b0140000 {
289 compatible = "sirf,prima2-efuse";
290 reg = <0xb0140000 0x10000>;
291 };
292
293 pulsec@b0150000 {
294 compatible = "sirf,prima2-pulsec";
295 reg = <0xb0150000 0x10000>;
296 interrupts = <48>;
297 };
298
299 pci-iobg {
300 compatible = "sirf,prima2-pciiobg", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges = <0x56000000 0x56000000 0x1b00000>;
304
305 sd0: sdhci@56000000 {
306 cell-index = <0>;
307 compatible = "sirf,prima2-sdhc";
308 reg = <0x56000000 0x100000>;
309 interrupts = <38>;
310 };
311
312 sd1: sdhci@56100000 {
313 cell-index = <1>;
314 compatible = "sirf,prima2-sdhc";
315 reg = <0x56100000 0x100000>;
316 interrupts = <38>;
317 };
318
319 sd2: sdhci@56200000 {
320 cell-index = <2>;
321 compatible = "sirf,prima2-sdhc";
322 reg = <0x56200000 0x100000>;
323 interrupts = <23>;
324 };
325
326 sd3: sdhci@56300000 {
327 cell-index = <3>;
328 compatible = "sirf,prima2-sdhc";
329 reg = <0x56300000 0x100000>;
330 interrupts = <23>;
331 };
332
333 sd4: sdhci@56400000 {
334 cell-index = <4>;
335 compatible = "sirf,prima2-sdhc";
336 reg = <0x56400000 0x100000>;
337 interrupts = <39>;
338 };
339
340 sd5: sdhci@56500000 {
341 cell-index = <5>;
342 compatible = "sirf,prima2-sdhc";
343 reg = <0x56500000 0x100000>;
344 interrupts = <39>;
345 };
346
347 pci-copy@57900000 {
348 compatible = "sirf,prima2-pcicp";
349 reg = <0x57900000 0x100000>;
350 interrupts = <40>;
351 };
352
353 rom-interface@57a00000 {
354 compatible = "sirf,prima2-romif";
355 reg = <0x57a00000 0x100000>;
356 };
357 };
358 };
359
360 rtc-iobg {
361 compatible = "sirf,prima2-rtciobg", "simple-bus";
362 #address-cells = <1>;
363 #size-cells = <1>;
364 reg = <0x80030000 0x10000>;
365
366 gpsrtc@1000 {
367 compatible = "sirf,prima2-gpsrtc";
368 reg = <0x1000 0x1000>;
369 interrupts = <55 56 57>;
370 };
371
372 sysrtc@2000 {
373 compatible = "sirf,prima2-sysrtc";
374 reg = <0x2000 0x1000>;
375 interrupts = <52 53 54>;
376 };
377
378 pwrc@3000 {
379 compatible = "sirf,prima2-pwrc";
380 reg = <0x3000 0x1000>;
381 interrupts = <32>;
382 };
383 };
384
385 uus-iobg {
386 compatible = "simple-bus";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0xb8000000 0xb8000000 0x40000>;
390
391 usb0: usb@b00e0000 {
392 compatible = "chipidea,ci13611a-prima2";
393 reg = <0xb8000000 0x10000>;
394 interrupts = <10>;
395 };
396
397 usb1: usb@b00f0000 {
398 compatible = "chipidea,ci13611a-prima2";
399 reg = <0xb8010000 0x10000>;
400 interrupts = <11>;
401 };
402
403 sata@b00f0000 {
404 compatible = "synopsys,dwc-ahsata";
405 reg = <0xb8020000 0x10000>;
406 interrupts = <37>;
407 };
408
409 security@b00f0000 {
410 compatible = "sirf,prima2-security";
411 reg = <0xb8030000 0x10000>;
412 interrupts = <42>;
413 };
414 };
415 };
416};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
new file mode 100644
index 000000000000..37ca192fb193
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-ep107.dts
@@ -0,0 +1,52 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/ {
16 model = "Xilinx Zynq EP107";
17 compatible = "xlnx,zynq-ep107";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
21
22 memory {
23 device_type = "memory";
24 reg = <0x0 0x10000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
29 linux,stdout-path = &uart0;
30 };
31
32 amba {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 intc: interrupt-controller@f8f01000 {
39 interrupt-controller;
40 compatible = "arm,gic";
41 reg = <0xF8F01000 0x1000>;
42 #interrupt-cells = <2>;
43 };
44
45 uart0: uart@e0000000 {
46 compatible = "xlnx,xuartps";
47 reg = <0xE0000000 0x1000>;
48 interrupts = <59 0>;
49 clock = <50000000>;
50 };
51 };
52};
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 044df38f65ce..5b7cab794fb9 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1397,6 +1397,40 @@ static struct clk dss_dss_clk = {
1397 .recalc = &followparent_recalc, 1397 .recalc = &followparent_recalc,
1398}; 1398};
1399 1399
1400static const struct clksel_rate div3_8to32_rates[] = {
1401 { .div = 8, .val = 0, .flags = RATE_IN_44XX },
1402 { .div = 16, .val = 1, .flags = RATE_IN_44XX },
1403 { .div = 32, .val = 2, .flags = RATE_IN_44XX },
1404 { .div = 0 },
1405};
1406
1407static const struct clksel div_ts_div[] = {
1408 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1409 { .parent = NULL },
1410};
1411
1412static struct clk div_ts_ck = {
1413 .name = "div_ts_ck",
1414 .parent = &l4_wkup_clk_mux_ck,
1415 .clksel = div_ts_div,
1416 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1417 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1418 .ops = &clkops_null,
1419 .recalc = &omap2_clksel_recalc,
1420 .round_rate = &omap2_clksel_round_rate,
1421 .set_rate = &omap2_clksel_set_rate,
1422};
1423
1424static struct clk bandgap_ts_fclk = {
1425 .name = "bandgap_ts_fclk",
1426 .ops = &clkops_omap2_dflt,
1427 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1428 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1429 .clkdm_name = "l4_wkup_clkdm",
1430 .parent = &div_ts_ck,
1431 .recalc = &followparent_recalc,
1432};
1433
1400static struct clk dss_48mhz_clk = { 1434static struct clk dss_48mhz_clk = {
1401 .name = "dss_48mhz_clk", 1435 .name = "dss_48mhz_clk",
1402 .ops = &clkops_omap2_dflt, 1436 .ops = &clkops_omap2_dflt,
@@ -3028,7 +3062,9 @@ static struct omap_clk omap44xx_clks[] = {
3028 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 3062 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3029 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 3063 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3030 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 3064 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3065 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3031 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 3066 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3067 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3032 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 3068 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3033 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 3069 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3034 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), 3070 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
@@ -3208,6 +3244,9 @@ int __init omap4xxx_clk_init(void)
3208 if (cpu_is_omap44xx()) { 3244 if (cpu_is_omap44xx()) {
3209 cpu_mask = RATE_IN_4430; 3245 cpu_mask = RATE_IN_4430;
3210 cpu_clkflg = CK_443X; 3246 cpu_clkflg = CK_443X;
3247 } else if (cpu_is_omap446x()) {
3248 cpu_mask = RATE_IN_4460;
3249 cpu_clkflg = CK_446X;
3211 } 3250 }
3212 3251
3213 clk_init(&omap2_clk_functions); 3252 clk_init(&omap2_clk_functions);
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 0e77945d26ec..65597a745638 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -101,6 +101,10 @@
101#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 101#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
102#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) 102#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
103 103
104/* Used by CM_L4CFG_CLKSTCTRL */
105#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
106#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
107
104/* Used by CM_CEFUSE_CLKSTCTRL */ 108/* Used by CM_CEFUSE_CLKSTCTRL */
105#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
106#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
@@ -413,6 +417,10 @@
413#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 417#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
414#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) 418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
415 419
420/* Used by CM_WKUP_CLKSTCTRL */
421#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
422#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
423
416/* 424/*
417 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, 425 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
418 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 426 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
@@ -444,6 +452,10 @@
444#define OMAP4430_CLKSEL_60M_SHIFT 24 452#define OMAP4430_CLKSEL_60M_SHIFT 24
445#define OMAP4430_CLKSEL_60M_MASK (1 << 24) 453#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
446 454
455/* Used by CM_MPU_MPU_CLKCTRL */
456#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
457#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
458
447/* Used by CM1_ABE_AESS_CLKCTRL */ 459/* Used by CM1_ABE_AESS_CLKCTRL */
448#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 460#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
449#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 461#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
@@ -460,6 +472,10 @@
460#define OMAP4430_CLKSEL_DIV_SHIFT 24 472#define OMAP4430_CLKSEL_DIV_SHIFT 24
461#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) 473#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
462 474
475/* Used by CM_MPU_MPU_CLKCTRL */
476#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
477#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
478
463/* Used by CM_CAM_FDIF_CLKCTRL */ 479/* Used by CM_CAM_FDIF_CLKCTRL */
464#define OMAP4430_CLKSEL_FCLK_SHIFT 24 480#define OMAP4430_CLKSEL_FCLK_SHIFT 24
465#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) 481#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
@@ -555,6 +571,14 @@
555#define OMAP4430_D2D_STATDEP_SHIFT 18 571#define OMAP4430_D2D_STATDEP_SHIFT 18
556#define OMAP4430_D2D_STATDEP_MASK (1 << 18) 572#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
557 573
574/* Used by CM_CLKSEL_DPLL_MPU */
575#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
576#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
577
578/* Used by CM_CLKSEL_DPLL_MPU */
579#define OMAP4460_DCC_EN_SHIFT 22
580#define OMAP4460_DCC_EN_MASK (1 << 22)
581
558/* 582/*
559 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 583 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
560 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, 584 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
@@ -564,6 +588,10 @@
564#define OMAP4430_DELTAMSTEP_SHIFT 0 588#define OMAP4430_DELTAMSTEP_SHIFT 0
565#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 589#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
566 590
591/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
592#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
593#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
594
567/* Used by CM_DLL_CTRL */ 595/* Used by CM_DLL_CTRL */
568#define OMAP4430_DLL_OVERRIDE_SHIFT 0 596#define OMAP4430_DLL_OVERRIDE_SHIFT 0
569#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) 597#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
@@ -1106,6 +1134,10 @@
1106#define OMAP4430_MODULEMODE_SHIFT 0 1134#define OMAP4430_MODULEMODE_SHIFT 0
1107#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 1135#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1108 1136
1137/* Used by CM_L4CFG_DYNAMICDEP */
1138#define OMAP4460_MPU_DYNDEP_SHIFT 19
1139#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
1140
1109/* Used by CM_DSS_DSS_CLKCTRL */ 1141/* Used by CM_DSS_DSS_CLKCTRL */
1110#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1142#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1111#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1143#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
@@ -1198,6 +1230,10 @@
1198#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1230#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1199#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1231#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1200 1232
1233/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1234#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
1235#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
1236
1201/* Used by CM_DSS_DSS_CLKCTRL */ 1237/* Used by CM_DSS_DSS_CLKCTRL */
1202#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1238#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1203#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) 1239#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2537090aa33a..37efb8696927 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -31,7 +31,7 @@
31static struct omap_chip_id omap_chip; 31static struct omap_chip_id omap_chip;
32static unsigned int omap_revision; 32static unsigned int omap_revision;
33 33
34u32 omap3_features; 34u32 omap_features;
35 35
36unsigned int omap_rev(void) 36unsigned int omap_rev(void)
37{ 37{
@@ -183,14 +183,14 @@ static void __init omap24xx_check_revision(void)
183#define OMAP3_CHECK_FEATURE(status,feat) \ 183#define OMAP3_CHECK_FEATURE(status,feat) \
184 if (((status & OMAP3_ ##feat## _MASK) \ 184 if (((status & OMAP3_ ##feat## _MASK) \
185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
186 omap3_features |= OMAP3_HAS_ ##feat; \ 186 omap_features |= OMAP3_HAS_ ##feat; \
187 } 187 }
188 188
189static void __init omap3_check_features(void) 189static void __init omap3_check_features(void)
190{ 190{
191 u32 status; 191 u32 status;
192 192
193 omap3_features = 0; 193 omap_features = 0;
194 194
195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
196 196
@@ -200,11 +200,11 @@ static void __init omap3_check_features(void)
200 OMAP3_CHECK_FEATURE(status, NEON); 200 OMAP3_CHECK_FEATURE(status, NEON);
201 OMAP3_CHECK_FEATURE(status, ISP); 201 OMAP3_CHECK_FEATURE(status, ISP);
202 if (cpu_is_omap3630()) 202 if (cpu_is_omap3630())
203 omap3_features |= OMAP3_HAS_192MHZ_CLK; 203 omap_features |= OMAP3_HAS_192MHZ_CLK;
204 if (!cpu_is_omap3505() && !cpu_is_omap3517()) 204 if (!cpu_is_omap3505() && !cpu_is_omap3517())
205 omap3_features |= OMAP3_HAS_IO_WAKEUP; 205 omap_features |= OMAP3_HAS_IO_WAKEUP;
206 206
207 omap3_features |= OMAP3_HAS_SDRC; 207 omap_features |= OMAP3_HAS_SDRC;
208 208
209 /* 209 /*
210 * TODO: Get additional info (where applicable) 210 * TODO: Get additional info (where applicable)
@@ -212,9 +212,34 @@ static void __init omap3_check_features(void)
212 */ 212 */
213} 213}
214 214
215static void __init omap4_check_features(void)
216{
217 u32 si_type;
218
219 if (cpu_is_omap443x())
220 omap_features |= OMAP4_HAS_MPU_1GHZ;
221
222
223 if (cpu_is_omap446x()) {
224 si_type =
225 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
226 switch ((si_type & (3 << 16)) >> 16) {
227 case 2:
228 /* High performance device */
229 omap_features |= OMAP4_HAS_MPU_1_5GHZ;
230 break;
231 case 1:
232 default:
233 /* Standard device */
234 omap_features |= OMAP4_HAS_MPU_1_2GHZ;
235 break;
236 }
237 }
238}
239
215static void __init ti816x_check_features(void) 240static void __init ti816x_check_features(void)
216{ 241{
217 omap3_features = OMAP3_HAS_NEON; 242 omap_features = OMAP3_HAS_NEON;
218} 243}
219 244
220static void __init omap3_check_revision(void) 245static void __init omap3_check_revision(void)
@@ -344,10 +369,10 @@ static void __init omap4_check_revision(void)
344 rev = (idcode >> 28) & 0xf; 369 rev = (idcode >> 28) & 0xf;
345 370
346 /* 371 /*
347 * Few initial ES2.0 samples IDCODE is same as ES1.0 372 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
348 * Use ARM register to detect the correct ES version 373 * Use ARM register to detect the correct ES version
349 */ 374 */
350 if (!rev) { 375 if (!rev && (hawkeye != 0xb94e)) {
351 idcode = read_cpuid(CPUID_ID); 376 idcode = read_cpuid(CPUID_ID);
352 rev = (idcode & 0xf) - 1; 377 rev = (idcode & 0xf) - 1;
353 } 378 }
@@ -377,6 +402,15 @@ static void __init omap4_check_revision(void)
377 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; 402 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
378 } 403 }
379 break; 404 break;
405 case 0xb94e:
406 switch (rev) {
407 case 0:
408 default:
409 omap_revision = OMAP4460_REV_ES1_0;
410 omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
411 break;
412 }
413 break;
380 default: 414 default:
381 /* Unknown default to latest silicon rev as default */ 415 /* Unknown default to latest silicon rev as default */
382 omap_revision = OMAP4430_REV_ES2_2; 416 omap_revision = OMAP4430_REV_ES2_2;
@@ -518,6 +552,7 @@ void __init omap2_check_revision(void)
518 return; 552 return;
519 } else if (cpu_is_omap44xx()) { 553 } else if (cpu_is_omap44xx()) {
520 omap4_check_revision(); 554 omap4_check_revision();
555 omap4_check_features();
521 return; 556 return;
522 } else { 557 } else {
523 pr_err("OMAP revision unknown, please fix!\n"); 558 pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 6d2776f6fc08..3cb247bebdaa 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -283,6 +283,14 @@
283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) 284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
285 285
286/* Used by PRM_DEVICE_OFF_CTRL */
287#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
288#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
289
290/* Used by PRM_DEVICE_OFF_CTRL */
291#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
292#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
293
286/* Used by RM_MPU_RSTST */ 294/* Used by RM_MPU_RSTST */
287#define OMAP4430_EMULATION_RST_SHIFT 0 295#define OMAP4430_EMULATION_RST_SHIFT 0
288#define OMAP4430_EMULATION_RST_MASK (1 << 0) 296#define OMAP4430_EMULATION_RST_MASK (1 << 0)
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
new file mode 100644
index 000000000000..7af7fc05d565
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile
@@ -0,0 +1,7 @@
1obj-y := timer.o
2obj-y += irq.o
3obj-y += clock.o
4obj-y += rstc.o
5obj-y += prima2.o
6obj-$(CONFIG_DEBUG_LL) += lluart.o
7obj-$(CONFIG_CACHE_L2X0) += l2x0.o
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
new file mode 100644
index 000000000000..d023db3ae4ff
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -0,0 +1,3 @@
1zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
new file mode 100644
index 000000000000..f9a2aaf63f71
--- /dev/null
+++ b/arch/arm/mach-prima2/clock.c
@@ -0,0 +1,509 @@
1/*
2 * Clock tree for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/err.h>
12#include <linux/errno.h>
13#include <linux/io.h>
14#include <linux/clkdev.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <asm/mach/map.h>
20#include <mach/map.h>
21
22#define SIRFSOC_CLKC_CLK_EN0 0x0000
23#define SIRFSOC_CLKC_CLK_EN1 0x0004
24#define SIRFSOC_CLKC_REF_CFG 0x0014
25#define SIRFSOC_CLKC_CPU_CFG 0x0018
26#define SIRFSOC_CLKC_MEM_CFG 0x001c
27#define SIRFSOC_CLKC_SYS_CFG 0x0020
28#define SIRFSOC_CLKC_IO_CFG 0x0024
29#define SIRFSOC_CLKC_DSP_CFG 0x0028
30#define SIRFSOC_CLKC_GFX_CFG 0x002c
31#define SIRFSOC_CLKC_MM_CFG 0x0030
32#define SIRFSOC_LKC_LCD_CFG 0x0034
33#define SIRFSOC_CLKC_MMC_CFG 0x0038
34#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
35#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
36#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
37#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
38#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
39#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
40#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
41#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
42#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
43
44#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
45
46#define KHZ 1000
47#define MHZ (KHZ * KHZ)
48
49struct clk_ops {
50 unsigned long (*get_rate)(struct clk *clk);
51 long (*round_rate)(struct clk *clk, unsigned long rate);
52 int (*set_rate)(struct clk *clk, unsigned long rate);
53 int (*enable)(struct clk *clk);
54 int (*disable)(struct clk *clk);
55 struct clk *(*get_parent)(struct clk *clk);
56 int (*set_parent)(struct clk *clk, struct clk *parent);
57};
58
59struct clk {
60 struct clk *parent; /* parent clk */
61 unsigned long rate; /* clock rate in Hz */
62 signed char usage; /* clock enable count */
63 signed char enable_bit; /* enable bit: 0 ~ 63 */
64 unsigned short regofs; /* register offset */
65 struct clk_ops *ops; /* clock operation */
66};
67
68static DEFINE_SPINLOCK(clocks_lock);
69
70static inline unsigned long clkc_readl(unsigned reg)
71{
72 return readl(SIRFSOC_CLOCK_VA_BASE + reg);
73}
74
75static inline void clkc_writel(u32 val, unsigned reg)
76{
77 writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
78}
79
80/*
81 * osc_rtc - real time oscillator - 32.768KHz
82 * osc_sys - high speed oscillator - 26MHz
83 */
84
85static struct clk clk_rtc = {
86 .rate = 32768,
87};
88
89static struct clk clk_osc = {
90 .rate = 26 * MHZ,
91};
92
93/*
94 * std pll
95 */
96static unsigned long std_pll_get_rate(struct clk *clk)
97{
98 unsigned long fin = clk_get_rate(clk->parent);
99 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
100 SIRFSOC_CLKC_PLL1_CFG0;
101
102 if (clkc_readl(regcfg2) & BIT(2)) {
103 /* pll bypass mode */
104 clk->rate = fin;
105 } else {
106 /* fout = fin * nf / nr / od */
107 u32 cfg0 = clkc_readl(clk->regofs);
108 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
109 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
110 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
111 WARN_ON(fin % MHZ);
112 clk->rate = fin / MHZ * nf / nr / od * MHZ;
113 }
114
115 return clk->rate;
116}
117
118static int std_pll_set_rate(struct clk *clk, unsigned long rate)
119{
120 unsigned long fin, nf, nr, od, reg;
121
122 /*
123 * fout = fin * nf / (nr * od);
124 * set od = 1, nr = fin/MHz, so fout = nf * MHz
125 */
126
127 nf = rate / MHZ;
128 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
129 return -EINVAL;
130
131 fin = clk_get_rate(clk->parent);
132 BUG_ON(fin < MHZ);
133
134 nr = fin / MHZ;
135 BUG_ON((fin % MHZ) || nr > BIT(6));
136
137 od = 1;
138
139 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
140 clkc_writel(reg, clk->regofs);
141
142 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
143 clkc_writel((nf >> 1) - 1, reg);
144
145 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
146 while (!(clkc_readl(reg) & BIT(6)))
147 cpu_relax();
148
149 clk->rate = 0; /* set to zero will force recalculation */
150 return 0;
151}
152
153static struct clk_ops std_pll_ops = {
154 .get_rate = std_pll_get_rate,
155 .set_rate = std_pll_set_rate,
156};
157
158static struct clk clk_pll1 = {
159 .parent = &clk_osc,
160 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
161 .ops = &std_pll_ops,
162};
163
164static struct clk clk_pll2 = {
165 .parent = &clk_osc,
166 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
167 .ops = &std_pll_ops,
168};
169
170static struct clk clk_pll3 = {
171 .parent = &clk_osc,
172 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
173 .ops = &std_pll_ops,
174};
175
176/*
177 * clock domains - cpu, mem, sys/io
178 */
179
180static struct clk clk_mem;
181
182static struct clk *dmn_get_parent(struct clk *clk)
183{
184 struct clk *clks[] = {
185 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
186 };
187 u32 cfg = clkc_readl(clk->regofs);
188 WARN_ON((cfg & (BIT(3) - 1)) > 4);
189 return clks[cfg & (BIT(3) - 1)];
190}
191
192static int dmn_set_parent(struct clk *clk, struct clk *parent)
193{
194 const struct clk *clks[] = {
195 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
196 };
197 u32 cfg = clkc_readl(clk->regofs);
198 int i;
199 for (i = 0; i < ARRAY_SIZE(clks); i++) {
200 if (clks[i] == parent) {
201 cfg &= ~(BIT(3) - 1);
202 clkc_writel(cfg | i, clk->regofs);
203 /* BIT(3) - switching status: 1 - busy, 0 - done */
204 while (clkc_readl(clk->regofs) & BIT(3))
205 cpu_relax();
206 return 0;
207 }
208 }
209 return -EINVAL;
210}
211
212static unsigned long dmn_get_rate(struct clk *clk)
213{
214 unsigned long fin = clk_get_rate(clk->parent);
215 u32 cfg = clkc_readl(clk->regofs);
216 if (cfg & BIT(24)) {
217 /* fcd bypass mode */
218 clk->rate = fin;
219 } else {
220 /*
221 * wait count: bit[19:16], hold count: bit[23:20]
222 */
223 u32 wait = (cfg >> 16) & (BIT(4) - 1);
224 u32 hold = (cfg >> 20) & (BIT(4) - 1);
225
226 clk->rate = fin / (wait + hold + 2);
227 }
228
229 return clk->rate;
230}
231
232static int dmn_set_rate(struct clk *clk, unsigned long rate)
233{
234 unsigned long fin;
235 unsigned ratio, wait, hold, reg;
236 unsigned bits = (clk == &clk_mem) ? 3 : 4;
237
238 fin = clk_get_rate(clk->parent);
239 ratio = fin / rate;
240
241 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
242 return -EINVAL;
243
244 WARN_ON(fin % rate);
245
246 wait = (ratio >> 1) - 1;
247 hold = ratio - wait - 2;
248
249 reg = clkc_readl(clk->regofs);
250 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
251 reg |= (wait << 16) | (hold << 20) | BIT(25);
252 clkc_writel(reg, clk->regofs);
253
254 /* waiting FCD been effective */
255 while (clkc_readl(clk->regofs) & BIT(25))
256 cpu_relax();
257
258 clk->rate = 0; /* set to zero will force recalculation */
259
260 return 0;
261}
262
263/*
264 * cpu clock has no FCD register in Prima2, can only change pll
265 */
266static int cpu_set_rate(struct clk *clk, unsigned long rate)
267{
268 int ret1, ret2;
269 struct clk *cur_parent, *tmp_parent;
270
271 cur_parent = dmn_get_parent(clk);
272 BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
273
274 /* switch to tmp pll before setting parent clock's rate */
275 tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
276 ret1 = dmn_set_parent(clk, tmp_parent);
277 BUG_ON(ret1);
278
279 ret2 = clk_set_rate(cur_parent, rate);
280
281 ret1 = dmn_set_parent(clk, cur_parent);
282
283 clk->rate = 0; /* set to zero will force recalculation */
284
285 return ret2 ? ret2 : ret1;
286}
287
288static struct clk_ops cpu_ops = {
289 .get_parent = dmn_get_parent,
290 .set_parent = dmn_set_parent,
291 .set_rate = cpu_set_rate,
292};
293
294static struct clk clk_cpu = {
295 .parent = &clk_pll1,
296 .regofs = SIRFSOC_CLKC_CPU_CFG,
297 .ops = &cpu_ops,
298};
299
300
301static struct clk_ops msi_ops = {
302 .set_rate = dmn_set_rate,
303 .get_rate = dmn_get_rate,
304 .set_parent = dmn_set_parent,
305 .get_parent = dmn_get_parent,
306};
307
308static struct clk clk_mem = {
309 .parent = &clk_pll2,
310 .regofs = SIRFSOC_CLKC_MEM_CFG,
311 .ops = &msi_ops,
312};
313
314static struct clk clk_sys = {
315 .parent = &clk_pll3,
316 .regofs = SIRFSOC_CLKC_SYS_CFG,
317 .ops = &msi_ops,
318};
319
320static struct clk clk_io = {
321 .parent = &clk_pll3,
322 .regofs = SIRFSOC_CLKC_IO_CFG,
323 .ops = &msi_ops,
324};
325
326/*
327 * on-chip clock sets
328 */
329static struct clk_lookup onchip_clks[] = {
330 {
331 .dev_id = "rtc",
332 .clk = &clk_rtc,
333 }, {
334 .dev_id = "osc",
335 .clk = &clk_osc,
336 }, {
337 .dev_id = "pll1",
338 .clk = &clk_pll1,
339 }, {
340 .dev_id = "pll2",
341 .clk = &clk_pll2,
342 }, {
343 .dev_id = "pll3",
344 .clk = &clk_pll3,
345 }, {
346 .dev_id = "cpu",
347 .clk = &clk_cpu,
348 }, {
349 .dev_id = "mem",
350 .clk = &clk_mem,
351 }, {
352 .dev_id = "sys",
353 .clk = &clk_sys,
354 }, {
355 .dev_id = "io",
356 .clk = &clk_io,
357 },
358};
359
360int clk_enable(struct clk *clk)
361{
362 unsigned long flags;
363
364 if (unlikely(IS_ERR_OR_NULL(clk)))
365 return -EINVAL;
366
367 if (clk->parent)
368 clk_enable(clk->parent);
369
370 spin_lock_irqsave(&clocks_lock, flags);
371 if (!clk->usage++ && clk->ops && clk->ops->enable)
372 clk->ops->enable(clk);
373 spin_unlock_irqrestore(&clocks_lock, flags);
374 return 0;
375}
376EXPORT_SYMBOL(clk_enable);
377
378void clk_disable(struct clk *clk)
379{
380 unsigned long flags;
381
382 if (unlikely(IS_ERR_OR_NULL(clk)))
383 return;
384
385 WARN_ON(!clk->usage);
386
387 spin_lock_irqsave(&clocks_lock, flags);
388 if (--clk->usage == 0 && clk->ops && clk->ops->disable)
389 clk->ops->disable(clk);
390 spin_unlock_irqrestore(&clocks_lock, flags);
391
392 if (clk->parent)
393 clk_disable(clk->parent);
394}
395EXPORT_SYMBOL(clk_disable);
396
397unsigned long clk_get_rate(struct clk *clk)
398{
399 if (unlikely(IS_ERR_OR_NULL(clk)))
400 return 0;
401
402 if (clk->rate)
403 return clk->rate;
404
405 if (clk->ops && clk->ops->get_rate)
406 return clk->ops->get_rate(clk);
407
408 return clk_get_rate(clk->parent);
409}
410EXPORT_SYMBOL(clk_get_rate);
411
412long clk_round_rate(struct clk *clk, unsigned long rate)
413{
414 if (unlikely(IS_ERR_OR_NULL(clk)))
415 return 0;
416
417 if (clk->ops && clk->ops->round_rate)
418 return clk->ops->round_rate(clk, rate);
419
420 return 0;
421}
422EXPORT_SYMBOL(clk_round_rate);
423
424int clk_set_rate(struct clk *clk, unsigned long rate)
425{
426 if (unlikely(IS_ERR_OR_NULL(clk)))
427 return -EINVAL;
428
429 if (!clk->ops || !clk->ops->set_rate)
430 return -EINVAL;
431
432 return clk->ops->set_rate(clk, rate);
433}
434EXPORT_SYMBOL(clk_set_rate);
435
436int clk_set_parent(struct clk *clk, struct clk *parent)
437{
438 int ret;
439 unsigned long flags;
440
441 if (unlikely(IS_ERR_OR_NULL(clk)))
442 return -EINVAL;
443
444 if (!clk->ops || !clk->ops->set_parent)
445 return -EINVAL;
446
447 spin_lock_irqsave(&clocks_lock, flags);
448 ret = clk->ops->set_parent(clk, parent);
449 if (!ret) {
450 parent->usage += clk->usage;
451 clk->parent->usage -= clk->usage;
452 BUG_ON(clk->parent->usage < 0);
453 clk->parent = parent;
454 }
455 spin_unlock_irqrestore(&clocks_lock, flags);
456 return ret;
457}
458EXPORT_SYMBOL(clk_set_parent);
459
460struct clk *clk_get_parent(struct clk *clk)
461{
462 unsigned long flags;
463
464 if (unlikely(IS_ERR_OR_NULL(clk)))
465 return NULL;
466
467 if (!clk->ops || !clk->ops->get_parent)
468 return clk->parent;
469
470 spin_lock_irqsave(&clocks_lock, flags);
471 clk->parent = clk->ops->get_parent(clk);
472 spin_unlock_irqrestore(&clocks_lock, flags);
473 return clk->parent;
474}
475EXPORT_SYMBOL(clk_get_parent);
476
477static void __init sirfsoc_clk_init(void)
478{
479 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
480}
481
482static struct of_device_id clkc_ids[] = {
483 { .compatible = "sirf,prima2-clkc" },
484};
485
486void __init sirfsoc_of_clk_init(void)
487{
488 struct device_node *np;
489 struct resource res;
490 struct map_desc sirfsoc_clkc_iodesc = {
491 .virtual = SIRFSOC_CLOCK_VA_BASE,
492 .type = MT_DEVICE,
493 };
494
495 np = of_find_matching_node(NULL, clkc_ids);
496 if (!np)
497 panic("unable to find compatible clkc node in dtb\n");
498
499 if (of_address_to_resource(np, 0, &res))
500 panic("unable to find clkc range in dtb");
501 of_node_put(np);
502
503 sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
504 sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
505
506 iotable_init(&sirfsoc_clkc_iodesc, 1);
507
508 sirfsoc_clk_init();
509}
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
new file mode 100644
index 000000000000..83e5d2128118
--- /dev/null
+++ b/arch/arm/mach-prima2/common.h
@@ -0,0 +1,26 @@
1/*
2 * This file contains common function prototypes to avoid externs in the c files.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_COMMON_H__
10#define __MACH_PRIMA2_COMMON_H__
11
12#include <linux/init.h>
13#include <asm/mach/time.h>
14
15extern struct sys_timer sirfsoc_timer;
16
17extern void __init sirfsoc_of_irq_init(void);
18extern void __init sirfsoc_of_clk_init(void);
19
20#ifndef CONFIG_DEBUG_LL
21static inline void sirfsoc_map_lluart(void) {}
22#else
23extern void __init sirfsoc_map_lluart(void);
24#endif
25
26#endif
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
new file mode 100644
index 000000000000..66932518b1b7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/clkdev.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-prima2/include/mach/clkdev.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_CLKDEV_H
10#define __MACH_CLKDEV_H
11
12#define __clk_get(clk) ({ 1; })
13#define __clk_put(clk) do { } while (0)
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
new file mode 100644
index 000000000000..bf75106333ff
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/debug-macro.S
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/debug-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10#include <mach/uart.h>
11
12 .macro addruart, rp, rv
13 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
14 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
15 .endm
16
17 .macro senduart,rd,rx
18 str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
19 .endm
20
21 .macro busyuart,rd,rx
22 .endm
23
24 .macro waituart,rd,rx
251001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
26 tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
27 beq 1001b
28 .endm
29
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1c8a50f102a7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/entry-macro.S
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/entry-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10
11#define SIRFSOC_INT_ID 0x38
12
13 .macro get_irqnr_preamble, base, tmp
14 ldr \base, =sirfsoc_intc_base
15 ldr \base, [\base]
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq
20 cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f
21 movges \irqnr, #0
22 .endm
23
24 .macro disable_fiq
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
new file mode 100644
index 000000000000..105b96964f25
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/hardware.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-prima2/include/mach/hardware.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_HARDWARE_H__
10#define __MACH_HARDWARE_H__
11
12#include <asm/sizes.h>
13#include <mach/map.h>
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/io.h b/arch/arm/mach-prima2/include/mach/io.h
new file mode 100644
index 000000000000..6c31e9ec279e
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/io.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/mach-prima2/include/mach/io.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_IO_H
10#define __MACH_PRIMA2_IO_H
11
12#define IO_SPACE_LIMIT ((resource_size_t)0)
13
14#define __mem_pci(a) (a)
15
16#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
new file mode 100644
index 000000000000..bb354f952fd6
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -0,0 +1,17 @@
1/*
2 * arch/arm/mach-prima2/include/mach/irqs.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_IRQS_H
10#define __ASM_ARCH_IRQS_H
11
12#define SIRFSOC_INTENAL_IRQ_START 0
13#define SIRFSOC_INTENAL_IRQ_END 59
14
15#define NR_IRQS 220
16
17#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
new file mode 100644
index 000000000000..66b1ae2e553f
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/map.h
@@ -0,0 +1,16 @@
1/*
2 * memory & I/O static mapping definitions for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_MAP_H__
10#define __MACH_PRIMA2_MAP_H__
11
12#include <mach/vmalloc.h>
13
14#define SIRFSOC_VA(x) (VMALLOC_END + ((x) & 0x00FFF000))
15
16#endif
diff --git a/arch/arm/mach-prima2/include/mach/memory.h b/arch/arm/mach-prima2/include/mach/memory.h
new file mode 100644
index 000000000000..368cd5a0601a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/memory.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/mach-prima2/include/mach/memory.h
3 *
4 * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12#define PLAT_PHYS_OFFSET UL(0x00000000)
13
14/*
15 * Restrict DMA-able region to workaround silicon limitation.
16 * The limitation restricts buffers available for DMA to SD/MMC
17 * hardware to be below 256MB
18 */
19#define ARM_DMA_ZONE_SIZE (SZ_256M)
20
21#endif
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
new file mode 100644
index 000000000000..0dbd257ad16d
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/system.h
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/system.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_SYSTEM_H__
10#define __MACH_SYSTEM_H__
11
12#include <linux/bitops.h>
13#include <mach/hardware.h>
14
15#define SIRFSOC_SYS_RST_BIT BIT(31)
16
17extern void __iomem *sirfsoc_rstc_base;
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24static inline void arch_reset(char mode, const char *cmd)
25{
26 writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
27}
28
29#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
new file mode 100644
index 000000000000..d6f98a75e562
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/timex.h
@@ -0,0 +1,14 @@
1/*
2 * arch/arm/mach-prima2/include/mach/timex.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_TIMEX_H__
10#define __MACH_TIMEX_H__
11
12#define CLOCK_TICK_RATE 1000000
13
14#endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
new file mode 100644
index 000000000000..c98b4d5ac24a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/mach-prima2/include/mach/uart.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
10#define __MACH_PRIMA2_SIRFSOC_UART_H
11
12/* UART-1: used as serial debug port */
13#define SIRFSOC_UART1_PA_BASE 0xb0060000
14#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
15#define SIRFSOC_UART1_SIZE SZ_4K
16
17#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
18#define SIRFSOC_UART_TXFIFO_DATA 0x0118
19
20#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
21#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
22
23#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
new file mode 100644
index 000000000000..83125c6a30b3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-prima2/include/mach/uncompress.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_UNCOMPRESS_H
10#define __ASM_ARCH_UNCOMPRESS_H
11
12#include <linux/io.h>
13#include <mach/hardware.h>
14#include <mach/uart.h>
15
16void arch_decomp_setup(void)
17{
18}
19
20#define arch_decomp_wdog()
21
22static __inline__ void putc(char c)
23{
24 /*
25 * during kernel decompression, all mappings are flat:
26 * virt_addr == phys_addr
27 */
28 while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
29 & SIRFSOC_UART1_TXFIFO_FULL)
30 barrier();
31
32 __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
33}
34
35static inline void flush(void)
36{
37}
38
39#endif
40
diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
new file mode 100644
index 000000000000..c9f90fec78e3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/ach-prima2/include/mach/vmalloc.h
3 *
4 * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_VMALLOC_H
10#define __MACH_VMALLOC_H
11
12#include <linux/const.h>
13
14#define VMALLOC_END _AC(0xFEC00000, UL)
15
16#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
new file mode 100644
index 000000000000..c3404cbb6ff7
--- /dev/null
+++ b/arch/arm/mach-prima2/irq.c
@@ -0,0 +1,71 @@
1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <mach/hardware.h>
13#include <asm/mach/irq.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#define SIRFSOC_INT_RISC_MASK0 0x0018
18#define SIRFSOC_INT_RISC_MASK1 0x001C
19#define SIRFSOC_INT_RISC_LEVEL0 0x0020
20#define SIRFSOC_INT_RISC_LEVEL1 0x0024
21
22void __iomem *sirfsoc_intc_base;
23
24static __init void
25sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
26{
27 struct irq_chip_generic *gc;
28 struct irq_chip_type *ct;
29
30 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
31 ct = gc->chip_types;
32
33 ct->chip.irq_mask = irq_gc_mask_clr_bit;
34 ct->chip.irq_unmask = irq_gc_mask_set_bit;
35 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
36
37 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
38}
39
40static __init void sirfsoc_irq_init(void)
41{
42 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
43 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
44
45 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
46 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
47
48 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
49 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
50}
51
52static struct of_device_id intc_ids[] = {
53 { .compatible = "sirf,prima2-intc" },
54};
55
56void __init sirfsoc_of_irq_init(void)
57{
58 struct device_node *np;
59
60 np = of_find_matching_node(NULL, intc_ids);
61 if (!np)
62 panic("unable to find compatible intc node in dtb\n");
63
64 sirfsoc_intc_base = of_iomap(np, 0);
65 if (!sirfsoc_intc_base)
66 panic("unable to map intc cpu registers\n");
67
68 of_node_put(np);
69
70 sirfsoc_irq_init();
71}
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
new file mode 100644
index 000000000000..9cda2057bcfb
--- /dev/null
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -0,0 +1,59 @@
1/*
2 * l2 cache initialization for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <asm/hardware/cache-l2x0.h>
16#include <mach/memory.h>
17
18#define L2X0_ADDR_FILTERING_START 0xC00
19#define L2X0_ADDR_FILTERING_END 0xC04
20
21static struct of_device_id l2x_ids[] = {
22 { .compatible = "arm,pl310-cache" },
23};
24
25static int __init sirfsoc_of_l2x_init(void)
26{
27 struct device_node *np;
28 void __iomem *sirfsoc_l2x_base;
29
30 np = of_find_matching_node(NULL, l2x_ids);
31 if (!np)
32 panic("unable to find compatible l2x node in dtb\n");
33
34 sirfsoc_l2x_base = of_iomap(np, 0);
35 if (!sirfsoc_l2x_base)
36 panic("unable to map l2x cpu registers\n");
37
38 of_node_put(np);
39
40 if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) {
41 /*
42 * set the physical memory windows L2 cache will cover
43 */
44 writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024,
45 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
46 writel_relaxed(PLAT_PHYS_OFFSET | 0x1,
47 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
48
49 writel_relaxed(0,
50 sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL);
51 writel_relaxed(0,
52 sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL);
53 }
54 l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000,
55 0x00000000);
56
57 return 0;
58}
59early_initcall(sirfsoc_of_l2x_init);
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
new file mode 100644
index 000000000000..a89f9b3c8cc5
--- /dev/null
+++ b/arch/arm/mach-prima2/lluart.c
@@ -0,0 +1,25 @@
1/*
2 * Static memory mapping for DEBUG_LL
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <asm/page.h>
11#include <asm/mach/map.h>
12#include <mach/map.h>
13#include <mach/uart.h>
14
15void __init sirfsoc_map_lluart(void)
16{
17 struct map_desc sirfsoc_lluart_map = {
18 .virtual = SIRFSOC_UART1_VA_BASE,
19 .pfn = __phys_to_pfn(SIRFSOC_UART1_PA_BASE),
20 .length = SIRFSOC_UART1_SIZE,
21 .type = MT_DEVICE,
22 };
23
24 iotable_init(&sirfsoc_lluart_map, 1);
25}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
new file mode 100644
index 000000000000..f57124bdd143
--- /dev/null
+++ b/arch/arm/mach-prima2/prima2.c
@@ -0,0 +1,41 @@
1/*
2 * Defines machines for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <asm/mach-types.h>
12#include <asm/mach/arch.h>
13#include <linux/of.h>
14#include <linux/of_platform.h>
15#include "common.h"
16
17static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
18 { .compatible = "simple-bus", },
19 {},
20};
21
22void __init sirfsoc_mach_init(void)
23{
24 of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
25}
26
27static const char *prima2cb_dt_match[] __initdata = {
28 "sirf,prima2-cb",
29 NULL
30};
31
32MACHINE_START(PRIMA2_EVB, "prima2cb")
33 /* Maintainer: Barry Song <baohua.song@csr.com> */
34 .boot_params = 0x00000100,
35 .init_early = sirfsoc_of_clk_init,
36 .map_io = sirfsoc_map_lluart,
37 .init_irq = sirfsoc_of_irq_init,
38 .timer = &sirfsoc_timer,
39 .init_machine = sirfsoc_mach_init,
40 .dt_compat = prima2cb_dt_match,
41MACHINE_END
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
new file mode 100644
index 000000000000..d074786e83d4
--- /dev/null
+++ b/arch/arm/mach-prima2/rstc.c
@@ -0,0 +1,69 @@
1/*
2 * reset controller for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/mutex.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17void __iomem *sirfsoc_rstc_base;
18static DEFINE_MUTEX(rstc_lock);
19
20static struct of_device_id rstc_ids[] = {
21 { .compatible = "sirf,prima2-rstc" },
22};
23
24static int __init sirfsoc_of_rstc_init(void)
25{
26 struct device_node *np;
27
28 np = of_find_matching_node(NULL, rstc_ids);
29 if (!np)
30 panic("unable to find compatible rstc node in dtb\n");
31
32 sirfsoc_rstc_base = of_iomap(np, 0);
33 if (!sirfsoc_rstc_base)
34 panic("unable to map rstc cpu registers\n");
35
36 of_node_put(np);
37
38 return 0;
39}
40early_initcall(sirfsoc_of_rstc_init);
41
42int sirfsoc_reset_device(struct device *dev)
43{
44 const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
45 unsigned int reset_bit;
46
47 if (!prop)
48 return -ENODEV;
49
50 reset_bit = be32_to_cpup(prop);
51
52 mutex_lock(&rstc_lock);
53
54 /*
55 * Writing 1 to this bit resets corresponding block. Writing 0 to this
56 * bit de-asserts reset signal of the corresponding block.
57 * datasheet doesn't require explicit delay between the set and clear
58 * of reset bit. it could be shorter if tests pass.
59 */
60 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
61 sirfsoc_rstc_base + (reset_bit / 32) * 4);
62 msleep(10);
63 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
64 sirfsoc_rstc_base + (reset_bit / 32) * 4);
65
66 mutex_unlock(&rstc_lock);
67
68 return 0;
69}
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
new file mode 100644
index 000000000000..44027f34a88a
--- /dev/null
+++ b/arch/arm/mach-prima2/timer.c
@@ -0,0 +1,217 @@
1/*
2 * System timer for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <mach/map.h>
21#include <asm/mach/time.h>
22
23#define SIRFSOC_TIMER_COUNTER_LO 0x0000
24#define SIRFSOC_TIMER_COUNTER_HI 0x0004
25#define SIRFSOC_TIMER_MATCH_0 0x0008
26#define SIRFSOC_TIMER_MATCH_1 0x000C
27#define SIRFSOC_TIMER_MATCH_2 0x0010
28#define SIRFSOC_TIMER_MATCH_3 0x0014
29#define SIRFSOC_TIMER_MATCH_4 0x0018
30#define SIRFSOC_TIMER_MATCH_5 0x001C
31#define SIRFSOC_TIMER_STATUS 0x0020
32#define SIRFSOC_TIMER_INT_EN 0x0024
33#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
34#define SIRFSOC_TIMER_DIV 0x002C
35#define SIRFSOC_TIMER_LATCH 0x0030
36#define SIRFSOC_TIMER_LATCHED_LO 0x0034
37#define SIRFSOC_TIMER_LATCHED_HI 0x0038
38
39#define SIRFSOC_TIMER_WDT_INDEX 5
40
41#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
42
43static void __iomem *sirfsoc_timer_base;
44static void __init sirfsoc_of_timer_map(void);
45
46/* timer0 interrupt handler */
47static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
48{
49 struct clock_event_device *ce = dev_id;
50
51 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
52
53 /* clear timer0 interrupt */
54 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
55
56 ce->event_handler(ce);
57
58 return IRQ_HANDLED;
59}
60
61/* read 64-bit timer counter */
62static cycle_t sirfsoc_timer_read(struct clocksource *cs)
63{
64 u64 cycles;
65
66 /* latch the 64-bit timer counter */
67 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
68 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
69 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
70
71 return cycles;
72}
73
74static int sirfsoc_timer_set_next_event(unsigned long delta,
75 struct clock_event_device *ce)
76{
77 unsigned long now, next;
78
79 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
80 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
81 next = now + delta;
82 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
83 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
84 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
85
86 return next - now > delta ? -ETIME : 0;
87}
88
89static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
90 struct clock_event_device *ce)
91{
92 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
93 switch (mode) {
94 case CLOCK_EVT_MODE_PERIODIC:
95 WARN_ON(1);
96 break;
97 case CLOCK_EVT_MODE_ONESHOT:
98 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
99 break;
100 case CLOCK_EVT_MODE_SHUTDOWN:
101 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
102 break;
103 case CLOCK_EVT_MODE_UNUSED:
104 case CLOCK_EVT_MODE_RESUME:
105 break;
106 }
107}
108
109static struct clock_event_device sirfsoc_clockevent = {
110 .name = "sirfsoc_clockevent",
111 .rating = 200,
112 .features = CLOCK_EVT_FEAT_ONESHOT,
113 .set_mode = sirfsoc_timer_set_mode,
114 .set_next_event = sirfsoc_timer_set_next_event,
115};
116
117static struct clocksource sirfsoc_clocksource = {
118 .name = "sirfsoc_clocksource",
119 .rating = 200,
120 .mask = CLOCKSOURCE_MASK(64),
121 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
122 .read = sirfsoc_timer_read,
123};
124
125static struct irqaction sirfsoc_timer_irq = {
126 .name = "sirfsoc_timer0",
127 .flags = IRQF_TIMER,
128 .irq = 0,
129 .handler = sirfsoc_timer_interrupt,
130 .dev_id = &sirfsoc_clockevent,
131};
132
133/* Overwrite weak default sched_clock with more precise one */
134unsigned long long notrace sched_clock(void)
135{
136 static int is_mapped = 0;
137
138 /*
139 * sched_clock is called earlier than .init of sys_timer
140 * if we map timer memory in .init of sys_timer, system
141 * will panic due to illegal memory access
142 */
143 if(!is_mapped) {
144 sirfsoc_of_timer_map();
145 is_mapped = 1;
146 }
147
148 return sirfsoc_timer_read(NULL) * (NSEC_PER_SEC / CLOCK_TICK_RATE);
149}
150
151static void __init sirfsoc_clockevent_init(void)
152{
153 clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
154
155 sirfsoc_clockevent.max_delta_ns =
156 clockevent_delta2ns(-2, &sirfsoc_clockevent);
157 sirfsoc_clockevent.min_delta_ns =
158 clockevent_delta2ns(2, &sirfsoc_clockevent);
159
160 sirfsoc_clockevent.cpumask = cpumask_of(0);
161 clockevents_register_device(&sirfsoc_clockevent);
162}
163
164/* initialize the kernel jiffy timer source */
165static void __init sirfsoc_timer_init(void)
166{
167 unsigned long rate;
168
169 /* timer's input clock is io clock */
170 struct clk *clk = clk_get_sys("io", NULL);
171
172 BUG_ON(IS_ERR(clk));
173
174 rate = clk_get_rate(clk);
175
176 BUG_ON(rate < CLOCK_TICK_RATE);
177 BUG_ON(rate % CLOCK_TICK_RATE);
178
179 writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
180 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
181 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
182 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
183
184 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
185
186 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
187
188 sirfsoc_clockevent_init();
189}
190
191static struct of_device_id timer_ids[] = {
192 { .compatible = "sirf,prima2-tick" },
193};
194
195static void __init sirfsoc_of_timer_map(void)
196{
197 struct device_node *np;
198 const unsigned int *intspec;
199
200 np = of_find_matching_node(NULL, timer_ids);
201 if (!np)
202 panic("unable to find compatible timer node in dtb\n");
203 sirfsoc_timer_base = of_iomap(np, 0);
204 if (!sirfsoc_timer_base)
205 panic("unable to map timer cpu registers\n");
206
207 /* Get the interrupts property */
208 intspec = of_get_property(np, "interrupts", NULL);
209 BUG_ON(!intspec);
210 sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
211
212 of_node_put(np);
213}
214
215struct sys_timer sirfsoc_timer = {
216 .init = sirfsoc_timer_init,
217};
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000000000000..c550c67aa893
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support
6obj-y := common.o timer.o board_dt.o
diff --git a/arch/arm/mach-zynq/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-zynq/board_dt.c b/arch/arm/mach-zynq/board_dt.c
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-zynq/board_dt.c
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
new file mode 100644
index 000000000000..73e93687b81a
--- /dev/null
+++ b/arch/arm/mach-zynq/common.c
@@ -0,0 +1,118 @@
1/*
2 * This file contains common code that is intended to be used across
3 * boards so that it's not replicated.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/cpumask.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/of_irq.h>
23#include <linux/of_platform.h>
24#include <linux/of.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach-types.h>
29#include <asm/page.h>
30#include <asm/hardware/gic.h>
31#include <asm/hardware/cache-l2x0.h>
32
33#include <mach/zynq_soc.h>
34#include <mach/clkdev.h>
35#include "common.h"
36
37static struct of_device_id zynq_of_bus_ids[] __initdata = {
38 { .compatible = "simple-bus", },
39 {}
40};
41
42/**
43 * xilinx_init_machine() - System specific initialization, intended to be
44 * called from board specific initialization.
45 */
46static void __init xilinx_init_machine(void)
47{
48#ifdef CONFIG_CACHE_L2X0
49 /*
50 * 64KB way size, 8-way associativity, parity disabled
51 */
52 l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
53#endif
54
55 of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
56}
57
58/**
59 * xilinx_irq_init() - Interrupt controller initialization for the GIC.
60 */
61static void __init xilinx_irq_init(void)
62{
63 gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
64}
65
66/* The minimum devices needed to be mapped before the VM system is up and
67 * running include the GIC, UART and Timer Counter.
68 */
69
70static struct map_desc io_desc[] __initdata = {
71 {
72 .virtual = TTC0_VIRT,
73 .pfn = __phys_to_pfn(TTC0_PHYS),
74 .length = SZ_4K,
75 .type = MT_DEVICE,
76 }, {
77 .virtual = SCU_PERIPH_VIRT,
78 .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
79 .length = SZ_8K,
80 .type = MT_DEVICE,
81 }, {
82 .virtual = PL310_L2CC_VIRT,
83 .pfn = __phys_to_pfn(PL310_L2CC_PHYS),
84 .length = SZ_4K,
85 .type = MT_DEVICE,
86 },
87
88#ifdef CONFIG_DEBUG_LL
89 {
90 .virtual = UART0_VIRT,
91 .pfn = __phys_to_pfn(UART0_PHYS),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 },
95#endif
96
97};
98
99/**
100 * xilinx_map_io() - Create memory mappings needed for early I/O.
101 */
102static void __init xilinx_map_io(void)
103{
104 iotable_init(io_desc, ARRAY_SIZE(io_desc));
105}
106
107static const char *xilinx_dt_match[] = {
108 "xlnx,zynq-ep107",
109 NULL
110};
111
112MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
113 .map_io = xilinx_map_io,
114 .init_irq = xilinx_irq_init,
115 .init_machine = xilinx_init_machine,
116 .timer = &xttcpss_sys_timer,
117 .dt_compat = xilinx_dt_match,
118MACHINE_END
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
new file mode 100644
index 000000000000..a009644a1555
--- /dev/null
+++ b/arch/arm/mach-zynq/common.h
@@ -0,0 +1,24 @@
1/*
2 * This file contains common function prototypes to avoid externs
3 * in the c files.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_ZYNQ_COMMON_H__
18#define __MACH_ZYNQ_COMMON_H__
19
20#include <asm/mach/time.h>
21
22extern struct sys_timer xttcpss_sys_timer;
23
24#endif
diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h
new file mode 100644
index 000000000000..c6e73d81a459
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/clkdev.h
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-zynq/include/mach/clkdev.h
3 *
4 * Copyright (C) 2011 Xilinx, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_CLKDEV_H__
18#define __MACH_CLKDEV_H__
19
20#include <plat/clock.h>
21
22struct clk {
23 unsigned long rate;
24 const struct clk_ops *ops;
25 const struct icst_params *params;
26 void __iomem *vcoreg;
27};
28
29#define __clk_get(clk) ({ 1; })
30#define __clk_put(clk) do { } while (0)
31
32#endif
diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/mach-zynq/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9f664d5eb81d
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
1/* arch/arm/mach-zynq/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <mach/zynq_soc.h>
18#include <mach/uart.h>
19
20 .macro addruart, rp, rv
21 ldr \rp, =LL_UART_PADDR @ physical
22 ldr \rv, =LL_UART_VADDR @ virtual
23 .endm
24
25 .macro senduart,rd,rx
26 str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
27 .endm
28
29 .macro waituart,rd,rx
30 .endm
31
32 .macro busyuart,rd,rx
331002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
34 tst \rd, #UART_SR_TXFULL @
35 bne 1002b @ wait if FIFO is full
36 .endm
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
new file mode 100644
index 000000000000..3cfc01b37461
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
1/*
2 * arch/arm/mach-zynq/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros
5 *
6 * Copyright (C) 2011 Xilinx
7 *
8 * based on arch/plat-mxc/include/mach/entry-macro.S
9 *
10 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
11 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
12 *
13 * This software is licensed under the terms of the GNU General Public
14 * License version 2, as published by the Free Software Foundation, and
15 * may be copied, distributed, and modified under those terms.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#include <mach/hardware.h>
24#include <asm/hardware/entry-macro-gic.S>
25
26 .macro disable_fiq
27 .endm
28
29 .macro arch_ret_to_user, tmp1, tmp2
30 .endm
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
new file mode 100644
index 000000000000..d558d8a94be7
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-zynq/include/mach/hardware.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_HARDWARE_H__
16#define __MACH_HARDWARE_H__
17
18#endif
diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h
new file mode 100644
index 000000000000..39d9885e0e9a
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/io.h
@@ -0,0 +1,33 @@
1/* arch/arm/mach-zynq/include/mach/io.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_IO_H__
16#define __MACH_IO_H__
17
18/* Allow IO space to be anywhere in the memory */
19
20#define IO_SPACE_LIMIT 0xffff
21
22/* IO address mapping macros, nothing special at this time but required */
23
24#ifdef __ASSEMBLER__
25#define IOMEM(x) (x)
26#else
27#define IOMEM(x) ((void __force __iomem *)(x))
28#endif
29
30#define __io(a) __typesafe_io(a)
31#define __mem_pci(a) (a)
32
33#endif
diff --git a/arch/arm/mach-zynq/include/mach/irqs.h b/arch/arm/mach-zynq/include/mach/irqs.h
new file mode 100644
index 000000000000..5fb04fd3bac8
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/irqs.h
@@ -0,0 +1,21 @@
1/* arch/arm/mach-zynq/include/mach/irqs.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_IRQS_H
16#define __MACH_IRQS_H
17
18#define ARCH_NR_GPIOS 118
19#define NR_IRQS (128 + ARCH_NR_GPIOS)
20
21#endif
diff --git a/arch/arm/mach-zynq/include/mach/memory.h b/arch/arm/mach-zynq/include/mach/memory.h
new file mode 100644
index 000000000000..35a92634dcc1
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/memory.h
@@ -0,0 +1,22 @@
1/* arch/arm/mach-zynq/include/mach/memory.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_MEMORY_H__
16#define __MACH_MEMORY_H__
17
18#include <asm/sizes.h>
19
20#define PLAT_PHYS_OFFSET UL(0x0)
21
22#endif
diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h
new file mode 100644
index 000000000000..1b84d705c675
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/system.h
@@ -0,0 +1,28 @@
1/* arch/arm/mach-zynq/include/mach/system.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_SYSTEM_H__
16#define __MACH_SYSTEM_H__
17
18static inline void arch_idle(void)
19{
20 cpu_do_idle();
21}
22
23static inline void arch_reset(char mode, const char *cmd)
24{
25 /* Add architecture specific reset processing here */
26}
27
28#endif
diff --git a/arch/arm/mach-zynq/include/mach/timex.h b/arch/arm/mach-zynq/include/mach/timex.h
new file mode 100644
index 000000000000..6c0245e42a5e
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/timex.h
@@ -0,0 +1,23 @@
1/* arch/arm/mach-zynq/include/mach/timex.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_TIMEX_H__
16#define __MACH_TIMEX_H__
17
18/* the following is needed for the system to build but will be removed
19 in the future, the value is not important but won't hurt
20*/
21#define CLOCK_TICK_RATE (100 * HZ)
22
23#endif
diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h
new file mode 100644
index 000000000000..5c47c97156f3
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/uart.h
@@ -0,0 +1,25 @@
1/* arch/arm/mach-zynq/include/mach/uart.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_UART_H__
16#define __MACH_UART_H__
17
18#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
19#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
20#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
21
22#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
23#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
24
25#endif
diff --git a/arch/arm/mach-zynq/include/mach/uncompress.h b/arch/arm/mach-zynq/include/mach/uncompress.h
new file mode 100644
index 000000000000..af4e8447bfa3
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/uncompress.h
@@ -0,0 +1,51 @@
1/* arch/arm/mach-zynq/include/mach/uncompress.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_UNCOMPRESS_H__
16#define __MACH_UNCOMPRESS_H__
17
18#include <linux/io.h>
19#include <asm/processor.h>
20#include <mach/zynq_soc.h>
21#include <mach/uart.h>
22
23void arch_decomp_setup(void)
24{
25}
26
27static inline void flush(void)
28{
29 /*
30 * Wait while the FIFO is not empty
31 */
32 while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
33 UART_SR_TXEMPTY))
34 cpu_relax();
35}
36
37#define arch_decomp_wdog()
38
39static void putc(char ch)
40{
41 /*
42 * Wait for room in the FIFO, then write the char into the FIFO
43 */
44 while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
45 UART_SR_TXFULL)
46 cpu_relax();
47
48 __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
49}
50
51#endif
diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h
new file mode 100644
index 000000000000..2398eff1e8b8
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/* arch/arm/mach-zynq/include/mach/vmalloc.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_VMALLOC_H__
16#define __MACH_VMALLOC_H__
17
18#define VMALLOC_END 0xE0000000UL
19
20#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
new file mode 100644
index 000000000000..d0d3f8fb06dd
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -0,0 +1,48 @@
1/* arch/arm/mach-zynq/include/mach/zynq_soc.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_XILINX_SOC_H__
16#define __MACH_XILINX_SOC_H__
17
18#define PERIPHERAL_CLOCK_RATE 2500000
19
20/* For now, all mappings are flat (physical = virtual)
21 */
22#define UART0_PHYS 0xE0000000
23#define UART0_VIRT UART0_PHYS
24
25#define TTC0_PHYS 0xF8001000
26#define TTC0_VIRT TTC0_PHYS
27
28#define PL310_L2CC_PHYS 0xF8F02000
29#define PL310_L2CC_VIRT PL310_L2CC_PHYS
30
31#define SCU_PERIPH_PHYS 0xF8F00000
32#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
33
34/* The following are intended for the devices that are mapped early */
35
36#define TTC0_BASE IOMEM(TTC0_VIRT)
37#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
38#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
39#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
40#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
41
42/*
43 * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
44 */
45#define LL_UART_PADDR UART0_PHYS
46#define LL_UART_VADDR UART0_VIRT
47
48#endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
new file mode 100644
index 000000000000..c2c96cc7d6e7
--- /dev/null
+++ b/arch/arm/mach-zynq/timer.c
@@ -0,0 +1,298 @@
1/*
2 * This file contains driver for the Xilinx PS Timer Counter IP.
3 *
4 * Copyright (C) 2011 Xilinx
5 *
6 * based on arch/mips/kernel/time.c timer driver
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/types.h>
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/io.h>
26
27#include <asm/mach/time.h>
28#include <mach/zynq_soc.h>
29#include "common.h"
30
31#define IRQ_TIMERCOUNTER0 42
32
33/*
34 * This driver configures the 2 16-bit count-up timers as follows:
35 *
36 * T1: Timer 1, clocksource for generic timekeeping
37 * T2: Timer 2, clockevent source for hrtimers
38 * T3: Timer 3, <unused>
39 *
40 * The input frequency to the timer module for emulation is 2.5MHz which is
41 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
42 * the timers are clocked at 78.125KHz (12.8 us resolution).
43 *
44 * The input frequency to the timer module in silicon will be 200MHz. With the
45 * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
46 */
47#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
48#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
49
50#define XTTCPSS_TIMER_BASE TTC0_BASE
51#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
52/*
53 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
54 * and use same offsets for Timer 2
55 */
56#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
57#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
58#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
59#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
60#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
61#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
62#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
63#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
64#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
65
66#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
67
68/* Setup the timers to use pre-scaling */
69
70#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
71
72/**
73 * struct xttcpss_timer - This definition defines local timer structure
74 *
75 * @base_addr: Base address of timer
76 **/
77struct xttcpss_timer {
78 void __iomem *base_addr;
79};
80
81static struct xttcpss_timer timers[2];
82static struct clock_event_device xttcpss_clockevent;
83
84/**
85 * xttcpss_set_interval - Set the timer interval value
86 *
87 * @timer: Pointer to the timer instance
88 * @cycles: Timer interval ticks
89 **/
90static void xttcpss_set_interval(struct xttcpss_timer *timer,
91 unsigned long cycles)
92{
93 u32 ctrl_reg;
94
95 /* Disable the counter, set the counter value and re-enable counter */
96 ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
97 ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
98 __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
99
100 __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
101
102 /* Reset the counter (0x10) so that it starts from 0, one-shot
103 mode makes this needed for timing to be right. */
104 ctrl_reg |= 0x10;
105 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
106 __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
107}
108
109/**
110 * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
111 *
112 * @irq: IRQ number of the Timer
113 * @dev_id: void pointer to the xttcpss_timer instance
114 *
115 * returns: Always IRQ_HANDLED - success
116 **/
117static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
118{
119 struct clock_event_device *evt = &xttcpss_clockevent;
120 struct xttcpss_timer *timer = dev_id;
121
122 /* Acknowledge the interrupt and call event handler */
123 __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
124 timer->base_addr + XTTCPSS_ISR_OFFSET);
125
126 evt->event_handler(evt);
127
128 return IRQ_HANDLED;
129}
130
131static struct irqaction event_timer_irq = {
132 .name = "xttcpss clockevent",
133 .flags = IRQF_DISABLED | IRQF_TIMER,
134 .handler = xttcpss_clock_event_interrupt,
135};
136
137/**
138 * xttcpss_timer_hardware_init - Initialize the timer hardware
139 *
140 * Initialize the hardware to start the clock source, get the clock
141 * event timer ready to use, and hook up the interrupt.
142 **/
143static void __init xttcpss_timer_hardware_init(void)
144{
145 /* Setup the clock source counter to be an incrementing counter
146 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
147 it by 32 also. Let it start running now.
148 */
149 timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
150
151 __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
152 XTTCPSS_IER_OFFSET);
153 __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
154 XTTCPSS_CLK_CNTRL_OFFSET);
155 __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
156 XTTCPSS_CNT_CNTRL_OFFSET);
157
158 /* Setup the clock event timer to be an interval timer which
159 * is prescaled by 32 using the interval interrupt. Leave it
160 * disabled for now.
161 */
162
163 timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
164
165 __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
166 XTTCPSS_CNT_CNTRL_OFFSET);
167 __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
168 XTTCPSS_CLK_CNTRL_OFFSET);
169 __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
170 XTTCPSS_IER_OFFSET);
171
172 /* Setup IRQ the clock event timer */
173 event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
174 setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
175}
176
177/**
178 * __raw_readl_cycles - Reads the timer counter register
179 *
180 * returns: Current timer counter register value
181 **/
182static cycle_t __raw_readl_cycles(struct clocksource *cs)
183{
184 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
185
186 return (cycle_t)__raw_readl(timer->base_addr +
187 XTTCPSS_COUNT_VAL_OFFSET);
188}
189
190
191/*
192 * Instantiate and initialize the clock source structure
193 */
194static struct clocksource clocksource_xttcpss = {
195 .name = "xttcpss_timer1",
196 .rating = 200, /* Reasonable clock source */
197 .read = __raw_readl_cycles,
198 .mask = CLOCKSOURCE_MASK(16),
199 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
200};
201
202
203/**
204 * xttcpss_set_next_event - Sets the time interval for next event
205 *
206 * @cycles: Timer interval ticks
207 * @evt: Address of clock event instance
208 *
209 * returns: Always 0 - success
210 **/
211static int xttcpss_set_next_event(unsigned long cycles,
212 struct clock_event_device *evt)
213{
214 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
215
216 xttcpss_set_interval(timer, cycles);
217 return 0;
218}
219
220/**
221 * xttcpss_set_mode - Sets the mode of timer
222 *
223 * @mode: Mode to be set
224 * @evt: Address of clock event instance
225 **/
226static void xttcpss_set_mode(enum clock_event_mode mode,
227 struct clock_event_device *evt)
228{
229 struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
230 u32 ctrl_reg;
231
232 switch (mode) {
233 case CLOCK_EVT_MODE_PERIODIC:
234 xttcpss_set_interval(timer, TIMER_RATE / HZ);
235 break;
236 case CLOCK_EVT_MODE_ONESHOT:
237 case CLOCK_EVT_MODE_UNUSED:
238 case CLOCK_EVT_MODE_SHUTDOWN:
239 ctrl_reg = __raw_readl(timer->base_addr +
240 XTTCPSS_CNT_CNTRL_OFFSET);
241 ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
242 __raw_writel(ctrl_reg,
243 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
244 break;
245 case CLOCK_EVT_MODE_RESUME:
246 ctrl_reg = __raw_readl(timer->base_addr +
247 XTTCPSS_CNT_CNTRL_OFFSET);
248 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
249 __raw_writel(ctrl_reg,
250 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
251 break;
252 }
253}
254
255/*
256 * Instantiate and initialize the clock event structure
257 */
258static struct clock_event_device xttcpss_clockevent = {
259 .name = "xttcpss_timer2",
260 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
261 .set_next_event = xttcpss_set_next_event,
262 .set_mode = xttcpss_set_mode,
263 .rating = 200,
264};
265
266/**
267 * xttcpss_timer_init - Initialize the timer
268 *
269 * Initializes the timer hardware and register the clock source and clock event
270 * timers with Linux kernal timer framework
271 **/
272static void __init xttcpss_timer_init(void)
273{
274 xttcpss_timer_hardware_init();
275 clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
276
277 /* Calculate the parameters to allow the clockevent to operate using
278 integer math
279 */
280 clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
281
282 xttcpss_clockevent.max_delta_ns =
283 clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
284 xttcpss_clockevent.min_delta_ns =
285 clockevent_delta2ns(1, &xttcpss_clockevent);
286
287 /* Indicate that clock event is on 1st CPU as SMP boot needs it */
288
289 xttcpss_clockevent.cpumask = cpumask_of(0);
290 clockevents_register_device(&xttcpss_clockevent);
291}
292
293/*
294 * Instantiate and initialize the system timer structure
295 */
296struct sys_timer xttcpss_sys_timer = {
297 .init = xttcpss_timer_init,
298};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0074b8dba793..a0ea5848d40d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,8 @@ config CACHE_L2X0
821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ 822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ 823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
825 ARCH_PRIMA2 || ARCH_ZYNQ
825 default y 826 default y
826 select OUTER_CACHE 827 select OUTER_CACHE
827 select OUTER_CACHE_SYNC 828 select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index f1899a3e4174..387a9638991b 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ 39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
40#define CK_443X (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_TI816X (1 << 12) 41#define CK_TI816X (1 << 12)
42#define CK_446X (1 << 13)
42 43
43 44
44#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 45#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index f57e0649ab30..df4b9683f17f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -58,10 +58,12 @@ struct clkops {
58#define RATE_IN_36XX (1 << 4) 58#define RATE_IN_36XX (1 << 4)
59#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_4430 (1 << 5)
60#define RATE_IN_TI816X (1 << 6) 60#define RATE_IN_TI816X (1 << 6)
61#define RATE_IN_4460 (1 << 7)
61 62
62#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
63#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
64#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 65#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
66#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
65 67
66/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 68/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
67#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 69#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 8198bb6cdb5e..67b3d75884cd 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -88,6 +88,7 @@ unsigned int omap_rev(void);
88 * cpu_is_omap243x(): True for OMAP2430 88 * cpu_is_omap243x(): True for OMAP2430
89 * cpu_is_omap343x(): True for OMAP3430 89 * cpu_is_omap343x(): True for OMAP3430
90 * cpu_is_omap443x(): True for OMAP4430 90 * cpu_is_omap443x(): True for OMAP4430
91 * cpu_is_omap446x(): True for OMAP4460
91 */ 92 */
92#define GET_OMAP_CLASS (omap_rev() & 0xff) 93#define GET_OMAP_CLASS (omap_rev() & 0xff)
93 94
@@ -123,6 +124,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
123IS_OMAP_SUBCLASS(343x, 0x343) 124IS_OMAP_SUBCLASS(343x, 0x343)
124IS_OMAP_SUBCLASS(363x, 0x363) 125IS_OMAP_SUBCLASS(363x, 0x363)
125IS_OMAP_SUBCLASS(443x, 0x443) 126IS_OMAP_SUBCLASS(443x, 0x443)
127IS_OMAP_SUBCLASS(446x, 0x446)
126 128
127IS_TI_SUBCLASS(816x, 0x816) 129IS_TI_SUBCLASS(816x, 0x816)
128 130
@@ -137,6 +139,7 @@ IS_TI_SUBCLASS(816x, 0x816)
137#define cpu_is_ti816x() 0 139#define cpu_is_ti816x() 0
138#define cpu_is_omap44xx() 0 140#define cpu_is_omap44xx() 0
139#define cpu_is_omap443x() 0 141#define cpu_is_omap443x() 0
142#define cpu_is_omap446x() 0
140 143
141#if defined(MULTI_OMAP1) 144#if defined(MULTI_OMAP1)
142# if defined(CONFIG_ARCH_OMAP730) 145# if defined(CONFIG_ARCH_OMAP730)
@@ -361,8 +364,10 @@ IS_OMAP_TYPE(3517, 0x3517)
361# if defined(CONFIG_ARCH_OMAP4) 364# if defined(CONFIG_ARCH_OMAP4)
362# undef cpu_is_omap44xx 365# undef cpu_is_omap44xx
363# undef cpu_is_omap443x 366# undef cpu_is_omap443x
367# undef cpu_is_omap446x
364# define cpu_is_omap44xx() is_omap44xx() 368# define cpu_is_omap44xx() is_omap44xx()
365# define cpu_is_omap443x() is_omap443x() 369# define cpu_is_omap443x() is_omap443x()
370# define cpu_is_omap446x() is_omap446x()
366# endif 371# endif
367 372
368/* Macros to detect if we have OMAP1 or OMAP2 */ 373/* Macros to detect if we have OMAP1 or OMAP2 */
@@ -410,6 +415,9 @@ IS_OMAP_TYPE(3517, 0x3517)
410#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) 415#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
411#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) 416#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
412 417
418#define OMAP446X_CLASS 0x44600044
419#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
420
413/* 421/*
414 * omap_chip bits 422 * omap_chip bits
415 * 423 *
@@ -439,13 +447,15 @@ IS_OMAP_TYPE(3517, 0x3517)
439#define CHIP_IS_OMAP4430ES2_1 (1 << 12) 447#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
440#define CHIP_IS_OMAP4430ES2_2 (1 << 13) 448#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
441#define CHIP_IS_TI816X (1 << 14) 449#define CHIP_IS_TI816X (1 << 14)
450#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
442 451
443#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
444 453
445#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
446 CHIP_IS_OMAP4430ES2 | \ 455 CHIP_IS_OMAP4430ES2 | \
447 CHIP_IS_OMAP4430ES2_1 | \ 456 CHIP_IS_OMAP4430ES2_1 | \
448 CHIP_IS_OMAP4430ES2_2) 457 CHIP_IS_OMAP4430ES2_2 | \
458 CHIP_IS_OMAP4460ES1_0)
449 459
450/* 460/*
451 * "GE" here represents "greater than or equal to" in terms of ES 461 * "GE" here represents "greater than or equal to" in terms of ES
@@ -468,7 +478,7 @@ void omap2_check_revision(void);
468/* 478/*
469 * Runtime detection of OMAP3 features 479 * Runtime detection of OMAP3 features
470 */ 480 */
471extern u32 omap3_features; 481extern u32 omap_features;
472 482
473#define OMAP3_HAS_L2CACHE BIT(0) 483#define OMAP3_HAS_L2CACHE BIT(0)
474#define OMAP3_HAS_IVA BIT(1) 484#define OMAP3_HAS_IVA BIT(1)
@@ -478,11 +488,15 @@ extern u32 omap3_features;
478#define OMAP3_HAS_192MHZ_CLK BIT(5) 488#define OMAP3_HAS_192MHZ_CLK BIT(5)
479#define OMAP3_HAS_IO_WAKEUP BIT(6) 489#define OMAP3_HAS_IO_WAKEUP BIT(6)
480#define OMAP3_HAS_SDRC BIT(7) 490#define OMAP3_HAS_SDRC BIT(7)
491#define OMAP4_HAS_MPU_1GHZ BIT(8)
492#define OMAP4_HAS_MPU_1_2GHZ BIT(9)
493#define OMAP4_HAS_MPU_1_5GHZ BIT(10)
494
481 495
482#define OMAP3_HAS_FEATURE(feat,flag) \ 496#define OMAP3_HAS_FEATURE(feat,flag) \
483static inline unsigned int omap3_has_ ##feat(void) \ 497static inline unsigned int omap3_has_ ##feat(void) \
484{ \ 498{ \
485 return (omap3_features & OMAP3_HAS_ ##flag); \ 499 return omap_features & OMAP3_HAS_ ##flag; \
486} \ 500} \
487 501
488OMAP3_HAS_FEATURE(l2cache, L2CACHE) 502OMAP3_HAS_FEATURE(l2cache, L2CACHE)
@@ -494,4 +508,19 @@ OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
494OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) 508OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
495OMAP3_HAS_FEATURE(sdrc, SDRC) 509OMAP3_HAS_FEATURE(sdrc, SDRC)
496 510
511/*
512 * Runtime detection of OMAP4 features
513 */
514extern u32 omap_features;
515
516#define OMAP4_HAS_FEATURE(feat, flag) \
517static inline unsigned int omap4_has_ ##feat(void) \
518{ \
519 return omap_features & OMAP4_HAS_ ##flag; \
520} \
521
522OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
523OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
524OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
525
497#endif 526#endif