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authorArnd Bergmann <arnd@arndb.de>2011-07-17 15:44:10 -0400
committerArnd Bergmann <arnd@arndb.de>2011-07-17 15:44:10 -0400
commit6c59c115b0f295434cc4f917d180fecd84d39f81 (patch)
tree659a2b63552dd53211f86c60930900520cba3686
parent3a6cb8ce07d994f6e4a3679c5478d0f18b6b86c4 (diff)
parent257d643d7d7cd81075b6dee88cfba14f773805c7 (diff)
Merge branch 'omap/4460' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc into next/soc
Diffstat
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c4
-rw-r--r--arch/arm/mach-omap1/board-fsample.c4
-rw-r--r--arch/arm/mach-omap1/board-generic.c4
-rw-r--r--arch/arm/mach-omap1/board-h2.c4
-rw-r--r--arch/arm/mach-omap1/board-h3.c4
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c4
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c4
-rw-r--r--arch/arm/mach-omap1/board-osk.c4
-rw-r--r--arch/arm/mach-omap1/board-palmte.c4
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c4
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c4
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c4
-rw-r--r--arch/arm/mach-omap1/board-sx1.c4
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c4
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap1/time.c6
-rw-r--r--arch/arm/mach-omap1/timer32k.c4
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c19
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c4
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c4
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c44
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c36
-rw-r--r--arch/arm/mach-omap2/board-flash.c4
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c4
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c35
-rw-r--r--arch/arm/mach-omap2/board-ldp.c14
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c12
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c37
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c51
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c19
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c67
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c37
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c44
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c19
-rw-r--r--arch/arm/mach-omap2/board-overo.c32
-rw-r--r--arch/arm/mach-omap2/board-rm680.c4
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c29
-rw-r--r--arch/arm/mach-omap2/board-rx51.c4
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c9
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c49
-rw-r--r--arch/arm/mach-omap2/board-zoom.c8
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c39
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h36
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c6
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c10
-rw-r--r--arch/arm/mach-omap2/id.c53
-rw-r--r--arch/arm/mach-omap2/io.c17
-rw-r--r--arch/arm/mach-omap2/irq.c32
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/pm-debug.c372
-rw-r--r--arch/arm/mach-omap2/pm.h16
-rw-r--r--arch/arm/mach-omap2/pm24xx.c6
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h8
-rw-r--r--arch/arm/mach-omap2/smartreflex.c38
-rw-r--r--arch/arm/mach-omap2/timer-gp.c266
-rw-r--r--arch/arm/mach-omap2/timer-gp.h16
-rw-r--r--arch/arm/mach-omap2/timer.c342
-rw-r--r--arch/arm/plat-omap/counter_32k.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c209
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h6
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h35
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h250
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h6
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h62
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h6
-rw-r--r--arch/arm/plat-omap/mcbsp.c596
77 files changed, 1178 insertions, 1954 deletions
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index de88c9297b68..f1ac7fbf54a9 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
138static void __init ams_delta_init_irq(void) 138static void __init ams_delta_init_irq(void)
139{ 139{
140 omap1_init_common_hw(); 140 omap1_init_common_hw();
141 omap_init_irq(); 141 omap1_init_irq();
142} 142}
143 143
144static struct map_desc ams_delta_io_desc[] __initdata = { 144static struct map_desc ams_delta_io_desc[] __initdata = {
@@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
391 .reserve = omap_reserve, 391 .reserve = omap_reserve,
392 .init_irq = ams_delta_init_irq, 392 .init_irq = ams_delta_init_irq,
393 .init_machine = ams_delta_init, 393 .init_machine = ams_delta_init,
394 .timer = &omap_timer, 394 .timer = &omap1_timer,
395MACHINE_END 395MACHINE_END
396 396
397EXPORT_SYMBOL(ams_delta_latch1_write); 397EXPORT_SYMBOL(ams_delta_latch1_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 87f173d93557..a6b1bea50371 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
329static void __init omap_fsample_init_irq(void) 329static void __init omap_fsample_init_irq(void)
330{ 330{
331 omap1_init_common_hw(); 331 omap1_init_common_hw();
332 omap_init_irq(); 332 omap1_init_irq();
333} 333}
334 334
335/* Only FPGA needs to be mapped here. All others are done with ioremap */ 335/* Only FPGA needs to be mapped here. All others are done with ioremap */
@@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
394 .reserve = omap_reserve, 394 .reserve = omap_reserve,
395 .init_irq = omap_fsample_init_irq, 395 .init_irq = omap_fsample_init_irq,
396 .init_machine = omap_fsample_init, 396 .init_machine = omap_fsample_init,
397 .timer = &omap_timer, 397 .timer = &omap1_timer,
398MACHINE_END 398MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 23f4ab9e2651..04fc356c40fa 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -31,7 +31,7 @@
31static void __init omap_generic_init_irq(void) 31static void __init omap_generic_init_irq(void)
32{ 32{
33 omap1_init_common_hw(); 33 omap1_init_common_hw();
34 omap_init_irq(); 34 omap1_init_irq();
35} 35}
36 36
37/* assume no Mini-AB port */ 37/* assume no Mini-AB port */
@@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
99 .reserve = omap_reserve, 99 .reserve = omap_reserve,
100 .init_irq = omap_generic_init_irq, 100 .init_irq = omap_generic_init_irq,
101 .init_machine = omap_generic_init, 101 .init_machine = omap_generic_init,
102 .timer = &omap_timer, 102 .timer = &omap1_timer,
103MACHINE_END 103MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index ba3bd09c4754..cb7fb1aa3dca 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
376static void __init h2_init_irq(void) 376static void __init h2_init_irq(void)
377{ 377{
378 omap1_init_common_hw(); 378 omap1_init_common_hw();
379 omap_init_irq(); 379 omap1_init_irq();
380} 380}
381 381
382static struct omap_usb_config h2_usb_config __initdata = { 382static struct omap_usb_config h2_usb_config __initdata = {
@@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
466 .reserve = omap_reserve, 466 .reserve = omap_reserve,
467 .init_irq = h2_init_irq, 467 .init_irq = h2_init_irq,
468 .init_machine = h2_init, 468 .init_machine = h2_init,
469 .timer = &omap_timer, 469 .timer = &omap1_timer,
470MACHINE_END 470MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ac48677672ee..31f34875ffad 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -439,7 +439,7 @@ static void __init h3_init(void)
439static void __init h3_init_irq(void) 439static void __init h3_init_irq(void)
440{ 440{
441 omap1_init_common_hw(); 441 omap1_init_common_hw();
442 omap_init_irq(); 442 omap1_init_irq();
443} 443}
444 444
445static void __init h3_map_io(void) 445static void __init h3_map_io(void)
@@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
454 .reserve = omap_reserve, 454 .reserve = omap_reserve,
455 .init_irq = h3_init_irq, 455 .init_irq = h3_init_irq,
456 .init_machine = h3_init, 456 .init_machine = h3_init,
457 .timer = &omap_timer, 457 .timer = &omap1_timer,
458MACHINE_END 458MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index ba05a51f9408..36e06ea7ec65 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
605{ 605{
606 printk(KERN_INFO "htcherald_init_irq.\n"); 606 printk(KERN_INFO "htcherald_init_irq.\n");
607 omap1_init_common_hw(); 607 omap1_init_common_hw();
608 omap_init_irq(); 608 omap1_init_irq();
609} 609}
610 610
611MACHINE_START(HERALD, "HTC Herald") 611MACHINE_START(HERALD, "HTC Herald")
@@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
616 .reserve = omap_reserve, 616 .reserve = omap_reserve,
617 .init_irq = htcherald_init_irq, 617 .init_irq = htcherald_init_irq,
618 .init_machine = htcherald_init, 618 .init_machine = htcherald_init,
619 .timer = &omap_timer, 619 .timer = &omap1_timer,
620MACHINE_END 620MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 2d9b8cbd7a14..0b1ba462d388 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
292static void __init innovator_init_irq(void) 292static void __init innovator_init_irq(void)
293{ 293{
294 omap1_init_common_hw(); 294 omap1_init_common_hw();
295 omap_init_irq(); 295 omap1_init_irq();
296} 296}
297 297
298#ifdef CONFIG_ARCH_OMAP15XX 298#ifdef CONFIG_ARCH_OMAP15XX
@@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
464 .reserve = omap_reserve, 464 .reserve = omap_reserve,
465 .init_irq = innovator_init_irq, 465 .init_irq = innovator_init_irq,
466 .init_machine = innovator_init, 466 .init_machine = innovator_init,
467 .timer = &omap_timer, 467 .timer = &omap1_timer,
468MACHINE_END 468MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index cfd084926146..5469ce247ffe 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
51 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004); 51 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
52 52
53 omap1_init_common_hw(); 53 omap1_init_common_hw();
54 omap_init_irq(); 54 omap1_init_irq();
55} 55}
56 56
57static const unsigned int nokia770_keymap[] = { 57static const unsigned int nokia770_keymap[] = {
@@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
269 .reserve = omap_reserve, 269 .reserve = omap_reserve,
270 .init_irq = omap_nokia770_init_irq, 270 .init_irq = omap_nokia770_init_irq,
271 .init_machine = omap_nokia770_init, 271 .init_machine = omap_nokia770_init,
272 .timer = &omap_timer, 272 .timer = &omap1_timer,
273MACHINE_END 273MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e68dfde1918e..b08a21380772 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
282static void __init osk_init_irq(void) 282static void __init osk_init_irq(void)
283{ 283{
284 omap1_init_common_hw(); 284 omap1_init_common_hw();
285 omap_init_irq(); 285 omap1_init_irq();
286} 286}
287 287
288static struct omap_usb_config osk_usb_config __initdata = { 288static struct omap_usb_config osk_usb_config __initdata = {
@@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
588 .reserve = omap_reserve, 588 .reserve = omap_reserve,
589 .init_irq = osk_init_irq, 589 .init_irq = osk_init_irq,
590 .init_machine = osk_init, 590 .init_machine = osk_init,
591 .timer = &omap_timer, 591 .timer = &omap1_timer,
592MACHINE_END 592MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index c9d38f47845f..459cb6bfed55 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -62,7 +62,7 @@
62static void __init omap_palmte_init_irq(void) 62static void __init omap_palmte_init_irq(void)
63{ 63{
64 omap1_init_common_hw(); 64 omap1_init_common_hw();
65 omap_init_irq(); 65 omap1_init_irq();
66} 66}
67 67
68static const unsigned int palmte_keymap[] = { 68static const unsigned int palmte_keymap[] = {
@@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
280 .reserve = omap_reserve, 280 .reserve = omap_reserve,
281 .init_irq = omap_palmte_init_irq, 281 .init_irq = omap_palmte_init_irq,
282 .init_machine = omap_palmte_init, 282 .init_machine = omap_palmte_init,
283 .timer = &omap_timer, 283 .timer = &omap1_timer,
284MACHINE_END 284MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index f04f2d36e7d3..b214f45f646c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
266static void __init omap_palmtt_init_irq(void) 266static void __init omap_palmtt_init_irq(void)
267{ 267{
268 omap1_init_common_hw(); 268 omap1_init_common_hw();
269 omap_init_irq(); 269 omap1_init_irq();
270} 270}
271 271
272static struct omap_usb_config palmtt_usb_config __initdata = { 272static struct omap_usb_config palmtt_usb_config __initdata = {
@@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
326 .reserve = omap_reserve, 326 .reserve = omap_reserve,
327 .init_irq = omap_palmtt_init_irq, 327 .init_irq = omap_palmtt_init_irq,
328 .init_machine = omap_palmtt_init, 328 .init_machine = omap_palmtt_init,
329 .timer = &omap_timer, 329 .timer = &omap1_timer,
330MACHINE_END 330MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 45f01d2c3a7a..9b0ea48d35fd 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -61,7 +61,7 @@ static void __init
61omap_palmz71_init_irq(void) 61omap_palmz71_init_irq(void)
62{ 62{
63 omap1_init_common_hw(); 63 omap1_init_common_hw();
64 omap_init_irq(); 64 omap1_init_irq();
65} 65}
66 66
67static const unsigned int palmz71_keymap[] = { 67static const unsigned int palmz71_keymap[] = {
@@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
346 .reserve = omap_reserve, 346 .reserve = omap_reserve,
347 .init_irq = omap_palmz71_init_irq, 347 .init_irq = omap_palmz71_init_irq,
348 .init_machine = omap_palmz71_init, 348 .init_machine = omap_palmz71_init,
349 .timer = &omap_timer, 349 .timer = &omap1_timer,
350MACHINE_END 350MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 3c8ee8489458..67acd4142639 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
297static void __init omap_perseus2_init_irq(void) 297static void __init omap_perseus2_init_irq(void)
298{ 298{
299 omap1_init_common_hw(); 299 omap1_init_common_hw();
300 omap_init_irq(); 300 omap1_init_irq();
301} 301}
302/* Only FPGA needs to be mapped here. All others are done with ioremap */ 302/* Only FPGA needs to be mapped here. All others are done with ioremap */
303static struct map_desc omap_perseus2_io_desc[] __initdata = { 303static struct map_desc omap_perseus2_io_desc[] __initdata = {
@@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
355 .reserve = omap_reserve, 355 .reserve = omap_reserve,
356 .init_irq = omap_perseus2_init_irq, 356 .init_irq = omap_perseus2_init_irq,
357 .init_machine = omap_perseus2_init, 357 .init_machine = omap_perseus2_init,
358 .timer = &omap_timer, 358 .timer = &omap1_timer,
359MACHINE_END 359MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0ad781db4e66..9c3b7c52d9cf 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
411static void __init omap_sx1_init_irq(void) 411static void __init omap_sx1_init_irq(void)
412{ 412{
413 omap1_init_common_hw(); 413 omap1_init_common_hw();
414 omap_init_irq(); 414 omap1_init_irq();
415} 415}
416/*----------------------------------------*/ 416/*----------------------------------------*/
417 417
@@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
426 .reserve = omap_reserve, 426 .reserve = omap_reserve,
427 .init_irq = omap_sx1_init_irq, 427 .init_irq = omap_sx1_init_irq,
428 .init_machine = omap_sx1_init, 428 .init_machine = omap_sx1_init,
429 .timer = &omap_timer, 429 .timer = &omap1_timer,
430MACHINE_END 430MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 65d24204937a..036edc0ee9b6 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
162static void __init voiceblue_init_irq(void) 162static void __init voiceblue_init_irq(void)
163{ 163{
164 omap1_init_common_hw(); 164 omap1_init_common_hw();
165 omap_init_irq(); 165 omap1_init_irq();
166} 166}
167 167
168static void __init voiceblue_map_io(void) 168static void __init voiceblue_map_io(void)
@@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
306 .reserve = omap_reserve, 306 .reserve = omap_reserve,
307 .init_irq = voiceblue_init_irq, 307 .init_irq = voiceblue_init_irq,
308 .init_machine = voiceblue_init, 308 .init_machine = voiceblue_init,
309 .timer = &omap_timer, 309 .timer = &omap1_timer,
310MACHINE_END 310MACHINE_END
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 5d3da7a63af3..e2b9c901ab67 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
175 .irq_set_wake = omap_wake_irq, 175 .irq_set_wake = omap_wake_irq,
176}; 176};
177 177
178void __init omap_init_irq(void) 178void __init omap1_init_irq(void)
179{ 179{
180 int i, j; 180 int i, j;
181 181
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 03e1e1062ad4..a1837771e031 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
297 * Timer initialization 297 * Timer initialization
298 * --------------------------------------------------------------------------- 298 * ---------------------------------------------------------------------------
299 */ 299 */
300static void __init omap_timer_init(void) 300static void __init omap1_timer_init(void)
301{ 301{
302 if (omap_32k_timer_usable()) { 302 if (omap_32k_timer_usable()) {
303 preferred_sched_clock_init(1); 303 preferred_sched_clock_init(1);
@@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
307 } 307 }
308} 308}
309 309
310struct sys_timer omap_timer = { 310struct sys_timer omap1_timer = {
311 .init = omap_timer_init, 311 .init = omap1_timer_init,
312}; 312};
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 13d7b8f145bd..96604a50c4fe 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
183bool __init omap_32k_timer_init(void) 183bool __init omap_32k_timer_init(void)
184{ 184{
185 omap_init_clocksource_32k(); 185 omap_init_clocksource_32k();
186
187#ifdef CONFIG_OMAP_DM_TIMER
188 omap_dm_timer_init();
189#endif
190 omap_init_32k_timer(); 186 omap_init_32k_timer();
191 187
192 return true; 188 return true;
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b14807794401..adbe82d72d4e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o 7 common.o gpio.o dma.o wd_timer.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 5de6eac0a725..2028464cf5b9 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
260 .reserve = omap_reserve, 260 .reserve = omap_reserve,
261 .map_io = omap_2430sdp_map_io, 261 .map_io = omap_2430sdp_map_io,
262 .init_early = omap_2430sdp_init_early, 262 .init_early = omap_2430sdp_init_early,
263 .init_irq = omap_init_irq, 263 .init_irq = omap2_init_irq,
264 .init_machine = omap_2430sdp_init, 264 .init_machine = omap_2430sdp_init,
265 .timer = &omap_timer, 265 .timer = &omap2_timer,
266MACHINE_END 266MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5dac974be625..12fae21346cf 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -804,7 +804,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
804 .reserve = omap_reserve, 804 .reserve = omap_reserve,
805 .map_io = omap3_map_io, 805 .map_io = omap3_map_io,
806 .init_early = omap_3430sdp_init_early, 806 .init_early = omap_3430sdp_init_early,
807 .init_irq = omap_init_irq, 807 .init_irq = omap3_init_irq,
808 .init_machine = omap_3430sdp_init, 808 .init_machine = omap_3430sdp_init,
809 .timer = &omap_timer, 809 .timer = &omap3_timer,
810MACHINE_END 810MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index a5933cc15caa..e4f37b57a0c4 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
219 .reserve = omap_reserve, 219 .reserve = omap_reserve,
220 .map_io = omap3_map_io, 220 .map_io = omap3_map_io,
221 .init_early = omap_sdp_init_early, 221 .init_early = omap_sdp_init_early,
222 .init_irq = omap_init_irq, 222 .init_irq = omap3_init_irq,
223 .init_machine = omap_sdp_init, 223 .init_machine = omap_sdp_init,
224 .timer = &omap_timer, 224 .timer = &omap3_timer,
225MACHINE_END 225MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 63de2d396e2d..d7df07ef2cea 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -40,7 +40,6 @@
40 40
41#include "mux.h" 41#include "mux.h"
42#include "hsmmc.h" 42#include "hsmmc.h"
43#include "timer-gp.h"
44#include "control.h" 43#include "control.h"
45#include "common-board-devices.h" 44#include "common-board-devices.h"
46 45
@@ -295,9 +294,6 @@ static void __init omap_4430sdp_init_early(void)
295{ 294{
296 omap2_init_common_infrastructure(); 295 omap2_init_common_infrastructure();
297 omap2_init_common_devices(NULL, NULL); 296 omap2_init_common_devices(NULL, NULL);
298#ifdef CONFIG_OMAP_32K_TIMER
299 omap2_gp_clockevent_set_gptimer(1);
300#endif
301} 297}
302 298
303static struct omap_musb_board_data musb_board_data = { 299static struct omap_musb_board_data musb_board_data = {
@@ -333,16 +329,11 @@ static struct omap2_hsmmc_info mmc[] = {
333}; 329};
334 330
335static struct regulator_consumer_supply sdp4430_vaux_supply[] = { 331static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
336 { 332 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
337 .supply = "vmmc",
338 .dev_name = "omap_hsmmc.1",
339 },
340}; 333};
334
341static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { 335static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
342 { 336 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
343 .supply = "vmmc",
344 .dev_name = "omap_hsmmc.0",
345 },
346}; 337};
347 338
348static int omap4_twl6030_hsmmc_late_init(struct device *dev) 339static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@@ -399,7 +390,7 @@ static struct regulator_init_data sdp4430_vaux1 = {
399 | REGULATOR_CHANGE_MODE 390 | REGULATOR_CHANGE_MODE
400 | REGULATOR_CHANGE_STATUS, 391 | REGULATOR_CHANGE_STATUS,
401 }, 392 },
402 .num_consumer_supplies = 1, 393 .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
403 .consumer_supplies = sdp4430_vaux_supply, 394 .consumer_supplies = sdp4430_vaux_supply,
404}; 395};
405 396
@@ -773,5 +764,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
773 .init_early = omap_4430sdp_init_early, 764 .init_early = omap_4430sdp_init_early,
774 .init_irq = gic_init_irq, 765 .init_irq = gic_init_irq,
775 .init_machine = omap_4430sdp_init, 766 .init_machine = omap_4430sdp_init,
776 .timer = &omap_timer, 767 .timer = &omap4_timer,
777MACHINE_END 768MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 5e438a77cd72..5f2b55ff04ff 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
104 .reserve = omap_reserve, 104 .reserve = omap_reserve,
105 .map_io = omap3_map_io, 105 .map_io = omap3_map_io,
106 .init_early = am3517_crane_init_early, 106 .init_early = am3517_crane_init_early,
107 .init_irq = omap_init_irq, 107 .init_irq = omap3_init_irq,
108 .init_machine = am3517_crane_init, 108 .init_machine = am3517_crane_init,
109 .timer = &omap_timer, 109 .timer = &omap3_timer,
110MACHINE_END 110MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 63af4171c043..f3006c304150 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
494 .reserve = omap_reserve, 494 .reserve = omap_reserve,
495 .map_io = omap3_map_io, 495 .map_io = omap3_map_io,
496 .init_early = am3517_evm_init_early, 496 .init_early = am3517_evm_init_early,
497 .init_irq = omap_init_irq, 497 .init_irq = omap3_init_irq,
498 .init_machine = am3517_evm_init, 498 .init_machine = am3517_evm_init,
499 .timer = &omap_timer, 499 .timer = &omap3_timer,
500MACHINE_END 500MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b124bdfb4239..70211703ff9f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
354 .reserve = omap_reserve, 354 .reserve = omap_reserve,
355 .map_io = omap_apollon_map_io, 355 .map_io = omap_apollon_map_io,
356 .init_early = omap_apollon_init_early, 356 .init_early = omap_apollon_init_early,
357 .init_irq = omap_init_irq, 357 .init_irq = omap2_init_irq,
358 .init_machine = omap_apollon_init, 358 .init_machine = omap_apollon_init,
359 .timer = &omap_timer, 359 .timer = &omap2_timer,
360MACHINE_END 360MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 77456dec93ea..d76dca788540 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -162,9 +162,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
162static struct omap_nand_platform_data cm_t35_nand_data = { 162static struct omap_nand_platform_data cm_t35_nand_data = {
163 .parts = cm_t35_nand_partitions, 163 .parts = cm_t35_nand_partitions,
164 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), 164 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
165 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
166 .cs = 0, 165 .cs = 0,
167
168}; 166};
169 167
170static void __init cm_t35_init_nand(void) 168static void __init cm_t35_init_nand(void)
@@ -337,19 +335,21 @@ static void __init cm_t35_init_display(void)
337 } 335 }
338} 336}
339 337
340static struct regulator_consumer_supply cm_t35_vmmc1_supply = { 338static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
341 .supply = "vmmc", 339 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
342}; 340};
343 341
344static struct regulator_consumer_supply cm_t35_vsim_supply = { 342static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
345 .supply = "vmmc_aux", 343 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
346}; 344};
347 345
348static struct regulator_consumer_supply cm_t35_vdac_supply = 346static struct regulator_consumer_supply cm_t35_vdac_supply[] = {
349 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 347 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
348};
350 349
351static struct regulator_consumer_supply cm_t35_vdvi_supply = 350static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
352 REGULATOR_SUPPLY("vdvi", "omapdss"); 351 REGULATOR_SUPPLY("vdvi", "omapdss"),
352};
353 353
354/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 354/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
355static struct regulator_init_data cm_t35_vmmc1 = { 355static struct regulator_init_data cm_t35_vmmc1 = {
@@ -362,8 +362,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
362 | REGULATOR_CHANGE_MODE 362 | REGULATOR_CHANGE_MODE
363 | REGULATOR_CHANGE_STATUS, 363 | REGULATOR_CHANGE_STATUS,
364 }, 364 },
365 .num_consumer_supplies = 1, 365 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
366 .consumer_supplies = &cm_t35_vmmc1_supply, 366 .consumer_supplies = cm_t35_vmmc1_supply,
367}; 367};
368 368
369/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 369/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -377,8 +377,8 @@ static struct regulator_init_data cm_t35_vsim = {
377 | REGULATOR_CHANGE_MODE 377 | REGULATOR_CHANGE_MODE
378 | REGULATOR_CHANGE_STATUS, 378 | REGULATOR_CHANGE_STATUS,
379 }, 379 },
380 .num_consumer_supplies = 1, 380 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
381 .consumer_supplies = &cm_t35_vsim_supply, 381 .consumer_supplies = cm_t35_vsim_supply,
382}; 382};
383 383
384/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ 384/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
@@ -391,8 +391,8 @@ static struct regulator_init_data cm_t35_vdac = {
391 .valid_ops_mask = REGULATOR_CHANGE_MODE 391 .valid_ops_mask = REGULATOR_CHANGE_MODE
392 | REGULATOR_CHANGE_STATUS, 392 | REGULATOR_CHANGE_STATUS,
393 }, 393 },
394 .num_consumer_supplies = 1, 394 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdac_supply),
395 .consumer_supplies = &cm_t35_vdac_supply, 395 .consumer_supplies = cm_t35_vdac_supply,
396}; 396};
397 397
398/* VPLL2 for digital video outputs */ 398/* VPLL2 for digital video outputs */
@@ -406,8 +406,8 @@ static struct regulator_init_data cm_t35_vpll2 = {
406 .valid_ops_mask = REGULATOR_CHANGE_MODE 406 .valid_ops_mask = REGULATOR_CHANGE_MODE
407 | REGULATOR_CHANGE_STATUS, 407 | REGULATOR_CHANGE_STATUS,
408 }, 408 },
409 .num_consumer_supplies = 1, 409 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vdvi_supply),
410 .consumer_supplies = &cm_t35_vdvi_supply, 410 .consumer_supplies = cm_t35_vdvi_supply,
411}; 411};
412 412
413static struct twl4030_usb_data cm_t35_usb_data = { 413static struct twl4030_usb_data cm_t35_usb_data = {
@@ -481,10 +481,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
481 mmc[0].gpio_cd = gpio + 0; 481 mmc[0].gpio_cd = gpio + 0;
482 omap2_hsmmc_init(mmc); 482 omap2_hsmmc_init(mmc);
483 483
484 /* link regulators to MMC adapters */
485 cm_t35_vmmc1_supply.dev = mmc[0].dev;
486 cm_t35_vsim_supply.dev = mmc[0].dev;
487
488 return 0; 484 return 0;
489} 485}
490 486
@@ -646,7 +642,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
646 .reserve = omap_reserve, 642 .reserve = omap_reserve,
647 .map_io = omap3_map_io, 643 .map_io = omap3_map_io,
648 .init_early = cm_t35_init_early, 644 .init_early = cm_t35_init_early,
649 .init_irq = omap_init_irq, 645 .init_irq = omap3_init_irq,
650 .init_machine = cm_t35_init, 646 .init_machine = cm_t35_init,
651 .timer = &omap_timer, 647 .timer = &omap3_timer,
652MACHINE_END 648MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index c3a9fd35034a..05c72f4c1b57 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
236static struct omap_nand_platform_data cm_t3517_nand_data = { 236static struct omap_nand_platform_data cm_t3517_nand_data = {
237 .parts = cm_t3517_nand_partitions, 237 .parts = cm_t3517_nand_partitions,
238 .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), 238 .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
239 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
240 .cs = 0, 239 .cs = 0,
241}; 240};
242 241
@@ -304,7 +303,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
304 .reserve = omap_reserve, 303 .reserve = omap_reserve,
305 .map_io = omap3_map_io, 304 .map_io = omap3_map_io,
306 .init_early = cm_t3517_init_early, 305 .init_early = cm_t3517_init_early,
307 .init_irq = omap_init_irq, 306 .init_irq = omap3_init_irq,
308 .init_machine = cm_t3517_init, 307 .init_machine = cm_t3517_init,
309 .timer = &omap_timer, 308 .timer = &omap3_timer,
310MACHINE_END 309MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 34956ec83296..949dbeabab26 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -58,7 +58,6 @@
58 58
59#include "mux.h" 59#include "mux.h"
60#include "hsmmc.h" 60#include "hsmmc.h"
61#include "timer-gp.h"
62#include "common-board-devices.h" 61#include "common-board-devices.h"
63 62
64#define OMAP_DM9000_GPIO_IRQ 25 63#define OMAP_DM9000_GPIO_IRQ 25
@@ -130,13 +129,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
130 gpio_set_value_cansleep(dssdev->reset_gpio, 0); 129 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
131} 130}
132 131
133static struct regulator_consumer_supply devkit8000_vmmc1_supply = 132static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
134 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 133 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
135 134};
136 135
137/* ads7846 on SPI */ 136/* ads7846 on SPI */
138static struct regulator_consumer_supply devkit8000_vio_supply = 137static struct regulator_consumer_supply devkit8000_vio_supply[] = {
139 REGULATOR_SUPPLY("vcc", "spi2.0"); 138 REGULATOR_SUPPLY("vcc", "spi2.0"),
139};
140 140
141static struct panel_generic_dpi_data lcd_panel = { 141static struct panel_generic_dpi_data lcd_panel = {
142 .name = "generic", 142 .name = "generic",
@@ -186,8 +186,9 @@ static struct omap_dss_board_info devkit8000_dss_data = {
186 .default_device = &devkit8000_lcd_device, 186 .default_device = &devkit8000_lcd_device,
187}; 187};
188 188
189static struct regulator_consumer_supply devkit8000_vdda_dac_supply = 189static struct regulator_consumer_supply devkit8000_vdda_dac_supply[] = {
190 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 190 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
191};
191 192
192static uint32_t board_keymap[] = { 193static uint32_t board_keymap[] = {
193 KEY(0, 0, KEY_1), 194 KEY(0, 0, KEY_1),
@@ -284,8 +285,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
284 | REGULATOR_CHANGE_MODE 285 | REGULATOR_CHANGE_MODE
285 | REGULATOR_CHANGE_STATUS, 286 | REGULATOR_CHANGE_STATUS,
286 }, 287 },
287 .num_consumer_supplies = 1, 288 .num_consumer_supplies = ARRAY_SIZE(devkit8000_vmmc1_supply),
288 .consumer_supplies = &devkit8000_vmmc1_supply, 289 .consumer_supplies = devkit8000_vmmc1_supply,
289}; 290};
290 291
291/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ 292/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
@@ -298,8 +299,8 @@ static struct regulator_init_data devkit8000_vdac = {
298 .valid_ops_mask = REGULATOR_CHANGE_MODE 299 .valid_ops_mask = REGULATOR_CHANGE_MODE
299 | REGULATOR_CHANGE_STATUS, 300 | REGULATOR_CHANGE_STATUS,
300 }, 301 },
301 .num_consumer_supplies = 1, 302 .num_consumer_supplies = ARRAY_SIZE(devkit8000_vdda_dac_supply),
302 .consumer_supplies = &devkit8000_vdda_dac_supply, 303 .consumer_supplies = devkit8000_vdda_dac_supply,
303}; 304};
304 305
305/* VPLL1 for digital video outputs */ 306/* VPLL1 for digital video outputs */
@@ -327,8 +328,8 @@ static struct regulator_init_data devkit8000_vio = {
327 .valid_ops_mask = REGULATOR_CHANGE_MODE 328 .valid_ops_mask = REGULATOR_CHANGE_MODE
328 | REGULATOR_CHANGE_STATUS, 329 | REGULATOR_CHANGE_STATUS,
329 }, 330 },
330 .num_consumer_supplies = 1, 331 .num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supply),
331 .consumer_supplies = &devkit8000_vio_supply, 332 .consumer_supplies = devkit8000_vio_supply,
332}; 333};
333 334
334static struct twl4030_usb_data devkit8000_usb_data = { 335static struct twl4030_usb_data devkit8000_usb_data = {
@@ -438,10 +439,7 @@ static void __init devkit8000_init_early(void)
438 439
439static void __init devkit8000_init_irq(void) 440static void __init devkit8000_init_irq(void)
440{ 441{
441 omap_init_irq(); 442 omap3_init_irq();
442#ifdef CONFIG_OMAP_32K_TIMER
443 omap2_gp_clockevent_set_gptimer(12);
444#endif
445} 443}
446 444
447#define OMAP_DM9000_BASE 0x2c000000 445#define OMAP_DM9000_BASE 0x2c000000
@@ -707,5 +705,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
707 .init_early = devkit8000_init_early, 705 .init_early = devkit8000_init_early,
708 .init_irq = devkit8000_init_irq, 706 .init_irq = devkit8000_init_irq,
709 .init_machine = devkit8000_init, 707 .init_machine = devkit8000_init,
710 .timer = &omap_timer, 708 .timer = &omap3_secure_timer,
711MACHINE_END 709MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 729892fdcf2e..aa1b0cbe19d2 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
132}; 132};
133 133
134static struct omap_nand_platform_data board_nand_data = { 134static struct omap_nand_platform_data board_nand_data = {
135 .nand_setup = NULL,
136 .gpmc_t = &nand_timings, 135 .gpmc_t = &nand_timings,
137 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
138 .dev_ready = NULL,
139 .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
140}; 136};
141 137
142void 138void
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 73e3c31e8508..c6ecf607ebd6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
70 .reserve = omap_reserve, 70 .reserve = omap_reserve,
71 .map_io = omap_generic_map_io, 71 .map_io = omap_generic_map_io,
72 .init_early = omap_generic_init_early, 72 .init_early = omap_generic_init_early,
73 .init_irq = omap_init_irq, 73 .init_irq = omap2_init_irq,
74 .init_machine = omap_generic_init, 74 .init_machine = omap_generic_init,
75 .timer = &omap_timer, 75 .timer = &omap3_timer,
76MACHINE_END 76MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bac7933b8cbb..45de2b319ec9 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
298 298
299static void __init omap_h4_init_irq(void) 299static void __init omap_h4_init_irq(void)
300{ 300{
301 omap_init_irq(); 301 omap2_init_irq();
302} 302}
303 303
304static struct at24_platform_data m24c01 = { 304static struct at24_platform_data m24c01 = {
@@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
388 .init_early = omap_h4_init_early, 388 .init_early = omap_h4_init_early,
389 .init_irq = omap_h4_init_irq, 389 .init_irq = omap_h4_init_irq,
390 .init_machine = omap_h4_init, 390 .init_machine = omap_h4_init,
391 .timer = &omap_timer, 391 .timer = &omap2_timer,
392MACHINE_END 392MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0c1bfca3f731..f683835f936c 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
222static inline void __init igep2_init_smsc911x(void) { } 222static inline void __init igep2_init_smsc911x(void) { }
223#endif 223#endif
224 224
225static struct regulator_consumer_supply igep_vmmc1_supply = 225static struct regulator_consumer_supply igep_vmmc1_supply[] = {
226 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 226 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
227};
227 228
228/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 229/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
229static struct regulator_init_data igep_vmmc1 = { 230static struct regulator_init_data igep_vmmc1 = {
@@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
236 | REGULATOR_CHANGE_MODE 237 | REGULATOR_CHANGE_MODE
237 | REGULATOR_CHANGE_STATUS, 238 | REGULATOR_CHANGE_STATUS,
238 }, 239 },
239 .num_consumer_supplies = 1, 240 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
240 .consumer_supplies = &igep_vmmc1_supply, 241 .consumer_supplies = igep_vmmc1_supply,
241}; 242};
242 243
243static struct regulator_consumer_supply igep_vio_supply = 244static struct regulator_consumer_supply igep_vio_supply[] = {
244 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); 245 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
246};
245 247
246static struct regulator_init_data igep_vio = { 248static struct regulator_init_data igep_vio = {
247 .constraints = { 249 .constraints = {
@@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
254 | REGULATOR_CHANGE_MODE 256 | REGULATOR_CHANGE_MODE
255 | REGULATOR_CHANGE_STATUS, 257 | REGULATOR_CHANGE_STATUS,
256 }, 258 },
257 .num_consumer_supplies = 1, 259 .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
258 .consumer_supplies = &igep_vio_supply, 260 .consumer_supplies = igep_vio_supply,
259}; 261};
260 262
261static struct regulator_consumer_supply igep_vmmc2_supply = 263static struct regulator_consumer_supply igep_vmmc2_supply[] = {
262 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 264 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
265};
263 266
264static struct regulator_init_data igep_vmmc2 = { 267static struct regulator_init_data igep_vmmc2 = {
265 .constraints = { 268 .constraints = {
266 .valid_modes_mask = REGULATOR_MODE_NORMAL, 269 .valid_modes_mask = REGULATOR_MODE_NORMAL,
267 .always_on = 1, 270 .always_on = 1,
268 }, 271 },
269 .num_consumer_supplies = 1, 272 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
270 .consumer_supplies = &igep_vmmc2_supply, 273 .consumer_supplies = igep_vmmc2_supply,
271}; 274};
272 275
273static struct fixed_voltage_config igep_vwlan = { 276static struct fixed_voltage_config igep_vwlan = {
@@ -703,9 +706,9 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
703 .reserve = omap_reserve, 706 .reserve = omap_reserve,
704 .map_io = omap3_map_io, 707 .map_io = omap3_map_io,
705 .init_early = igep_init_early, 708 .init_early = igep_init_early,
706 .init_irq = omap_init_irq, 709 .init_irq = omap3_init_irq,
707 .init_machine = igep_init, 710 .init_machine = igep_init,
708 .timer = &omap_timer, 711 .timer = &omap3_timer,
709MACHINE_END 712MACHINE_END
710 713
711MACHINE_START(IGEP0030, "IGEP OMAP3 module") 714MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -713,7 +716,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
713 .reserve = omap_reserve, 716 .reserve = omap_reserve,
714 .map_io = omap3_map_io, 717 .map_io = omap3_map_io,
715 .init_early = igep_init_early, 718 .init_early = igep_init_early,
716 .init_irq = omap_init_irq, 719 .init_irq = omap3_init_irq,
717 .init_machine = igep_init, 720 .init_machine = igep_init,
718 .timer = &omap_timer, 721 .timer = &omap3_timer,
719MACHINE_END 722MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f7d6038075f0..5d4328f19c0f 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -213,8 +213,8 @@ static struct twl4030_madc_platform_data ldp_madc_data = {
213 .irq_line = 1, 213 .irq_line = 1,
214}; 214};
215 215
216static struct regulator_consumer_supply ldp_vmmc1_supply = { 216static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
217 .supply = "vmmc", 217 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
218}; 218};
219 219
220/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 220/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -228,8 +228,8 @@ static struct regulator_init_data ldp_vmmc1 = {
228 | REGULATOR_CHANGE_MODE 228 | REGULATOR_CHANGE_MODE
229 | REGULATOR_CHANGE_STATUS, 229 | REGULATOR_CHANGE_STATUS,
230 }, 230 },
231 .num_consumer_supplies = 1, 231 .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
232 .consumer_supplies = &ldp_vmmc1_supply, 232 .consumer_supplies = ldp_vmmc1_supply,
233}; 233};
234 234
235/* ads7846 on SPI */ 235/* ads7846 on SPI */
@@ -341,8 +341,6 @@ static void __init omap_ldp_init(void)
341 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); 341 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
342 342
343 omap2_hsmmc_init(mmc); 343 omap2_hsmmc_init(mmc);
344 /* link regulators to MMC adapters */
345 ldp_vmmc1_supply.dev = mmc[0].dev;
346} 344}
347 345
348MACHINE_START(OMAP_LDP, "OMAP LDP board") 346MACHINE_START(OMAP_LDP, "OMAP LDP board")
@@ -350,7 +348,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
350 .reserve = omap_reserve, 348 .reserve = omap_reserve,
351 .map_io = omap3_map_io, 349 .map_io = omap3_map_io,
352 .init_early = omap_ldp_init_early, 350 .init_early = omap_ldp_init_early,
353 .init_irq = omap_init_irq, 351 .init_irq = omap3_init_irq,
354 .init_machine = omap_ldp_init, 352 .init_machine = omap_ldp_init,
355 .timer = &omap_timer, 353 .timer = &omap3_timer,
356MACHINE_END 354MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8d74318ed495..e11f0c5d608a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -699,9 +699,9 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
699 .reserve = omap_reserve, 699 .reserve = omap_reserve,
700 .map_io = n8x0_map_io, 700 .map_io = n8x0_map_io,
701 .init_early = n8x0_init_early, 701 .init_early = n8x0_init_early,
702 .init_irq = omap_init_irq, 702 .init_irq = omap2_init_irq,
703 .init_machine = n8x0_init_machine, 703 .init_machine = n8x0_init_machine,
704 .timer = &omap_timer, 704 .timer = &omap2_timer,
705MACHINE_END 705MACHINE_END
706 706
707MACHINE_START(NOKIA_N810, "Nokia N810") 707MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -709,9 +709,9 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
709 .reserve = omap_reserve, 709 .reserve = omap_reserve,
710 .map_io = n8x0_map_io, 710 .map_io = n8x0_map_io,
711 .init_early = n8x0_init_early, 711 .init_early = n8x0_init_early,
712 .init_irq = omap_init_irq, 712 .init_irq = omap2_init_irq,
713 .init_machine = n8x0_init_machine, 713 .init_machine = n8x0_init_machine,
714 .timer = &omap_timer, 714 .timer = &omap2_timer,
715MACHINE_END 715MACHINE_END
716 716
717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") 717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
719 .reserve = omap_reserve, 719 .reserve = omap_reserve,
720 .map_io = n8x0_map_io, 720 .map_io = n8x0_map_io,
721 .init_early = n8x0_init_early, 721 .init_early = n8x0_init_early,
722 .init_irq = omap_init_irq, 722 .init_irq = omap2_init_irq,
723 .init_machine = n8x0_init_machine, 723 .init_machine = n8x0_init_machine,
724 .timer = &omap_timer, 724 .timer = &omap2_timer,
725MACHINE_END 725MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7f21d24bd437..2d8dfb3213bf 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -50,7 +50,6 @@
50 50
51#include "mux.h" 51#include "mux.h"
52#include "hsmmc.h" 52#include "hsmmc.h"
53#include "timer-gp.h"
54#include "pm.h" 53#include "pm.h"
55#include "common-board-devices.h" 54#include "common-board-devices.h"
56 55
@@ -210,8 +209,9 @@ static struct omap_dss_board_info beagle_dss_data = {
210 .default_device = &beagle_dvi_device, 209 .default_device = &beagle_dvi_device,
211}; 210};
212 211
213static struct regulator_consumer_supply beagle_vdac_supply = 212static struct regulator_consumer_supply beagle_vdac_supply[] = {
214 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 213 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
214};
215 215
216static struct regulator_consumer_supply beagle_vdvi_supplies[] = { 216static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
217 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 217 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
@@ -239,12 +239,12 @@ static struct omap2_hsmmc_info mmc[] = {
239 {} /* Terminator */ 239 {} /* Terminator */
240}; 240};
241 241
242static struct regulator_consumer_supply beagle_vmmc1_supply = { 242static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
243 .supply = "vmmc", 243 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
244}; 244};
245 245
246static struct regulator_consumer_supply beagle_vsim_supply = { 246static struct regulator_consumer_supply beagle_vsim_supply[] = {
247 .supply = "vmmc_aux", 247 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
248}; 248};
249 249
250static struct gpio_led gpio_leds[]; 250static struct gpio_led gpio_leds[];
@@ -267,10 +267,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
267 mmc[0].gpio_cd = gpio + 0; 267 mmc[0].gpio_cd = gpio + 0;
268 omap2_hsmmc_init(mmc); 268 omap2_hsmmc_init(mmc);
269 269
270 /* link regulators to MMC adapters */
271 beagle_vmmc1_supply.dev = mmc[0].dev;
272 beagle_vsim_supply.dev = mmc[0].dev;
273
274 /* 270 /*
275 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active 271 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
276 * high / others active low) 272 * high / others active low)
@@ -336,8 +332,8 @@ static struct regulator_init_data beagle_vmmc1 = {
336 | REGULATOR_CHANGE_MODE 332 | REGULATOR_CHANGE_MODE
337 | REGULATOR_CHANGE_STATUS, 333 | REGULATOR_CHANGE_STATUS,
338 }, 334 },
339 .num_consumer_supplies = 1, 335 .num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
340 .consumer_supplies = &beagle_vmmc1_supply, 336 .consumer_supplies = beagle_vmmc1_supply,
341}; 337};
342 338
343/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 339/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -351,8 +347,8 @@ static struct regulator_init_data beagle_vsim = {
351 | REGULATOR_CHANGE_MODE 347 | REGULATOR_CHANGE_MODE
352 | REGULATOR_CHANGE_STATUS, 348 | REGULATOR_CHANGE_STATUS,
353 }, 349 },
354 .num_consumer_supplies = 1, 350 .num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
355 .consumer_supplies = &beagle_vsim_supply, 351 .consumer_supplies = beagle_vsim_supply,
356}; 352};
357 353
358/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ 354/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
@@ -365,8 +361,8 @@ static struct regulator_init_data beagle_vdac = {
365 .valid_ops_mask = REGULATOR_CHANGE_MODE 361 .valid_ops_mask = REGULATOR_CHANGE_MODE
366 | REGULATOR_CHANGE_STATUS, 362 | REGULATOR_CHANGE_STATUS,
367 }, 363 },
368 .num_consumer_supplies = 1, 364 .num_consumer_supplies = ARRAY_SIZE(beagle_vdac_supply),
369 .consumer_supplies = &beagle_vdac_supply, 365 .consumer_supplies = beagle_vdac_supply,
370}; 366};
371 367
372/* VPLL2 for digital video outputs */ 368/* VPLL2 for digital video outputs */
@@ -486,10 +482,7 @@ static void __init omap3_beagle_init_early(void)
486 482
487static void __init omap3_beagle_init_irq(void) 483static void __init omap3_beagle_init_irq(void)
488{ 484{
489 omap_init_irq(); 485 omap3_init_irq();
490#ifdef CONFIG_OMAP_32K_TIMER
491 omap2_gp_clockevent_set_gptimer(12);
492#endif
493} 486}
494 487
495static struct platform_device *omap3_beagle_devices[] __initdata = { 488static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -599,5 +592,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
599 .init_early = omap3_beagle_init_early, 592 .init_early = omap3_beagle_init_early,
600 .init_irq = omap3_beagle_init_irq, 593 .init_irq = omap3_beagle_init_irq,
601 .init_machine = omap3_beagle_init, 594 .init_machine = omap3_beagle_init,
602 .timer = &omap_timer, 595 .timer = &omap3_secure_timer,
603MACHINE_END 596MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b4d43464a303..57bce0f2e195 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
273 .default_device = &omap3_evm_lcd_device, 273 .default_device = &omap3_evm_lcd_device,
274}; 274};
275 275
276static struct regulator_consumer_supply omap3evm_vmmc1_supply = { 276static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
277 .supply = "vmmc", 277 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
278}; 278};
279 279
280static struct regulator_consumer_supply omap3evm_vsim_supply = { 280static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
281 .supply = "vmmc_aux", 281 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
282}; 282};
283 283
284/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 284/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
292 | REGULATOR_CHANGE_MODE 292 | REGULATOR_CHANGE_MODE
293 | REGULATOR_CHANGE_STATUS, 293 | REGULATOR_CHANGE_STATUS,
294 }, 294 },
295 .num_consumer_supplies = 1, 295 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
296 .consumer_supplies = &omap3evm_vmmc1_supply, 296 .consumer_supplies = omap3evm_vmmc1_supply,
297}; 297};
298 298
299/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 299/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
307 | REGULATOR_CHANGE_MODE 307 | REGULATOR_CHANGE_MODE
308 | REGULATOR_CHANGE_STATUS, 308 | REGULATOR_CHANGE_STATUS,
309 }, 309 },
310 .num_consumer_supplies = 1, 310 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
311 .consumer_supplies = &omap3evm_vsim_supply, 311 .consumer_supplies = omap3evm_vsim_supply,
312}; 312};
313 313
314static struct omap2_hsmmc_info mmc[] = { 314static struct omap2_hsmmc_info mmc[] = {
@@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
365 mmc[0].gpio_cd = gpio + 0; 365 mmc[0].gpio_cd = gpio + 0;
366 omap2_hsmmc_init(mmc); 366 omap2_hsmmc_init(mmc);
367 367
368 /* link regulators to MMC adapters */
369 omap3evm_vmmc1_supply.dev = mmc[0].dev;
370 omap3evm_vsim_supply.dev = mmc[0].dev;
371
372 /* 368 /*
373 * Most GPIOs are for USB OTG. Some are mostly sent to 369 * Most GPIOs are for USB OTG. Some are mostly sent to
374 * the P2 connector; notably LEDA for the LCD backlight. 370 * the P2 connector; notably LEDA for the LCD backlight.
@@ -449,8 +445,9 @@ static struct twl4030_codec_data omap3evm_codec_data = {
449 .audio = &omap3evm_audio_data, 445 .audio = &omap3evm_audio_data,
450}; 446};
451 447
452static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = 448static struct regulator_consumer_supply omap3_evm_vdda_dac_supply[] = {
453 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 449 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
450};
454 451
455/* VDAC for DSS driving S-Video */ 452/* VDAC for DSS driving S-Video */
456static struct regulator_init_data omap3_evm_vdac = { 453static struct regulator_init_data omap3_evm_vdac = {
@@ -463,8 +460,8 @@ static struct regulator_init_data omap3_evm_vdac = {
463 .valid_ops_mask = REGULATOR_CHANGE_MODE 460 .valid_ops_mask = REGULATOR_CHANGE_MODE
464 | REGULATOR_CHANGE_STATUS, 461 | REGULATOR_CHANGE_STATUS,
465 }, 462 },
466 .num_consumer_supplies = 1, 463 .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vdda_dac_supply),
467 .consumer_supplies = &omap3_evm_vdda_dac_supply, 464 .consumer_supplies = omap3_evm_vdda_dac_supply,
468}; 465};
469 466
470/* VPLL2 for digital video outputs */ 467/* VPLL2 for digital video outputs */
@@ -488,8 +485,9 @@ static struct regulator_init_data omap3_evm_vpll2 = {
488}; 485};
489 486
490/* ads7846 on SPI */ 487/* ads7846 on SPI */
491static struct regulator_consumer_supply omap3evm_vio_supply = 488static struct regulator_consumer_supply omap3evm_vio_supply[] = {
492 REGULATOR_SUPPLY("vcc", "spi1.0"); 489 REGULATOR_SUPPLY("vcc", "spi1.0"),
490};
493 491
494/* VIO for ads7846 */ 492/* VIO for ads7846 */
495static struct regulator_init_data omap3evm_vio = { 493static struct regulator_init_data omap3evm_vio = {
@@ -502,8 +500,8 @@ static struct regulator_init_data omap3evm_vio = {
502 .valid_ops_mask = REGULATOR_CHANGE_MODE 500 .valid_ops_mask = REGULATOR_CHANGE_MODE
503 | REGULATOR_CHANGE_STATUS, 501 | REGULATOR_CHANGE_STATUS,
504 }, 502 },
505 .num_consumer_supplies = 1, 503 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
506 .consumer_supplies = &omap3evm_vio_supply, 504 .consumer_supplies = omap3evm_vio_supply,
507}; 505};
508 506
509#ifdef CONFIG_WL12XX_PLATFORM_DATA 507#ifdef CONFIG_WL12XX_PLATFORM_DATA
@@ -511,16 +509,17 @@ static struct regulator_init_data omap3evm_vio = {
511#define OMAP3EVM_WLAN_PMENA_GPIO (150) 509#define OMAP3EVM_WLAN_PMENA_GPIO (150)
512#define OMAP3EVM_WLAN_IRQ_GPIO (149) 510#define OMAP3EVM_WLAN_IRQ_GPIO (149)
513 511
514static struct regulator_consumer_supply omap3evm_vmmc2_supply = 512static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
515 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 513 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
514};
516 515
517/* VMMC2 for driving the WL12xx module */ 516/* VMMC2 for driving the WL12xx module */
518static struct regulator_init_data omap3evm_vmmc2 = { 517static struct regulator_init_data omap3evm_vmmc2 = {
519 .constraints = { 518 .constraints = {
520 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 519 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
521 }, 520 },
522 .num_consumer_supplies = 1, 521 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
523 .consumer_supplies = &omap3evm_vmmc2_supply, 522 .consumer_supplies = omap3evm_vmmc2_supply,
524}; 523};
525 524
526static struct fixed_voltage_config omap3evm_vwlan = { 525static struct fixed_voltage_config omap3evm_vwlan = {
@@ -740,7 +739,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
740 .reserve = omap_reserve, 739 .reserve = omap_reserve,
741 .map_io = omap3_map_io, 740 .map_io = omap3_map_io,
742 .init_early = omap3_evm_init_early, 741 .init_early = omap3_evm_init_early,
743 .init_irq = omap_init_irq, 742 .init_irq = omap3_init_irq,
744 .init_machine = omap3_evm_init, 743 .init_machine = omap3_evm_init,
745 .timer = &omap_timer, 744 .timer = &omap3_timer,
746MACHINE_END 745MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 60d9be49dbab..703aeb5b8fd4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -35,7 +35,6 @@
35 35
36#include "mux.h" 36#include "mux.h"
37#include "hsmmc.h" 37#include "hsmmc.h"
38#include "timer-gp.h"
39#include "control.h" 38#include "control.h"
40#include "common-board-devices.h" 39#include "common-board-devices.h"
41 40
@@ -55,8 +54,8 @@
55#define OMAP3_TORPEDO_MMC_GPIO_CD 127 54#define OMAP3_TORPEDO_MMC_GPIO_CD 127
56#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 55#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
57 56
58static struct regulator_consumer_supply omap3logic_vmmc1_supply = { 57static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
59 .supply = "vmmc", 58 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
60}; 59};
61 60
62/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 61/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -71,8 +70,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
71 | REGULATOR_CHANGE_MODE 70 | REGULATOR_CHANGE_MODE
72 | REGULATOR_CHANGE_STATUS, 71 | REGULATOR_CHANGE_STATUS,
73 }, 72 },
74 .num_consumer_supplies = 1, 73 .num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
75 .consumer_supplies = &omap3logic_vmmc1_supply, 74 .consumer_supplies = omap3logic_vmmc1_supply,
76}; 75};
77 76
78static struct twl4030_gpio_platform_data omap3logic_gpio_data = { 77static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
@@ -130,8 +129,6 @@ static void __init board_mmc_init(void)
130 } 129 }
131 130
132 omap2_hsmmc_init(board_mmc_info); 131 omap2_hsmmc_init(board_mmc_info);
133 /* link regulators to MMC adapters */
134 omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
135} 132}
136 133
137static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { 134static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -215,16 +212,16 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
215 .boot_params = 0x80000100, 212 .boot_params = 0x80000100,
216 .map_io = omap3_map_io, 213 .map_io = omap3_map_io,
217 .init_early = omap3logic_init_early, 214 .init_early = omap3logic_init_early,
218 .init_irq = omap_init_irq, 215 .init_irq = omap3_init_irq,
219 .init_machine = omap3logic_init, 216 .init_machine = omap3logic_init,
220 .timer = &omap_timer, 217 .timer = &omap3_timer,
221MACHINE_END 218MACHINE_END
222 219
223MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") 220MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
224 .boot_params = 0x80000100, 221 .boot_params = 0x80000100,
225 .map_io = omap3_map_io, 222 .map_io = omap3_map_io,
226 .init_early = omap3logic_init_early, 223 .init_early = omap3logic_init_early,
227 .init_irq = omap_init_irq, 224 .init_irq = omap3_init_irq,
228 .init_machine = omap3logic_init, 225 .init_machine = omap3logic_init,
229 .timer = &omap_timer, 226 .timer = &omap3_timer,
230MACHINE_END 227MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 23f71d40883e..d4ea9408560e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -320,17 +320,21 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
320 .setup = omap3pandora_twl_gpio_setup, 320 .setup = omap3pandora_twl_gpio_setup,
321}; 321};
322 322
323static struct regulator_consumer_supply pandora_vmmc1_supply = 323static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
324 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 324 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
325};
325 326
326static struct regulator_consumer_supply pandora_vmmc2_supply = 327static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
327 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 328 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
329};
328 330
329static struct regulator_consumer_supply pandora_vmmc3_supply = 331static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
330 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); 332 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
333};
331 334
332static struct regulator_consumer_supply pandora_vdda_dac_supply = 335static struct regulator_consumer_supply pandora_vdda_dac_supply[] = {
333 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 336 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
337};
334 338
335static struct regulator_consumer_supply pandora_vdds_supplies[] = { 339static struct regulator_consumer_supply pandora_vdds_supplies[] = {
336 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 340 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
@@ -338,11 +342,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
338 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), 342 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
339}; 343};
340 344
341static struct regulator_consumer_supply pandora_vcc_lcd_supply = 345static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
342 REGULATOR_SUPPLY("vcc", "display0"); 346 REGULATOR_SUPPLY("vcc", "display0"),
347};
343 348
344static struct regulator_consumer_supply pandora_usb_phy_supply = 349static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
345 REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"); 350 REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
351};
346 352
347/* ads7846 on SPI and 2 nub controllers on I2C */ 353/* ads7846 on SPI and 2 nub controllers on I2C */
348static struct regulator_consumer_supply pandora_vaux4_supplies[] = { 354static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
@@ -351,8 +357,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
351 REGULATOR_SUPPLY("vcc", "3-0067"), 357 REGULATOR_SUPPLY("vcc", "3-0067"),
352}; 358};
353 359
354static struct regulator_consumer_supply pandora_adac_supply = 360static struct regulator_consumer_supply pandora_adac_supply[] = {
355 REGULATOR_SUPPLY("vcc", "soc-audio"); 361 REGULATOR_SUPPLY("vcc", "soc-audio"),
362};
356 363
357/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 364/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
358static struct regulator_init_data pandora_vmmc1 = { 365static struct regulator_init_data pandora_vmmc1 = {
@@ -365,8 +372,8 @@ static struct regulator_init_data pandora_vmmc1 = {
365 | REGULATOR_CHANGE_MODE 372 | REGULATOR_CHANGE_MODE
366 | REGULATOR_CHANGE_STATUS, 373 | REGULATOR_CHANGE_STATUS,
367 }, 374 },
368 .num_consumer_supplies = 1, 375 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply),
369 .consumer_supplies = &pandora_vmmc1_supply, 376 .consumer_supplies = pandora_vmmc1_supply,
370}; 377};
371 378
372/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */ 379/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
@@ -380,8 +387,8 @@ static struct regulator_init_data pandora_vmmc2 = {
380 | REGULATOR_CHANGE_MODE 387 | REGULATOR_CHANGE_MODE
381 | REGULATOR_CHANGE_STATUS, 388 | REGULATOR_CHANGE_STATUS,
382 }, 389 },
383 .num_consumer_supplies = 1, 390 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply),
384 .consumer_supplies = &pandora_vmmc2_supply, 391 .consumer_supplies = pandora_vmmc2_supply,
385}; 392};
386 393
387/* VDAC for DSS driving S-Video */ 394/* VDAC for DSS driving S-Video */
@@ -395,8 +402,8 @@ static struct regulator_init_data pandora_vdac = {
395 .valid_ops_mask = REGULATOR_CHANGE_MODE 402 .valid_ops_mask = REGULATOR_CHANGE_MODE
396 | REGULATOR_CHANGE_STATUS, 403 | REGULATOR_CHANGE_STATUS,
397 }, 404 },
398 .num_consumer_supplies = 1, 405 .num_consumer_supplies = ARRAY_SIZE(pandora_vdda_dac_supply),
399 .consumer_supplies = &pandora_vdda_dac_supply, 406 .consumer_supplies = pandora_vdda_dac_supply,
400}; 407};
401 408
402/* VPLL2 for digital video outputs */ 409/* VPLL2 for digital video outputs */
@@ -425,8 +432,8 @@ static struct regulator_init_data pandora_vaux1 = {
425 .valid_ops_mask = REGULATOR_CHANGE_MODE 432 .valid_ops_mask = REGULATOR_CHANGE_MODE
426 | REGULATOR_CHANGE_STATUS, 433 | REGULATOR_CHANGE_STATUS,
427 }, 434 },
428 .num_consumer_supplies = 1, 435 .num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply),
429 .consumer_supplies = &pandora_vcc_lcd_supply, 436 .consumer_supplies = pandora_vcc_lcd_supply,
430}; 437};
431 438
432/* VAUX2 for USB host PHY */ 439/* VAUX2 for USB host PHY */
@@ -440,8 +447,8 @@ static struct regulator_init_data pandora_vaux2 = {
440 .valid_ops_mask = REGULATOR_CHANGE_MODE 447 .valid_ops_mask = REGULATOR_CHANGE_MODE
441 | REGULATOR_CHANGE_STATUS, 448 | REGULATOR_CHANGE_STATUS,
442 }, 449 },
443 .num_consumer_supplies = 1, 450 .num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply),
444 .consumer_supplies = &pandora_usb_phy_supply, 451 .consumer_supplies = pandora_usb_phy_supply,
445}; 452};
446 453
447/* VAUX4 for ads7846 and nubs */ 454/* VAUX4 for ads7846 and nubs */
@@ -470,8 +477,8 @@ static struct regulator_init_data pandora_vsim = {
470 .valid_ops_mask = REGULATOR_CHANGE_MODE 477 .valid_ops_mask = REGULATOR_CHANGE_MODE
471 | REGULATOR_CHANGE_STATUS, 478 | REGULATOR_CHANGE_STATUS,
472 }, 479 },
473 .num_consumer_supplies = 1, 480 .num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply),
474 .consumer_supplies = &pandora_adac_supply, 481 .consumer_supplies = pandora_adac_supply,
475}; 482};
476 483
477/* Fixed regulator internal to Wifi module */ 484/* Fixed regulator internal to Wifi module */
@@ -479,8 +486,8 @@ static struct regulator_init_data pandora_vmmc3 = {
479 .constraints = { 486 .constraints = {
480 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 487 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
481 }, 488 },
482 .num_consumer_supplies = 1, 489 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
483 .consumer_supplies = &pandora_vmmc3_supply, 490 .consumer_supplies = pandora_vmmc3_supply,
484}; 491};
485 492
486static struct fixed_voltage_config pandora_vwlan = { 493static struct fixed_voltage_config pandora_vwlan = {
@@ -643,7 +650,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
643 .reserve = omap_reserve, 650 .reserve = omap_reserve,
644 .map_io = omap3_map_io, 651 .map_io = omap3_map_io,
645 .init_early = omap3pandora_init_early, 652 .init_early = omap3pandora_init_early,
646 .init_irq = omap_init_irq, 653 .init_irq = omap3_init_irq,
647 .init_machine = omap3pandora_init, 654 .init_machine = omap3pandora_init,
648 .timer = &omap_timer, 655 .timer = &omap3_timer,
649MACHINE_END 656MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 0c108a212ea2..b8ad4dd5bbbf 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -52,7 +52,6 @@
52#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
53#include "mux.h" 53#include "mux.h"
54#include "hsmmc.h" 54#include "hsmmc.h"
55#include "timer-gp.h"
56#include "common-board-devices.h" 55#include "common-board-devices.h"
57 56
58#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 57#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -206,12 +205,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
206 .default_device = &omap3_stalker_dvi_device, 205 .default_device = &omap3_stalker_dvi_device,
207}; 206};
208 207
209static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { 208static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
210 .supply = "vmmc", 209 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
211}; 210};
212 211
213static struct regulator_consumer_supply omap3stalker_vsim_supply = { 212static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
214 .supply = "vmmc_aux", 213 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
215}; 214};
216 215
217/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 216/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -224,8 +223,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE 223 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
225 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, 224 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
226 }, 225 },
227 .num_consumer_supplies = 1, 226 .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vmmc1_supply),
228 .consumer_supplies = &omap3stalker_vmmc1_supply, 227 .consumer_supplies = omap3stalker_vmmc1_supply,
229}; 228};
230 229
231/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 230/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -238,8 +237,8 @@ static struct regulator_init_data omap3stalker_vsim = {
238 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE 237 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
239 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, 238 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
240 }, 239 },
241 .num_consumer_supplies = 1, 240 .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vsim_supply),
242 .consumer_supplies = &omap3stalker_vsim_supply, 241 .consumer_supplies = omap3stalker_vsim_supply,
243}; 242};
244 243
245static struct omap2_hsmmc_info mmc[] = { 244static struct omap2_hsmmc_info mmc[] = {
@@ -321,10 +320,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
321 mmc[0].gpio_cd = gpio + 0; 320 mmc[0].gpio_cd = gpio + 0;
322 omap2_hsmmc_init(mmc); 321 omap2_hsmmc_init(mmc);
323 322
324 /* link regulators to MMC adapters */
325 omap3stalker_vmmc1_supply.dev = mmc[0].dev;
326 omap3stalker_vsim_supply.dev = mmc[0].dev;
327
328 /* 323 /*
329 * Most GPIOs are for USB OTG. Some are mostly sent to 324 * Most GPIOs are for USB OTG. Some are mostly sent to
330 * the P2 connector; notably LEDA for the LCD backlight. 325 * the P2 connector; notably LEDA for the LCD backlight.
@@ -403,8 +398,9 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
403 .audio = &omap3stalker_audio_data, 398 .audio = &omap3stalker_audio_data,
404}; 399};
405 400
406static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = 401static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply[] = {
407 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 402 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
403};
408 404
409/* VDAC for DSS driving S-Video */ 405/* VDAC for DSS driving S-Video */
410static struct regulator_init_data omap3_stalker_vdac = { 406static struct regulator_init_data omap3_stalker_vdac = {
@@ -417,8 +413,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
417 .valid_ops_mask = REGULATOR_CHANGE_MODE 413 .valid_ops_mask = REGULATOR_CHANGE_MODE
418 | REGULATOR_CHANGE_STATUS, 414 | REGULATOR_CHANGE_STATUS,
419 }, 415 },
420 .num_consumer_supplies = 1, 416 .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vdda_dac_supply),
421 .consumer_supplies = &omap3_stalker_vdda_dac_supply, 417 .consumer_supplies = omap3_stalker_vdda_dac_supply,
422}; 418};
423 419
424/* VPLL2 for digital video outputs */ 420/* VPLL2 for digital video outputs */
@@ -494,10 +490,7 @@ static void __init omap3_stalker_init_early(void)
494 490
495static void __init omap3_stalker_init_irq(void) 491static void __init omap3_stalker_init_irq(void)
496{ 492{
497 omap_init_irq(); 493 omap3_init_irq();
498#ifdef CONFIG_OMAP_32K_TIMER
499 omap2_gp_clockevent_set_gptimer(12);
500#endif
501} 494}
502 495
503static struct platform_device *omap3_stalker_devices[] __initdata = { 496static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -560,5 +553,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
560 .init_early = omap3_stalker_init_early, 553 .init_early = omap3_stalker_init_early,
561 .init_irq = omap3_stalker_init_irq, 554 .init_irq = omap3_stalker_init_irq,
562 .init_machine = omap3_stalker_init, 555 .init_machine = omap3_stalker_init,
563 .timer = &omap_timer, 556 .timer = &omap3_secure_timer,
564MACHINE_END 557MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 5f649faf7377..57e6ed34ebbc 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,7 +51,6 @@
51 51
52#include "mux.h" 52#include "mux.h"
53#include "hsmmc.h" 53#include "hsmmc.h"
54#include "timer-gp.h"
55#include "common-board-devices.h" 54#include "common-board-devices.h"
56 55
57#include <asm/setup.h> 56#include <asm/setup.h>
@@ -114,12 +113,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
114 .ctrl_name = "internal", 113 .ctrl_name = "internal",
115}; 114};
116 115
117static struct regulator_consumer_supply touchbook_vmmc1_supply = { 116static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
118 .supply = "vmmc", 117 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
119}; 118};
120 119
121static struct regulator_consumer_supply touchbook_vsim_supply = { 120static struct regulator_consumer_supply touchbook_vsim_supply[] = {
122 .supply = "vmmc_aux", 121 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
123}; 122};
124 123
125static struct gpio_led gpio_leds[]; 124static struct gpio_led gpio_leds[];
@@ -137,10 +136,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
137 mmc[0].gpio_cd = gpio + 0; 136 mmc[0].gpio_cd = gpio + 0;
138 omap2_hsmmc_init(mmc); 137 omap2_hsmmc_init(mmc);
139 138
140 /* link regulators to MMC adapters */
141 touchbook_vmmc1_supply.dev = mmc[0].dev;
142 touchbook_vsim_supply.dev = mmc[0].dev;
143
144 /* REVISIT: need ehci-omap hooks for external VBUS 139 /* REVISIT: need ehci-omap hooks for external VBUS
145 * power switch and overcurrent detect 140 * power switch and overcurrent detect
146 */ 141 */
@@ -167,14 +162,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
167 .setup = touchbook_twl_gpio_setup, 162 .setup = touchbook_twl_gpio_setup,
168}; 163};
169 164
170static struct regulator_consumer_supply touchbook_vdac_supply = { 165static struct regulator_consumer_supply touchbook_vdac_supply[] = {
166{
171 .supply = "vdac", 167 .supply = "vdac",
172 .dev = &omap3_touchbook_lcd_device.dev, 168 .dev = &omap3_touchbook_lcd_device.dev,
169},
173}; 170};
174 171
175static struct regulator_consumer_supply touchbook_vdvi_supply = { 172static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
173{
176 .supply = "vdvi", 174 .supply = "vdvi",
177 .dev = &omap3_touchbook_lcd_device.dev, 175 .dev = &omap3_touchbook_lcd_device.dev,
176},
178}; 177};
179 178
180/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 179/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -188,8 +187,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
188 | REGULATOR_CHANGE_MODE 187 | REGULATOR_CHANGE_MODE
189 | REGULATOR_CHANGE_STATUS, 188 | REGULATOR_CHANGE_STATUS,
190 }, 189 },
191 .num_consumer_supplies = 1, 190 .num_consumer_supplies = ARRAY_SIZE(touchbook_vmmc1_supply),
192 .consumer_supplies = &touchbook_vmmc1_supply, 191 .consumer_supplies = touchbook_vmmc1_supply,
193}; 192};
194 193
195/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 194/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -203,8 +202,8 @@ static struct regulator_init_data touchbook_vsim = {
203 | REGULATOR_CHANGE_MODE 202 | REGULATOR_CHANGE_MODE
204 | REGULATOR_CHANGE_STATUS, 203 | REGULATOR_CHANGE_STATUS,
205 }, 204 },
206 .num_consumer_supplies = 1, 205 .num_consumer_supplies = ARRAY_SIZE(touchbook_vsim_supply),
207 .consumer_supplies = &touchbook_vsim_supply, 206 .consumer_supplies = touchbook_vsim_supply,
208}; 207};
209 208
210/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ 209/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
@@ -217,8 +216,8 @@ static struct regulator_init_data touchbook_vdac = {
217 .valid_ops_mask = REGULATOR_CHANGE_MODE 216 .valid_ops_mask = REGULATOR_CHANGE_MODE
218 | REGULATOR_CHANGE_STATUS, 217 | REGULATOR_CHANGE_STATUS,
219 }, 218 },
220 .num_consumer_supplies = 1, 219 .num_consumer_supplies = ARRAY_SIZE(touchbook_vdac_supply),
221 .consumer_supplies = &touchbook_vdac_supply, 220 .consumer_supplies = touchbook_vdac_supply,
222}; 221};
223 222
224/* VPLL2 for digital video outputs */ 223/* VPLL2 for digital video outputs */
@@ -232,8 +231,8 @@ static struct regulator_init_data touchbook_vpll2 = {
232 .valid_ops_mask = REGULATOR_CHANGE_MODE 231 .valid_ops_mask = REGULATOR_CHANGE_MODE
233 | REGULATOR_CHANGE_STATUS, 232 | REGULATOR_CHANGE_STATUS,
234 }, 233 },
235 .num_consumer_supplies = 1, 234 .num_consumer_supplies = ARRAY_SIZE(touchbook_vdvi_supply),
236 .consumer_supplies = &touchbook_vdvi_supply, 235 .consumer_supplies = touchbook_vdvi_supply,
237}; 236};
238 237
239static struct twl4030_usb_data touchbook_usb_data = { 238static struct twl4030_usb_data touchbook_usb_data = {
@@ -371,10 +370,7 @@ static void __init omap3_touchbook_init_early(void)
371 370
372static void __init omap3_touchbook_init_irq(void) 371static void __init omap3_touchbook_init_irq(void)
373{ 372{
374 omap_init_irq(); 373 omap3_init_irq();
375#ifdef CONFIG_OMAP_32K_TIMER
376 omap2_gp_clockevent_set_gptimer(12);
377#endif
378} 374}
379 375
380static struct platform_device *omap3_touchbook_devices[] __initdata = { 376static struct platform_device *omap3_touchbook_devices[] __initdata = {
@@ -449,5 +445,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
449 .init_early = omap3_touchbook_init_early, 445 .init_early = omap3_touchbook_init_early,
450 .init_irq = omap3_touchbook_init_irq, 446 .init_irq = omap3_touchbook_init_irq,
451 .init_machine = omap3_touchbook_init, 447 .init_machine = omap3_touchbook_init,
452 .timer = &omap_timer, 448 .timer = &omap3_secure_timer,
453MACHINE_END 449MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe2005cb50..ee2034e37468 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -41,7 +41,6 @@
41#include <plat/usb.h> 41#include <plat/usb.h>
42#include <plat/mmc.h> 42#include <plat/mmc.h>
43#include <video/omap-panel-generic-dpi.h> 43#include <video/omap-panel-generic-dpi.h>
44#include "timer-gp.h"
45 44
46#include "hsmmc.h" 45#include "hsmmc.h"
47#include "control.h" 46#include "control.h"
@@ -183,23 +182,19 @@ static struct omap2_hsmmc_info mmc[] = {
183}; 182};
184 183
185static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { 184static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
186 { 185 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
187 .supply = "vmmc",
188 .dev_name = "omap_hsmmc.0",
189 },
190}; 186};
191 187
192static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { 188static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
193 .supply = "vmmc", 189 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
194 .dev_name = "omap_hsmmc.4",
195}; 190};
196 191
197static struct regulator_init_data panda_vmmc5 = { 192static struct regulator_init_data panda_vmmc5 = {
198 .constraints = { 193 .constraints = {
199 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 194 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
200 }, 195 },
201 .num_consumer_supplies = 1, 196 .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
202 .consumer_supplies = &omap4_panda_vmmc5_supply, 197 .consumer_supplies = omap4_panda_vmmc5_supply,
203}; 198};
204 199
205static struct fixed_voltage_config panda_vwlan = { 200static struct fixed_voltage_config panda_vwlan = {
@@ -312,7 +307,7 @@ static struct regulator_init_data omap4_panda_vmmc = {
312 | REGULATOR_CHANGE_MODE 307 | REGULATOR_CHANGE_MODE
313 | REGULATOR_CHANGE_STATUS, 308 | REGULATOR_CHANGE_STATUS,
314 }, 309 },
315 .num_consumer_supplies = 1, 310 .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc_supply),
316 .consumer_supplies = omap4_panda_vmmc_supply, 311 .consumer_supplies = omap4_panda_vmmc_supply,
317}; 312};
318 313
@@ -716,5 +711,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
716 .init_early = omap4_panda_init_early, 711 .init_early = omap4_panda_init_early,
717 .init_irq = gic_init_irq, 712 .init_irq = gic_init_irq,
718 .init_machine = omap4_panda_init, 713 .init_machine = omap4_panda_init,
719 .timer = &omap_timer, 714 .timer = &omap4_timer,
720MACHINE_END 715MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 175e1ab2b04d..1bf2f39b9d0e 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -74,15 +74,16 @@
74 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 74 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
75 75
76/* fixed regulator for ads7846 */ 76/* fixed regulator for ads7846 */
77static struct regulator_consumer_supply ads7846_supply = 77static struct regulator_consumer_supply ads7846_supply[] = {
78 REGULATOR_SUPPLY("vcc", "spi1.0"); 78 REGULATOR_SUPPLY("vcc", "spi1.0"),
79};
79 80
80static struct regulator_init_data vads7846_regulator = { 81static struct regulator_init_data vads7846_regulator = {
81 .constraints = { 82 .constraints = {
82 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 83 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
83 }, 84 },
84 .num_consumer_supplies = 1, 85 .num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
85 .consumer_supplies = &ads7846_supply, 86 .consumer_supplies = ads7846_supply,
86}; 87};
87 88
88static struct fixed_voltage_config vads7846 = { 89static struct fixed_voltage_config vads7846 = {
@@ -264,8 +265,9 @@ static struct omap_dss_board_info overo_dss_data = {
264 .default_device = &overo_dvi_device, 265 .default_device = &overo_dvi_device,
265}; 266};
266 267
267static struct regulator_consumer_supply overo_vdda_dac_supply = 268static struct regulator_consumer_supply overo_vdda_dac_supply[] = {
268 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 269 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
270};
269 271
270static struct regulator_consumer_supply overo_vdds_dsi_supply[] = { 272static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
271 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 273 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
@@ -319,8 +321,8 @@ static struct omap2_hsmmc_info mmc[] = {
319 {} /* Terminator */ 321 {} /* Terminator */
320}; 322};
321 323
322static struct regulator_consumer_supply overo_vmmc1_supply = { 324static struct regulator_consumer_supply overo_vmmc1_supply[] = {
323 .supply = "vmmc", 325 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
324}; 326};
325 327
326#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 328#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
@@ -415,8 +417,6 @@ static int overo_twl_gpio_setup(struct device *dev,
415{ 417{
416 omap2_hsmmc_init(mmc); 418 omap2_hsmmc_init(mmc);
417 419
418 overo_vmmc1_supply.dev = mmc[0].dev;
419
420#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 420#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
421 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ 421 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
422 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; 422 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -447,8 +447,8 @@ static struct regulator_init_data overo_vmmc1 = {
447 | REGULATOR_CHANGE_MODE 447 | REGULATOR_CHANGE_MODE
448 | REGULATOR_CHANGE_STATUS, 448 | REGULATOR_CHANGE_STATUS,
449 }, 449 },
450 .num_consumer_supplies = 1, 450 .num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
451 .consumer_supplies = &overo_vmmc1_supply, 451 .consumer_supplies = overo_vmmc1_supply,
452}; 452};
453 453
454/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ 454/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
@@ -461,8 +461,8 @@ static struct regulator_init_data overo_vdac = {
461 .valid_ops_mask = REGULATOR_CHANGE_MODE 461 .valid_ops_mask = REGULATOR_CHANGE_MODE
462 | REGULATOR_CHANGE_STATUS, 462 | REGULATOR_CHANGE_STATUS,
463 }, 463 },
464 .num_consumer_supplies = 1, 464 .num_consumer_supplies = ARRAY_SIZE(overo_vdda_dac_supply),
465 .consumer_supplies = &overo_vdda_dac_supply, 465 .consumer_supplies = overo_vdda_dac_supply,
466}; 466};
467 467
468/* VPLL2 for digital video outputs */ 468/* VPLL2 for digital video outputs */
@@ -615,7 +615,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
615 .reserve = omap_reserve, 615 .reserve = omap_reserve,
616 .map_io = omap3_map_io, 616 .map_io = omap3_map_io,
617 .init_early = overo_init_early, 617 .init_early = overo_init_early,
618 .init_irq = omap_init_irq, 618 .init_irq = omap3_init_irq,
619 .init_machine = overo_init, 619 .init_machine = overo_init,
620 .timer = &omap_timer, 620 .timer = &omap3_timer,
621MACHINE_END 621MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 42d10b12da3c..54dceb163415 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -163,7 +163,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
163 .reserve = omap_reserve, 163 .reserve = omap_reserve,
164 .map_io = rm680_map_io, 164 .map_io = rm680_map_io,
165 .init_early = rm680_init_early, 165 .init_early = rm680_init_early,
166 .init_irq = omap_init_irq, 166 .init_irq = omap3_init_irq,
167 .init_machine = rm680_init, 167 .init_machine = rm680_init,
168 .timer = &omap_timer, 168 .timer = &omap3_timer,
169MACHINE_END 169MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 990366726c58..5e559dda3cc3 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -358,14 +358,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
358 {} /* Terminator */ 358 {} /* Terminator */
359}; 359};
360 360
361static struct regulator_consumer_supply rx51_vmmc1_supply = 361static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
362 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 362 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
363};
363 364
364static struct regulator_consumer_supply rx51_vaux3_supply = 365static struct regulator_consumer_supply rx51_vaux3_supply[] = {
365 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 366 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
367};
366 368
367static struct regulator_consumer_supply rx51_vsim_supply = 369static struct regulator_consumer_supply rx51_vsim_supply[] = {
368 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); 370 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
371};
369 372
370static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { 373static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
371 /* tlv320aic3x analog supplies */ 374 /* tlv320aic3x analog supplies */
@@ -452,8 +455,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
452 | REGULATOR_CHANGE_MODE 455 | REGULATOR_CHANGE_MODE
453 | REGULATOR_CHANGE_STATUS, 456 | REGULATOR_CHANGE_STATUS,
454 }, 457 },
455 .num_consumer_supplies = 1, 458 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
456 .consumer_supplies = &rx51_vaux3_supply, 459 .consumer_supplies = rx51_vaux3_supply,
457}; 460};
458 461
459static struct regulator_init_data rx51_vaux4 = { 462static struct regulator_init_data rx51_vaux4 = {
@@ -479,8 +482,8 @@ static struct regulator_init_data rx51_vmmc1 = {
479 | REGULATOR_CHANGE_MODE 482 | REGULATOR_CHANGE_MODE
480 | REGULATOR_CHANGE_STATUS, 483 | REGULATOR_CHANGE_STATUS,
481 }, 484 },
482 .num_consumer_supplies = 1, 485 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
483 .consumer_supplies = &rx51_vmmc1_supply, 486 .consumer_supplies = rx51_vmmc1_supply,
484}; 487};
485 488
486static struct regulator_init_data rx51_vmmc2 = { 489static struct regulator_init_data rx51_vmmc2 = {
@@ -511,8 +514,8 @@ static struct regulator_init_data rx51_vsim = {
511 .valid_ops_mask = REGULATOR_CHANGE_MODE 514 .valid_ops_mask = REGULATOR_CHANGE_MODE
512 | REGULATOR_CHANGE_STATUS, 515 | REGULATOR_CHANGE_STATUS,
513 }, 516 },
514 .num_consumer_supplies = 1, 517 .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
515 .consumer_supplies = &rx51_vsim_supply, 518 .consumer_supplies = rx51_vsim_supply,
516}; 519};
517 520
518static struct regulator_init_data rx51_vdac = { 521static struct regulator_init_data rx51_vdac = {
@@ -526,7 +529,7 @@ static struct regulator_init_data rx51_vdac = {
526 .valid_ops_mask = REGULATOR_CHANGE_MODE 529 .valid_ops_mask = REGULATOR_CHANGE_MODE
527 | REGULATOR_CHANGE_STATUS, 530 | REGULATOR_CHANGE_STATUS,
528 }, 531 },
529 .num_consumer_supplies = 1, 532 .num_consumer_supplies = ARRAY_SIZE(rx51_vdac_supply),
530 .consumer_supplies = rx51_vdac_supply, 533 .consumer_supplies = rx51_vdac_supply,
531}; 534};
532 535
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index fec4cac8fa0a..5ea142f9bc97 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
160 .reserve = rx51_reserve, 160 .reserve = rx51_reserve,
161 .map_io = rx51_map_io, 161 .map_io = rx51_map_io,
162 .init_early = rx51_init_early, 162 .init_early = rx51_init_early,
163 .init_irq = omap_init_irq, 163 .init_irq = omap3_init_irq,
164 .init_machine = rx51_init, 164 .init_machine = rx51_init,
165 .timer = &omap_timer, 165 .timer = &omap3_timer,
166MACHINE_END 166MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 09fa7bfff8d6..a85d5b0b11da 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
33 omap2_init_common_devices(NULL, NULL); 33 omap2_init_common_devices(NULL, NULL);
34} 34}
35 35
36static void __init ti8168_evm_init_irq(void)
37{
38 omap_init_irq();
39}
40
41static void __init ti8168_evm_init(void) 36static void __init ti8168_evm_init(void)
42{ 37{
43 omap_serial_init(); 38 omap_serial_init();
@@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
56 .boot_params = 0x80000100, 51 .boot_params = 0x80000100,
57 .map_io = ti8168_evm_map_io, 52 .map_io = ti8168_evm_map_io,
58 .init_early = ti8168_init_early, 53 .init_early = ti8168_init_early,
59 .init_irq = ti8168_evm_init_irq, 54 .init_irq = ti816x_init_irq,
60 .timer = &omap_timer, 55 .timer = &omap3_timer,
61 .init_machine = ti8168_evm_init, 56 .init_machine = ti8168_evm_init,
62MACHINE_END 57MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 118c6f53c5eb..8495f82fcbab 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
105 .rep = 1, 105 .rep = 1,
106}; 106};
107 107
108static struct regulator_consumer_supply zoom_vmmc1_supply = { 108static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
109 .supply = "vmmc", 109 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
110}; 110};
111 111
112static struct regulator_consumer_supply zoom_vsim_supply = { 112static struct regulator_consumer_supply zoom_vsim_supply[] = {
113 .supply = "vmmc_aux", 113 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
114}; 114};
115 115
116static struct regulator_consumer_supply zoom_vmmc2_supply = { 116static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
117 .supply = "vmmc", 117 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
118}; 118};
119 119
120static struct regulator_consumer_supply zoom_vmmc3_supply = { 120static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
121 .supply = "vmmc", 121 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
122 .dev_name = "omap_hsmmc.2",
123}; 122};
124 123
125/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
133 | REGULATOR_CHANGE_MODE 132 | REGULATOR_CHANGE_MODE
134 | REGULATOR_CHANGE_STATUS, 133 | REGULATOR_CHANGE_STATUS,
135 }, 134 },
136 .num_consumer_supplies = 1, 135 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
137 .consumer_supplies = &zoom_vmmc1_supply, 136 .consumer_supplies = zoom_vmmc1_supply,
138}; 137};
139 138
140/* VMMC2 for MMC2 card */ 139/* VMMC2 for MMC2 card */
@@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
148 .valid_ops_mask = REGULATOR_CHANGE_MODE 147 .valid_ops_mask = REGULATOR_CHANGE_MODE
149 | REGULATOR_CHANGE_STATUS, 148 | REGULATOR_CHANGE_STATUS,
150 }, 149 },
151 .num_consumer_supplies = 1, 150 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
152 .consumer_supplies = &zoom_vmmc2_supply, 151 .consumer_supplies = zoom_vmmc2_supply,
153}; 152};
154 153
155/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ 154/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
163 | REGULATOR_CHANGE_MODE 162 | REGULATOR_CHANGE_MODE
164 | REGULATOR_CHANGE_STATUS, 163 | REGULATOR_CHANGE_STATUS,
165 }, 164 },
166 .num_consumer_supplies = 1, 165 .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
167 .consumer_supplies = &zoom_vsim_supply, 166 .consumer_supplies = zoom_vsim_supply,
168}; 167};
169 168
170static struct regulator_init_data zoom_vmmc3 = { 169static struct regulator_init_data zoom_vmmc3 = {
171 .constraints = { 170 .constraints = {
172 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 171 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
173 }, 172 },
174 .num_consumer_supplies = 1, 173 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
175 .consumer_supplies = &zoom_vmmc3_supply, 174 .consumer_supplies = zoom_vmmc3_supply,
176}; 175};
177 176
178static struct fixed_voltage_config zoom_vwlan = { 177static struct fixed_voltage_config zoom_vwlan = {
@@ -232,8 +231,9 @@ static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
232 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), 231 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
233}; 232};
234 233
235static struct regulator_consumer_supply zoom_vdda_dac_supply = 234static struct regulator_consumer_supply zoom_vdda_dac_supply[] = {
236 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 235 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
236};
237 237
238static struct regulator_init_data zoom_vpll2 = { 238static struct regulator_init_data zoom_vpll2 = {
239 .constraints = { 239 .constraints = {
@@ -257,8 +257,8 @@ static struct regulator_init_data zoom_vdac = {
257 .valid_ops_mask = REGULATOR_CHANGE_MODE 257 .valid_ops_mask = REGULATOR_CHANGE_MODE
258 | REGULATOR_CHANGE_STATUS, 258 | REGULATOR_CHANGE_STATUS,
259 }, 259 },
260 .num_consumer_supplies = 1, 260 .num_consumer_supplies = ARRAY_SIZE(zoom_vdda_dac_supply),
261 .consumer_supplies = &zoom_vdda_dac_supply, 261 .consumer_supplies = zoom_vdda_dac_supply,
262}; 262};
263 263
264static int zoom_twl_gpio_setup(struct device *dev, 264static int zoom_twl_gpio_setup(struct device *dev,
@@ -270,13 +270,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
270 mmc[0].gpio_cd = gpio + 0; 270 mmc[0].gpio_cd = gpio + 0;
271 omap2_hsmmc_init(mmc); 271 omap2_hsmmc_init(mmc);
272 272
273 /* link regulators to MMC adapters ... we "know" the
274 * regulators will be set up only *after* we return.
275 */
276 zoom_vmmc1_supply.dev = mmc[0].dev;
277 zoom_vsim_supply.dev = mmc[0].dev;
278 zoom_vmmc2_supply.dev = mmc[1].dev;
279
280 ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, 273 ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
281 "lcd enable"); 274 "lcd enable");
282 if (ret) 275 if (ret)
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4b133d75c935..8a98c3c303fc 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,9 +137,9 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
137 .reserve = omap_reserve, 137 .reserve = omap_reserve,
138 .map_io = omap3_map_io, 138 .map_io = omap3_map_io,
139 .init_early = omap_zoom_init_early, 139 .init_early = omap_zoom_init_early,
140 .init_irq = omap_init_irq, 140 .init_irq = omap3_init_irq,
141 .init_machine = omap_zoom_init, 141 .init_machine = omap_zoom_init,
142 .timer = &omap_timer, 142 .timer = &omap3_timer,
143MACHINE_END 143MACHINE_END
144 144
145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
147 .reserve = omap_reserve, 147 .reserve = omap_reserve,
148 .map_io = omap3_map_io, 148 .map_io = omap3_map_io,
149 .init_early = omap_zoom_init_early, 149 .init_early = omap_zoom_init_early,
150 .init_irq = omap_init_irq, 150 .init_irq = omap3_init_irq,
151 .init_machine = omap_zoom_init, 151 .init_machine = omap_zoom_init,
152 .timer = &omap_timer, 152 .timer = &omap3_timer,
153MACHINE_END 153MACHINE_END
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d4..639e00e0eac2 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1486,6 +1486,40 @@ static struct clk dss_dss_clk = {
1486 .recalc = &followparent_recalc, 1486 .recalc = &followparent_recalc,
1487}; 1487};
1488 1488
1489static const struct clksel_rate div3_8to32_rates[] = {
1490 { .div = 8, .val = 0, .flags = RATE_IN_44XX },
1491 { .div = 16, .val = 1, .flags = RATE_IN_44XX },
1492 { .div = 32, .val = 2, .flags = RATE_IN_44XX },
1493 { .div = 0 },
1494};
1495
1496static const struct clksel div_ts_div[] = {
1497 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1498 { .parent = NULL },
1499};
1500
1501static struct clk div_ts_ck = {
1502 .name = "div_ts_ck",
1503 .parent = &l4_wkup_clk_mux_ck,
1504 .clksel = div_ts_div,
1505 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1506 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1507 .ops = &clkops_null,
1508 .recalc = &omap2_clksel_recalc,
1509 .round_rate = &omap2_clksel_round_rate,
1510 .set_rate = &omap2_clksel_set_rate,
1511};
1512
1513static struct clk bandgap_ts_fclk = {
1514 .name = "bandgap_ts_fclk",
1515 .ops = &clkops_omap2_dflt,
1516 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1517 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1518 .clkdm_name = "l4_wkup_clkdm",
1519 .parent = &div_ts_ck,
1520 .recalc = &followparent_recalc,
1521};
1522
1489static struct clk dss_48mhz_clk = { 1523static struct clk dss_48mhz_clk = {
1490 .name = "dss_48mhz_clk", 1524 .name = "dss_48mhz_clk",
1491 .ops = &clkops_omap2_dflt, 1525 .ops = &clkops_omap2_dflt,
@@ -3110,7 +3144,9 @@ static struct omap_clk omap44xx_clks[] = {
3110 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 3144 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3111 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 3145 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3112 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 3146 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3147 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3113 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 3148 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3149 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3114 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 3150 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3115 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 3151 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3116 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), 3152 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
@@ -3293,6 +3329,9 @@ int __init omap4xxx_clk_init(void)
3293 if (cpu_is_omap44xx()) { 3329 if (cpu_is_omap44xx()) {
3294 cpu_mask = RATE_IN_4430; 3330 cpu_mask = RATE_IN_4430;
3295 cpu_clkflg = CK_443X; 3331 cpu_clkflg = CK_443X;
3332 } else if (cpu_is_omap446x()) {
3333 cpu_mask = RATE_IN_4460;
3334 cpu_clkflg = CK_446X;
3296 } 3335 }
3297 3336
3298 clk_init(&omap2_clk_functions); 3337 clk_init(&omap2_clk_functions);
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b4..28e20d3a9f77 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -106,6 +106,10 @@
106#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 106#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
107#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) 107#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
108 108
109/* Used by CM_L4CFG_CLKSTCTRL */
110#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
111#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
112
109/* Used by CM_CEFUSE_CLKSTCTRL */ 113/* Used by CM_CEFUSE_CLKSTCTRL */
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 114#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
111#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 115#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
@@ -418,6 +422,10 @@
418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 422#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
419#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) 423#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
420 424
425/* Used by CM_WKUP_CLKSTCTRL */
426#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
427#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
428
421/* 429/*
422 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, 430 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
423 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 431 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
@@ -449,6 +457,10 @@
449#define OMAP4430_CLKSEL_60M_SHIFT 24 457#define OMAP4430_CLKSEL_60M_SHIFT 24
450#define OMAP4430_CLKSEL_60M_MASK (1 << 24) 458#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
451 459
460/* Used by CM_MPU_MPU_CLKCTRL */
461#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
462#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
463
452/* Used by CM1_ABE_AESS_CLKCTRL */ 464/* Used by CM1_ABE_AESS_CLKCTRL */
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 465#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 466#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
@@ -468,6 +480,10 @@
468#define OMAP4430_CLKSEL_DIV_SHIFT 24 480#define OMAP4430_CLKSEL_DIV_SHIFT 24
469#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) 481#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
470 482
483/* Used by CM_MPU_MPU_CLKCTRL */
484#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
485#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
486
471/* Used by CM_CAM_FDIF_CLKCTRL */ 487/* Used by CM_CAM_FDIF_CLKCTRL */
472#define OMAP4430_CLKSEL_FCLK_SHIFT 24 488#define OMAP4430_CLKSEL_FCLK_SHIFT 24
473#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) 489#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
@@ -572,6 +588,14 @@
572#define OMAP4430_D2D_STATDEP_SHIFT 18 588#define OMAP4430_D2D_STATDEP_SHIFT 18
573#define OMAP4430_D2D_STATDEP_MASK (1 << 18) 589#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
574 590
591/* Used by CM_CLKSEL_DPLL_MPU */
592#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
593#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
594
595/* Used by CM_CLKSEL_DPLL_MPU */
596#define OMAP4460_DCC_EN_SHIFT 22
597#define OMAP4460_DCC_EN_MASK (1 << 22)
598
575/* 599/*
576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 600 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 601 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
@@ -582,6 +606,10 @@
582#define OMAP4430_DELTAMSTEP_SHIFT 0 606#define OMAP4430_DELTAMSTEP_SHIFT 0
583#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 607#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
584 608
609/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
610#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
611#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
612
585/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 613/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
586#define OMAP4430_DLL_OVERRIDE_SHIFT 2 614#define OMAP4430_DLL_OVERRIDE_SHIFT 2
587#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 615#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
@@ -1204,6 +1232,10 @@
1204#define OMAP4430_MODULEMODE_SHIFT 0 1232#define OMAP4430_MODULEMODE_SHIFT 0
1205#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 1233#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1206 1234
1235/* Used by CM_L4CFG_DYNAMICDEP */
1236#define OMAP4460_MPU_DYNDEP_SHIFT 19
1237#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
1238
1207/* Used by CM_DSS_DSS_CLKCTRL */ 1239/* Used by CM_DSS_DSS_CLKCTRL */
1208#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1240#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1209#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1241#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
@@ -1298,6 +1330,10 @@
1298#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1330#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1299#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1331#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1300 1332
1333/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1334#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
1335#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
1336
1301/* Used by CM_DSS_DSS_CLKCTRL */ 1337/* Used by CM_DSS_DSS_CLKCTRL */
1302#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1338#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1303#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) 1339#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 94ccf464677b..0043fa8e3703 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -115,9 +115,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
115#endif 115#endif
116 116
117#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) 117#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
118static struct omap_nand_platform_data nand_data = { 118static struct omap_nand_platform_data nand_data;
119 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
120};
121 119
122void __init omap_nand_flash_init(int options, struct mtd_partition *parts, 120void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
123 int nr_parts) 121 int nr_parts)
@@ -148,7 +146,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
148 nand_data.cs = nandcs; 146 nand_data.cs = nandcs;
149 nand_data.parts = parts; 147 nand_data.parts = parts;
150 nand_data.nr_parts = nr_parts; 148 nand_data.nr_parts = nr_parts;
151 nand_data.options = options; 149 nand_data.devsize = options;
152 150
153 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); 151 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
154 if (gpmc_nand_init(&nand_data) < 0) 152 if (gpmc_nand_init(&nand_data) < 0)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index c1791d08ae56..8ad210bda9a9 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -20,8 +20,6 @@
20#include <plat/board.h> 20#include <plat/board.h>
21#include <plat/gpmc.h> 21#include <plat/gpmc.h>
22 22
23static struct omap_nand_platform_data *gpmc_nand_data;
24
25static struct resource gpmc_nand_resource = { 23static struct resource gpmc_nand_resource = {
26 .flags = IORESOURCE_MEM, 24 .flags = IORESOURCE_MEM,
27}; 25};
@@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
33 .resource = &gpmc_nand_resource, 31 .resource = &gpmc_nand_resource,
34}; 32};
35 33
36static int omap2_nand_gpmc_retime(void) 34static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
37{ 35{
38 struct gpmc_timings t; 36 struct gpmc_timings t;
39 int err; 37 int err;
@@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
83 return 0; 81 return 0;
84} 82}
85 83
86int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) 84int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
87{ 85{
88 int err = 0; 86 int err = 0;
89 struct device *dev = &gpmc_nand_device.dev; 87 struct device *dev = &gpmc_nand_device.dev;
90 88
91 gpmc_nand_data = _nand_data;
92 gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
93 gpmc_nand_device.dev.platform_data = gpmc_nand_data; 89 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
94 90
95 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, 91 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
100 } 96 }
101 97
102 /* Set timings in GPMC */ 98 /* Set timings in GPMC */
103 err = omap2_nand_gpmc_retime(); 99 err = omap2_nand_gpmc_retime(gpmc_nand_data);
104 if (err < 0) { 100 if (err < 0) {
105 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 101 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
106 return err; 102 return err;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2537090aa33a..37efb8696927 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -31,7 +31,7 @@
31static struct omap_chip_id omap_chip; 31static struct omap_chip_id omap_chip;
32static unsigned int omap_revision; 32static unsigned int omap_revision;
33 33
34u32 omap3_features; 34u32 omap_features;
35 35
36unsigned int omap_rev(void) 36unsigned int omap_rev(void)
37{ 37{
@@ -183,14 +183,14 @@ static void __init omap24xx_check_revision(void)
183#define OMAP3_CHECK_FEATURE(status,feat) \ 183#define OMAP3_CHECK_FEATURE(status,feat) \
184 if (((status & OMAP3_ ##feat## _MASK) \ 184 if (((status & OMAP3_ ##feat## _MASK) \
185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
186 omap3_features |= OMAP3_HAS_ ##feat; \ 186 omap_features |= OMAP3_HAS_ ##feat; \
187 } 187 }
188 188
189static void __init omap3_check_features(void) 189static void __init omap3_check_features(void)
190{ 190{
191 u32 status; 191 u32 status;
192 192
193 omap3_features = 0; 193 omap_features = 0;
194 194
195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
196 196
@@ -200,11 +200,11 @@ static void __init omap3_check_features(void)
200 OMAP3_CHECK_FEATURE(status, NEON); 200 OMAP3_CHECK_FEATURE(status, NEON);
201 OMAP3_CHECK_FEATURE(status, ISP); 201 OMAP3_CHECK_FEATURE(status, ISP);
202 if (cpu_is_omap3630()) 202 if (cpu_is_omap3630())
203 omap3_features |= OMAP3_HAS_192MHZ_CLK; 203 omap_features |= OMAP3_HAS_192MHZ_CLK;
204 if (!cpu_is_omap3505() && !cpu_is_omap3517()) 204 if (!cpu_is_omap3505() && !cpu_is_omap3517())
205 omap3_features |= OMAP3_HAS_IO_WAKEUP; 205 omap_features |= OMAP3_HAS_IO_WAKEUP;
206 206
207 omap3_features |= OMAP3_HAS_SDRC; 207 omap_features |= OMAP3_HAS_SDRC;
208 208
209 /* 209 /*
210 * TODO: Get additional info (where applicable) 210 * TODO: Get additional info (where applicable)
@@ -212,9 +212,34 @@ static void __init omap3_check_features(void)
212 */ 212 */
213} 213}
214 214
215static void __init omap4_check_features(void)
216{
217 u32 si_type;
218
219 if (cpu_is_omap443x())
220 omap_features |= OMAP4_HAS_MPU_1GHZ;
221
222
223 if (cpu_is_omap446x()) {
224 si_type =
225 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
226 switch ((si_type & (3 << 16)) >> 16) {
227 case 2:
228 /* High performance device */
229 omap_features |= OMAP4_HAS_MPU_1_5GHZ;
230 break;
231 case 1:
232 default:
233 /* Standard device */
234 omap_features |= OMAP4_HAS_MPU_1_2GHZ;
235 break;
236 }
237 }
238}
239
215static void __init ti816x_check_features(void) 240static void __init ti816x_check_features(void)
216{ 241{
217 omap3_features = OMAP3_HAS_NEON; 242 omap_features = OMAP3_HAS_NEON;
218} 243}
219 244
220static void __init omap3_check_revision(void) 245static void __init omap3_check_revision(void)
@@ -344,10 +369,10 @@ static void __init omap4_check_revision(void)
344 rev = (idcode >> 28) & 0xf; 369 rev = (idcode >> 28) & 0xf;
345 370
346 /* 371 /*
347 * Few initial ES2.0 samples IDCODE is same as ES1.0 372 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
348 * Use ARM register to detect the correct ES version 373 * Use ARM register to detect the correct ES version
349 */ 374 */
350 if (!rev) { 375 if (!rev && (hawkeye != 0xb94e)) {
351 idcode = read_cpuid(CPUID_ID); 376 idcode = read_cpuid(CPUID_ID);
352 rev = (idcode & 0xf) - 1; 377 rev = (idcode & 0xf) - 1;
353 } 378 }
@@ -377,6 +402,15 @@ static void __init omap4_check_revision(void)
377 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; 402 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
378 } 403 }
379 break; 404 break;
405 case 0xb94e:
406 switch (rev) {
407 case 0:
408 default:
409 omap_revision = OMAP4460_REV_ES1_0;
410 omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
411 break;
412 }
413 break;
380 default: 414 default:
381 /* Unknown default to latest silicon rev as default */ 415 /* Unknown default to latest silicon rev as default */
382 omap_revision = OMAP4430_REV_ES2_2; 416 omap_revision = OMAP4430_REV_ES2_2;
@@ -518,6 +552,7 @@ void __init omap2_check_revision(void)
518 return; 552 return;
519 } else if (cpu_is_omap44xx()) { 553 } else if (cpu_is_omap44xx()) {
520 omap4_check_revision(); 554 omap4_check_revision();
555 omap4_check_features();
521 return; 556 return;
522 } else { 557 } else {
523 pr_err("OMAP revision unknown, please fix!\n"); 558 pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 441e79d043a7..2ce1ce6fb4db 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334} 334}
335 335
336/* See irq.c, omap4-common.c and entry-macro.S */
336void __iomem *omap_irq_base; 337void __iomem *omap_irq_base;
337 338
338/*
339 * Initialize asm_irq_base for entry-macro.S
340 */
341static inline void omap_irq_base_init(void)
342{
343 if (cpu_is_omap24xx())
344 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
345 else if (cpu_is_omap34xx())
346 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
347 else if (cpu_is_omap44xx())
348 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
349 else
350 pr_err("Could not initialize omap_irq_base\n");
351}
352
353void __init omap2_init_common_infrastructure(void) 339void __init omap2_init_common_infrastructure(void)
354{ 340{
355 u8 postsetup_state; 341 u8 postsetup_state;
@@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
422 _omap2_init_reprogram_sdrc(); 408 _omap2_init_reprogram_sdrc();
423 } 409 }
424 410
425 omap_irq_base_init();
426} 411}
427 412
428/* 413/*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3af2b7a1045e..3a12f7586a4c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
141 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 141 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
142} 142}
143 143
144void __init omap_init_irq(void) 144static void __init omap_init_irq(u32 base, int nr_irqs)
145{ 145{
146 unsigned long nr_of_irqs = 0; 146 unsigned long nr_of_irqs = 0;
147 unsigned int nr_banks = 0; 147 unsigned int nr_banks = 0;
148 int i, j; 148 int i, j;
149 149
150 omap_irq_base = ioremap(base, SZ_4K);
151 if (WARN_ON(!omap_irq_base))
152 return;
153
150 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 154 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
151 unsigned long base = 0;
152 struct omap_irq_bank *bank = irq_banks + i; 155 struct omap_irq_bank *bank = irq_banks + i;
153 156
154 if (cpu_is_omap24xx()) 157 bank->nr_irqs = nr_irqs;
155 base = OMAP24XX_IC_BASE;
156 else if (cpu_is_omap34xx())
157 base = OMAP34XX_IC_BASE;
158
159 BUG_ON(!base);
160
161 if (cpu_is_ti816x())
162 bank->nr_irqs = 128;
163 158
164 /* Static mapping, never released */ 159 /* Static mapping, never released */
165 bank->base_reg = ioremap(base, SZ_4K); 160 bank->base_reg = ioremap(base, SZ_4K);
@@ -181,6 +176,21 @@ void __init omap_init_irq(void)
181 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); 176 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
182} 177}
183 178
179void __init omap2_init_irq(void)
180{
181 omap_init_irq(OMAP24XX_IC_BASE, 96);
182}
183
184void __init omap3_init_irq(void)
185{
186 omap_init_irq(OMAP34XX_IC_BASE, 96);
187}
188
189void __init ti816x_init_irq(void)
190{
191 omap_init_irq(OMAP34XX_IC_BASE, 128);
192}
193
184#ifdef CONFIG_ARCH_OMAP3 194#ifdef CONFIG_ARCH_OMAP3
185static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; 195static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
186 196
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 9ef8c29dd817..35ac3e5f6e94 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -19,6 +19,8 @@
19#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
20#include <asm/hardware/cache-l2x0.h> 20#include <asm/hardware/cache-l2x0.h>
21 21
22#include <plat/irqs.h>
23
22#include <mach/hardware.h> 24#include <mach/hardware.h>
23#include <mach/omap4-common.h> 25#include <mach/omap4-common.h>
24 26
@@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
31 33
32void __init gic_init_irq(void) 34void __init gic_init_irq(void)
33{ 35{
34 void __iomem *gic_cpu_base;
35
36 /* Static mapping, never released */ 36 /* Static mapping, never released */
37 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); 37 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
38 BUG_ON(!gic_dist_base_addr); 38 BUG_ON(!gic_dist_base_addr);
39 39
40 /* Static mapping, never released */ 40 /* Static mapping, never released */
41 gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); 41 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
42 BUG_ON(!gic_cpu_base); 42 BUG_ON(!omap_irq_base);
43 43
44 gic_init(0, 29, gic_dist_base_addr, gic_cpu_base); 44 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
45} 45}
46 46
47#ifdef CONFIG_CACHE_L2X0 47#ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index e01da45c0537..4411163e012d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,155 +38,12 @@
38#include "prm2xxx_3xxx.h" 38#include "prm2xxx_3xxx.h"
39#include "pm.h" 39#include "pm.h"
40 40
41int omap2_pm_debug;
42u32 enable_off_mode; 41u32 enable_off_mode;
43u32 sleep_while_idle;
44u32 wakeup_timer_seconds;
45u32 wakeup_timer_milliseconds;
46
47#define DUMP_PRM_MOD_REG(mod, reg) \
48 regs[reg_count].name = #mod "." #reg; \
49 regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
50#define DUMP_CM_MOD_REG(mod, reg) \
51 regs[reg_count].name = #mod "." #reg; \
52 regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
53#define DUMP_PRM_REG(reg) \
54 regs[reg_count].name = #reg; \
55 regs[reg_count++].val = __raw_readl(reg)
56#define DUMP_CM_REG(reg) \
57 regs[reg_count].name = #reg; \
58 regs[reg_count++].val = __raw_readl(reg)
59#define DUMP_INTC_REG(reg, off) \
60 regs[reg_count].name = #reg; \
61 regs[reg_count++].val = \
62 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
63
64void omap2_pm_dump(int mode, int resume, unsigned int us)
65{
66 struct reg {
67 const char *name;
68 u32 val;
69 } regs[32];
70 int reg_count = 0, i;
71 const char *s1 = NULL, *s2 = NULL;
72
73 if (!resume) {
74#if 0
75 /* MPU */
76 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
77 DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
78 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
79 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
80 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
81#endif
82#if 0
83 /* INTC */
84 DUMP_INTC_REG(INTC_MIR0, 0x0084);
85 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
86 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
87#endif
88#if 0
89 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
90 if (cpu_is_omap24xx()) {
91 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
92 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
93 OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
94 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
95 OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
96 }
97 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
98 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
99 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
100 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
101 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
102 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
103 DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
104#endif
105#if 0
106 /* DSP */
107 if (cpu_is_omap24xx()) {
108 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
109 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
110 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
111 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
112 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
113 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
114 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
115 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
116 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
117 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
118 }
119#endif
120 } else {
121 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
122 if (cpu_is_omap24xx())
123 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
124 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
125 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
126#if 1
127 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
128 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
129 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
130#endif
131 }
132
133 switch (mode) {
134 case 0:
135 s1 = "full";
136 s2 = "retention";
137 break;
138 case 1:
139 s1 = "MPU";
140 s2 = "retention";
141 break;
142 case 2:
143 s1 = "MPU";
144 s2 = "idle";
145 break;
146 }
147
148 if (!resume)
149#ifdef CONFIG_NO_HZ
150 printk(KERN_INFO
151 "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
152 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
153 jiffies));
154#else
155 printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
156#endif
157 else
158 printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
159 us / 1000, us % 1000);
160
161 for (i = 0; i < reg_count; i++)
162 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
163}
164
165void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
166{
167 u32 tick_rate, cycles;
168
169 if (!seconds && !milliseconds)
170 return;
171
172 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
173 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
174 omap_dm_timer_stop(gptimer_wakeup);
175 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
176
177 pr_info("PM: Resume timer in %u.%03u secs"
178 " (%d ticks at %d ticks/sec.)\n",
179 seconds, milliseconds, cycles, tick_rate);
180}
181 42
182#ifdef CONFIG_DEBUG_FS 43#ifdef CONFIG_DEBUG_FS
183#include <linux/debugfs.h> 44#include <linux/debugfs.h>
184#include <linux/seq_file.h> 45#include <linux/seq_file.h>
185 46
186static void pm_dbg_regset_store(u32 *ptr);
187
188static struct dentry *pm_dbg_dir;
189
190static int pm_dbg_init_done; 47static int pm_dbg_init_done;
191 48
192static int pm_dbg_init(void); 49static int pm_dbg_init(void);
@@ -196,160 +53,6 @@ enum {
196 DEBUG_FILE_TIMERS, 53 DEBUG_FILE_TIMERS,
197}; 54};
198 55
199struct pm_module_def {
200 char name[8]; /* Name of the module */
201 short type; /* CM or PRM */
202 unsigned short offset;
203 int low; /* First register address on this module */
204 int high; /* Last register address on this module */
205};
206
207#define MOD_CM 0
208#define MOD_PRM 1
209
210static const struct pm_module_def *pm_dbg_reg_modules;
211static const struct pm_module_def omap3_pm_reg_modules[] = {
212 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
213 { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
214 { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
215 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
216 { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
217 { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
218 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
219 { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
220 { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
221 { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
222 { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
223 { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
224 { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
225
226 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
227 { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
228 { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
229 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
230 { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
231 { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
232 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
233 { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
234 { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
235 { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
236 { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
237 { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
238 { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
239 { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
240 { "", 0, 0, 0, 0 },
241};
242
243#define PM_DBG_MAX_REG_SETS 4
244
245static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
246
247static int pm_dbg_get_regset_size(void)
248{
249 static int regset_size;
250
251 if (regset_size == 0) {
252 int i = 0;
253
254 while (pm_dbg_reg_modules[i].name[0] != 0) {
255 regset_size += pm_dbg_reg_modules[i].high +
256 4 - pm_dbg_reg_modules[i].low;
257 i++;
258 }
259 }
260 return regset_size;
261}
262
263static int pm_dbg_show_regs(struct seq_file *s, void *unused)
264{
265 int i, j;
266 unsigned long val;
267 int reg_set = (int)s->private;
268 u32 *ptr;
269 void *store = NULL;
270 int regs;
271 int linefeed;
272
273 if (reg_set == 0) {
274 store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
275 ptr = store;
276 pm_dbg_regset_store(ptr);
277 } else {
278 ptr = pm_dbg_reg_set[reg_set - 1];
279 }
280
281 i = 0;
282
283 while (pm_dbg_reg_modules[i].name[0] != 0) {
284 regs = 0;
285 linefeed = 0;
286 if (pm_dbg_reg_modules[i].type == MOD_CM)
287 seq_printf(s, "MOD: CM_%s (%08x)\n",
288 pm_dbg_reg_modules[i].name,
289 (u32)(OMAP3430_CM_BASE +
290 pm_dbg_reg_modules[i].offset));
291 else
292 seq_printf(s, "MOD: PRM_%s (%08x)\n",
293 pm_dbg_reg_modules[i].name,
294 (u32)(OMAP3430_PRM_BASE +
295 pm_dbg_reg_modules[i].offset));
296
297 for (j = pm_dbg_reg_modules[i].low;
298 j <= pm_dbg_reg_modules[i].high; j += 4) {
299 val = *(ptr++);
300 if (val != 0) {
301 regs++;
302 if (linefeed) {
303 seq_printf(s, "\n");
304 linefeed = 0;
305 }
306 seq_printf(s, " %02x => %08lx", j, val);
307 if (regs % 4 == 0)
308 linefeed = 1;
309 }
310 }
311 seq_printf(s, "\n");
312 i++;
313 }
314
315 if (store != NULL)
316 kfree(store);
317
318 return 0;
319}
320
321static void pm_dbg_regset_store(u32 *ptr)
322{
323 int i, j;
324 u32 val;
325
326 i = 0;
327
328 while (pm_dbg_reg_modules[i].name[0] != 0) {
329 for (j = pm_dbg_reg_modules[i].low;
330 j <= pm_dbg_reg_modules[i].high; j += 4) {
331 if (pm_dbg_reg_modules[i].type == MOD_CM)
332 val = omap2_cm_read_mod_reg(
333 pm_dbg_reg_modules[i].offset, j);
334 else
335 val = omap2_prm_read_mod_reg(
336 pm_dbg_reg_modules[i].offset, j);
337 *(ptr++) = val;
338 }
339 i++;
340 }
341}
342
343int pm_dbg_regset_save(int reg_set)
344{
345 if (pm_dbg_reg_set[reg_set-1] == NULL)
346 return -EINVAL;
347
348 pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
349
350 return 0;
351}
352
353static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { 56static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
354 "OFF", 57 "OFF",
355 "RET", 58 "RET",
@@ -469,11 +172,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
469 }; 172 };
470} 173}
471 174
472static int pm_dbg_reg_open(struct inode *inode, struct file *file)
473{
474 return single_open(file, pm_dbg_show_regs, inode->i_private);
475}
476
477static const struct file_operations debug_fops = { 175static const struct file_operations debug_fops = {
478 .open = pm_dbg_open, 176 .open = pm_dbg_open,
479 .read = seq_read, 177 .read = seq_read,
@@ -481,40 +179,6 @@ static const struct file_operations debug_fops = {
481 .release = single_release, 179 .release = single_release,
482}; 180};
483 181
484static const struct file_operations debug_reg_fops = {
485 .open = pm_dbg_reg_open,
486 .read = seq_read,
487 .llseek = seq_lseek,
488 .release = single_release,
489};
490
491int pm_dbg_regset_init(int reg_set)
492{
493 char name[2];
494
495 if (!pm_dbg_init_done)
496 pm_dbg_init();
497
498 if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
499 pm_dbg_reg_set[reg_set-1] != NULL)
500 return -EINVAL;
501
502 pm_dbg_reg_set[reg_set-1] =
503 kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
504
505 if (pm_dbg_reg_set[reg_set-1] == NULL)
506 return -ENOMEM;
507
508 if (pm_dbg_dir != NULL) {
509 sprintf(name, "%d", reg_set);
510
511 (void) debugfs_create_file(name, S_IRUGO,
512 pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
513 }
514
515 return 0;
516}
517
518static int pwrdm_suspend_get(void *data, u64 *val) 182static int pwrdm_suspend_get(void *data, u64 *val)
519{ 183{
520 int ret = -EINVAL; 184 int ret = -EINVAL;
@@ -576,9 +240,6 @@ static int option_set(void *data, u64 val)
576{ 240{
577 u32 *option = data; 241 u32 *option = data;
578 242
579 if (option == &wakeup_timer_milliseconds && val >= 1000)
580 return -EINVAL;
581
582 *option = val; 243 *option = val;
583 244
584 if (option == &enable_off_mode) { 245 if (option == &enable_off_mode) {
@@ -595,22 +256,13 @@ static int option_set(void *data, u64 val)
595 256
596DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n"); 257DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
597 258
598static int pm_dbg_init(void) 259static int __init pm_dbg_init(void)
599{ 260{
600 int i;
601 struct dentry *d; 261 struct dentry *d;
602 char name[2];
603 262
604 if (pm_dbg_init_done) 263 if (pm_dbg_init_done)
605 return 0; 264 return 0;
606 265
607 if (cpu_is_omap34xx())
608 pm_dbg_reg_modules = omap3_pm_reg_modules;
609 else {
610 printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
611 return -ENODEV;
612 }
613
614 d = debugfs_create_dir("pm_debug", NULL); 266 d = debugfs_create_dir("pm_debug", NULL);
615 if (IS_ERR(d)) 267 if (IS_ERR(d))
616 return PTR_ERR(d); 268 return PTR_ERR(d);
@@ -622,30 +274,8 @@ static int pm_dbg_init(void)
622 274
623 pwrdm_for_each(pwrdms_setup, (void *)d); 275 pwrdm_for_each(pwrdms_setup, (void *)d);
624 276
625 pm_dbg_dir = debugfs_create_dir("registers", d);
626 if (IS_ERR(pm_dbg_dir))
627 return PTR_ERR(pm_dbg_dir);
628
629 (void) debugfs_create_file("current", S_IRUGO,
630 pm_dbg_dir, (void *)0, &debug_reg_fops);
631
632 for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
633 if (pm_dbg_reg_set[i] != NULL) {
634 sprintf(name, "%d", i+1);
635 (void) debugfs_create_file(name, S_IRUGO,
636 pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
637
638 }
639
640 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d, 277 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
641 &enable_off_mode, &pm_dbg_option_fops); 278 &enable_off_mode, &pm_dbg_option_fops);
642 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
643 &sleep_while_idle, &pm_dbg_option_fops);
644 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
645 &wakeup_timer_seconds, &pm_dbg_option_fops);
646 (void) debugfs_create_file("wakeup_timer_milliseconds",
647 S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
648 &pm_dbg_option_fops);
649 pm_dbg_init_done = 1; 279 pm_dbg_init_done = 1;
650 280
651 return 0; 281 return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 45bcfce77352..babac19e3ec1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -60,32 +60,16 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
60extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 60extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
61extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 61extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
62 62
63extern u32 wakeup_timer_seconds;
64extern u32 wakeup_timer_milliseconds;
65extern struct omap_dm_timer *gptimer_wakeup;
66
67#ifdef CONFIG_PM_DEBUG 63#ifdef CONFIG_PM_DEBUG
68extern void omap2_pm_dump(int mode, int resume, unsigned int us);
69extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
70extern int omap2_pm_debug;
71extern u32 enable_off_mode; 64extern u32 enable_off_mode;
72extern u32 sleep_while_idle;
73#else 65#else
74#define omap2_pm_dump(mode, resume, us) do {} while (0);
75#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
76#define omap2_pm_debug 0
77#define enable_off_mode 0 66#define enable_off_mode 0
78#define sleep_while_idle 0
79#endif 67#endif
80 68
81#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 69#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
82extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 70extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
83extern int pm_dbg_regset_save(int reg_set);
84extern int pm_dbg_regset_init(int reg_set);
85#else 71#else
86#define pm_dbg_update_time(pwrdm, prev) do {} while (0); 72#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
87#define pm_dbg_regset_save(reg_set) do {} while (0);
88#define pm_dbg_regset_init(reg_set) do {} while (0);
89#endif /* CONFIG_PM_DEBUG */ 73#endif /* CONFIG_PM_DEBUG */
90 74
91extern void omap24xx_idle_loop_suspend(void); 75extern void omap24xx_idle_loop_suspend(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index df3ded6fe194..bf089e743ed9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,8 @@
53#include "powerdomain.h" 53#include "powerdomain.h"
54#include "clockdomain.h" 54#include "clockdomain.h"
55 55
56static int omap2_pm_debug;
57
56#ifdef CONFIG_SUSPEND 58#ifdef CONFIG_SUSPEND
57static suspend_state_t suspend_state = PM_SUSPEND_ON; 59static suspend_state_t suspend_state = PM_SUSPEND_ON;
58static inline bool is_suspending(void) 60static inline bool is_suspending(void)
@@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
123 omap2_gpio_prepare_for_idle(0); 125 omap2_gpio_prepare_for_idle(0);
124 126
125 if (omap2_pm_debug) { 127 if (omap2_pm_debug) {
126 omap2_pm_dump(0, 0, 0);
127 getnstimeofday(&ts_preidle); 128 getnstimeofday(&ts_preidle);
128 } 129 }
129 130
@@ -160,7 +161,6 @@ no_sleep:
160 getnstimeofday(&ts_postidle); 161 getnstimeofday(&ts_postidle);
161 ts_idle = timespec_sub(ts_postidle, ts_preidle); 162 ts_idle = timespec_sub(ts_postidle, ts_preidle);
162 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; 163 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
163 omap2_pm_dump(0, 1, tmp);
164 } 164 }
165 omap2_gpio_resume_after_idle(); 165 omap2_gpio_resume_after_idle();
166 166
@@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
247 } 247 }
248 248
249 if (omap2_pm_debug) { 249 if (omap2_pm_debug) {
250 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
251 getnstimeofday(&ts_preidle); 250 getnstimeofday(&ts_preidle);
252 } 251 }
253 252
@@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
259 getnstimeofday(&ts_postidle); 258 getnstimeofday(&ts_postidle);
260 ts_idle = timespec_sub(ts_postidle, ts_preidle); 259 ts_idle = timespec_sub(ts_postidle, ts_preidle);
261 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; 260 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
262 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
263 } 261 }
264} 262}
265 263
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d1c82c..96a76245284c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -497,8 +497,6 @@ console_still_active:
497 497
498int omap3_can_sleep(void) 498int omap3_can_sleep(void)
499{ 499{
500 if (!sleep_while_idle)
501 return 0;
502 if (!omap_uart_can_sleep()) 500 if (!omap_uart_can_sleep())
503 return 0; 501 return 0;
504 return 1; 502 return 1;
@@ -534,10 +532,6 @@ static int omap3_pm_suspend(void)
534 struct power_state *pwrst; 532 struct power_state *pwrst;
535 int state, ret = 0; 533 int state, ret = 0;
536 534
537 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
538 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
539 wakeup_timer_milliseconds);
540
541 /* Read current next_pwrsts */ 535 /* Read current next_pwrsts */
542 list_for_each_entry(pwrst, &pwrst_list, node) 536 list_for_each_entry(pwrst, &pwrst_list, node)
543 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 537 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 6d2776f6fc08..3cb247bebdaa 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -283,6 +283,14 @@
283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) 284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
285 285
286/* Used by PRM_DEVICE_OFF_CTRL */
287#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
288#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
289
290/* Used by PRM_DEVICE_OFF_CTRL */
291#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
292#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
293
286/* Used by RM_MPU_RSTST */ 294/* Used by RM_MPU_RSTST */
287#define OMAP4430_EMULATION_RST_SHIFT 0 295#define OMAP4430_EMULATION_RST_SHIFT 0
288#define OMAP4430_EMULATION_RST_MASK (1 << 0) 296#define OMAP4430_EMULATION_RST_MASK (1 << 0)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index fb7dc52394a8..2ce2fb7664bc 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
143 sr_write_reg(sr_info, IRQSTATUS, status); 143 sr_write_reg(sr_info, IRQSTATUS, status);
144 } 144 }
145 145
146 if (sr_class->class_type == SR_CLASS2 && sr_class->notify) 146 if (sr_class->notify)
147 sr_class->notify(sr_info->voltdm, status); 147 sr_class->notify(sr_info->voltdm, status);
148 148
149 return IRQ_HANDLED; 149 return IRQ_HANDLED;
@@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
258 struct resource *mem; 258 struct resource *mem;
259 int ret = 0; 259 int ret = 0;
260 260
261 if (sr_class->class_type == SR_CLASS2 && 261 if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
262 sr_class->notify_flags && sr_info->irq) {
263
264 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name); 262 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
265 if (name == NULL) { 263 if (name == NULL) {
266 ret = -ENOMEM; 264 ret = -ENOMEM;
@@ -270,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
270 0, name, (void *)sr_info); 268 0, name, (void *)sr_info);
271 if (ret) 269 if (ret)
272 goto error; 270 goto error;
271 disable_irq(sr_info->irq);
273 } 272 }
274 273
275 if (pdata && pdata->enable_on_init) 274 if (pdata && pdata->enable_on_init)
@@ -278,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
278 return ret; 277 return ret;
279 278
280error: 279error:
281 iounmap(sr_info->base); 280 iounmap(sr_info->base);
282 mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0); 281 mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
283 release_mem_region(mem->start, resource_size(mem)); 282 release_mem_region(mem->start, resource_size(mem));
284 list_del(&sr_info->node); 283 list_del(&sr_info->node);
285 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" 284 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
286 "interrupt handler. Smartreflex will" 285 "interrupt handler. Smartreflex will"
287 "not function as desired\n", __func__); 286 "not function as desired\n", __func__);
288 kfree(name); 287 kfree(name);
289 kfree(sr_info); 288 kfree(sr_info);
290 return ret; 289 return ret;
291} 290}
292 291
293static void sr_v1_disable(struct omap_sr *sr) 292static void sr_v1_disable(struct omap_sr *sr)
@@ -808,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
808 return -EINVAL; 807 return -EINVAL;
809 } 808 }
810 809
811 if (!val) 810 /* control enable/disable only if there is a delta in value */
812 sr_stop_vddautocomp(sr_info); 811 if (sr_info->autocomp_active != val) {
813 else 812 if (!val)
814 sr_start_vddautocomp(sr_info); 813 sr_stop_vddautocomp(sr_info);
814 else
815 sr_start_vddautocomp(sr_info);
816 }
815 817
816 return 0; 818 return 0;
817} 819}
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
deleted file mode 100644
index 3b9cf85f4bb9..000000000000
--- a/arch/arm/mach-omap2/timer-gp.c
+++ /dev/null
@@ -1,266 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38
39#include <asm/mach/time.h>
40#include <plat/dmtimer.h>
41#include <asm/localtimer.h>
42#include <asm/sched_clock.h>
43#include <plat/common.h>
44#include <plat/omap_hwmod.h>
45
46#include "timer-gp.h"
47
48
49/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
50#define MAX_GPTIMER_ID 12
51
52static struct omap_dm_timer *gptimer;
53static struct clock_event_device clockevent_gpt;
54static u8 __initdata gptimer_id = 1;
55static u8 __initdata inited;
56struct omap_dm_timer *gptimer_wakeup;
57
58static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
59{
60 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
61 struct clock_event_device *evt = &clockevent_gpt;
62
63 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
64
65 evt->event_handler(evt);
66 return IRQ_HANDLED;
67}
68
69static struct irqaction omap2_gp_timer_irq = {
70 .name = "gp timer",
71 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
72 .handler = omap2_gp_timer_interrupt,
73};
74
75static int omap2_gp_timer_set_next_event(unsigned long cycles,
76 struct clock_event_device *evt)
77{
78 omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
79
80 return 0;
81}
82
83static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
84 struct clock_event_device *evt)
85{
86 u32 period;
87
88 omap_dm_timer_stop(gptimer);
89
90 switch (mode) {
91 case CLOCK_EVT_MODE_PERIODIC:
92 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
93 period -= 1;
94 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
95 break;
96 case CLOCK_EVT_MODE_ONESHOT:
97 break;
98 case CLOCK_EVT_MODE_UNUSED:
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_RESUME:
101 break;
102 }
103}
104
105static struct clock_event_device clockevent_gpt = {
106 .name = "gp timer",
107 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
108 .shift = 32,
109 .set_next_event = omap2_gp_timer_set_next_event,
110 .set_mode = omap2_gp_timer_set_mode,
111};
112
113/**
114 * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
115 * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
116 *
117 * Define the GPTIMER that the system should use for the tick timer.
118 * Meant to be called from board-*.c files in the event that GPTIMER1, the
119 * default, is unsuitable. Returns -EINVAL on error or 0 on success.
120 */
121int __init omap2_gp_clockevent_set_gptimer(u8 id)
122{
123 if (id < 1 || id > MAX_GPTIMER_ID)
124 return -EINVAL;
125
126 BUG_ON(inited);
127
128 gptimer_id = id;
129
130 return 0;
131}
132
133static void __init omap2_gp_clockevent_init(void)
134{
135 u32 tick_rate;
136 int src;
137 char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
138
139 inited = 1;
140
141 sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
142 omap_hwmod_setup_one(clockevent_hwmod_name);
143
144 gptimer = omap_dm_timer_request_specific(gptimer_id);
145 BUG_ON(gptimer == NULL);
146 gptimer_wakeup = gptimer;
147
148#if defined(CONFIG_OMAP_32K_TIMER)
149 src = OMAP_TIMER_SRC_32_KHZ;
150#else
151 src = OMAP_TIMER_SRC_SYS_CLK;
152 WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
153 "secure 32KiHz clock source\n");
154#endif
155
156 if (gptimer_id != 12)
157 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
158 "timer-gp: omap_dm_timer_set_source() failed\n");
159
160 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
161
162 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
163 gptimer_id, tick_rate);
164
165 omap2_gp_timer_irq.dev_id = (void *)gptimer;
166 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
167 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
168
169 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
170 clockevent_gpt.shift);
171 clockevent_gpt.max_delta_ns =
172 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
173 clockevent_gpt.min_delta_ns =
174 clockevent_delta2ns(3, &clockevent_gpt);
175 /* Timer internal resynch latency. */
176
177 clockevent_gpt.cpumask = cpumask_of(0);
178 clockevents_register_device(&clockevent_gpt);
179}
180
181/* Clocksource code */
182
183#ifdef CONFIG_OMAP_32K_TIMER
184/*
185 * When 32k-timer is enabled, don't use GPTimer for clocksource
186 * instead, just leave default clocksource which uses the 32k
187 * sync counter. See clocksource setup in plat-omap/counter_32k.c
188 */
189
190static void __init omap2_gp_clocksource_init(void)
191{
192 omap_init_clocksource_32k();
193}
194
195#else
196/*
197 * clocksource
198 */
199static DEFINE_CLOCK_DATA(cd);
200static struct omap_dm_timer *gpt_clocksource;
201static cycle_t clocksource_read_cycles(struct clocksource *cs)
202{
203 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
204}
205
206static struct clocksource clocksource_gpt = {
207 .name = "gp timer",
208 .rating = 300,
209 .read = clocksource_read_cycles,
210 .mask = CLOCKSOURCE_MASK(32),
211 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
212};
213
214static void notrace dmtimer_update_sched_clock(void)
215{
216 u32 cyc;
217
218 cyc = omap_dm_timer_read_counter(gpt_clocksource);
219
220 update_sched_clock(&cd, cyc, (u32)~0);
221}
222
223/* Setup free-running counter for clocksource */
224static void __init omap2_gp_clocksource_init(void)
225{
226 static struct omap_dm_timer *gpt;
227 u32 tick_rate;
228 static char err1[] __initdata = KERN_ERR
229 "%s: failed to request dm-timer\n";
230 static char err2[] __initdata = KERN_ERR
231 "%s: can't register clocksource!\n";
232
233 gpt = omap_dm_timer_request();
234 if (!gpt)
235 printk(err1, clocksource_gpt.name);
236 gpt_clocksource = gpt;
237
238 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
239 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
240
241 omap_dm_timer_set_load_start(gpt, 1, 0);
242
243 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
244
245 if (clocksource_register_hz(&clocksource_gpt, tick_rate))
246 printk(err2, clocksource_gpt.name);
247}
248#endif
249
250static void __init omap2_gp_timer_init(void)
251{
252#ifdef CONFIG_LOCAL_TIMERS
253 if (cpu_is_omap44xx()) {
254 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
255 BUG_ON(!twd_base);
256 }
257#endif
258 omap_dm_timer_init();
259
260 omap2_gp_clockevent_init();
261 omap2_gp_clocksource_init();
262}
263
264struct sys_timer omap_timer = {
265 .init = omap2_gp_timer_init,
266};
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
deleted file mode 100644
index 5c1072c6783b..000000000000
--- a/arch/arm/mach-omap2/timer-gp.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
new file mode 100644
index 000000000000..e9640728239b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer.c
@@ -0,0 +1,342 @@
1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38
39#include <asm/mach/time.h>
40#include <plat/dmtimer.h>
41#include <asm/localtimer.h>
42#include <asm/sched_clock.h>
43#include <plat/common.h>
44#include <plat/omap_hwmod.h>
45
46/* Parent clocks, eventually these will come from the clock framework */
47
48#define OMAP2_MPU_SOURCE "sys_ck"
49#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
50#define OMAP4_MPU_SOURCE "sys_clkin_ck"
51#define OMAP2_32K_SOURCE "func_32k_ck"
52#define OMAP3_32K_SOURCE "omap_32k_fck"
53#define OMAP4_32K_SOURCE "sys_32k_ck"
54
55#ifdef CONFIG_OMAP_32K_TIMER
56#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
57#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
58#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
59#define OMAP3_SECURE_TIMER 12
60#else
61#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
62#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
63#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
64#define OMAP3_SECURE_TIMER 1
65#endif
66
67/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
68#define MAX_GPTIMER_ID 12
69
70u32 sys_timer_reserved;
71
72/* Clockevent code */
73
74static struct omap_dm_timer clkev;
75static struct clock_event_device clockevent_gpt;
76
77static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
78{
79 struct clock_event_device *evt = &clockevent_gpt;
80
81 __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
82
83 evt->event_handler(evt);
84 return IRQ_HANDLED;
85}
86
87static struct irqaction omap2_gp_timer_irq = {
88 .name = "gp timer",
89 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
90 .handler = omap2_gp_timer_interrupt,
91};
92
93static int omap2_gp_timer_set_next_event(unsigned long cycles,
94 struct clock_event_device *evt)
95{
96 __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
97 0xffffffff - cycles, 1);
98
99 return 0;
100}
101
102static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
104{
105 u32 period;
106
107 __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
108
109 switch (mode) {
110 case CLOCK_EVT_MODE_PERIODIC:
111 period = clkev.rate / HZ;
112 period -= 1;
113 /* Looks like we need to first set the load value separately */
114 __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
115 0xffffffff - period, 1);
116 __omap_dm_timer_load_start(clkev.io_base,
117 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
118 0xffffffff - period, 1);
119 break;
120 case CLOCK_EVT_MODE_ONESHOT:
121 break;
122 case CLOCK_EVT_MODE_UNUSED:
123 case CLOCK_EVT_MODE_SHUTDOWN:
124 case CLOCK_EVT_MODE_RESUME:
125 break;
126 }
127}
128
129static struct clock_event_device clockevent_gpt = {
130 .name = "gp timer",
131 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
132 .shift = 32,
133 .set_next_event = omap2_gp_timer_set_next_event,
134 .set_mode = omap2_gp_timer_set_mode,
135};
136
137static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
138 int gptimer_id,
139 const char *fck_source)
140{
141 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
142 struct omap_hwmod *oh;
143 size_t size;
144 int res = 0;
145
146 sprintf(name, "timer%d", gptimer_id);
147 omap_hwmod_setup_one(name);
148 oh = omap_hwmod_lookup(name);
149 if (!oh)
150 return -ENODEV;
151
152 timer->irq = oh->mpu_irqs[0].irq;
153 timer->phys_base = oh->slaves[0]->addr->pa_start;
154 size = oh->slaves[0]->addr->pa_end - timer->phys_base;
155
156 /* Static mapping, never released */
157 timer->io_base = ioremap(timer->phys_base, size);
158 if (!timer->io_base)
159 return -ENXIO;
160
161 /* After the dmtimer is using hwmod these clocks won't be needed */
162 sprintf(name, "gpt%d_fck", gptimer_id);
163 timer->fclk = clk_get(NULL, name);
164 if (IS_ERR(timer->fclk))
165 return -ENODEV;
166
167 sprintf(name, "gpt%d_ick", gptimer_id);
168 timer->iclk = clk_get(NULL, name);
169 if (IS_ERR(timer->iclk)) {
170 clk_put(timer->fclk);
171 return -ENODEV;
172 }
173
174 omap_hwmod_enable(oh);
175
176 sys_timer_reserved |= (1 << (gptimer_id - 1));
177
178 if (gptimer_id != 12) {
179 struct clk *src;
180
181 src = clk_get(NULL, fck_source);
182 if (IS_ERR(src)) {
183 res = -EINVAL;
184 } else {
185 res = __omap_dm_timer_set_source(timer->fclk, src);
186 if (IS_ERR_VALUE(res))
187 pr_warning("%s: timer%i cannot set source\n",
188 __func__, gptimer_id);
189 clk_put(src);
190 }
191 }
192 __omap_dm_timer_reset(timer->io_base, 1, 1);
193 timer->posted = 1;
194
195 timer->rate = clk_get_rate(timer->fclk);
196
197 timer->reserved = 1;
198
199 return res;
200}
201
202static void __init omap2_gp_clockevent_init(int gptimer_id,
203 const char *fck_source)
204{
205 int res;
206
207 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
208 BUG_ON(res);
209
210 omap2_gp_timer_irq.dev_id = (void *)&clkev;
211 setup_irq(clkev.irq, &omap2_gp_timer_irq);
212
213 __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
214
215 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
216 clockevent_gpt.shift);
217 clockevent_gpt.max_delta_ns =
218 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
219 clockevent_gpt.min_delta_ns =
220 clockevent_delta2ns(3, &clockevent_gpt);
221 /* Timer internal resynch latency. */
222
223 clockevent_gpt.cpumask = cpumask_of(0);
224 clockevents_register_device(&clockevent_gpt);
225
226 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
227 gptimer_id, clkev.rate);
228}
229
230/* Clocksource code */
231
232#ifdef CONFIG_OMAP_32K_TIMER
233/*
234 * When 32k-timer is enabled, don't use GPTimer for clocksource
235 * instead, just leave default clocksource which uses the 32k
236 * sync counter. See clocksource setup in plat-omap/counter_32k.c
237 */
238
239static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
240{
241 omap_init_clocksource_32k();
242}
243
244#else
245
246static struct omap_dm_timer clksrc;
247
248/*
249 * clocksource
250 */
251static DEFINE_CLOCK_DATA(cd);
252static cycle_t clocksource_read_cycles(struct clocksource *cs)
253{
254 return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
255}
256
257static struct clocksource clocksource_gpt = {
258 .name = "gp timer",
259 .rating = 300,
260 .read = clocksource_read_cycles,
261 .mask = CLOCKSOURCE_MASK(32),
262 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
263};
264
265static void notrace dmtimer_update_sched_clock(void)
266{
267 u32 cyc;
268
269 cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
270
271 update_sched_clock(&cd, cyc, (u32)~0);
272}
273
274unsigned long long notrace sched_clock(void)
275{
276 u32 cyc = 0;
277
278 if (clksrc.reserved)
279 cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
280
281 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
282}
283
284/* Setup free-running counter for clocksource */
285static void __init omap2_gp_clocksource_init(int gptimer_id,
286 const char *fck_source)
287{
288 int res;
289
290 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
291 BUG_ON(res);
292
293 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
294 gptimer_id, clksrc.rate);
295
296 __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
297 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
298
299 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
300 pr_err("Could not register clocksource %s\n",
301 clocksource_gpt.name);
302}
303#endif
304
305#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
306 clksrc_nr, clksrc_src) \
307static void __init omap##name##_timer_init(void) \
308{ \
309 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
310 omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
311}
312
313#define OMAP_SYS_TIMER(name) \
314struct sys_timer omap##name##_timer = { \
315 .init = omap##name##_timer_init, \
316};
317
318#ifdef CONFIG_ARCH_OMAP2
319OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
320OMAP_SYS_TIMER(2)
321#endif
322
323#ifdef CONFIG_ARCH_OMAP3
324OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
325OMAP_SYS_TIMER(3)
326OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
327 2, OMAP3_MPU_SOURCE)
328OMAP_SYS_TIMER(3_secure)
329#endif
330
331#ifdef CONFIG_ARCH_OMAP4
332static void __init omap4_timer_init(void)
333{
334#ifdef CONFIG_LOCAL_TIMERS
335 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
336 BUG_ON(!twd_base);
337#endif
338 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
339 omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
340}
341OMAP_SYS_TIMER(4)
342#endif
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index f7fed6080190..c13bc3d3eb2c 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -126,7 +126,7 @@ static inline unsigned long long notrace _omap_32k_sched_clock(void)
126 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); 126 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
127} 127}
128 128
129#ifndef CONFIG_OMAP_MPU_TIMER 129#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
130unsigned long long notrace sched_clock(void) 130unsigned long long notrace sched_clock(void)
131{ 131{
132 return _omap_32k_sched_clock(); 132 return _omap_32k_sched_clock();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee9f6ebba29b..8dfb8186b2c2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,127 +41,6 @@
41#include <plat/dmtimer.h> 41#include <plat/dmtimer.h>
42#include <mach/irqs.h> 42#include <mach/irqs.h>
43 43
44/* register offsets */
45#define _OMAP_TIMER_ID_OFFSET 0x00
46#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
47#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
48#define _OMAP_TIMER_STAT_OFFSET 0x18
49#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
50#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
51#define _OMAP_TIMER_CTRL_OFFSET 0x24
52#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
53#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
54#define OMAP_TIMER_CTRL_PT (1 << 12)
55#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
56#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
57#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
58#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
59#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
60#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
61#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
62#define OMAP_TIMER_CTRL_POSTED (1 << 2)
63#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
64#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
65#define _OMAP_TIMER_COUNTER_OFFSET 0x28
66#define _OMAP_TIMER_LOAD_OFFSET 0x2c
67#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
68#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
69#define WP_NONE 0 /* no write pending bit */
70#define WP_TCLR (1 << 0)
71#define WP_TCRR (1 << 1)
72#define WP_TLDR (1 << 2)
73#define WP_TTGR (1 << 3)
74#define WP_TMAR (1 << 4)
75#define WP_TPIR (1 << 5)
76#define WP_TNIR (1 << 6)
77#define WP_TCVR (1 << 7)
78#define WP_TOCR (1 << 8)
79#define WP_TOWR (1 << 9)
80#define _OMAP_TIMER_MATCH_OFFSET 0x38
81#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
82#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
83#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
84#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
85#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
86#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
87#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
88#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
89
90/* register offsets with the write pending bit encoded */
91#define WPSHIFT 16
92
93#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
94 | (WP_NONE << WPSHIFT))
95
96#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
97 | (WP_NONE << WPSHIFT))
98
99#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
109 | (WP_NONE << WPSHIFT))
110
111#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
112 | (WP_TCLR << WPSHIFT))
113
114#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
115 | (WP_TCRR << WPSHIFT))
116
117#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
118 | (WP_TLDR << WPSHIFT))
119
120#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
121 | (WP_TTGR << WPSHIFT))
122
123#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
124 | (WP_NONE << WPSHIFT))
125
126#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
127 | (WP_TMAR << WPSHIFT))
128
129#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
133 | (WP_NONE << WPSHIFT))
134
135#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
136 | (WP_NONE << WPSHIFT))
137
138#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
139 | (WP_TPIR << WPSHIFT))
140
141#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
142 | (WP_TNIR << WPSHIFT))
143
144#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
145 | (WP_TCVR << WPSHIFT))
146
147#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
148 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
149
150#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
151 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
152
153struct omap_dm_timer {
154 unsigned long phys_base;
155 int irq;
156#ifdef CONFIG_ARCH_OMAP2PLUS
157 struct clk *iclk, *fclk;
158#endif
159 void __iomem *io_base;
160 unsigned reserved:1;
161 unsigned enabled:1;
162 unsigned posted:1;
163};
164
165static int dm_timer_count; 44static int dm_timer_count;
166 45
167#ifdef CONFIG_ARCH_OMAP1 46#ifdef CONFIG_ARCH_OMAP1
@@ -291,11 +170,7 @@ static spinlock_t dm_timer_lock;
291 */ 170 */
292static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) 171static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
293{ 172{
294 if (timer->posted) 173 return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
295 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
296 & (reg >> WPSHIFT))
297 cpu_relax();
298 return readl(timer->io_base + (reg & 0xff));
299} 174}
300 175
301/* 176/*
@@ -307,11 +182,7 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
307static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 182static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
308 u32 value) 183 u32 value)
309{ 184{
310 if (timer->posted) 185 __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
311 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
312 & (reg >> WPSHIFT))
313 cpu_relax();
314 writel(value, timer->io_base + (reg & 0xff));
315} 186}
316 187
317static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 188static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -330,7 +201,7 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
330 201
331static void omap_dm_timer_reset(struct omap_dm_timer *timer) 202static void omap_dm_timer_reset(struct omap_dm_timer *timer)
332{ 203{
333 u32 l; 204 int autoidle = 0, wakeup = 0;
334 205
335 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) { 206 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
336 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 207 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
@@ -338,28 +209,21 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
338 } 209 }
339 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 210 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
340 211
341 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
342 l |= 0x02 << 3; /* Set to smart-idle mode */
343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
344
345 /* Enable autoidle on OMAP2 / OMAP3 */ 212 /* Enable autoidle on OMAP2 / OMAP3 */
346 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 213 if (cpu_is_omap24xx() || cpu_is_omap34xx())
347 l |= 0x1 << 0; 214 autoidle = 1;
348 215
349 /* 216 /*
350 * Enable wake-up on OMAP2 CPUs. 217 * Enable wake-up on OMAP2 CPUs.
351 */ 218 */
352 if (cpu_class_is_omap2()) 219 if (cpu_class_is_omap2())
353 l |= 1 << 2; 220 wakeup = 1;
354 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
355 221
356 /* Match hardware reset default of posted mode */ 222 __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
357 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
358 OMAP_TIMER_CTRL_POSTED);
359 timer->posted = 1; 223 timer->posted = 1;
360} 224}
361 225
362static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 226void omap_dm_timer_prepare(struct omap_dm_timer *timer)
363{ 227{
364 omap_dm_timer_enable(timer); 228 omap_dm_timer_enable(timer);
365 omap_dm_timer_reset(timer); 229 omap_dm_timer_reset(timer);
@@ -531,25 +395,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
531 395
532void omap_dm_timer_stop(struct omap_dm_timer *timer) 396void omap_dm_timer_stop(struct omap_dm_timer *timer)
533{ 397{
534 u32 l; 398 unsigned long rate = 0;
535 399
536 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
537 if (l & OMAP_TIMER_CTRL_ST) {
538 l &= ~0x1;
539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
540#ifdef CONFIG_ARCH_OMAP2PLUS 400#ifdef CONFIG_ARCH_OMAP2PLUS
541 /* Readback to make sure write has completed */ 401 rate = clk_get_rate(timer->fclk);
542 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
543 /*
544 * Wait for functional clock period x 3.5 to make sure that
545 * timer is stopped
546 */
547 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
548#endif 402#endif
549 } 403
550 /* Ack possibly pending interrupt */ 404 __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
551 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
552 OMAP_TIMER_INT_OVERFLOW);
553} 405}
554EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 406EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
555 407
@@ -572,22 +424,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
572 424
573int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 425int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
574{ 426{
575 int ret = -EINVAL;
576
577 if (source < 0 || source >= 3) 427 if (source < 0 || source >= 3)
578 return -EINVAL; 428 return -EINVAL;
579 429
580 clk_disable(timer->fclk); 430 return __omap_dm_timer_set_source(timer->fclk,
581 ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); 431 dm_source_clocks[source]);
582 clk_enable(timer->fclk);
583
584 /*
585 * When the functional clock disappears, too quick writes seem
586 * to cause an abort. XXX Is this still necessary?
587 */
588 __delay(300000);
589
590 return ret;
591} 432}
592EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); 433EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
593 434
@@ -625,8 +466,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
625 } 466 }
626 l |= OMAP_TIMER_CTRL_ST; 467 l |= OMAP_TIMER_CTRL_ST;
627 468
628 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); 469 __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
629 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
630} 470}
631EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); 471EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
632 472
@@ -679,8 +519,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
679void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 519void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
680 unsigned int value) 520 unsigned int value)
681{ 521{
682 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); 522 __omap_dm_timer_int_enable(timer->io_base, value);
683 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
684} 523}
685EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); 524EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
686 525
@@ -696,17 +535,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
696 535
697void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 536void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
698{ 537{
699 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); 538 __omap_dm_timer_write_status(timer->io_base, value);
700} 539}
701EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); 540EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
702 541
703unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 542unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
704{ 543{
705 unsigned int l; 544 return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
706
707 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
708
709 return l;
710} 545}
711EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); 546EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
712 547
@@ -737,7 +572,7 @@ int omap_dm_timers_active(void)
737} 572}
738EXPORT_SYMBOL_GPL(omap_dm_timers_active); 573EXPORT_SYMBOL_GPL(omap_dm_timers_active);
739 574
740int __init omap_dm_timer_init(void) 575static int __init omap_dm_timer_init(void)
741{ 576{
742 struct omap_dm_timer *timer; 577 struct omap_dm_timer *timer;
743 int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 578 int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
@@ -790,8 +625,16 @@ int __init omap_dm_timer_init(void)
790 sprintf(clk_name, "gpt%d_fck", i + 1); 625 sprintf(clk_name, "gpt%d_fck", i + 1);
791 timer->fclk = clk_get(NULL, clk_name); 626 timer->fclk = clk_get(NULL, clk_name);
792 } 627 }
628
629 /* One or two timers may be set up early for sys_timer */
630 if (sys_timer_reserved & (1 << i)) {
631 timer->reserved = 1;
632 timer->posted = 1;
633 }
793#endif 634#endif
794 } 635 }
795 636
796 return 0; 637 return 0;
797} 638}
639
640arch_initcall(omap_dm_timer_init);
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index f1899a3e4174..387a9638991b 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ 39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
40#define CK_443X (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_TI816X (1 << 12) 41#define CK_TI816X (1 << 12)
42#define CK_446X (1 << 13)
42 43
43 44
44#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 45#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c6613..21b1beb23e5e 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -58,10 +58,12 @@ struct clkops {
58#define RATE_IN_36XX (1 << 4) 58#define RATE_IN_36XX (1 << 4)
59#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_4430 (1 << 5)
60#define RATE_IN_TI816X (1 << 6) 60#define RATE_IN_TI816X (1 << 6)
61#define RATE_IN_4460 (1 << 7)
61 62
62#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
63#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
64#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 65#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
66#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
65 67
66/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 68/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
67#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 69#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5288130be96e..4564cc697d7f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,7 +34,11 @@
34struct sys_timer; 34struct sys_timer;
35 35
36extern void omap_map_common_io(void); 36extern void omap_map_common_io(void);
37extern struct sys_timer omap_timer; 37extern struct sys_timer omap1_timer;
38extern struct sys_timer omap2_timer;
39extern struct sys_timer omap3_timer;
40extern struct sys_timer omap3_secure_timer;
41extern struct sys_timer omap4_timer;
38extern bool omap_32k_timer_init(void); 42extern bool omap_32k_timer_init(void);
39extern int __init omap_init_clocksource_32k(void); 43extern int __init omap_init_clocksource_32k(void);
40extern unsigned long long notrace omap_32k_sched_clock(void); 44extern unsigned long long notrace omap_32k_sched_clock(void);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 8198bb6cdb5e..67b3d75884cd 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -88,6 +88,7 @@ unsigned int omap_rev(void);
88 * cpu_is_omap243x(): True for OMAP2430 88 * cpu_is_omap243x(): True for OMAP2430
89 * cpu_is_omap343x(): True for OMAP3430 89 * cpu_is_omap343x(): True for OMAP3430
90 * cpu_is_omap443x(): True for OMAP4430 90 * cpu_is_omap443x(): True for OMAP4430
91 * cpu_is_omap446x(): True for OMAP4460
91 */ 92 */
92#define GET_OMAP_CLASS (omap_rev() & 0xff) 93#define GET_OMAP_CLASS (omap_rev() & 0xff)
93 94
@@ -123,6 +124,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
123IS_OMAP_SUBCLASS(343x, 0x343) 124IS_OMAP_SUBCLASS(343x, 0x343)
124IS_OMAP_SUBCLASS(363x, 0x363) 125IS_OMAP_SUBCLASS(363x, 0x363)
125IS_OMAP_SUBCLASS(443x, 0x443) 126IS_OMAP_SUBCLASS(443x, 0x443)
127IS_OMAP_SUBCLASS(446x, 0x446)
126 128
127IS_TI_SUBCLASS(816x, 0x816) 129IS_TI_SUBCLASS(816x, 0x816)
128 130
@@ -137,6 +139,7 @@ IS_TI_SUBCLASS(816x, 0x816)
137#define cpu_is_ti816x() 0 139#define cpu_is_ti816x() 0
138#define cpu_is_omap44xx() 0 140#define cpu_is_omap44xx() 0
139#define cpu_is_omap443x() 0 141#define cpu_is_omap443x() 0
142#define cpu_is_omap446x() 0
140 143
141#if defined(MULTI_OMAP1) 144#if defined(MULTI_OMAP1)
142# if defined(CONFIG_ARCH_OMAP730) 145# if defined(CONFIG_ARCH_OMAP730)
@@ -361,8 +364,10 @@ IS_OMAP_TYPE(3517, 0x3517)
361# if defined(CONFIG_ARCH_OMAP4) 364# if defined(CONFIG_ARCH_OMAP4)
362# undef cpu_is_omap44xx 365# undef cpu_is_omap44xx
363# undef cpu_is_omap443x 366# undef cpu_is_omap443x
367# undef cpu_is_omap446x
364# define cpu_is_omap44xx() is_omap44xx() 368# define cpu_is_omap44xx() is_omap44xx()
365# define cpu_is_omap443x() is_omap443x() 369# define cpu_is_omap443x() is_omap443x()
370# define cpu_is_omap446x() is_omap446x()
366# endif 371# endif
367 372
368/* Macros to detect if we have OMAP1 or OMAP2 */ 373/* Macros to detect if we have OMAP1 or OMAP2 */
@@ -410,6 +415,9 @@ IS_OMAP_TYPE(3517, 0x3517)
410#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) 415#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
411#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) 416#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
412 417
418#define OMAP446X_CLASS 0x44600044
419#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
420
413/* 421/*
414 * omap_chip bits 422 * omap_chip bits
415 * 423 *
@@ -439,13 +447,15 @@ IS_OMAP_TYPE(3517, 0x3517)
439#define CHIP_IS_OMAP4430ES2_1 (1 << 12) 447#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
440#define CHIP_IS_OMAP4430ES2_2 (1 << 13) 448#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
441#define CHIP_IS_TI816X (1 << 14) 449#define CHIP_IS_TI816X (1 << 14)
450#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
442 451
443#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
444 453
445#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
446 CHIP_IS_OMAP4430ES2 | \ 455 CHIP_IS_OMAP4430ES2 | \
447 CHIP_IS_OMAP4430ES2_1 | \ 456 CHIP_IS_OMAP4430ES2_1 | \
448 CHIP_IS_OMAP4430ES2_2) 457 CHIP_IS_OMAP4430ES2_2 | \
458 CHIP_IS_OMAP4460ES1_0)
449 459
450/* 460/*
451 * "GE" here represents "greater than or equal to" in terms of ES 461 * "GE" here represents "greater than or equal to" in terms of ES
@@ -468,7 +478,7 @@ void omap2_check_revision(void);
468/* 478/*
469 * Runtime detection of OMAP3 features 479 * Runtime detection of OMAP3 features
470 */ 480 */
471extern u32 omap3_features; 481extern u32 omap_features;
472 482
473#define OMAP3_HAS_L2CACHE BIT(0) 483#define OMAP3_HAS_L2CACHE BIT(0)
474#define OMAP3_HAS_IVA BIT(1) 484#define OMAP3_HAS_IVA BIT(1)
@@ -478,11 +488,15 @@ extern u32 omap3_features;
478#define OMAP3_HAS_192MHZ_CLK BIT(5) 488#define OMAP3_HAS_192MHZ_CLK BIT(5)
479#define OMAP3_HAS_IO_WAKEUP BIT(6) 489#define OMAP3_HAS_IO_WAKEUP BIT(6)
480#define OMAP3_HAS_SDRC BIT(7) 490#define OMAP3_HAS_SDRC BIT(7)
491#define OMAP4_HAS_MPU_1GHZ BIT(8)
492#define OMAP4_HAS_MPU_1_2GHZ BIT(9)
493#define OMAP4_HAS_MPU_1_5GHZ BIT(10)
494
481 495
482#define OMAP3_HAS_FEATURE(feat,flag) \ 496#define OMAP3_HAS_FEATURE(feat,flag) \
483static inline unsigned int omap3_has_ ##feat(void) \ 497static inline unsigned int omap3_has_ ##feat(void) \
484{ \ 498{ \
485 return (omap3_features & OMAP3_HAS_ ##flag); \ 499 return omap_features & OMAP3_HAS_ ##flag; \
486} \ 500} \
487 501
488OMAP3_HAS_FEATURE(l2cache, L2CACHE) 502OMAP3_HAS_FEATURE(l2cache, L2CACHE)
@@ -494,4 +508,19 @@ OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
494OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) 508OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
495OMAP3_HAS_FEATURE(sdrc, SDRC) 509OMAP3_HAS_FEATURE(sdrc, SDRC)
496 510
511/*
512 * Runtime detection of OMAP4 features
513 */
514extern u32 omap_features;
515
516#define OMAP4_HAS_FEATURE(feat, flag) \
517static inline unsigned int omap4_has_ ##feat(void) \
518{ \
519 return omap_features & OMAP4_HAS_ ##flag; \
520} \
521
522OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
523OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
524OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
525
497#endif 526#endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index d6c70d2f4030..d0f3a2d22fd3 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,6 +32,9 @@
32 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */ 33 */
34 34
35#include <linux/clk.h>
36#include <linux/delay.h>
37
35#ifndef __ASM_ARCH_DMTIMER_H 38#ifndef __ASM_ARCH_DMTIMER_H
36#define __ASM_ARCH_DMTIMER_H 39#define __ASM_ARCH_DMTIMER_H
37 40
@@ -56,12 +59,8 @@
56 */ 59 */
57#define OMAP_TIMER_IP_VERSION_1 0x1 60#define OMAP_TIMER_IP_VERSION_1 0x1
58struct omap_dm_timer; 61struct omap_dm_timer;
59extern struct omap_dm_timer *gptimer_wakeup;
60extern struct sys_timer omap_timer;
61struct clk; 62struct clk;
62 63
63int omap_dm_timer_init(void);
64
65struct omap_dm_timer *omap_dm_timer_request(void); 64struct omap_dm_timer *omap_dm_timer_request(void);
66struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 65struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
67void omap_dm_timer_free(struct omap_dm_timer *timer); 66void omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -93,5 +92,248 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
93 92
94int omap_dm_timers_active(void); 93int omap_dm_timers_active(void);
95 94
95/*
96 * Do not use the defines below, they are not needed. They should be only
97 * used by dmtimer.c and sys_timer related code.
98 */
99
100/* register offsets */
101#define _OMAP_TIMER_ID_OFFSET 0x00
102#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
103#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
104#define _OMAP_TIMER_STAT_OFFSET 0x18
105#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
106#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
107#define _OMAP_TIMER_CTRL_OFFSET 0x24
108#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
109#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
110#define OMAP_TIMER_CTRL_PT (1 << 12)
111#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
112#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
113#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
114#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
115#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
116#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
117#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
118#define OMAP_TIMER_CTRL_POSTED (1 << 2)
119#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
120#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
121#define _OMAP_TIMER_COUNTER_OFFSET 0x28
122#define _OMAP_TIMER_LOAD_OFFSET 0x2c
123#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
124#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
125#define WP_NONE 0 /* no write pending bit */
126#define WP_TCLR (1 << 0)
127#define WP_TCRR (1 << 1)
128#define WP_TLDR (1 << 2)
129#define WP_TTGR (1 << 3)
130#define WP_TMAR (1 << 4)
131#define WP_TPIR (1 << 5)
132#define WP_TNIR (1 << 6)
133#define WP_TCVR (1 << 7)
134#define WP_TOCR (1 << 8)
135#define WP_TOWR (1 << 9)
136#define _OMAP_TIMER_MATCH_OFFSET 0x38
137#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
138#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
139#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
140#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
141#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
142#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
143#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
144#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
145
146/* register offsets with the write pending bit encoded */
147#define WPSHIFT 16
148
149#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
150 | (WP_NONE << WPSHIFT))
151
152#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
153 | (WP_NONE << WPSHIFT))
154
155#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
156 | (WP_NONE << WPSHIFT))
157
158#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
159 | (WP_NONE << WPSHIFT))
160
161#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
162 | (WP_NONE << WPSHIFT))
163
164#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
165 | (WP_NONE << WPSHIFT))
166
167#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
168 | (WP_TCLR << WPSHIFT))
169
170#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
171 | (WP_TCRR << WPSHIFT))
172
173#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
174 | (WP_TLDR << WPSHIFT))
175
176#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
177 | (WP_TTGR << WPSHIFT))
178
179#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
180 | (WP_NONE << WPSHIFT))
181
182#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
183 | (WP_TMAR << WPSHIFT))
184
185#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
186 | (WP_NONE << WPSHIFT))
187
188#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
189 | (WP_NONE << WPSHIFT))
190
191#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
192 | (WP_NONE << WPSHIFT))
193
194#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
195 | (WP_TPIR << WPSHIFT))
196
197#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
198 | (WP_TNIR << WPSHIFT))
199
200#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
201 | (WP_TCVR << WPSHIFT))
202
203#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
204 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
205
206#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
207 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
208
209struct omap_dm_timer {
210 unsigned long phys_base;
211 int irq;
212#ifdef CONFIG_ARCH_OMAP2PLUS
213 struct clk *iclk, *fclk;
214#endif
215 void __iomem *io_base;
216 unsigned long rate;
217 unsigned reserved:1;
218 unsigned enabled:1;
219 unsigned posted:1;
220};
221
222extern u32 sys_timer_reserved;
223void omap_dm_timer_prepare(struct omap_dm_timer *timer);
224
225static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
226 int posted)
227{
228 if (posted)
229 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
230 & (reg >> WPSHIFT))
231 cpu_relax();
232
233 return __raw_readl(base + (reg & 0xff));
234}
235
236static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
237 int posted)
238{
239 if (posted)
240 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
241 & (reg >> WPSHIFT))
242 cpu_relax();
243
244 __raw_writel(val, base + (reg & 0xff));
245}
246
247/* Assumes the source clock has been set by caller */
248static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
249 int wakeup)
250{
251 u32 l;
252
253 l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
254 l |= 0x02 << 3; /* Set to smart-idle mode */
255 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
256
257 if (autoidle)
258 l |= 0x1 << 0;
259
260 if (wakeup)
261 l |= 1 << 2;
262
263 __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
264
265 /* Match hardware reset default of posted mode */
266 __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
267 OMAP_TIMER_CTRL_POSTED, 0);
268}
269
270static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
271 struct clk *parent)
272{
273 int ret;
274
275 clk_disable(timer_fck);
276 ret = clk_set_parent(timer_fck, parent);
277 clk_enable(timer_fck);
278
279 /*
280 * When the functional clock disappears, too quick writes seem
281 * to cause an abort. XXX Is this still necessary?
282 */
283 __delay(300000);
284
285 return ret;
286}
287
288static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
289 unsigned long rate)
290{
291 u32 l;
292
293 l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
294 if (l & OMAP_TIMER_CTRL_ST) {
295 l &= ~0x1;
296 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
297#ifdef CONFIG_ARCH_OMAP2PLUS
298 /* Readback to make sure write has completed */
299 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
300 /*
301 * Wait for functional clock period x 3.5 to make sure that
302 * timer is stopped
303 */
304 udelay(3500000 / rate + 1);
305#endif
306 }
307
308 /* Ack possibly pending interrupt */
309 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
310 OMAP_TIMER_INT_OVERFLOW, 0);
311}
312
313static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
314 unsigned int load, int posted)
315{
316 __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
317 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
318}
319
320static inline void __omap_dm_timer_int_enable(void __iomem *base,
321 unsigned int value)
322{
323 __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
324 __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
325}
326
327static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
328 int posted)
329{
330 return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
331}
332
333static inline void __omap_dm_timer_write_status(void __iomem *base,
334 unsigned int value)
335{
336 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
337}
96 338
97#endif /* __ASM_ARCH_DMTIMER_H */ 339#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 5a25098ea7ea..c88432005665 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,7 +428,11 @@
428#define INTCPS_NR_IRQS 96 428#define INTCPS_NR_IRQS 96
429 429
430#ifndef __ASSEMBLY__ 430#ifndef __ASSEMBLY__
431extern void omap_init_irq(void); 431extern void __iomem *omap_irq_base;
432void omap1_init_irq(void);
433void omap2_init_irq(void);
434void omap3_init_irq(void);
435void ti816x_init_irq(void);
432extern int omap_irq_pending(void); 436extern int omap_irq_pending(void);
433void omap_intc_save_context(void); 437void omap_intc_save_context(void);
434void omap_intc_restore_context(void); 438void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index f8f690ab2997..6c5350832407 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -24,7 +24,6 @@
24#ifndef __ASM_ARCH_OMAP_MCBSP_H 24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/completion.h>
28#include <linux/spinlock.h> 27#include <linux/spinlock.h>
29 28
30#include <mach/hardware.h> 29#include <mach/hardware.h>
@@ -340,10 +339,6 @@ typedef enum {
340 OMAP_MCBSP5 339 OMAP_MCBSP5
341} omap_mcbsp_id; 340} omap_mcbsp_id;
342 341
343typedef int __bitwise omap_mcbsp_io_type_t;
344#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
345#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
346
347typedef enum { 342typedef enum {
348 OMAP_MCBSP_WORD_8 = 0, 343 OMAP_MCBSP_WORD_8 = 0,
349 OMAP_MCBSP_WORD_12, 344 OMAP_MCBSP_WORD_12,
@@ -353,38 +348,6 @@ typedef enum {
353 OMAP_MCBSP_WORD_32, 348 OMAP_MCBSP_WORD_32,
354} omap_mcbsp_word_length; 349} omap_mcbsp_word_length;
355 350
356typedef enum {
357 OMAP_MCBSP_CLK_RISING = 0,
358 OMAP_MCBSP_CLK_FALLING,
359} omap_mcbsp_clk_polarity;
360
361typedef enum {
362 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
363 OMAP_MCBSP_FS_ACTIVE_LOW,
364} omap_mcbsp_fs_polarity;
365
366typedef enum {
367 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
368 OMAP_MCBSP_CLK_STP_MODE_DELAY,
369} omap_mcbsp_clk_stp_mode;
370
371
372/******* SPI specific mode **********/
373typedef enum {
374 OMAP_MCBSP_SPI_MASTER = 0,
375 OMAP_MCBSP_SPI_SLAVE,
376} omap_mcbsp_spi_mode;
377
378struct omap_mcbsp_spi_cfg {
379 omap_mcbsp_spi_mode spi_mode;
380 omap_mcbsp_clk_polarity rx_clock_polarity;
381 omap_mcbsp_clk_polarity tx_clock_polarity;
382 omap_mcbsp_fs_polarity fsx_polarity;
383 u8 clk_div;
384 omap_mcbsp_clk_stp_mode clk_stp_mode;
385 omap_mcbsp_word_length word_length;
386};
387
388/* Platform specific configuration */ 351/* Platform specific configuration */
389struct omap_mcbsp_ops { 352struct omap_mcbsp_ops {
390 void (*request)(unsigned int); 353 void (*request)(unsigned int);
@@ -425,22 +388,12 @@ struct omap_mcbsp {
425 omap_mcbsp_word_length rx_word_length; 388 omap_mcbsp_word_length rx_word_length;
426 omap_mcbsp_word_length tx_word_length; 389 omap_mcbsp_word_length tx_word_length;
427 390
428 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
429 /* IRQ based TX/RX */
430 int rx_irq; 391 int rx_irq;
431 int tx_irq; 392 int tx_irq;
432 393
433 /* DMA stuff */ 394 /* DMA stuff */
434 u8 dma_rx_sync; 395 u8 dma_rx_sync;
435 short dma_rx_lch;
436 u8 dma_tx_sync; 396 u8 dma_tx_sync;
437 short dma_tx_lch;
438
439 /* Completion queues */
440 struct completion tx_irq_completion;
441 struct completion rx_irq_completion;
442 struct completion tx_dma_completion;
443 struct completion rx_dma_completion;
444 397
445 /* Protect the field .free, while checking if the mcbsp is in use */ 398 /* Protect the field .free, while checking if the mcbsp is in use */
446 spinlock_t lock; 399 spinlock_t lock;
@@ -499,24 +452,9 @@ int omap_mcbsp_request(unsigned int id);
499void omap_mcbsp_free(unsigned int id); 452void omap_mcbsp_free(unsigned int id);
500void omap_mcbsp_start(unsigned int id, int tx, int rx); 453void omap_mcbsp_start(unsigned int id, int tx, int rx);
501void omap_mcbsp_stop(unsigned int id, int tx, int rx); 454void omap_mcbsp_stop(unsigned int id, int tx, int rx);
502void omap_mcbsp_xmit_word(unsigned int id, u32 word);
503u32 omap_mcbsp_recv_word(unsigned int id);
504
505int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
506int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
507int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
508int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
509
510 455
511/* McBSP functional clock source changing function */ 456/* McBSP functional clock source changing function */
512extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); 457extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
513/* SPI specific API */
514void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
515
516/* Polled read/write functions */
517int omap_mcbsp_pollread(unsigned int id, u16 * buf);
518int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
519int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
520 458
521/* McBSP signal muxing API */ 459/* McBSP signal muxing API */
522void omap2_mcbsp1_mux_clkr_src(u8 mux); 460void omap2_mcbsp1_mux_clkr_src(u8 mux);
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d86d1ecf0068..67fc5060183e 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -19,15 +19,11 @@ enum nand_io {
19}; 19};
20 20
21struct omap_nand_platform_data { 21struct omap_nand_platform_data {
22 unsigned int options;
23 int cs; 22 int cs;
24 int gpio_irq;
25 struct mtd_partition *parts; 23 struct mtd_partition *parts;
26 struct gpmc_timings *gpmc_t; 24 struct gpmc_timings *gpmc_t;
27 int nr_parts; 25 int nr_parts;
28 int (*nand_setup)(void); 26 bool dev_ready;
29 int (*dev_ready)(struct omap_nand_platform_data *);
30 int dma_channel;
31 int gpmc_irq; 27 int gpmc_irq;
32 enum nand_io xfer_type; 28 enum nand_io xfer_type;
33 unsigned long phys_base; 29 unsigned long phys_base;
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 5587acf0eb2c..455eadcd820c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -16,8 +16,6 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h> 19#include <linux/interrupt.h>
22#include <linux/err.h> 20#include <linux/err.h>
23#include <linux/clk.h> 21#include <linux/clk.h>
@@ -25,7 +23,6 @@
25#include <linux/io.h> 23#include <linux/io.h>
26#include <linux/slab.h> 24#include <linux/slab.h>
27 25
28#include <plat/dma.h>
29#include <plat/mcbsp.h> 26#include <plat/mcbsp.h>
30#include <plat/omap_device.h> 27#include <plat/omap_device.h>
31#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
@@ -136,8 +133,6 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
136 irqst_spcr2); 133 irqst_spcr2);
137 /* Writing zero to XSYNC_ERR clears the IRQ */ 134 /* Writing zero to XSYNC_ERR clears the IRQ */
138 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2)); 135 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
139 } else {
140 complete(&mcbsp_tx->tx_irq_completion);
141 } 136 }
142 137
143 return IRQ_HANDLED; 138 return IRQ_HANDLED;
@@ -156,41 +151,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
156 irqst_spcr1); 151 irqst_spcr1);
157 /* Writing zero to RSYNC_ERR clears the IRQ */ 152 /* Writing zero to RSYNC_ERR clears the IRQ */
158 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1)); 153 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
159 } else {
160 complete(&mcbsp_rx->rx_irq_completion);
161 } 154 }
162 155
163 return IRQ_HANDLED; 156 return IRQ_HANDLED;
164} 157}
165 158
166static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
167{
168 struct omap_mcbsp *mcbsp_dma_tx = data;
169
170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
172
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
176
177 complete(&mcbsp_dma_tx->tx_dma_completion);
178}
179
180static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
181{
182 struct omap_mcbsp *mcbsp_dma_rx = data;
183
184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
186
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
190
191 complete(&mcbsp_dma_rx->rx_dma_completion);
192}
193
194/* 159/*
195 * omap_mcbsp_config simply write a config to the 160 * omap_mcbsp_config simply write a config to the
196 * appropriate McBSP. 161 * appropriate McBSP.
@@ -758,37 +723,6 @@ static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
758static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {} 723static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
759#endif 724#endif
760 725
761/*
762 * We can choose between IRQ based or polled IO.
763 * This needs to be called before omap_mcbsp_request().
764 */
765int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
766{
767 struct omap_mcbsp *mcbsp;
768
769 if (!omap_mcbsp_check_valid_id(id)) {
770 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
771 return -ENODEV;
772 }
773 mcbsp = id_to_mcbsp_ptr(id);
774
775 spin_lock(&mcbsp->lock);
776
777 if (!mcbsp->free) {
778 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
779 mcbsp->id);
780 spin_unlock(&mcbsp->lock);
781 return -EINVAL;
782 }
783
784 mcbsp->io_type = io_type;
785
786 spin_unlock(&mcbsp->lock);
787
788 return 0;
789}
790EXPORT_SYMBOL(omap_mcbsp_set_io_type);
791
792int omap_mcbsp_request(unsigned int id) 726int omap_mcbsp_request(unsigned int id)
793{ 727{
794 struct omap_mcbsp *mcbsp; 728 struct omap_mcbsp *mcbsp;
@@ -833,29 +767,24 @@ int omap_mcbsp_request(unsigned int id)
833 MCBSP_WRITE(mcbsp, SPCR1, 0); 767 MCBSP_WRITE(mcbsp, SPCR1, 0);
834 MCBSP_WRITE(mcbsp, SPCR2, 0); 768 MCBSP_WRITE(mcbsp, SPCR2, 0);
835 769
836 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { 770 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
837 /* We need to get IRQs here */ 771 0, "McBSP", (void *)mcbsp);
838 init_completion(&mcbsp->tx_irq_completion); 772 if (err != 0) {
839 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 773 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
840 0, "McBSP", (void *)mcbsp); 774 "for McBSP%d\n", mcbsp->tx_irq,
775 mcbsp->id);
776 goto err_clk_disable;
777 }
778
779 if (mcbsp->rx_irq) {
780 err = request_irq(mcbsp->rx_irq,
781 omap_mcbsp_rx_irq_handler,
782 0, "McBSP", (void *)mcbsp);
841 if (err != 0) { 783 if (err != 0) {
842 dev_err(mcbsp->dev, "Unable to request TX IRQ %d " 784 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
843 "for McBSP%d\n", mcbsp->tx_irq, 785 "for McBSP%d\n", mcbsp->rx_irq,
844 mcbsp->id); 786 mcbsp->id);
845 goto err_clk_disable; 787 goto err_free_irq;
846 }
847
848 if (mcbsp->rx_irq) {
849 init_completion(&mcbsp->rx_irq_completion);
850 err = request_irq(mcbsp->rx_irq,
851 omap_mcbsp_rx_irq_handler,
852 0, "McBSP", (void *)mcbsp);
853 if (err != 0) {
854 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
855 "for McBSP%d\n", mcbsp->rx_irq,
856 mcbsp->id);
857 goto err_free_irq;
858 }
859 } 788 }
860 } 789 }
861 790
@@ -901,12 +830,9 @@ void omap_mcbsp_free(unsigned int id)
901 830
902 pm_runtime_put_sync(mcbsp->dev); 831 pm_runtime_put_sync(mcbsp->dev);
903 832
904 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { 833 if (mcbsp->rx_irq)
905 /* Free IRQs */ 834 free_irq(mcbsp->rx_irq, (void *)mcbsp);
906 if (mcbsp->rx_irq) 835 free_irq(mcbsp->tx_irq, (void *)mcbsp);
907 free_irq(mcbsp->rx_irq, (void *)mcbsp);
908 free_irq(mcbsp->tx_irq, (void *)mcbsp);
909 }
910 836
911 reg_cache = mcbsp->reg_cache; 837 reg_cache = mcbsp->reg_cache;
912 838
@@ -1043,485 +969,6 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
1043} 969}
1044EXPORT_SYMBOL(omap_mcbsp_stop); 970EXPORT_SYMBOL(omap_mcbsp_stop);
1045 971
1046/* polled mcbsp i/o operations */
1047int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
1048{
1049 struct omap_mcbsp *mcbsp;
1050
1051 if (!omap_mcbsp_check_valid_id(id)) {
1052 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1053 return -ENODEV;
1054 }
1055
1056 mcbsp = id_to_mcbsp_ptr(id);
1057
1058 MCBSP_WRITE(mcbsp, DXR1, buf);
1059 /* if frame sync error - clear the error */
1060 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1061 /* clear error */
1062 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1063 /* resend */
1064 return -1;
1065 } else {
1066 /* wait for transmit confirmation */
1067 int attemps = 0;
1068 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1069 if (attemps++ > 1000) {
1070 MCBSP_WRITE(mcbsp, SPCR2,
1071 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1072 (~XRST));
1073 udelay(10);
1074 MCBSP_WRITE(mcbsp, SPCR2,
1075 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1076 (XRST));
1077 udelay(10);
1078 dev_err(mcbsp->dev, "Could not write to"
1079 " McBSP%d Register\n", mcbsp->id);
1080 return -2;
1081 }
1082 }
1083 }
1084
1085 return 0;
1086}
1087EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1088
1089int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1090{
1091 struct omap_mcbsp *mcbsp;
1092
1093 if (!omap_mcbsp_check_valid_id(id)) {
1094 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1095 return -ENODEV;
1096 }
1097 mcbsp = id_to_mcbsp_ptr(id);
1098
1099 /* if frame sync error - clear the error */
1100 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1101 /* clear error */
1102 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1103 /* resend */
1104 return -1;
1105 } else {
1106 /* wait for receive confirmation */
1107 int attemps = 0;
1108 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1109 if (attemps++ > 1000) {
1110 MCBSP_WRITE(mcbsp, SPCR1,
1111 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1112 (~RRST));
1113 udelay(10);
1114 MCBSP_WRITE(mcbsp, SPCR1,
1115 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1116 (RRST));
1117 udelay(10);
1118 dev_err(mcbsp->dev, "Could not read from"
1119 " McBSP%d Register\n", mcbsp->id);
1120 return -2;
1121 }
1122 }
1123 }
1124 *buf = MCBSP_READ(mcbsp, DRR1);
1125
1126 return 0;
1127}
1128EXPORT_SYMBOL(omap_mcbsp_pollread);
1129
1130/*
1131 * IRQ based word transmission.
1132 */
1133void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1134{
1135 struct omap_mcbsp *mcbsp;
1136 omap_mcbsp_word_length word_length;
1137
1138 if (!omap_mcbsp_check_valid_id(id)) {
1139 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1140 return;
1141 }
1142
1143 mcbsp = id_to_mcbsp_ptr(id);
1144 word_length = mcbsp->tx_word_length;
1145
1146 wait_for_completion(&mcbsp->tx_irq_completion);
1147
1148 if (word_length > OMAP_MCBSP_WORD_16)
1149 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1151}
1152EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1153
1154u32 omap_mcbsp_recv_word(unsigned int id)
1155{
1156 struct omap_mcbsp *mcbsp;
1157 u16 word_lsb, word_msb = 0;
1158 omap_mcbsp_word_length word_length;
1159
1160 if (!omap_mcbsp_check_valid_id(id)) {
1161 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1162 return -ENODEV;
1163 }
1164 mcbsp = id_to_mcbsp_ptr(id);
1165
1166 word_length = mcbsp->rx_word_length;
1167
1168 wait_for_completion(&mcbsp->rx_irq_completion);
1169
1170 if (word_length > OMAP_MCBSP_WORD_16)
1171 word_msb = MCBSP_READ(mcbsp, DRR2);
1172 word_lsb = MCBSP_READ(mcbsp, DRR1);
1173
1174 return (word_lsb | (word_msb << 16));
1175}
1176EXPORT_SYMBOL(omap_mcbsp_recv_word);
1177
1178int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1179{
1180 struct omap_mcbsp *mcbsp;
1181 omap_mcbsp_word_length tx_word_length;
1182 omap_mcbsp_word_length rx_word_length;
1183 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1184
1185 if (!omap_mcbsp_check_valid_id(id)) {
1186 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1187 return -ENODEV;
1188 }
1189 mcbsp = id_to_mcbsp_ptr(id);
1190 tx_word_length = mcbsp->tx_word_length;
1191 rx_word_length = mcbsp->rx_word_length;
1192
1193 if (tx_word_length != rx_word_length)
1194 return -EINVAL;
1195
1196 /* First we wait for the transmitter to be ready */
1197 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1198 while (!(spcr2 & XRDY)) {
1199 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1200 if (attempts++ > 1000) {
1201 /* We must reset the transmitter */
1202 MCBSP_WRITE(mcbsp, SPCR2,
1203 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1204 udelay(10);
1205 MCBSP_WRITE(mcbsp, SPCR2,
1206 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1207 udelay(10);
1208 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1209 "ready\n", mcbsp->id);
1210 return -EAGAIN;
1211 }
1212 }
1213
1214 /* Now we can push the data */
1215 if (tx_word_length > OMAP_MCBSP_WORD_16)
1216 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1217 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1218
1219 /* We wait for the receiver to be ready */
1220 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1221 while (!(spcr1 & RRDY)) {
1222 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1223 if (attempts++ > 1000) {
1224 /* We must reset the receiver */
1225 MCBSP_WRITE(mcbsp, SPCR1,
1226 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1227 udelay(10);
1228 MCBSP_WRITE(mcbsp, SPCR1,
1229 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1230 udelay(10);
1231 dev_err(mcbsp->dev, "McBSP%d receiver not "
1232 "ready\n", mcbsp->id);
1233 return -EAGAIN;
1234 }
1235 }
1236
1237 /* Receiver is ready, let's read the dummy data */
1238 if (rx_word_length > OMAP_MCBSP_WORD_16)
1239 word_msb = MCBSP_READ(mcbsp, DRR2);
1240 word_lsb = MCBSP_READ(mcbsp, DRR1);
1241
1242 return 0;
1243}
1244EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1245
1246int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1247{
1248 struct omap_mcbsp *mcbsp;
1249 u32 clock_word = 0;
1250 omap_mcbsp_word_length tx_word_length;
1251 omap_mcbsp_word_length rx_word_length;
1252 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1253
1254 if (!omap_mcbsp_check_valid_id(id)) {
1255 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1256 return -ENODEV;
1257 }
1258
1259 mcbsp = id_to_mcbsp_ptr(id);
1260
1261 tx_word_length = mcbsp->tx_word_length;
1262 rx_word_length = mcbsp->rx_word_length;
1263
1264 if (tx_word_length != rx_word_length)
1265 return -EINVAL;
1266
1267 /* First we wait for the transmitter to be ready */
1268 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1269 while (!(spcr2 & XRDY)) {
1270 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1271 if (attempts++ > 1000) {
1272 /* We must reset the transmitter */
1273 MCBSP_WRITE(mcbsp, SPCR2,
1274 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1275 udelay(10);
1276 MCBSP_WRITE(mcbsp, SPCR2,
1277 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1278 udelay(10);
1279 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1280 "ready\n", mcbsp->id);
1281 return -EAGAIN;
1282 }
1283 }
1284
1285 /* We first need to enable the bus clock */
1286 if (tx_word_length > OMAP_MCBSP_WORD_16)
1287 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1288 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1289
1290 /* We wait for the receiver to be ready */
1291 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1292 while (!(spcr1 & RRDY)) {
1293 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1294 if (attempts++ > 1000) {
1295 /* We must reset the receiver */
1296 MCBSP_WRITE(mcbsp, SPCR1,
1297 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1298 udelay(10);
1299 MCBSP_WRITE(mcbsp, SPCR1,
1300 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1301 udelay(10);
1302 dev_err(mcbsp->dev, "McBSP%d receiver not "
1303 "ready\n", mcbsp->id);
1304 return -EAGAIN;
1305 }
1306 }
1307
1308 /* Receiver is ready, there is something for us */
1309 if (rx_word_length > OMAP_MCBSP_WORD_16)
1310 word_msb = MCBSP_READ(mcbsp, DRR2);
1311 word_lsb = MCBSP_READ(mcbsp, DRR1);
1312
1313 word[0] = (word_lsb | (word_msb << 16));
1314
1315 return 0;
1316}
1317EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1318
1319/*
1320 * Simple DMA based buffer rx/tx routines.
1321 * Nothing fancy, just a single buffer tx/rx through DMA.
1322 * The DMA resources are released once the transfer is done.
1323 * For anything fancier, you should use your own customized DMA
1324 * routines and callbacks.
1325 */
1326int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1327 unsigned int length)
1328{
1329 struct omap_mcbsp *mcbsp;
1330 int dma_tx_ch;
1331 int src_port = 0;
1332 int dest_port = 0;
1333 int sync_dev = 0;
1334
1335 if (!omap_mcbsp_check_valid_id(id)) {
1336 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1337 return -ENODEV;
1338 }
1339 mcbsp = id_to_mcbsp_ptr(id);
1340
1341 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1342 omap_mcbsp_tx_dma_callback,
1343 mcbsp,
1344 &dma_tx_ch)) {
1345 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1346 "McBSP%d TX. Trying IRQ based TX\n",
1347 mcbsp->id);
1348 return -EAGAIN;
1349 }
1350 mcbsp->dma_tx_lch = dma_tx_ch;
1351
1352 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1353 dma_tx_ch);
1354
1355 init_completion(&mcbsp->tx_dma_completion);
1356
1357 if (cpu_class_is_omap1()) {
1358 src_port = OMAP_DMA_PORT_TIPB;
1359 dest_port = OMAP_DMA_PORT_EMIFF;
1360 }
1361 if (cpu_class_is_omap2())
1362 sync_dev = mcbsp->dma_tx_sync;
1363
1364 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1365 OMAP_DMA_DATA_TYPE_S16,
1366 length >> 1, 1,
1367 OMAP_DMA_SYNC_ELEMENT,
1368 sync_dev, 0);
1369
1370 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1371 src_port,
1372 OMAP_DMA_AMODE_CONSTANT,
1373 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1374 0, 0);
1375
1376 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1377 dest_port,
1378 OMAP_DMA_AMODE_POST_INC,
1379 buffer,
1380 0, 0);
1381
1382 omap_start_dma(mcbsp->dma_tx_lch);
1383 wait_for_completion(&mcbsp->tx_dma_completion);
1384
1385 return 0;
1386}
1387EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1388
1389int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1390 unsigned int length)
1391{
1392 struct omap_mcbsp *mcbsp;
1393 int dma_rx_ch;
1394 int src_port = 0;
1395 int dest_port = 0;
1396 int sync_dev = 0;
1397
1398 if (!omap_mcbsp_check_valid_id(id)) {
1399 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1400 return -ENODEV;
1401 }
1402 mcbsp = id_to_mcbsp_ptr(id);
1403
1404 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1405 omap_mcbsp_rx_dma_callback,
1406 mcbsp,
1407 &dma_rx_ch)) {
1408 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1409 "McBSP%d RX. Trying IRQ based RX\n",
1410 mcbsp->id);
1411 return -EAGAIN;
1412 }
1413 mcbsp->dma_rx_lch = dma_rx_ch;
1414
1415 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1416 dma_rx_ch);
1417
1418 init_completion(&mcbsp->rx_dma_completion);
1419
1420 if (cpu_class_is_omap1()) {
1421 src_port = OMAP_DMA_PORT_TIPB;
1422 dest_port = OMAP_DMA_PORT_EMIFF;
1423 }
1424 if (cpu_class_is_omap2())
1425 sync_dev = mcbsp->dma_rx_sync;
1426
1427 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1428 OMAP_DMA_DATA_TYPE_S16,
1429 length >> 1, 1,
1430 OMAP_DMA_SYNC_ELEMENT,
1431 sync_dev, 0);
1432
1433 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1434 src_port,
1435 OMAP_DMA_AMODE_CONSTANT,
1436 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1437 0, 0);
1438
1439 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1440 dest_port,
1441 OMAP_DMA_AMODE_POST_INC,
1442 buffer,
1443 0, 0);
1444
1445 omap_start_dma(mcbsp->dma_rx_lch);
1446 wait_for_completion(&mcbsp->rx_dma_completion);
1447
1448 return 0;
1449}
1450EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1451
1452/*
1453 * SPI wrapper.
1454 * Since SPI setup is much simpler than the generic McBSP one,
1455 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1456 * Once this is done, you can call omap_mcbsp_start().
1457 */
1458void omap_mcbsp_set_spi_mode(unsigned int id,
1459 const struct omap_mcbsp_spi_cfg *spi_cfg)
1460{
1461 struct omap_mcbsp *mcbsp;
1462 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1463
1464 if (!omap_mcbsp_check_valid_id(id)) {
1465 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1466 return;
1467 }
1468 mcbsp = id_to_mcbsp_ptr(id);
1469
1470 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1471
1472 /* SPI has only one frame */
1473 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1474 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1475
1476 /* Clock stop mode */
1477 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1478 mcbsp_cfg.spcr1 |= (1 << 12);
1479 else
1480 mcbsp_cfg.spcr1 |= (3 << 11);
1481
1482 /* Set clock parities */
1483 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1484 mcbsp_cfg.pcr0 |= CLKRP;
1485 else
1486 mcbsp_cfg.pcr0 &= ~CLKRP;
1487
1488 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1489 mcbsp_cfg.pcr0 &= ~CLKXP;
1490 else
1491 mcbsp_cfg.pcr0 |= CLKXP;
1492
1493 /* Set SCLKME to 0 and CLKSM to 1 */
1494 mcbsp_cfg.pcr0 &= ~SCLKME;
1495 mcbsp_cfg.srgr2 |= CLKSM;
1496
1497 /* Set FSXP */
1498 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1499 mcbsp_cfg.pcr0 &= ~FSXP;
1500 else
1501 mcbsp_cfg.pcr0 |= FSXP;
1502
1503 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1504 mcbsp_cfg.pcr0 |= CLKXM;
1505 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1506 mcbsp_cfg.pcr0 |= FSXM;
1507 mcbsp_cfg.srgr2 &= ~FSGM;
1508 mcbsp_cfg.xcr2 |= XDATDLY(1);
1509 mcbsp_cfg.rcr2 |= RDATDLY(1);
1510 } else {
1511 mcbsp_cfg.pcr0 &= ~CLKXM;
1512 mcbsp_cfg.srgr1 |= CLKGDV(1);
1513 mcbsp_cfg.pcr0 &= ~FSXM;
1514 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1515 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1516 }
1517
1518 mcbsp_cfg.xcr2 &= ~XPHASE;
1519 mcbsp_cfg.rcr2 &= ~RPHASE;
1520
1521 omap_mcbsp_config(id, &mcbsp_cfg);
1522}
1523EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1524
1525#ifdef CONFIG_ARCH_OMAP3 972#ifdef CONFIG_ARCH_OMAP3
1526#define max_thres(m) (mcbsp->pdata->buffer_size) 973#define max_thres(m) (mcbsp->pdata->buffer_size)
1527#define valid_threshold(m, val) ((val) <= max_thres(m)) 974#define valid_threshold(m, val) ((val) <= max_thres(m))
@@ -1833,8 +1280,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1833 spin_lock_init(&mcbsp->lock); 1280 spin_lock_init(&mcbsp->lock);
1834 mcbsp->id = id + 1; 1281 mcbsp->id = id + 1;
1835 mcbsp->free = true; 1282 mcbsp->free = true;
1836 mcbsp->dma_tx_lch = -1;
1837 mcbsp->dma_rx_lch = -1;
1838 1283
1839 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 1284 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1840 if (!res) { 1285 if (!res) {
@@ -1860,9 +1305,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1860 else 1305 else
1861 mcbsp->phys_dma_base = res->start; 1306 mcbsp->phys_dma_base = res->start;
1862 1307
1863 /* Default I/O is IRQ based */
1864 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1865
1866 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 1308 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1867 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 1309 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1868 1310
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 09:15:48 -0500