diff options
author | Christian König <christian.koenig@amd.com> | 2014-06-05 23:56:50 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-06-09 22:06:54 -0400 |
commit | 4510fb985d3c3c5dae4d66af0fbbf95cc0662f35 (patch) | |
tree | 6bd9b76c16c5879d79125ef402a7b2507f12f0b0 | |
parent | c1c4413258e46aef9c27696052a5b7110bdf2941 (diff) |
drm/radeon: make vm_block_size a module parameter
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_vm.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 2 |
7 files changed, 35 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 5e0a41a8e793..e4b2f2b51bb8 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -5446,7 +5446,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) | |||
5446 | (u32)(rdev->dummy_page.addr >> 12)); | 5446 | (u32)(rdev->dummy_page.addr >> 12)); |
5447 | WREG32(VM_CONTEXT1_CNTL2, 4); | 5447 | WREG32(VM_CONTEXT1_CNTL2, 4); |
5448 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | | 5448 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
5449 | PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | | 5449 | PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | |
5450 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 5450 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
5451 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | | 5451 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
5452 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 5452 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 8c3fbb1d412b..c0fd8f647cf0 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1268,7 +1268,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) | |||
1268 | (u32)(rdev->dummy_page.addr >> 12)); | 1268 | (u32)(rdev->dummy_page.addr >> 12)); |
1269 | WREG32(VM_CONTEXT1_CNTL2, 4); | 1269 | WREG32(VM_CONTEXT1_CNTL2, 4); |
1270 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | | 1270 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
1271 | PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | | 1271 | PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | |
1272 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 1272 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
1273 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | | 1273 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
1274 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 1274 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 6f32f16e12dc..dd77111096bd 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -101,6 +101,7 @@ extern int radeon_aspm; | |||
101 | extern int radeon_runtime_pm; | 101 | extern int radeon_runtime_pm; |
102 | extern int radeon_hard_reset; | 102 | extern int radeon_hard_reset; |
103 | extern int radeon_vm_size; | 103 | extern int radeon_vm_size; |
104 | extern int radeon_vm_block_size; | ||
104 | 105 | ||
105 | /* | 106 | /* |
106 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | 107 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
@@ -838,13 +839,8 @@ struct radeon_mec { | |||
838 | /* maximum number of VMIDs */ | 839 | /* maximum number of VMIDs */ |
839 | #define RADEON_NUM_VM 16 | 840 | #define RADEON_NUM_VM 16 |
840 | 841 | ||
841 | /* defines number of bits in page table versus page directory, | ||
842 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | ||
843 | * table and the remaining 19 bits are in the page directory */ | ||
844 | #define RADEON_VM_BLOCK_SIZE 9 | ||
845 | |||
846 | /* number of entries in page table */ | 842 | /* number of entries in page table */ |
847 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | 843 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
848 | 844 | ||
849 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | 845 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
850 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 | 846 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 3f1e3060377c..03686fab842d 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -1073,6 +1073,22 @@ static void radeon_check_arguments(struct radeon_device *rdev) | |||
1073 | radeon_vm_size); | 1073 | radeon_vm_size); |
1074 | radeon_vm_size = 4096; | 1074 | radeon_vm_size = 4096; |
1075 | } | 1075 | } |
1076 | |||
1077 | /* defines number of bits in page table versus page directory, | ||
1078 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | ||
1079 | * page table and the remaining bits are in the page directory */ | ||
1080 | if (radeon_vm_block_size < 9) { | ||
1081 | dev_warn(rdev->dev, "VM page table size (%d) to small\n", | ||
1082 | radeon_vm_block_size); | ||
1083 | radeon_vm_block_size = 9; | ||
1084 | } | ||
1085 | |||
1086 | if (radeon_vm_block_size > 24 || | ||
1087 | radeon_vm_size < (1ull << radeon_vm_block_size)) { | ||
1088 | dev_warn(rdev->dev, "VM page table size (%d) to large\n", | ||
1089 | radeon_vm_block_size); | ||
1090 | radeon_vm_block_size = 9; | ||
1091 | } | ||
1076 | } | 1092 | } |
1077 | 1093 | ||
1078 | /** | 1094 | /** |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index a09426c7a2f7..b7a2ec2d1598 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -173,6 +173,7 @@ int radeon_aspm = -1; | |||
173 | int radeon_runtime_pm = -1; | 173 | int radeon_runtime_pm = -1; |
174 | int radeon_hard_reset = 0; | 174 | int radeon_hard_reset = 0; |
175 | int radeon_vm_size = 4096; | 175 | int radeon_vm_size = 4096; |
176 | int radeon_vm_block_size = 9; | ||
176 | 177 | ||
177 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); | 178 | MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); |
178 | module_param_named(no_wb, radeon_no_wb, int, 0444); | 179 | module_param_named(no_wb, radeon_no_wb, int, 0444); |
@@ -243,6 +244,9 @@ module_param_named(hard_reset, radeon_hard_reset, int, 0444); | |||
243 | MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)"); | 244 | MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)"); |
244 | module_param_named(vm_size, radeon_vm_size, int, 0444); | 245 | module_param_named(vm_size, radeon_vm_size, int, 0444); |
245 | 246 | ||
247 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)"); | ||
248 | module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); | ||
249 | |||
246 | static struct pci_device_id pciidlist[] = { | 250 | static struct pci_device_id pciidlist[] = { |
247 | radeon_PCI_IDS | 251 | radeon_PCI_IDS |
248 | }; | 252 | }; |
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index d3c9161aab8c..899d9126cad6 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c | |||
@@ -59,7 +59,7 @@ | |||
59 | */ | 59 | */ |
60 | static unsigned radeon_vm_num_pdes(struct radeon_device *rdev) | 60 | static unsigned radeon_vm_num_pdes(struct radeon_device *rdev) |
61 | { | 61 | { |
62 | return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE; | 62 | return rdev->vm_manager.max_pfn >> radeon_vm_block_size; |
63 | } | 63 | } |
64 | 64 | ||
65 | /** | 65 | /** |
@@ -474,8 +474,10 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |||
474 | bo_va->valid = false; | 474 | bo_va->valid = false; |
475 | list_move(&bo_va->vm_list, head); | 475 | list_move(&bo_va->vm_list, head); |
476 | 476 | ||
477 | soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE; | 477 | soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> radeon_vm_block_size; |
478 | eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE; | 478 | eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> radeon_vm_block_size; |
479 | |||
480 | BUG_ON(eoffset >= radeon_vm_num_pdes(rdev)); | ||
479 | 481 | ||
480 | if (eoffset > vm->max_pde_used) | 482 | if (eoffset > vm->max_pde_used) |
481 | vm->max_pde_used = eoffset; | 483 | vm->max_pde_used = eoffset; |
@@ -583,10 +585,9 @@ static uint32_t radeon_vm_page_flags(uint32_t flags) | |||
583 | int radeon_vm_update_page_directory(struct radeon_device *rdev, | 585 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
584 | struct radeon_vm *vm) | 586 | struct radeon_vm *vm) |
585 | { | 587 | { |
586 | static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; | ||
587 | |||
588 | struct radeon_bo *pd = vm->page_directory; | 588 | struct radeon_bo *pd = vm->page_directory; |
589 | uint64_t pd_addr = radeon_bo_gpu_offset(pd); | 589 | uint64_t pd_addr = radeon_bo_gpu_offset(pd); |
590 | uint32_t incr = RADEON_VM_PTE_COUNT * 8; | ||
590 | uint64_t last_pde = ~0, last_pt = ~0; | 591 | uint64_t last_pde = ~0, last_pt = ~0; |
591 | unsigned count = 0, pt_idx, ndw; | 592 | unsigned count = 0, pt_idx, ndw; |
592 | struct radeon_ib ib; | 593 | struct radeon_ib ib; |
@@ -757,8 +758,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev, | |||
757 | uint64_t start, uint64_t end, | 758 | uint64_t start, uint64_t end, |
758 | uint64_t dst, uint32_t flags) | 759 | uint64_t dst, uint32_t flags) |
759 | { | 760 | { |
760 | static const uint64_t mask = RADEON_VM_PTE_COUNT - 1; | 761 | uint64_t mask = RADEON_VM_PTE_COUNT - 1; |
761 | |||
762 | uint64_t last_pte = ~0, last_dst = ~0; | 762 | uint64_t last_pte = ~0, last_dst = ~0; |
763 | unsigned count = 0; | 763 | unsigned count = 0; |
764 | uint64_t addr; | 764 | uint64_t addr; |
@@ -768,7 +768,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev, | |||
768 | 768 | ||
769 | /* walk over the address space and update the page tables */ | 769 | /* walk over the address space and update the page tables */ |
770 | for (addr = start; addr < end; ) { | 770 | for (addr = start; addr < end; ) { |
771 | uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE; | 771 | uint64_t pt_idx = addr >> radeon_vm_block_size; |
772 | struct radeon_bo *pt = vm->page_tables[pt_idx].bo; | 772 | struct radeon_bo *pt = vm->page_tables[pt_idx].bo; |
773 | unsigned nptes; | 773 | unsigned nptes; |
774 | uint64_t pte; | 774 | uint64_t pte; |
@@ -873,13 +873,13 @@ int radeon_vm_bo_update(struct radeon_device *rdev, | |||
873 | /* padding, etc. */ | 873 | /* padding, etc. */ |
874 | ndw = 64; | 874 | ndw = 64; |
875 | 875 | ||
876 | if (RADEON_VM_BLOCK_SIZE > 11) | 876 | if (radeon_vm_block_size > 11) |
877 | /* reserve space for one header for every 2k dwords */ | 877 | /* reserve space for one header for every 2k dwords */ |
878 | ndw += (nptes >> 11) * 4; | 878 | ndw += (nptes >> 11) * 4; |
879 | else | 879 | else |
880 | /* reserve space for one header for | 880 | /* reserve space for one header for |
881 | every (1 << BLOCK_SIZE) entries */ | 881 | every (1 << BLOCK_SIZE) entries */ |
882 | ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4; | 882 | ndw += (nptes >> radeon_vm_block_size) * 4; |
883 | 883 | ||
884 | /* reserve space for pte addresses */ | 884 | /* reserve space for pte addresses */ |
885 | ndw += nptes * 2; | 885 | ndw += nptes * 2; |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 85d030ecebae..ec13e8df4c30 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -4095,7 +4095,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) | |||
4095 | (u32)(rdev->dummy_page.addr >> 12)); | 4095 | (u32)(rdev->dummy_page.addr >> 12)); |
4096 | WREG32(VM_CONTEXT1_CNTL2, 4); | 4096 | WREG32(VM_CONTEXT1_CNTL2, 4); |
4097 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | | 4097 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
4098 | PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | | 4098 | PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | |
4099 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 4099 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
4100 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | | 4100 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
4101 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | | 4101 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |