drm/radeon: make VM size a module parameter (v2)

v2: agd5f: simplify patch

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 29 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3c543eff793b..6f32f16e12dc 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -100,6 +100,7 @@ extern int radeon_dpm;
 extern int radeon_aspm;
 extern int radeon_runtime_pm;
 extern int radeon_hard_reset;
+extern int radeon_vm_size;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 31565de1116c..3f1e3060377c 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1052,6 +1052,27 @@ static void radeon_check_arguments(struct radeon_device *rdev)
                 radeon_agpmode = 0;
                 break;
         }
+
+        if (!radeon_check_pot_argument(radeon_vm_size)) {
+                dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
+                         radeon_vm_size);
+                radeon_vm_size = 4096;
+        }
+
+        if (radeon_vm_size < 4) {
+                dev_warn(rdev->dev, "VM size (%d) to small, min is 4MB\n",
+                         radeon_vm_size);
+                radeon_vm_size = 4096;
+        }
+
+       /*
+        * Max GPUVM size for Cayman, SI and CI are 40 bits.
+        */
+        if (radeon_vm_size > 1024*1024) {
+                dev_warn(rdev->dev, "VM size (%d) to large, max is 1TB\n",
+                         radeon_vm_size);
+                radeon_vm_size = 4096;
+        }
 }
 
 /**
@@ -1197,17 +1218,16 @@ int radeon_device_init(struct radeon_device *rdev,
         if (r)
                 return r;
 
+        radeon_check_arguments(rdev);
         /* Adjust VM size here.
-         * Currently set to 4GB ((1 << 20) 4k pages).
-         * Max GPUVM size for cayman and SI is 40 bits.
+         * Max GPUVM size for cayman+ is 40 bits.
          */
-        rdev->vm_manager.max_pfn = 1 << 20;
+        rdev->vm_manager.max_pfn = radeon_vm_size << 8;
 
         /* Set asic functions */
         r = radeon_asic_init(rdev);
         if (r)
                 return r;
-        radeon_check_arguments(rdev);
 
         /* all of the newer IGP chips have an internal gart
          * However some rs4xx report as AGP, so remove that here.
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 15447a4119f4..a09426c7a2f7 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -172,6 +172,7 @@ int radeon_dpm = -1;
 int radeon_aspm = -1;
 int radeon_runtime_pm = -1;
 int radeon_hard_reset = 0;
+int radeon_vm_size = 4096;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -239,6 +240,9 @@ module_param_named(runpm, radeon_runtime_pm, int, 0444);
 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
 
+MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");
+module_param_named(vm_size, radeon_vm_size, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
         radeon_PCI_IDS
 };