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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-25 11:53:21 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-31 05:50:03 -0500
commit44cec74040564cba2ace8c3756d2fc908bc7a373 (patch)
treeb319a4c18137cb9f7ed611918436880d5951001a
parentd8157a3687323ae5a76f1ecd0fc592b1d87be81b (diff)
drm/i915: dont save/restore VGA state for kms
The only thing we really care about that it is off. To do so, reuse the recently created i915_redisable_vga function, which is already used to put obnoxious firmware into check on lid reopening. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c48
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
3 files changed, 28 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a263a0c247fd..bffe222e1616 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1789,6 +1789,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
1789extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1789extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1790extern void intel_modeset_setup_hw_state(struct drm_device *dev, 1790extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1791 bool force_restore); 1791 bool force_restore);
1792extern void i915_redisable_vga(struct drm_device *dev);
1792extern bool intel_fbc_enabled(struct drm_device *dev); 1793extern bool intel_fbc_enabled(struct drm_device *dev);
1793extern void intel_disable_fbc(struct drm_device *dev); 1794extern void intel_disable_fbc(struct drm_device *dev);
1794extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1795extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 1f581fcb3120..3b9baea9a4c2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -69,6 +69,15 @@ static void i915_save_vga(struct drm_device *dev)
69 int i; 69 int i;
70 u16 cr_index, cr_data, st01; 70 u16 cr_index, cr_data, st01;
71 71
72 /* VGA state */
73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
76 if (HAS_PCH_SPLIT(dev))
77 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
78 else
79 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
80
72 /* VGA color palette registers */ 81 /* VGA color palette registers */
73 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK); 82 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
74 83
@@ -127,6 +136,18 @@ static void i915_restore_vga(struct drm_device *dev)
127 int i; 136 int i;
128 u16 cr_index, cr_data, st01; 137 u16 cr_index, cr_data, st01;
129 138
139 /* VGA state */
140 if (HAS_PCH_SPLIT(dev))
141 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
142 else
143 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
144
145 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
146 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
147 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
148 POSTING_READ(VGA_PD);
149 udelay(150);
150
130 /* MSR bits */ 151 /* MSR bits */
131 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR); 152 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
132 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) { 153 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
@@ -251,16 +272,8 @@ static void i915_save_display(struct drm_device *dev)
251 } 272 }
252 } 273 }
253 274
254 /* VGA state */ 275 if (!drm_core_check_feature(dev, DRIVER_MODESET))
255 dev_priv->regfile.saveVGA0 = I915_READ(VGA0); 276 i915_save_vga(dev);
256 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
257 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
258 if (HAS_PCH_SPLIT(dev))
259 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
260 else
261 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
262
263 i915_save_vga(dev);
264} 277}
265 278
266static void i915_restore_display(struct drm_device *dev) 279static void i915_restore_display(struct drm_device *dev)
@@ -334,19 +347,10 @@ static void i915_restore_display(struct drm_device *dev)
334 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); 347 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
335 } 348 }
336 } 349 }
337 /* VGA state */ 350 if (!drm_core_check_feature(dev, DRIVER_MODESET))
338 if (HAS_PCH_SPLIT(dev)) 351 i915_restore_vga(dev);
339 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
340 else 352 else
341 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL); 353 i915_redisable_vga(dev);
342
343 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
344 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
345 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
346 POSTING_READ(VGA_PD);
347 udelay(150);
348
349 i915_restore_vga(dev);
350} 354}
351 355
352int i915_save_state(struct drm_device *dev) 356int i915_save_state(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c0fadf7686f7..56c51ddf54ec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8903,7 +8903,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
8903 * the crtc fixup. */ 8903 * the crtc fixup. */
8904} 8904}
8905 8905
8906static void i915_redisable_vga(struct drm_device *dev) 8906void i915_redisable_vga(struct drm_device *dev)
8907{ 8907{
8908 struct drm_i915_private *dev_priv = dev->dev_private; 8908 struct drm_i915_private *dev_priv = dev->dev_private;
8909 u32 vga_reg; 8909 u32 vga_reg;