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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-25 11:53:20 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-31 05:50:03 -0500
commitd8157a3687323ae5a76f1ecd0fc592b1d87be81b (patch)
tree610f96d2598e2962f59ec45b984373ac22f0bded
parent2e9723a3e76a050f80064249dac644f86541d3b4 (diff)
drm/i915: extract ums suspend/resume into i915_ums.c
Similarly to how i915_dma.c is shaping up to be the dungeon hole for all things supporting dri1, create a new one to hide all the crazy things which are only really useful for ums support. Biggest part is the register suspend/resume support. Unfortunately a lot of it is still intermingled with bits and pieces we might still need, so needs more analysis and needs to stay in i915_suspend.c for now. Reviewed-by: Imre Deak <imre.deak@intel.com> v2: s/modeset_reg/display_reg/ as suggested by Imre, to avoid confusion between the kernel modeset code and display save/restore to support ums. v3: Fixup alphabetical order in the Makefile, spotted by Chris Wilson. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat
-rw-r--r--drivers/gpu/drm/i915/Makefile1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h6
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c451
-rw-r--r--drivers/gpu/drm/i915/i915_ums.c479
4 files changed, 485 insertions, 452 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0f2c5493242b..91f3ac6cef35 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -16,6 +16,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
16 i915_gem_tiling.o \ 16 i915_gem_tiling.o \
17 i915_sysfs.o \ 17 i915_sysfs.o \
18 i915_trace_points.o \ 18 i915_trace_points.o \
19 i915_ums.o \
19 intel_display.o \ 20 intel_display.o \
20 intel_crt.o \ 21 intel_crt.o \
21 intel_lvds.o \ 22 intel_lvds.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 09753e56b6d0..a263a0c247fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1730,9 +1730,9 @@ void i915_debugfs_cleanup(struct drm_minor *minor);
1730extern int i915_save_state(struct drm_device *dev); 1730extern int i915_save_state(struct drm_device *dev);
1731extern int i915_restore_state(struct drm_device *dev); 1731extern int i915_restore_state(struct drm_device *dev);
1732 1732
1733/* i915_suspend.c */ 1733/* i915_ums.c */
1734extern int i915_save_state(struct drm_device *dev); 1734void i915_save_display_reg(struct drm_device *dev);
1735extern int i915_restore_state(struct drm_device *dev); 1735void i915_restore_display_reg(struct drm_device *dev);
1736 1736
1737/* i915_sysfs.c */ 1737/* i915_sysfs.c */
1738void i915_setup_sysfs(struct drm_device *dev_priv); 1738void i915_setup_sysfs(struct drm_device *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bcde494b3805..1f581fcb3120 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -29,67 +29,6 @@
29#include "intel_drv.h" 29#include "intel_drv.h"
30#include "i915_reg.h" 30#include "i915_reg.h"
31 31
32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg;
36
37 /* On IVB, 3rd pipe shares PLL with another one */
38 if (pipe > 1)
39 return false;
40
41 if (HAS_PCH_SPLIT(dev))
42 dpll_reg = _PCH_DPLL(pipe);
43 else
44 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
45
46 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
47}
48
49static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
50{
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
53 u32 *array;
54 int i;
55
56 if (!i915_pipe_enabled(dev, pipe))
57 return;
58
59 if (HAS_PCH_SPLIT(dev))
60 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
61
62 if (pipe == PIPE_A)
63 array = dev_priv->regfile.save_palette_a;
64 else
65 array = dev_priv->regfile.save_palette_b;
66
67 for (i = 0; i < 256; i++)
68 array[i] = I915_READ(reg + (i << 2));
69}
70
71static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
72{
73 struct drm_i915_private *dev_priv = dev->dev_private;
74 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
75 u32 *array;
76 int i;
77
78 if (!i915_pipe_enabled(dev, pipe))
79 return;
80
81 if (HAS_PCH_SPLIT(dev))
82 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
83
84 if (pipe == PIPE_A)
85 array = dev_priv->regfile.save_palette_a;
86 else
87 array = dev_priv->regfile.save_palette_b;
88
89 for (i = 0; i < 256; i++)
90 I915_WRITE(reg + (i << 2), array[i]);
91}
92
93static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) 32static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
94{ 33{
95 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -235,392 +174,6 @@ static void i915_restore_vga(struct drm_device *dev)
235 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK); 174 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
236} 175}
237 176
238static void i915_save_modeset_reg(struct drm_device *dev)
239{
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 int i;
242
243 /* Cursor state */
244 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
245 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
246 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
247 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
248 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
249 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
250 if (IS_GEN2(dev))
251 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
252
253 if (HAS_PCH_SPLIT(dev)) {
254 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
255 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
256 }
257
258 /* Pipe & plane A info */
259 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
260 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
261 if (HAS_PCH_SPLIT(dev)) {
262 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
263 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
264 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
265 } else {
266 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
267 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
268 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
269 }
270 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
271 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
272 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
273 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
274 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
275 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
276 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
277 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
278 if (!HAS_PCH_SPLIT(dev))
279 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
280
281 if (HAS_PCH_SPLIT(dev)) {
282 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
283 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
284 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
285 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
286
287 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
288 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
289
290 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
291 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
292 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
293
294 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
295 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
296 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
297 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
298 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
299 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
300 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
301 }
302
303 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
304 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
305 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
306 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
307 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
308 if (INTEL_INFO(dev)->gen >= 4) {
309 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
310 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
311 }
312 i915_save_palette(dev, PIPE_A);
313 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
314
315 /* Pipe & plane B info */
316 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
317 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
318 if (HAS_PCH_SPLIT(dev)) {
319 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
320 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
321 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
322 } else {
323 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
324 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
325 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
326 }
327 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
328 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
329 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
330 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
331 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
332 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
333 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
334 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
335 if (!HAS_PCH_SPLIT(dev))
336 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
337
338 if (HAS_PCH_SPLIT(dev)) {
339 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
340 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
341 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
342 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
343
344 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
345 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
346
347 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
348 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
349 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
350
351 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
352 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
353 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
354 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
355 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
356 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
357 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
358 }
359
360 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
361 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
362 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
363 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
364 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
365 if (INTEL_INFO(dev)->gen >= 4) {
366 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
367 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
368 }
369 i915_save_palette(dev, PIPE_B);
370 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
371
372 /* Fences */
373 switch (INTEL_INFO(dev)->gen) {
374 case 7:
375 case 6:
376 for (i = 0; i < 16; i++)
377 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
378 break;
379 case 5:
380 case 4:
381 for (i = 0; i < 16; i++)
382 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
383 break;
384 case 3:
385 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
386 for (i = 0; i < 8; i++)
387 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
388 case 2:
389 for (i = 0; i < 8; i++)
390 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
391 break;
392 }
393
394 /* CRT state */
395 if (HAS_PCH_SPLIT(dev))
396 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
397 else
398 dev_priv->regfile.saveADPA = I915_READ(ADPA);
399
400 return;
401}
402
403static void i915_restore_modeset_reg(struct drm_device *dev)
404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 int dpll_a_reg, fpa0_reg, fpa1_reg;
407 int dpll_b_reg, fpb0_reg, fpb1_reg;
408 int i;
409
410 /* Display port ratios (must be done before clock is set) */
411 if (SUPPORTS_INTEGRATED_DP(dev)) {
412 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
413 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
414 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
415 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
416 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
417 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
418 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
419 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
420 }
421
422 /* Fences */
423 switch (INTEL_INFO(dev)->gen) {
424 case 7:
425 case 6:
426 for (i = 0; i < 16; i++)
427 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
428 break;
429 case 5:
430 case 4:
431 for (i = 0; i < 16; i++)
432 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
433 break;
434 case 3:
435 case 2:
436 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
437 for (i = 0; i < 8; i++)
438 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
439 for (i = 0; i < 8; i++)
440 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
441 break;
442 }
443
444
445 if (HAS_PCH_SPLIT(dev)) {
446 dpll_a_reg = _PCH_DPLL_A;
447 dpll_b_reg = _PCH_DPLL_B;
448 fpa0_reg = _PCH_FPA0;
449 fpb0_reg = _PCH_FPB0;
450 fpa1_reg = _PCH_FPA1;
451 fpb1_reg = _PCH_FPB1;
452 } else {
453 dpll_a_reg = _DPLL_A;
454 dpll_b_reg = _DPLL_B;
455 fpa0_reg = _FPA0;
456 fpb0_reg = _FPB0;
457 fpa1_reg = _FPA1;
458 fpb1_reg = _FPB1;
459 }
460
461 if (HAS_PCH_SPLIT(dev)) {
462 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
463 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
464 }
465
466 /* Pipe & plane A info */
467 /* Prime the clock */
468 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
469 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
470 ~DPLL_VCO_ENABLE);
471 POSTING_READ(dpll_a_reg);
472 udelay(150);
473 }
474 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
475 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
476 /* Actually enable it */
477 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
478 POSTING_READ(dpll_a_reg);
479 udelay(150);
480 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
481 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
482 POSTING_READ(_DPLL_A_MD);
483 }
484 udelay(150);
485
486 /* Restore mode */
487 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
488 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
489 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
490 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
491 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
492 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
493 if (!HAS_PCH_SPLIT(dev))
494 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
495
496 if (HAS_PCH_SPLIT(dev)) {
497 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
498 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
499 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
500 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
501
502 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
503 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
504
505 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
506 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
507 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
508
509 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
510 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
511 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
512 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
513 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
514 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
515 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
516 }
517
518 /* Restore plane info */
519 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
520 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
521 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
522 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
523 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
524 if (INTEL_INFO(dev)->gen >= 4) {
525 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
526 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
527 }
528
529 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
530
531 i915_restore_palette(dev, PIPE_A);
532 /* Enable the plane */
533 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
534 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
535
536 /* Pipe & plane B info */
537 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
538 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
539 ~DPLL_VCO_ENABLE);
540 POSTING_READ(dpll_b_reg);
541 udelay(150);
542 }
543 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
544 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
545 /* Actually enable it */
546 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
547 POSTING_READ(dpll_b_reg);
548 udelay(150);
549 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
550 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
551 POSTING_READ(_DPLL_B_MD);
552 }
553 udelay(150);
554
555 /* Restore mode */
556 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
557 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
558 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
559 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
560 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
561 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
562 if (!HAS_PCH_SPLIT(dev))
563 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
564
565 if (HAS_PCH_SPLIT(dev)) {
566 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
567 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
568 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
569 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
570
571 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
572 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
573
574 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
575 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
576 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
577
578 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
579 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
580 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
581 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
582 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
583 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
584 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
585 }
586
587 /* Restore plane info */
588 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
589 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
590 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
591 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
592 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
593 if (INTEL_INFO(dev)->gen >= 4) {
594 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
595 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
596 }
597
598 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
599
600 i915_restore_palette(dev, PIPE_B);
601 /* Enable the plane */
602 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
603 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
604
605 /* Cursor state */
606 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
607 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
608 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
609 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
610 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
611 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
612 if (IS_GEN2(dev))
613 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
614
615 /* CRT state */
616 if (HAS_PCH_SPLIT(dev))
617 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
618 else
619 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
620
621 return;
622}
623
624static void i915_save_display(struct drm_device *dev) 177static void i915_save_display(struct drm_device *dev)
625{ 178{
626 struct drm_i915_private *dev_priv = dev->dev_private; 179 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -632,7 +185,7 @@ static void i915_save_display(struct drm_device *dev)
632 /* This is only meaningful in non-KMS mode */ 185 /* This is only meaningful in non-KMS mode */
633 /* Don't regfile.save them in KMS mode */ 186 /* Don't regfile.save them in KMS mode */
634 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 187 if (!drm_core_check_feature(dev, DRIVER_MODESET))
635 i915_save_modeset_reg(dev); 188 i915_save_display_reg(dev);
636 189
637 /* LVDS state */ 190 /* LVDS state */
638 if (HAS_PCH_SPLIT(dev)) { 191 if (HAS_PCH_SPLIT(dev)) {
@@ -719,7 +272,7 @@ static void i915_restore_display(struct drm_device *dev)
719 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); 272 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
720 273
721 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 274 if (!drm_core_check_feature(dev, DRIVER_MODESET))
722 i915_restore_modeset_reg(dev); 275 i915_restore_display_reg(dev);
723 276
724 /* LVDS state */ 277 /* LVDS state */
725 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 278 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
new file mode 100644
index 000000000000..359c77b7b1b2
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -0,0 +1,479 @@
1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 * Copyright 2013 (c) Intel Corporation
6 * Daniel Vetter <daniel.vetter@ffwll.ch>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
31#include "intel_drv.h"
32#include "i915_reg.h"
33
34static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
35{
36 struct drm_i915_private *dev_priv = dev->dev_private;
37 u32 dpll_reg;
38
39 /* On IVB, 3rd pipe shares PLL with another one */
40 if (pipe > 1)
41 return false;
42
43 if (HAS_PCH_SPLIT(dev))
44 dpll_reg = _PCH_DPLL(pipe);
45 else
46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
47
48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
49}
50
51static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
52{
53 struct drm_i915_private *dev_priv = dev->dev_private;
54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
55 u32 *array;
56 int i;
57
58 if (!i915_pipe_enabled(dev, pipe))
59 return;
60
61 if (HAS_PCH_SPLIT(dev))
62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
63
64 if (pipe == PIPE_A)
65 array = dev_priv->regfile.save_palette_a;
66 else
67 array = dev_priv->regfile.save_palette_b;
68
69 for (i = 0; i < 256; i++)
70 array[i] = I915_READ(reg + (i << 2));
71}
72
73static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
77 u32 *array;
78 int i;
79
80 if (!i915_pipe_enabled(dev, pipe))
81 return;
82
83 if (HAS_PCH_SPLIT(dev))
84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
85
86 if (pipe == PIPE_A)
87 array = dev_priv->regfile.save_palette_a;
88 else
89 array = dev_priv->regfile.save_palette_b;
90
91 for (i = 0; i < 256; i++)
92 I915_WRITE(reg + (i << 2), array[i]);
93}
94
95void i915_save_display_reg(struct drm_device *dev)
96{
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 int i;
99
100 /* Cursor state */
101 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
102 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
103 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
104 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
105 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
106 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
107 if (IS_GEN2(dev))
108 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
109
110 if (HAS_PCH_SPLIT(dev)) {
111 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
112 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
113 }
114
115 /* Pipe & plane A info */
116 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
117 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
118 if (HAS_PCH_SPLIT(dev)) {
119 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
120 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
121 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
122 } else {
123 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
124 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
125 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
126 }
127 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
128 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
129 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
130 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
131 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
132 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
133 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
134 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
135 if (!HAS_PCH_SPLIT(dev))
136 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
137
138 if (HAS_PCH_SPLIT(dev)) {
139 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
140 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
141 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
142 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
143
144 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
145 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
146
147 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
148 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
149 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
150
151 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
152 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
153 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
154 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
155 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
156 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
157 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
158 }
159
160 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
161 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
162 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
163 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
164 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
165 if (INTEL_INFO(dev)->gen >= 4) {
166 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
167 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
168 }
169 i915_save_palette(dev, PIPE_A);
170 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
171
172 /* Pipe & plane B info */
173 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
174 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
175 if (HAS_PCH_SPLIT(dev)) {
176 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
177 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
178 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
179 } else {
180 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
181 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
182 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
183 }
184 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
185 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
186 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
187 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
188 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
189 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
190 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
191 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
192 if (!HAS_PCH_SPLIT(dev))
193 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
194
195 if (HAS_PCH_SPLIT(dev)) {
196 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
197 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
198 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
199 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
200
201 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
202 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
203
204 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
205 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
206 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
207
208 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
209 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
210 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
211 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
212 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
213 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
214 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
215 }
216
217 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
218 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
219 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
220 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
221 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
222 if (INTEL_INFO(dev)->gen >= 4) {
223 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
224 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
225 }
226 i915_save_palette(dev, PIPE_B);
227 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
228
229 /* Fences */
230 switch (INTEL_INFO(dev)->gen) {
231 case 7:
232 case 6:
233 for (i = 0; i < 16; i++)
234 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
235 break;
236 case 5:
237 case 4:
238 for (i = 0; i < 16; i++)
239 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
240 break;
241 case 3:
242 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
243 for (i = 0; i < 8; i++)
244 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
245 case 2:
246 for (i = 0; i < 8; i++)
247 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
248 break;
249 }
250
251 /* CRT state */
252 if (HAS_PCH_SPLIT(dev))
253 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
254 else
255 dev_priv->regfile.saveADPA = I915_READ(ADPA);
256
257 return;
258}
259
260void i915_restore_display_reg(struct drm_device *dev)
261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 int dpll_a_reg, fpa0_reg, fpa1_reg;
264 int dpll_b_reg, fpb0_reg, fpb1_reg;
265 int i;
266
267 /* Display port ratios (must be done before clock is set) */
268 if (SUPPORTS_INTEGRATED_DP(dev)) {
269 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
270 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
271 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
272 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
273 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
274 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
275 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
276 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
277 }
278
279 /* Fences */
280 switch (INTEL_INFO(dev)->gen) {
281 case 7:
282 case 6:
283 for (i = 0; i < 16; i++)
284 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
285 break;
286 case 5:
287 case 4:
288 for (i = 0; i < 16; i++)
289 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
290 break;
291 case 3:
292 case 2:
293 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
294 for (i = 0; i < 8; i++)
295 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
296 for (i = 0; i < 8; i++)
297 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
298 break;
299 }
300
301
302 if (HAS_PCH_SPLIT(dev)) {
303 dpll_a_reg = _PCH_DPLL_A;
304 dpll_b_reg = _PCH_DPLL_B;
305 fpa0_reg = _PCH_FPA0;
306 fpb0_reg = _PCH_FPB0;
307 fpa1_reg = _PCH_FPA1;
308 fpb1_reg = _PCH_FPB1;
309 } else {
310 dpll_a_reg = _DPLL_A;
311 dpll_b_reg = _DPLL_B;
312 fpa0_reg = _FPA0;
313 fpb0_reg = _FPB0;
314 fpa1_reg = _FPA1;
315 fpb1_reg = _FPB1;
316 }
317
318 if (HAS_PCH_SPLIT(dev)) {
319 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
320 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
321 }
322
323 /* Pipe & plane A info */
324 /* Prime the clock */
325 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
326 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
327 ~DPLL_VCO_ENABLE);
328 POSTING_READ(dpll_a_reg);
329 udelay(150);
330 }
331 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
332 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
333 /* Actually enable it */
334 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
335 POSTING_READ(dpll_a_reg);
336 udelay(150);
337 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
338 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
339 POSTING_READ(_DPLL_A_MD);
340 }
341 udelay(150);
342
343 /* Restore mode */
344 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
345 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
346 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
347 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
348 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
349 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
350 if (!HAS_PCH_SPLIT(dev))
351 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
352
353 if (HAS_PCH_SPLIT(dev)) {
354 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
355 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
356 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
357 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
358
359 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
360 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
361
362 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
363 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
364 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
365
366 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
367 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
368 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
369 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
370 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
371 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
372 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
373 }
374
375 /* Restore plane info */
376 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
377 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
378 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
379 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
380 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
381 if (INTEL_INFO(dev)->gen >= 4) {
382 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
383 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
384 }
385
386 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
387
388 i915_restore_palette(dev, PIPE_A);
389 /* Enable the plane */
390 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
391 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
392
393 /* Pipe & plane B info */
394 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
395 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
396 ~DPLL_VCO_ENABLE);
397 POSTING_READ(dpll_b_reg);
398 udelay(150);
399 }
400 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
401 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
402 /* Actually enable it */
403 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
404 POSTING_READ(dpll_b_reg);
405 udelay(150);
406 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
407 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
408 POSTING_READ(_DPLL_B_MD);
409 }
410 udelay(150);
411
412 /* Restore mode */
413 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
414 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
415 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
416 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
417 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
418 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
419 if (!HAS_PCH_SPLIT(dev))
420 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
421
422 if (HAS_PCH_SPLIT(dev)) {
423 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
424 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
425 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
426 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
427
428 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
429 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
430
431 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
432 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
433 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
434
435 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
436 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
437 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
438 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
439 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
440 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
441 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
442 }
443
444 /* Restore plane info */
445 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
446 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
447 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
448 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
449 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
450 if (INTEL_INFO(dev)->gen >= 4) {
451 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
452 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
453 }
454
455 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
456
457 i915_restore_palette(dev, PIPE_B);
458 /* Enable the plane */
459 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
460 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
461
462 /* Cursor state */
463 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
464 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
465 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
466 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
467 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
468 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
469 if (IS_GEN2(dev))
470 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
471
472 /* CRT state */
473 if (HAS_PCH_SPLIT(dev))
474 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
475 else
476 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
477
478 return;
479}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 05:30:30 -0400