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authorLinus Torvalds <torvalds@linux-foundation.org>2013-11-07 18:32:58 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-11-07 18:32:58 -0500
commit3ae423fe4734af3b2f7ac718c6e64e72bfe443b3 (patch)
treee323d3bd2ce253f739a1faa4b4486e6c603a36b8
parent280c84d1c1726be7ada045735858acdc8cfdd65a (diff)
parent723ff7943249efcea8fd814ec1eff728f38f5935 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: - Some minor work bringing the Cobalt MIPS platforms in line with other MIPS platforms - Make vmlinux.32 and vmlinux.64 build messages less verbose - Always register the R4k clocksource when selected, the clock source's rating will decide if this or another clock source is actually going to be used - Drop support for the Cisco (formerly Scientific Atlanta) PowerTV platform. There appears to be nobody left who cares and the USB driver went stale while waiting for years to be merged - Some cleanup of Loongson 2 related #ifdefery - Various minor cleanups - Major rework on all things related to tracing / ptrace on MIPS, including switching the MIPS ELF core dumper to regsets, enabling the entries for SIGSYS in struct siginfo for MIPS, enabling ftrace syscall trace points - Some more work to bring DECstation support code in line with other more modern code - Report the name of the detected CPU, not just its CP0 PrID value - Some more BCM 47xx and atheros ath79xx work - Support for compressed kernels using the XZ compression scheme * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (53 commits) MIPS: remove duplicate define MIPS: Random whitespace clean-ups MIPS: traps: Reformat notify_die invocations to 80 columns. MIPS: Print correct PC in trace dump after NMI exception MIPS: kernel: cpu-probe: Report CPU id during probe MIPS: Remove unused defines in piix4.h MIPS: Get rid of hard-coded values for Malta PIIX4 fixups MIPS: Always register R4K clock when selected MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips. MIPS: cacheops.h: Increase indentation by one tab. MIPS: Remove bogus BUG_ON() MIPS: PowerTV: Remove support code. MIPS: ftrace: Add support for syscall tracepoints. MIPS: ptrace: Switch syscall reporting to tracehook_report_syscall_entry(). MIPS: Move audit_arch() helper function to __syscall_get_arch(). MIPS: Enable HAVE_ARCH_TRACEHOOK. MIPS: Switch ELF core dumper to use regsets. MIPS: Implement task_user_regset_view. MIPS: ptrace: Use tracehook helpers. MIPS: O32 / 32-bit: Always copy 4 stack arguments. ...
Diffstat
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig27
-rw-r--r--arch/mips/Kconfig.debug8
-rw-r--r--arch/mips/Makefile14
-rw-r--r--arch/mips/alchemy/devboards/db1235.c2
-rw-r--r--arch/mips/ath79/dev-common.c6
-rw-r--r--arch/mips/bcm47xx/Makefile1
-rw-r--r--arch/mips/bcm47xx/board.c309
-rw-r--r--arch/mips/bcm47xx/nvram.c20
-rw-r--r--arch/mips/bcm47xx/prom.c27
-rw-r--r--arch/mips/bcm47xx/setup.c2
-rw-r--r--arch/mips/bcm47xx/time.c23
-rw-r--r--arch/mips/boot/compressed/Makefile6
-rw-r--r--arch/mips/boot/compressed/decompress.c13
-rw-r--r--arch/mips/boot/compressed/ld.script5
-rw-r--r--arch/mips/boot/ecoff.h1
-rw-r--r--arch/mips/cavium-octeon/setup.c4
-rw-r--r--arch/mips/cobalt/Makefile1
-rw-r--r--arch/mips/cobalt/console.c20
-rw-r--r--arch/mips/cobalt/setup.c3
-rw-r--r--arch/mips/configs/powertv_defconfig136
-rw-r--r--arch/mips/dec/int-handler.S8
-rw-r--r--arch/mips/dec/ioasic-irq.c43
-rw-r--r--arch/mips/dec/prom/call_o32.S2
-rw-r--r--arch/mips/dec/prom/init.c2
-rw-r--r--arch/mips/dec/prom/memory.c2
-rw-r--r--arch/mips/dec/setup.c4
-rw-r--r--arch/mips/include/asm/addrspace.h4
-rw-r--r--arch/mips/include/asm/atomic.h2
-rw-r--r--arch/mips/include/asm/barrier.h6
-rw-r--r--arch/mips/include/asm/cacheops.h93
-rw-r--r--arch/mips/include/asm/dec/ioasic.h2
-rw-r--r--arch/mips/include/asm/dec/ioasic_addrs.h2
-rw-r--r--arch/mips/include/asm/dec/kn01.h12
-rw-r--r--arch/mips/include/asm/dec/kn02ca.h2
-rw-r--r--arch/mips/include/asm/dec/prom.h2
-rw-r--r--arch/mips/include/asm/elf.h1
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h110
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h12
-rw-r--r--arch/mips/include/asm/mach-dec/cpu-feature-overrides.h87
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h11
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h120
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h125
-rw-r--r--arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h60
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h117
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h253
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h167
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h27
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h78
-rw-r--r--arch/mips/include/asm/mmu_context.h22
-rw-r--r--arch/mips/include/asm/ptrace.h14
-rw-r--r--arch/mips/include/asm/r4kcache.h41
-rw-r--r--arch/mips/include/asm/setup.h8
-rw-r--r--arch/mips/include/asm/stackframe.h24
-rw-r--r--arch/mips/include/asm/syscall.h116
-rw-r--r--arch/mips/include/asm/thread_info.h42
-rw-r--r--arch/mips/include/asm/time.h2
-rw-r--r--arch/mips/include/asm/unistd.h7
-rw-r--r--arch/mips/include/uapi/asm/siginfo.h9
-rw-r--r--arch/mips/kernel/Makefile3
-rw-r--r--arch/mips/kernel/cpu-probe.c32
-rw-r--r--arch/mips/kernel/csrc-powertv.c151
-rw-r--r--arch/mips/kernel/early_printk_8250.c66
-rw-r--r--arch/mips/kernel/ftrace.c33
-rw-r--r--arch/mips/kernel/genex.S14
-rw-r--r--arch/mips/kernel/irq_cpu.c2
-rw-r--r--arch/mips/kernel/module.c3
-rw-r--r--arch/mips/kernel/ptrace.c199
-rw-r--r--arch/mips/kernel/scall32-o32.S846
-rw-r--r--arch/mips/kernel/scall64-64.S3
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/scall64-o32.S10
-rw-r--r--arch/mips/kernel/setup.c19
-rw-r--r--arch/mips/kernel/smp-bmips.c4
-rw-r--r--arch/mips/kernel/smp.c1
-rw-r--r--arch/mips/kernel/traps.c38
-rw-r--r--arch/mips/lantiq/irq.c2
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c2
-rw-r--r--arch/mips/mm/c-r4k.c52
-rw-r--r--arch/mips/mm/dma-default.c4
-rw-r--r--arch/mips/mm/tlb-funcs.S2
-rw-r--r--arch/mips/mm/tlb-r4k.c37
-rw-r--r--arch/mips/mm/tlbex.c307
-rw-r--r--arch/mips/mti-malta/malta-int.c1
-rw-r--r--arch/mips/netlogic/common/smp.c2
-rw-r--r--arch/mips/pci/fixup-malta.c36
-rw-r--r--arch/mips/pci/pci-ar71xx.c3
-rw-r--r--arch/mips/pci/pci-ar724x.c9
-rw-r--r--arch/mips/pci/pci.c50
-rw-r--r--arch/mips/powertv/Kconfig12
-rw-r--r--arch/mips/powertv/Makefile29
-rw-r--r--arch/mips/powertv/Platform7
-rw-r--r--arch/mips/powertv/asic/Makefile21
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c101
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c101
-rw-r--r--arch/mips/powertv/asic/asic-gaia.c96
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c101
-rw-r--r--arch/mips/powertv/asic/asic_devices.c549
-rw-r--r--arch/mips/powertv/asic/asic_int.c125
-rw-r--r--arch/mips/powertv/asic/irq_asic.c115
-rw-r--r--arch/mips/powertv/asic/prealloc-calliope.c385
-rw-r--r--arch/mips/powertv/asic/prealloc-cronus.c340
-rw-r--r--arch/mips/powertv/asic/prealloc-cronuslite.c174
-rw-r--r--arch/mips/powertv/asic/prealloc-gaia.c589
-rw-r--r--arch/mips/powertv/asic/prealloc-zeus.c304
-rw-r--r--arch/mips/powertv/asic/prealloc.h70
-rw-r--r--arch/mips/powertv/init.c90
-rw-r--r--arch/mips/powertv/init.h28
-rw-r--r--arch/mips/powertv/ioremap.c136
-rw-r--r--arch/mips/powertv/memory.c353
-rw-r--r--arch/mips/powertv/pci/Makefile19
-rw-r--r--arch/mips/powertv/pci/fixup-powertv.c37
-rw-r--r--arch/mips/powertv/pci/powertv-pci.h31
-rw-r--r--arch/mips/powertv/powertv-clock.h26
-rw-r--r--arch/mips/powertv/powertv-usb.c404
-rw-r--r--arch/mips/powertv/powertv_setup.c319
-rw-r--r--arch/mips/powertv/reset.c35
-rw-r--r--arch/mips/powertv/reset.h26
-rw-r--r--arch/mips/powertv/time.c36
-rw-r--r--arch/mips/ralink/clk.c2
-rw-r--r--arch/mips/ralink/mt7620.c2
-rw-r--r--arch/mips/ralink/of.c2
-rw-r--r--arch/mips/ralink/rt305x.c2
-rw-r--r--drivers/net/ethernet/amd/declance.c3
133 files changed, 1984 insertions, 7090 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index d9d81c219253..6e239123d6fe 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,7 +20,6 @@ platforms += mti-sead3
20platforms += netlogic 20platforms += netlogic
21platforms += pmcs-msp71xx 21platforms += pmcs-msp71xx
22platforms += pnx833x 22platforms += pnx833x
23platforms += powertv
24platforms += ralink 23platforms += ralink
25platforms += rb532 24platforms += rb532
26platforms += sgi-ip22 25platforms += sgi-ip22
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f75ab4a2f246..17cc7ff8458c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -8,6 +8,7 @@ config MIPS
8 select HAVE_PERF_EVENTS 8 select HAVE_PERF_EVENTS
9 select PERF_USE_VMALLOC 9 select PERF_USE_VMALLOC
10 select HAVE_ARCH_KGDB 10 select HAVE_ARCH_KGDB
11 select HAVE_ARCH_TRACEHOOK
11 select ARCH_HAVE_CUSTOM_GPIO_H 12 select ARCH_HAVE_CUSTOM_GPIO_H
12 select HAVE_FUNCTION_TRACER 13 select HAVE_FUNCTION_TRACER
13 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 14 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
@@ -18,6 +19,7 @@ config MIPS
18 select HAVE_KPROBES 19 select HAVE_KPROBES
19 select HAVE_KRETPROBES 20 select HAVE_KRETPROBES
20 select HAVE_DEBUG_KMEMLEAK 21 select HAVE_DEBUG_KMEMLEAK
22 select HAVE_SYSCALL_TRACEPOINTS
21 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 23 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
22 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT 24 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
23 select RTC_LIB if !MACH_LOONGSON 25 select RTC_LIB if !MACH_LOONGSON
@@ -146,6 +148,7 @@ config MIPS_COBALT
146 select CSRC_R4K 148 select CSRC_R4K
147 select CEVT_GT641XX 149 select CEVT_GT641XX
148 select DMA_NONCOHERENT 150 select DMA_NONCOHERENT
151 select EARLY_PRINTK_8250 if EARLY_PRINTK
149 select HW_HAS_PCI 152 select HW_HAS_PCI
150 select I8253 153 select I8253
151 select I8259 154 select I8259
@@ -412,23 +415,6 @@ config PMC_MSP
412 of integrated peripherals, interfaces and DSPs in addition to 415 of integrated peripherals, interfaces and DSPs in addition to
413 a variety of MIPS cores. 416 a variety of MIPS cores.
414 417
415config POWERTV
416 bool "Cisco PowerTV"
417 select BOOT_ELF32
418 select CEVT_R4K
419 select CPU_MIPSR2_IRQ_VI
420 select CPU_MIPSR2_IRQ_EI
421 select CSRC_POWERTV
422 select DMA_NONCOHERENT
423 select HW_HAS_PCI
424 select SYS_HAS_CPU_MIPS32_R2
425 select SYS_SUPPORTS_32BIT_KERNEL
426 select SYS_SUPPORTS_BIG_ENDIAN
427 select SYS_SUPPORTS_HIGHMEM
428 select USB_OHCI_LITTLE_ENDIAN
429 help
430 This enables support for the Cisco PowerTV Platform.
431
432config RALINK 418config RALINK
433 bool "Ralink based machines" 419 bool "Ralink based machines"
434 select CEVT_R4K 420 select CEVT_R4K
@@ -811,7 +797,6 @@ source "arch/mips/jz4740/Kconfig"
811source "arch/mips/lantiq/Kconfig" 797source "arch/mips/lantiq/Kconfig"
812source "arch/mips/lasat/Kconfig" 798source "arch/mips/lasat/Kconfig"
813source "arch/mips/pmcs-msp71xx/Kconfig" 799source "arch/mips/pmcs-msp71xx/Kconfig"
814source "arch/mips/powertv/Kconfig"
815source "arch/mips/ralink/Kconfig" 800source "arch/mips/ralink/Kconfig"
816source "arch/mips/sgi-ip27/Kconfig" 801source "arch/mips/sgi-ip27/Kconfig"
817source "arch/mips/sibyte/Kconfig" 802source "arch/mips/sibyte/Kconfig"
@@ -890,9 +875,6 @@ config CSRC_BCM1480
890config CSRC_IOASIC 875config CSRC_IOASIC
891 bool 876 bool
892 877
893config CSRC_POWERTV
894 bool
895
896config CSRC_R4K 878config CSRC_R4K
897 bool 879 bool
898 880
@@ -1489,8 +1471,10 @@ config SYS_SUPPORTS_ZBOOT
1489 bool 1471 bool
1490 select HAVE_KERNEL_GZIP 1472 select HAVE_KERNEL_GZIP
1491 select HAVE_KERNEL_BZIP2 1473 select HAVE_KERNEL_BZIP2
1474 select HAVE_KERNEL_LZ4
1492 select HAVE_KERNEL_LZMA 1475 select HAVE_KERNEL_LZMA
1493 select HAVE_KERNEL_LZO 1476 select HAVE_KERNEL_LZO
1477 select HAVE_KERNEL_XZ
1494 1478
1495config SYS_SUPPORTS_ZBOOT_UART16550 1479config SYS_SUPPORTS_ZBOOT_UART16550
1496 bool 1480 bool
@@ -1977,6 +1961,7 @@ config MIPS_VPE_APSP_API
1977config MIPS_CMP 1961config MIPS_CMP
1978 bool "MIPS CMP framework support" 1962 bool "MIPS CMP framework support"
1979 depends on SYS_SUPPORTS_MIPS_CMP 1963 depends on SYS_SUPPORTS_MIPS_CMP
1964 select SMP
1980 select SYNC_R4K 1965 select SYNC_R4K
1981 select SYS_SUPPORTS_SMP 1966 select SYS_SUPPORTS_SMP
1982 select SYS_SUPPORTS_SCHED_SMT if SMP 1967 select SYS_SUPPORTS_SCHED_SMT if SMP
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 37871f0de15e..b147e7038ff0 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -20,6 +20,14 @@ config EARLY_PRINTK
20 doesn't cooperate with an X server. You should normally say N here, 20 doesn't cooperate with an X server. You should normally say N here,
21 unless you want to debug such a crash. 21 unless you want to debug such a crash.
22 22
23config EARLY_PRINTK_8250
24 bool "8250/16550 and compatible serial early printk driver"
25 depends on EARLY_PRINTK
26 default n
27 help
28 If you say Y here, it will be possible to use a 8250/16550 serial
29 port as the boot console.
30
23config CMDLINE_BOOL 31config CMDLINE_BOOL
24 bool "Built-in kernel command line" 32 bool "Built-in kernel command line"
25 default n 33 default n
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index ca8f8340d75f..de300b993607 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -285,15 +285,19 @@ endif
285# Other need ECOFF, so we build a 32-bit ELF binary for them which we then 285# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
286# convert to ECOFF using elf2ecoff. 286# convert to ECOFF using elf2ecoff.
287# 287#
288quiet_cmd_32 = OBJCOPY $@
289 cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
288vmlinux.32: vmlinux 290vmlinux.32: vmlinux
289 $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ 291 $(call cmd,32)
290 292
291# 293#
292# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit 294# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
293# ELF files from 32-bit files by conversion. 295# ELF files from 32-bit files by conversion.
294# 296#
297quiet_cmd_64 = OBJCOPY $@
298 cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
295vmlinux.64: vmlinux 299vmlinux.64: vmlinux
296 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ 300 $(call cmd,64)
297 301
298all: $(all-y) 302all: $(all-y)
299 303
@@ -302,10 +306,16 @@ $(boot-y): $(vmlinux-32) FORCE
302 $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \ 306 $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
303 $(bootvars-y) arch/mips/boot/$@ 307 $(bootvars-y) arch/mips/boot/$@
304 308
309ifdef CONFIG_SYS_SUPPORTS_ZBOOT
305# boot/compressed 310# boot/compressed
306$(bootz-y): $(vmlinux-32) FORCE 311$(bootz-y): $(vmlinux-32) FORCE
307 $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ 312 $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
308 $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@ 313 $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
314else
315vmlinuz: FORCE
316 @echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled'
317 /bin/false
318endif
309 319
310 320
311CLEAN_FILES += vmlinux.32 vmlinux.64 321CLEAN_FILES += vmlinux.32 vmlinux.64
diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c
index c76a90f78664..bac19dc43d1d 100644
--- a/arch/mips/alchemy/devboards/db1235.c
+++ b/arch/mips/alchemy/devboards/db1235.c
@@ -59,7 +59,7 @@ void __init board_setup(void)
59 ret = -ENODEV; 59 ret = -ENODEV;
60 } 60 }
61 if (ret) 61 if (ret)
62 panic("cannot initialize board support\n"); 62 panic("cannot initialize board support");
63} 63}
64 64
65int __init db1235_arch_init(void) 65int __init db1235_arch_init(void)
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index c3b04c929f29..516225d207ee 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -20,7 +20,6 @@
20 20
21#include <asm/mach-ath79/ath79.h> 21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h> 22#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ar933x_uart_platform.h>
24#include "common.h" 23#include "common.h"
25#include "dev-common.h" 24#include "dev-common.h"
26 25
@@ -68,15 +67,11 @@ static struct resource ar933x_uart_resources[] = {
68 }, 67 },
69}; 68};
70 69
71static struct ar933x_uart_platform_data ar933x_uart_data;
72static struct platform_device ar933x_uart_device = { 70static struct platform_device ar933x_uart_device = {
73 .name = "ar933x-uart", 71 .name = "ar933x-uart",
74 .id = -1, 72 .id = -1,
75 .resource = ar933x_uart_resources, 73 .resource = ar933x_uart_resources,
76 .num_resources = ARRAY_SIZE(ar933x_uart_resources), 74 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
77 .dev = {
78 .platform_data = &ar933x_uart_data,
79 },
80}; 75};
81 76
82void __init ath79_register_uart(void) 77void __init ath79_register_uart(void)
@@ -93,7 +88,6 @@ void __init ath79_register_uart(void)
93 ath79_uart_data[0].uartclk = uart_clk_rate; 88 ath79_uart_data[0].uartclk = uart_clk_rate;
94 platform_device_register(&ath79_uart_device); 89 platform_device_register(&ath79_uart_device);
95 } else if (soc_is_ar933x()) { 90 } else if (soc_is_ar933x()) {
96 ar933x_uart_data.uartclk = uart_clk_rate;
97 platform_device_register(&ar933x_uart_device); 91 platform_device_register(&ar933x_uart_device);
98 } else { 92 } else {
99 BUG(); 93 BUG();
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
index f3bf6d5bfb9d..c52daf9b05c6 100644
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -4,4 +4,5 @@
4# 4#
5 5
6obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o 6obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
7obj-y += board.o
7obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o 8obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
new file mode 100644
index 000000000000..f3f6bfe68a2a
--- /dev/null
+++ b/arch/mips/bcm47xx/board.c
@@ -0,0 +1,309 @@
1#include <linux/export.h>
2#include <linux/string.h>
3#include <bcm47xx_board.h>
4#include <bcm47xx_nvram.h>
5
6struct bcm47xx_board_type {
7 const enum bcm47xx_board board;
8 const char *name;
9};
10
11struct bcm47xx_board_type_list1 {
12 struct bcm47xx_board_type board;
13 const char *value1;
14};
15
16struct bcm47xx_board_type_list2 {
17 struct bcm47xx_board_type board;
18 const char *value1;
19 const char *value2;
20};
21
22struct bcm47xx_board_type_list3 {
23 struct bcm47xx_board_type board;
24 const char *value1;
25 const char *value2;
26 const char *value3;
27};
28
29struct bcm47xx_board_store {
30 enum bcm47xx_board board;
31 char name[BCM47XX_BOARD_MAX_NAME];
32};
33
34/* model_name */
35static const
36struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
37 {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"},
38 {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"},
39 { {0}, 0},
40};
41
42/* model_no */
43static const
44struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
45 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
46 { {0}, 0},
47};
48
49/* machine_name */
50static const
51struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
52 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
53 { {0}, 0},
54};
55
56/* hardware_version */
57static const
58struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
59 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
60 {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"},
61 {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"},
62 {{BCM47XX_BOARD_ASUS_WL500GD, "Asus WL500GD"}, "WL500gd-"},
63 {{BCM47XX_BOARD_ASUS_WL500GPV1, "Asus WL500GP V1"}, "WL500gp-"},
64 {{BCM47XX_BOARD_ASUS_WL500GPV2, "Asus WL500GP V2"}, "WL500GPV2-"},
65 {{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"},
66 {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
67 {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
68 {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
69 { {0}, 0},
70};
71
72/* productid */
73static const
74struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
75 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
76 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
77 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
78 {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"},
79 {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
80 {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"},
81 {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"},
82 {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"},
83 {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"},
84 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
85 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
86 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
87 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
88 {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"},
89 {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"},
90 { {0}, 0},
91};
92
93/* ModelId */
94static const
95struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
96 {{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565"},
97 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
98 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
99 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
100 { {0}, 0},
101};
102
103/* melco_id or buf1falo_id */
104static const
105struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = {
106 {{BCM47XX_BOARD_BUFFALO_WBR2_G54, "Buffalo WBR2-G54"}, "29bb0332"},
107 {{BCM47XX_BOARD_BUFFALO_WHR2_A54G54, "Buffalo WHR2-A54G54"}, "290441dd"},
108 {{BCM47XX_BOARD_BUFFALO_WHR_G125, "Buffalo WHR-G125"}, "32093"},
109 {{BCM47XX_BOARD_BUFFALO_WHR_G54S, "Buffalo WHR-G54S"}, "30182"},
110 {{BCM47XX_BOARD_BUFFALO_WHR_HP_G54, "Buffalo WHR-HP-G54"}, "30189"},
111 {{BCM47XX_BOARD_BUFFALO_WLA2_G54L, "Buffalo WLA2-G54L"}, "29129"},
112 {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"},
113 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"},
114 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"},
115 { {0}, 0},
116};
117
118/* boot_hw_model, boot_hw_ver */
119static const
120struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
121 /* like WRT160N v3.0 */
122 {{BCM47XX_BOARD_CISCO_M10V1, "Cisco M10"}, "M10", "1.0"},
123 /* like WRT310N v2.0 */
124 {{BCM47XX_BOARD_CISCO_M20V1, "Cisco M20"}, "M20", "1.0"},
125 {{BCM47XX_BOARD_LINKSYS_E900V1, "Linksys E900 V1"}, "E900", "1.0"},
126 /* like WRT160N v3.0 */
127 {{BCM47XX_BOARD_LINKSYS_E1000V1, "Linksys E1000 V1"}, "E100", "1.0"},
128 {{BCM47XX_BOARD_LINKSYS_E1000V2, "Linksys E1000 V2"}, "E1000", "2.0"},
129 {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"},
130 {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"},
131 {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
132 /* like WRT610N v2.0 */
133 {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"},
134 {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
135 {{BCM47XX_BOARD_LINKSYS_E4200V1, "Linksys E4200 V1"}, "E4200", "1.0"},
136 {{BCM47XX_BOARD_LINKSYS_WRT150NV11, "Linksys WRT150N V1.1"}, "WRT150N", "1.1"},
137 {{BCM47XX_BOARD_LINKSYS_WRT150NV1, "Linksys WRT150N V1"}, "WRT150N", "1"},
138 {{BCM47XX_BOARD_LINKSYS_WRT160NV1, "Linksys WRT160N V1"}, "WRT160N", "1.0"},
139 {{BCM47XX_BOARD_LINKSYS_WRT160NV3, "Linksys WRT160N V3"}, "WRT160N", "3.0"},
140 {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
141 {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
142 {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
143 {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
144 {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
145 {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
146 { {0}, 0},
147};
148
149/* board_id */
150static const
151struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
152 {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
153 {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
154 {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
155 {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
156 {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
157 {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"},
158 {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"},
159 {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"},
160 {{BCM47XX_BOARD_NETGEAR_WNDR4500V1, "Netgear WNDR4500 V1"}, "U12H189T00_NETGEAR"},
161 {{BCM47XX_BOARD_NETGEAR_WNDR4500V2, "Netgear WNDR4500 V2"}, "U12H224T00_NETGEAR"},
162 {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"},
163 {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"},
164 {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"},
165 {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
166 {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
167 {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"},
168 { {0}, 0},
169};
170
171/* boardtype, boardnum, boardrev */
172static const
173struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
174 {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
175 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
176 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
177 { {0}, 0},
178};
179
180static const
181struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = {
182 {BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
183};
184
185static struct bcm47xx_board_store bcm47xx_board = {BCM47XX_BOARD_NO, "Unknown Board"};
186
187static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
188{
189 char buf1[30];
190 char buf2[30];
191 char buf3[30];
192 const struct bcm47xx_board_type_list1 *e1;
193 const struct bcm47xx_board_type_list2 *e2;
194 const struct bcm47xx_board_type_list3 *e3;
195
196 if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) {
197 for (e1 = bcm47xx_board_list_model_name; e1->value1; e1++) {
198 if (!strcmp(buf1, e1->value1))
199 return &e1->board;
200 }
201 }
202
203 if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
204 for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
205 if (strstarts(buf1, e1->value1))
206 return &e1->board;
207 }
208 }
209
210 if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
211 for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
212 if (strstarts(buf1, e1->value1))
213 return &e1->board;
214 }
215 }
216
217 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
218 for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
219 if (strstarts(buf1, e1->value1))
220 return &e1->board;
221 }
222 }
223
224 if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) {
225 for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) {
226 if (!strcmp(buf1, e1->value1))
227 return &e1->board;
228 }
229 }
230
231 if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) {
232 for (e1 = bcm47xx_board_list_ModelId; e1->value1; e1++) {
233 if (!strcmp(buf1, e1->value1))
234 return &e1->board;
235 }
236 }
237
238 if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 ||
239 bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) {
240 /* buffalo hardware, check id for specific hardware matches */
241 for (e1 = bcm47xx_board_list_melco_id; e1->value1; e1++) {
242 if (!strcmp(buf1, e1->value1))
243 return &e1->board;
244 }
245 }
246
247 if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 &&
248 bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) {
249 for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
250 if (!strcmp(buf1, e2->value1) &&
251 !strcmp(buf2, e2->value2))
252 return &e2->board;
253 }
254 }
255
256 if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) {
257 for (e1 = bcm47xx_board_list_board_id; e1->value1; e1++) {
258 if (!strcmp(buf1, e1->value1))
259 return &e1->board;
260 }
261 }
262
263 if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 &&
264 bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0 &&
265 bcm47xx_nvram_getenv("boardrev", buf3, sizeof(buf3)) >= 0) {
266 for (e3 = bcm47xx_board_list_board; e3->value1; e3++) {
267 if (!strcmp(buf1, e3->value1) &&
268 !strcmp(buf2, e3->value2) &&
269 !strcmp(buf3, e3->value3))
270 return &e3->board;
271 }
272 }
273 return bcm47xx_board_unknown;
274}
275
276void __init bcm47xx_board_detect(void)
277{
278 int err;
279 char buf[10];
280 const struct bcm47xx_board_type *board_detected;
281
282 if (bcm47xx_board.board != BCM47XX_BOARD_NO)
283 return;
284
285 /* check if the nvram is available */
286 err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
287
288 /* init of nvram failed, probably too early now */
289 if (err == -ENXIO) {
290 return;
291 }
292
293 board_detected = bcm47xx_board_get_nvram();
294 bcm47xx_board.board = board_detected->board;
295 strlcpy(bcm47xx_board.name, board_detected->name,
296 BCM47XX_BOARD_MAX_NAME);
297}
298
299enum bcm47xx_board bcm47xx_board_get(void)
300{
301 return bcm47xx_board.board;
302}
303EXPORT_SYMBOL(bcm47xx_board_get);
304
305const char *bcm47xx_board_get_name(void)
306{
307 return bcm47xx_board.name;
308}
309EXPORT_SYMBOL(bcm47xx_board_get_name);
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index cc40b74940f5..b4c585b1c62e 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -190,3 +190,23 @@ int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
190 return -ENOENT; 190 return -ENOENT;
191} 191}
192EXPORT_SYMBOL(bcm47xx_nvram_getenv); 192EXPORT_SYMBOL(bcm47xx_nvram_getenv);
193
194int bcm47xx_nvram_gpio_pin(const char *name)
195{
196 int i, err;
197 char nvram_var[10];
198 char buf[30];
199
200 for (i = 0; i < 16; i++) {
201 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
202 if (err <= 0)
203 continue;
204 err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf));
205 if (err <= 0)
206 continue;
207 if (!strcmp(name, buf))
208 return i;
209 }
210 return -ENOENT;
211}
212EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 8c155afb1299..5cba318bc1cd 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -32,12 +32,37 @@
32#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
33#include <asm/fw/cfe/cfe_api.h> 33#include <asm/fw/cfe/cfe_api.h>
34#include <asm/fw/cfe/cfe_error.h> 34#include <asm/fw/cfe/cfe_error.h>
35#include <bcm47xx.h>
36#include <bcm47xx_board.h>
35 37
36static int cfe_cons_handle; 38static int cfe_cons_handle;
37 39
40static u16 get_chip_id(void)
41{
42 switch (bcm47xx_bus_type) {
43#ifdef CONFIG_BCM47XX_SSB
44 case BCM47XX_BUS_TYPE_SSB:
45 return bcm47xx_bus.ssb.chip_id;
46#endif
47#ifdef CONFIG_BCM47XX_BCMA
48 case BCM47XX_BUS_TYPE_BCMA:
49 return bcm47xx_bus.bcma.bus.chipinfo.id;
50#endif
51 }
52 return 0;
53}
54
38const char *get_system_type(void) 55const char *get_system_type(void)
39{ 56{
40 return "Broadcom BCM47XX"; 57 static char buf[50];
58 u16 chip_id = get_chip_id();
59
60 snprintf(buf, sizeof(buf),
61 (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
62 "Broadcom BCM%04X (%s)",
63 chip_id, bcm47xx_board_get_name());
64
65 return buf;
41} 66}
42 67
43void prom_putchar(char c) 68void prom_putchar(char c)
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index b2246cd9ca12..1f30571968e7 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -36,6 +36,7 @@
36#include <asm/time.h> 36#include <asm/time.h>
37#include <bcm47xx.h> 37#include <bcm47xx.h>
38#include <bcm47xx_nvram.h> 38#include <bcm47xx_nvram.h>
39#include <bcm47xx_board.h>
39 40
40union bcm47xx_bus bcm47xx_bus; 41union bcm47xx_bus bcm47xx_bus;
41EXPORT_SYMBOL(bcm47xx_bus); 42EXPORT_SYMBOL(bcm47xx_bus);
@@ -221,6 +222,7 @@ void __init plat_mem_setup(void)
221 _machine_restart = bcm47xx_machine_restart; 222 _machine_restart = bcm47xx_machine_restart;
222 _machine_halt = bcm47xx_machine_halt; 223 _machine_halt = bcm47xx_machine_halt;
223 pm_power_off = bcm47xx_machine_halt; 224 pm_power_off = bcm47xx_machine_halt;
225 bcm47xx_board_detect();
224} 226}
225 227
226static int __init bcm47xx_register_bus_complete(void) 228static int __init bcm47xx_register_bus_complete(void)
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
index 536374dcba78..2c85d9254b5e 100644
--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -27,10 +27,16 @@
27#include <linux/ssb/ssb.h> 27#include <linux/ssb/ssb.h>
28#include <asm/time.h> 28#include <asm/time.h>
29#include <bcm47xx.h> 29#include <bcm47xx.h>
30#include <bcm47xx_nvram.h>
31#include <bcm47xx_board.h>
30 32
31void __init plat_time_init(void) 33void __init plat_time_init(void)
32{ 34{
33 unsigned long hz = 0; 35 unsigned long hz = 0;
36 u16 chip_id = 0;
37 char buf[10];
38 int len;
39 enum bcm47xx_board board = bcm47xx_board_get();
34 40
35 /* 41 /*
36 * Use deterministic values for initial counter interrupt 42 * Use deterministic values for initial counter interrupt
@@ -43,15 +49,32 @@ void __init plat_time_init(void)
43#ifdef CONFIG_BCM47XX_SSB 49#ifdef CONFIG_BCM47XX_SSB
44 case BCM47XX_BUS_TYPE_SSB: 50 case BCM47XX_BUS_TYPE_SSB:
45 hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; 51 hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
52 chip_id = bcm47xx_bus.ssb.chip_id;
46 break; 53 break;
47#endif 54#endif
48#ifdef CONFIG_BCM47XX_BCMA 55#ifdef CONFIG_BCM47XX_BCMA
49 case BCM47XX_BUS_TYPE_BCMA: 56 case BCM47XX_BUS_TYPE_BCMA:
50 hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; 57 hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
58 chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
51 break; 59 break;
52#endif 60#endif
53 } 61 }
54 62
63 if (chip_id == 0x5354) {
64 len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
65 if (len >= 0 && !strncmp(buf, "200", 4))
66 hz = 100000000;
67 }
68
69 switch (board) {
70 case BCM47XX_BOARD_ASUS_WL520GC:
71 case BCM47XX_BOARD_ASUS_WL520GU:
72 hz = 100000000;
73 break;
74 default:
75 break;
76 }
77
55 if (!hz) 78 if (!hz)
56 hz = 100000000; 79 hz = 100000000;
57 80
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 0048c0897896..ca0c343c9ea5 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -37,6 +37,10 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
37vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o 37vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
38endif 38endif
39 39
40ifdef CONFIG_KERNEL_XZ
41vmlinuzobjs-y += $(obj)/../../lib/ashldi3.o
42endif
43
40targets += vmlinux.bin 44targets += vmlinux.bin
41OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S 45OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
42$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE 46$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
@@ -44,8 +48,10 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
44 48
45tool_$(CONFIG_KERNEL_GZIP) = gzip 49tool_$(CONFIG_KERNEL_GZIP) = gzip
46tool_$(CONFIG_KERNEL_BZIP2) = bzip2 50tool_$(CONFIG_KERNEL_BZIP2) = bzip2
51tool_$(CONFIG_KERNEL_LZ4) = lz4
47tool_$(CONFIG_KERNEL_LZMA) = lzma 52tool_$(CONFIG_KERNEL_LZMA) = lzma
48tool_$(CONFIG_KERNEL_LZO) = lzo 53tool_$(CONFIG_KERNEL_LZO) = lzo
54tool_$(CONFIG_KERNEL_XZ) = xzkern
49 55
50targets += vmlinux.bin.z 56targets += vmlinux.bin.z
51$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE 57$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 2c9573098c0d..a8c6fd6a4406 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -43,7 +43,8 @@ void error(char *x)
43/* activate the code for pre-boot environment */ 43/* activate the code for pre-boot environment */
44#define STATIC static 44#define STATIC static
45 45
46#ifdef CONFIG_KERNEL_GZIP 46#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \
47 defined(CONFIG_KERNEL_LZ4)
47void *memcpy(void *dest, const void *src, size_t n) 48void *memcpy(void *dest, const void *src, size_t n)
48{ 49{
49 int i; 50 int i;
@@ -54,6 +55,8 @@ void *memcpy(void *dest, const void *src, size_t n)
54 d[i] = s[i]; 55 d[i] = s[i];
55 return dest; 56 return dest;
56} 57}
58#endif
59#ifdef CONFIG_KERNEL_GZIP
57#include "../../../../lib/decompress_inflate.c" 60#include "../../../../lib/decompress_inflate.c"
58#endif 61#endif
59 62
@@ -70,6 +73,10 @@ void *memset(void *s, int c, size_t n)
70#include "../../../../lib/decompress_bunzip2.c" 73#include "../../../../lib/decompress_bunzip2.c"
71#endif 74#endif
72 75
76#ifdef CONFIG_KERNEL_LZ4
77#include "../../../../lib/decompress_unlz4.c"
78#endif
79
73#ifdef CONFIG_KERNEL_LZMA 80#ifdef CONFIG_KERNEL_LZMA
74#include "../../../../lib/decompress_unlzma.c" 81#include "../../../../lib/decompress_unlzma.c"
75#endif 82#endif
@@ -78,6 +85,10 @@ void *memset(void *s, int c, size_t n)
78#include "../../../../lib/decompress_unlzo.c" 85#include "../../../../lib/decompress_unlzo.c"
79#endif 86#endif
80 87
88#ifdef CONFIG_KERNEL_XZ
89#include "../../../../lib/decompress_unxz.c"
90#endif
91
81void decompress_kernel(unsigned long boot_heap_start) 92void decompress_kernel(unsigned long boot_heap_start)
82{ 93{
83 unsigned long zimage_start, zimage_size; 94 unsigned long zimage_start, zimage_size;
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
index 8e6b07ca2f5e..5a33409c7f63 100644
--- a/arch/mips/boot/compressed/ld.script
+++ b/arch/mips/boot/compressed/ld.script
@@ -8,6 +8,9 @@
8 8
9OUTPUT_ARCH(mips) 9OUTPUT_ARCH(mips)
10ENTRY(start) 10ENTRY(start)
11PHDRS {
12 text PT_LOAD FLAGS(7); /* RWX */
13}
11SECTIONS 14SECTIONS
12{ 15{
13 /* Text and read-only data */ 16 /* Text and read-only data */
@@ -15,7 +18,7 @@ SECTIONS
15 .text : { 18 .text : {
16 *(.text) 19 *(.text)
17 *(.rodata) 20 *(.rodata)
18 } 21 }: text
19 /* End of text section */ 22 /* End of text section */
20 23
21 /* Writable data */ 24 /* Writable data */
diff --git a/arch/mips/boot/ecoff.h b/arch/mips/boot/ecoff.h
index 83e5c3813d67..7a75ce2c1bcd 100644
--- a/arch/mips/boot/ecoff.h
+++ b/arch/mips/boot/ecoff.h
@@ -12,7 +12,6 @@ typedef struct filehdr {
12} FILHDR; 12} FILHDR;
13#define FILHSZ sizeof(FILHDR) 13#define FILHSZ sizeof(FILHDR)
14 14
15#define OMAGIC 0407
16#define MIPSEBMAGIC 0x160 15#define MIPSEBMAGIC 0x160
17#define MIPSELMAGIC 0x162 16#define MIPSELMAGIC 0x162
18 17
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b212ae12e5ac..331b837cec57 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -999,7 +999,7 @@ void __init plat_mem_setup(void)
999 999
1000 if (total == 0) 1000 if (total == 0)
1001 panic("Unable to allocate memory from " 1001 panic("Unable to allocate memory from "
1002 "cvmx_bootmem_phy_alloc\n"); 1002 "cvmx_bootmem_phy_alloc");
1003} 1003}
1004 1004
1005/* 1005/*
@@ -1081,7 +1081,7 @@ void __init device_tree_init(void)
1081 /* Copy the default tree from init memory. */ 1081 /* Copy the default tree from init memory. */
1082 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); 1082 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8);
1083 if (initial_boot_params == NULL) 1083 if (initial_boot_params == NULL)
1084 panic("Could not allocate initial_boot_params\n"); 1084 panic("Could not allocate initial_boot_params");
1085 memcpy(initial_boot_params, fdt, dt_size); 1085 memcpy(initial_boot_params, fdt, dt_size);
1086 1086
1087 if (do_prune) { 1087 if (do_prune) {
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 61a334ac43ac..558e94977942 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -5,5 +5,4 @@
5obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o 5obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
6 6
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o
9obj-$(CONFIG_MTD_PHYSMAP) += mtd.o 8obj-$(CONFIG_MTD_PHYSMAP) += mtd.o
diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c
deleted file mode 100644
index d1ba701c9dd1..000000000000
--- a/arch/mips/cobalt/console.c
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * (C) P. Horton 2006
3 */
4#include <linux/io.h>
5#include <linux/serial_reg.h>
6
7#include <cobalt.h>
8
9#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
10
11void prom_putchar(char c)
12{
13 if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
14 return;
15
16 while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
17 ;
18
19 writeb(c, UART_BASE + UART_TX);
20}
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index ec3b2c417f7c..9a8c2fe8d334 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -17,6 +17,7 @@
17 17
18#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
19#include <asm/reboot.h> 19#include <asm/reboot.h>
20#include <asm/setup.h>
20#include <asm/gt64120.h> 21#include <asm/gt64120.h>
21 22
22#include <cobalt.h> 23#include <cobalt.h>
@@ -112,6 +113,8 @@ void __init prom_init(void)
112 } 113 }
113 114
114 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 115 add_memory_region(0x0, memsz, BOOT_MEM_RAM);
116
117 setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0);
115} 118}
116 119
117void __init prom_free_prom_memory(void) 120void __init prom_free_prom_memory(void)
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
deleted file mode 100644
index 7fda0ce5f692..000000000000
--- a/arch/mips/configs/powertv_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
1CONFIG_POWERTV=y
2CONFIG_BOOTLOADER_FAMILY="R2"
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_1000=y
6CONFIG_PREEMPT=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_CROSS_COMPILE=""
10# CONFIG_SWAP is not set
11CONFIG_SYSVIPC=y
12CONFIG_LOG_BUF_SHIFT=16
13CONFIG_RELAY=y
14CONFIG_BLK_DEV_INITRD=y
15# CONFIG_RD_GZIP is not set
16# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
17CONFIG_EXPERT=y
18# CONFIG_SYSCTL_SYSCALL is not set
19CONFIG_KALLSYMS_ALL=y
20# CONFIG_PCSPKR_PLATFORM is not set
21# CONFIG_EPOLL is not set
22# CONFIG_SIGNALFD is not set
23# CONFIG_EVENTFD is not set
24# CONFIG_VM_EVENT_COUNTERS is not set
25# CONFIG_SLUB_DEBUG is not set
26CONFIG_MODULES=y
27CONFIG_MODULE_UNLOAD=y
28CONFIG_MODVERSIONS=y
29CONFIG_MODULE_SRCVERSION_ALL=y
30# CONFIG_BLK_DEV_BSG is not set
31# CONFIG_IOSCHED_DEADLINE is not set
32# CONFIG_IOSCHED_CFQ is not set
33CONFIG_PCI=y
34CONFIG_NET=y
35CONFIG_PACKET=y
36CONFIG_UNIX=y
37CONFIG_INET=y
38CONFIG_IP_MULTICAST=y
39CONFIG_IP_ADVANCED_ROUTER=y
40CONFIG_IP_PNP=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47CONFIG_IPV6=y
48CONFIG_IPV6_PRIVACY=y
49CONFIG_INET6_AH=y
50CONFIG_INET6_ESP=y
51CONFIG_INET6_IPCOMP=y
52# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
53# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
54# CONFIG_INET6_XFRM_MODE_BEET is not set
55# CONFIG_IPV6_SIT is not set
56CONFIG_IPV6_TUNNEL=y
57CONFIG_NETFILTER=y
58# CONFIG_BRIDGE_NETFILTER is not set
59CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
60CONFIG_IP_NF_IPTABLES=y
61CONFIG_IP_NF_FILTER=y
62CONFIG_IP_NF_ARPTABLES=y
63CONFIG_IP_NF_ARPFILTER=y
64CONFIG_IP6_NF_IPTABLES=y
65CONFIG_IP6_NF_FILTER=y
66CONFIG_BRIDGE=y
67CONFIG_NET_SCHED=y
68CONFIG_NET_SCH_TBF=y
69CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
70CONFIG_MTD=y
71CONFIG_MTD_PARTITIONS=y
72CONFIG_MTD_CMDLINE_PARTS=y
73CONFIG_MTD_CHAR=y
74CONFIG_MTD_BLOCK=y
75CONFIG_MTD_NAND=y
76CONFIG_BLK_DEV_LOOP=y
77CONFIG_BLK_DEV_RAM=y
78CONFIG_BLK_DEV_RAM_SIZE=32768
79# CONFIG_MISC_DEVICES is not set
80# CONFIG_SCSI_PROC_FS is not set
81CONFIG_BLK_DEV_SD=y
82# CONFIG_SCSI_LOWLEVEL is not set
83CONFIG_ATA=y
84CONFIG_NETDEVICES=y
85CONFIG_NET_ETHERNET=y
86# CONFIG_WLAN is not set
87CONFIG_USB_RTL8150=y
88# CONFIG_INPUT_MOUSEDEV is not set
89CONFIG_INPUT_EVDEV=y
90# CONFIG_INPUT_KEYBOARD is not set
91# CONFIG_INPUT_MOUSE is not set
92# CONFIG_SERIO is not set
93# CONFIG_VT is not set
94# CONFIG_DEVKMEM is not set
95# CONFIG_LEGACY_PTYS is not set
96# CONFIG_HW_RANDOM is not set
97# CONFIG_HWMON is not set
98# CONFIG_MFD_SUPPORT is not set
99# CONFIG_VGA_ARB is not set
100CONFIG_USB_HIDDEV=y
101CONFIG_USB=y
102CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
103CONFIG_USB_DEVICEFS=y
104# CONFIG_USB_DEVICE_CLASS is not set
105CONFIG_USB_EHCI_HCD=y
106# CONFIG_USB_EHCI_TT_NEWSCHED is not set
107CONFIG_USB_OHCI_HCD=y
108CONFIG_USB_STORAGE=y
109CONFIG_USB_SERIAL=y
110CONFIG_USB_SERIAL_CONSOLE=y
111CONFIG_USB_SERIAL_CP210X=y
112CONFIG_EXT2_FS=y
113CONFIG_EXT3_FS=y
114# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
115# CONFIG_EXT3_FS_XATTR is not set
116# CONFIG_DNOTIFY is not set
117CONFIG_FUSE_FS=y
118CONFIG_PROC_KCORE=y
119CONFIG_TMPFS=y
120CONFIG_JFFS2_FS=y
121CONFIG_CRAMFS=y
122CONFIG_NFS_FS=y
123CONFIG_NFS_V3=y
124CONFIG_ROOT_NFS=y
125CONFIG_PRINTK_TIME=y
126CONFIG_DEBUG_FS=y
127CONFIG_DEBUG_KERNEL=y
128CONFIG_DETECT_HUNG_TASK=y
129# CONFIG_SCHED_DEBUG is not set
130# CONFIG_DEBUG_PREEMPT is not set
131CONFIG_DEBUG_INFO=y
132# CONFIG_RCU_CPU_STALL_DETECTOR is not set
133# CONFIG_EARLY_PRINTK is not set
134CONFIG_CMDLINE_BOOL=y
135# CONFIG_CRYPTO_ANSI_CPRNG is not set
136# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 22afed16ccde..41a2fa1fa12e 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -118,7 +118,7 @@
118 * 7 FPU/R4k timer 118 * 7 FPU/R4k timer
119 * 119 *
120 * We handle the IRQ according to _our_ priority (see setup.c), 120 * We handle the IRQ according to _our_ priority (see setup.c),
121 * then we just return. If multiple IRQs are pending then we will 121 * then we just return. If multiple IRQs are pending then we will
122 * just take another exception, big deal. 122 * just take another exception, big deal.
123 */ 123 */
124 .align 5 124 .align 5
@@ -146,7 +146,7 @@
146 /* 146 /*
147 * Find irq with highest priority 147 * Find irq with highest priority
148 */ 148 */
149 PTR_LA t1,cpu_mask_nr_tbl 149 PTR_LA t1,cpu_mask_nr_tbl
1501: lw t2,(t1) 1501: lw t2,(t1)
151 nop 151 nop
152 and t2,t0 152 and t2,t0
@@ -195,7 +195,7 @@
195 /* 195 /*
196 * Find irq with highest priority 196 * Find irq with highest priority
197 */ 197 */
198 PTR_LA t1,asic_mask_nr_tbl 198 PTR_LA t1,asic_mask_nr_tbl
1992: lw t2,(t1) 1992: lw t2,(t1)
200 nop 200 nop
201 and t2,t0 201 and t2,t0
@@ -221,7 +221,7 @@
221 FEXPORT(cpu_all_int) # HALT, timers, software junk 221 FEXPORT(cpu_all_int) # HALT, timers, software junk
222 li a0,DEC_CPU_IRQ_BASE 222 li a0,DEC_CPU_IRQ_BASE
223 srl t0,CAUSEB_IP 223 srl t0,CAUSEB_IP
224 li t1,CAUSEF_IP>>CAUSEB_IP # mask 224 li t1,CAUSEF_IP>>CAUSEB_IP # mask
225 b 1f 225 b 1f
226 li t2,4 # nr of bits / 2 226 li t2,4 # nr of bits / 2
227 227
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 4b3e3a4375a6..e04d973ce5aa 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DEC I/O ASIC interrupts. 2 * DEC I/O ASIC interrupts.
3 * 3 *
4 * Copyright (c) 2002, 2003 Maciej W. Rozycki 4 * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
@@ -51,22 +51,51 @@ static struct irq_chip ioasic_irq_type = {
51 .irq_unmask = unmask_ioasic_irq, 51 .irq_unmask = unmask_ioasic_irq,
52}; 52};
53 53
54void clear_ioasic_dma_irq(unsigned int irq) 54static void clear_ioasic_dma_irq(struct irq_data *d)
55{ 55{
56 u32 sir; 56 u32 sir;
57 57
58 sir = ~(1 << (irq - ioasic_irq_base)); 58 sir = ~(1 << (d->irq - ioasic_irq_base));
59 ioasic_write(IO_REG_SIR, sir); 59 ioasic_write(IO_REG_SIR, sir);
60 fast_iob();
60} 61}
61 62
62static struct irq_chip ioasic_dma_irq_type = { 63static struct irq_chip ioasic_dma_irq_type = {
63 .name = "IO-ASIC-DMA", 64 .name = "IO-ASIC-DMA",
64 .irq_ack = ack_ioasic_irq, 65 .irq_ack = clear_ioasic_dma_irq,
65 .irq_mask = mask_ioasic_irq, 66 .irq_mask = mask_ioasic_irq,
66 .irq_mask_ack = ack_ioasic_irq,
67 .irq_unmask = unmask_ioasic_irq, 67 .irq_unmask = unmask_ioasic_irq,
68 .irq_eoi = clear_ioasic_dma_irq,
68}; 69};
69 70
71/*
72 * I/O ASIC implements two kinds of DMA interrupts, informational and
73 * error interrupts.
74 *
75 * The formers do not stop DMA and should be cleared as soon as possible
76 * so that if they retrigger before the handler has completed, usually as
77 * a side effect of actions taken by the handler, then they are reissued.
78 * These use the `handle_edge_irq' handler that clears the request right
79 * away.
80 *
81 * The latters stop DMA and do not resume it until the interrupt has been
82 * cleared. This cannot be done until after a corrective action has been
83 * taken and this also means they will not retrigger. Therefore they use
84 * the `handle_fasteoi_irq' handler that only clears the request on the
85 * way out. Because MIPS processor interrupt inputs, one of which the I/O
86 * ASIC is cascaded to, are level-triggered it is recommended that error
87 * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
88 * set so that they are run with the interrupt line masked.
89 *
90 * This mask has `1' bits in the positions of informational interrupts.
91 */
92#define IO_IRQ_DMA_INFO \
93 (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \
94 IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \
95 IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \
96 IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \
97 IO_IRQ_MASK(IO_INR_ASC_DMA))
98
70void __init init_ioasic_irqs(int base) 99void __init init_ioasic_irqs(int base)
71{ 100{
72 int i; 101 int i;
@@ -79,7 +108,9 @@ void __init init_ioasic_irqs(int base)
79 irq_set_chip_and_handler(i, &ioasic_irq_type, 108 irq_set_chip_and_handler(i, &ioasic_irq_type,
80 handle_level_irq); 109 handle_level_irq);
81 for (; i < base + IO_IRQ_LINES; i++) 110 for (; i < base + IO_IRQ_LINES; i++)
82 irq_set_chip(i, &ioasic_dma_irq_type); 111 irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
112 1 << (i - base) & IO_IRQ_DMA_INFO ?
113 handle_edge_irq : handle_fasteoi_irq);
83 114
84 ioasic_irq_base = base; 115 ioasic_irq_base = base;
85} 116}
diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S
index c0d1522d448f..8c8498159e43 100644
--- a/arch/mips/dec/prom/call_o32.S
+++ b/arch/mips/dec/prom/call_o32.S
@@ -14,7 +14,7 @@
14 14
15/* Maximum number of arguments supported. Must be even! */ 15/* Maximum number of arguments supported. Must be even! */
16#define O32_ARGC 32 16#define O32_ARGC 32
17/* Number of static registers we save. */ 17/* Number of static registers we save. */
18#define O32_STATC 11 18#define O32_STATC 11
19/* Frame size for both of the above. */ 19/* Frame size for both of the above. */
20#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC) 20#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 468f665de7bb..4e1761e0a09a 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -104,7 +104,7 @@ void __init prom_init(void)
104 if (prom_is_rex(magic)) 104 if (prom_is_rex(magic))
105 rex_clear_cache(); 105 rex_clear_cache();
106 106
107 /* Register the early console. */ 107 /* Register the early console. */
108 register_prom_console(); 108 register_prom_console();
109 109
110 /* Were we compiled with the right CPU option? */ 110 /* Were we compiled with the right CPU option? */
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index 0aadac742900..8c62316f22f4 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -22,7 +22,7 @@ volatile unsigned long mem_err; /* So we know an error occurred */
22 22
23/* 23/*
24 * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen 24 * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen
25 * off the end of real memory. Only suitable for the 2100/3100's (PMAX). 25 * off the end of real memory. Only suitable for the 2100/3100's (PMAX).
26 */ 26 */
27 27
28#define CHUNK_SIZE 0x400000 28#define CHUNK_SIZE 0x400000
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 741cb4235bde..56e6e2c23683 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -65,7 +65,7 @@ EXPORT_SYMBOL(ioasic_base);
65/* 65/*
66 * IRQ routing and priority tables. Priorites are set as follows: 66 * IRQ routing and priority tables. Priorites are set as follows:
67 * 67 *
68 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 68 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
69 * 69 *
70 * MEMORY CPU CPU CPU ASIC CPU CPU 70 * MEMORY CPU CPU CPU ASIC CPU CPU
71 * RTC CPU CPU CPU ASIC CPU CPU 71 * RTC CPU CPU CPU ASIC CPU CPU
@@ -413,7 +413,7 @@ static void __init dec_init_kn02(void)
413 413
414/* 414/*
415 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 415 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
416 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 416 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
417 * DS5000/150, aka 4min. 417 * DS5000/150, aka 4min.
418 */ 418 */
419static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 419static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 13d61c002e4f..3f745459fdb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -58,7 +58,7 @@
58 58
59/* 59/*
60 * Memory segments (64bit kernel mode addresses) 60 * Memory segments (64bit kernel mode addresses)
61 * The compatibility segments use the full 64-bit sign extended value. Note 61 * The compatibility segments use the full 64-bit sign extended value. Note
62 * the R8000 doesn't have them so don't reference these in generic MIPS code. 62 * the R8000 doesn't have them so don't reference these in generic MIPS code.
63 */ 63 */
64#define XKUSEG _CONST64_(0x0000000000000000) 64#define XKUSEG _CONST64_(0x0000000000000000)
@@ -131,7 +131,7 @@
131 131
132/* 132/*
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting 133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
134 * the region, 3 bits for the CCA mode. This leaves 59 bits of which the 134 * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
135 * R8000 implements most with its 48-bit physical address space. 135 * R8000 implements most with its 48-bit physical address space.
136 */ 136 */
137#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ 137#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 08b607969a16..7eed2f261710 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Atomic operations that C can't guarantee us. Useful for 2 * Atomic operations that C can't guarantee us. Useful for
3 * resource counting etc.. 3 * resource counting etc..
4 * 4 *
5 * But use these as seldom as possible since they are much more slower 5 * But use these as seldom as possible since they are much more slower
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 314ab5532019..f26d8e1bf3c3 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -18,7 +18,7 @@
18 * over this barrier. All reads preceding this primitive are guaranteed 18 * over this barrier. All reads preceding this primitive are guaranteed
19 * to access memory (but not necessarily other CPUs' caches) before any 19 * to access memory (but not necessarily other CPUs' caches) before any
20 * reads following this primitive that depend on the data return by 20 * reads following this primitive that depend on the data return by
21 * any of the preceding reads. This primitive is much lighter weight than 21 * any of the preceding reads. This primitive is much lighter weight than
22 * rmb() on most CPUs, and is never heavier weight than is 22 * rmb() on most CPUs, and is never heavier weight than is
23 * rmb(). 23 * rmb().
24 * 24 *
@@ -43,7 +43,7 @@
43 * </programlisting> 43 * </programlisting>
44 * 44 *
45 * because the read of "*q" depends on the read of "p" and these 45 * because the read of "*q" depends on the read of "p" and these
46 * two reads are separated by a read_barrier_depends(). However, 46 * two reads are separated by a read_barrier_depends(). However,
47 * the following code, with the same initial values for "a" and "b": 47 * the following code, with the same initial values for "a" and "b":
48 * 48 *
49 * <programlisting> 49 * <programlisting>
@@ -57,7 +57,7 @@
57 * </programlisting> 57 * </programlisting>
58 * 58 *
59 * does not enforce ordering, since there is no data dependency between 59 * does not enforce ordering, since there is no data dependency between
60 * the read of "a" and the read of "b". Therefore, on some CPUs, such 60 * the read of "a" and the read of "b". Therefore, on some CPUs, such
61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() 61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
62 * in cases like this where there are no data dependencies. 62 * in cases like this where there are no data dependencies.
63 */ 63 */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 68f37e3eccc7..c75025f27c20 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,56 +14,52 @@
14/* 14/*
15 * Cache Operations available on all MIPS processors with R4000-style caches 15 * Cache Operations available on all MIPS processors with R4000-style caches
16 */ 16 */
17#define Index_Invalidate_I 0x00 17#define Index_Invalidate_I 0x00
18#define Index_Writeback_Inv_D 0x01 18#define Index_Writeback_Inv_D 0x01
19#define Index_Load_Tag_I 0x04 19#define Index_Load_Tag_I 0x04
20#define Index_Load_Tag_D 0x05 20#define Index_Load_Tag_D 0x05
21#define Index_Store_Tag_I 0x08 21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09 22#define Index_Store_Tag_D 0x09
23#if defined(CONFIG_CPU_LOONGSON2) 23#define Hit_Invalidate_I 0x10
24#define Hit_Invalidate_I 0x00 24#define Hit_Invalidate_D 0x11
25#else 25#define Hit_Writeback_Inv_D 0x15
26#define Hit_Invalidate_I 0x10
27#endif
28#define Hit_Invalidate_D 0x11
29#define Hit_Writeback_Inv_D 0x15
30 26
31/* 27/*
32 * R4000-specific cacheops 28 * R4000-specific cacheops
33 */ 29 */
34#define Create_Dirty_Excl_D 0x0d 30#define Create_Dirty_Excl_D 0x0d
35#define Fill 0x14 31#define Fill 0x14
36#define Hit_Writeback_I 0x18 32#define Hit_Writeback_I 0x18
37#define Hit_Writeback_D 0x19 33#define Hit_Writeback_D 0x19
38 34
39/* 35/*
40 * R4000SC and R4400SC-specific cacheops 36 * R4000SC and R4400SC-specific cacheops
41 */ 37 */
42#define Index_Invalidate_SI 0x02 38#define Index_Invalidate_SI 0x02
43#define Index_Writeback_Inv_SD 0x03 39#define Index_Writeback_Inv_SD 0x03
44#define Index_Load_Tag_SI 0x06 40#define Index_Load_Tag_SI 0x06
45#define Index_Load_Tag_SD 0x07 41#define Index_Load_Tag_SD 0x07
46#define Index_Store_Tag_SI 0x0A 42#define Index_Store_Tag_SI 0x0A
47#define Index_Store_Tag_SD 0x0B 43#define Index_Store_Tag_SD 0x0B
48#define Create_Dirty_Excl_SD 0x0f 44#define Create_Dirty_Excl_SD 0x0f
49#define Hit_Invalidate_SI 0x12 45#define Hit_Invalidate_SI 0x12
50#define Hit_Invalidate_SD 0x13 46#define Hit_Invalidate_SD 0x13
51#define Hit_Writeback_Inv_SD 0x17 47#define Hit_Writeback_Inv_SD 0x17
52#define Hit_Writeback_SD 0x1b 48#define Hit_Writeback_SD 0x1b
53#define Hit_Set_Virtual_SI 0x1e 49#define Hit_Set_Virtual_SI 0x1e
54#define Hit_Set_Virtual_SD 0x1f 50#define Hit_Set_Virtual_SD 0x1f
55 51
56/* 52/*
57 * R5000-specific cacheops 53 * R5000-specific cacheops
58 */ 54 */
59#define R5K_Page_Invalidate_S 0x17 55#define R5K_Page_Invalidate_S 0x17
60 56
61/* 57/*
62 * RM7000-specific cacheops 58 * RM7000-specific cacheops
63 */ 59 */
64#define Page_Invalidate_T 0x16 60#define Page_Invalidate_T 0x16
65#define Index_Store_Tag_T 0x0a 61#define Index_Store_Tag_T 0x0a
66#define Index_Load_Tag_T 0x06 62#define Index_Load_Tag_T 0x06
67 63
68/* 64/*
69 * R10000-specific cacheops 65 * R10000-specific cacheops
@@ -71,17 +67,22 @@
71 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 67 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
72 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 68 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
73 */ 69 */
74#define Index_Writeback_Inv_S 0x03 70#define Index_Writeback_Inv_S 0x03
75#define Index_Load_Tag_S 0x07 71#define Index_Load_Tag_S 0x07
76#define Index_Store_Tag_S 0x0B 72#define Index_Store_Tag_S 0x0B
77#define Hit_Invalidate_S 0x13 73#define Hit_Invalidate_S 0x13
78#define Cache_Barrier 0x14 74#define Cache_Barrier 0x14
79#define Hit_Writeback_Inv_S 0x17 75#define Hit_Writeback_Inv_S 0x17
80#define Index_Load_Data_I 0x18 76#define Index_Load_Data_I 0x18
81#define Index_Load_Data_D 0x19 77#define Index_Load_Data_D 0x19
82#define Index_Load_Data_S 0x1b 78#define Index_Load_Data_S 0x1b
83#define Index_Store_Data_I 0x1c 79#define Index_Store_Data_I 0x1c
84#define Index_Store_Data_D 0x1d 80#define Index_Store_Data_D 0x1d
85#define Index_Store_Data_S 0x1f 81#define Index_Store_Data_S 0x1f
82
83/*
84 * Loongson2-specific cacheops
85 */
86#define Hit_Invalidate_I_Loongson23 0x00
86 87
87#endif /* __ASM_CACHEOPS_H */ 88#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
index a6e505a0e44b..be4d62a5a10e 100644
--- a/arch/mips/include/asm/dec/ioasic.h
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -31,8 +31,6 @@ static inline u32 ioasic_read(unsigned int reg)
31 return ioasic_base[reg / 4]; 31 return ioasic_base[reg / 4];
32} 32}
33 33
34extern void clear_ioasic_dma_irq(unsigned int irq);
35
36extern void init_ioasic_irqs(int base); 34extern void init_ioasic_irqs(int base);
37 35
38extern int dec_ioasic_clocksource_init(void); 36extern int dec_ioasic_clocksource_init(void);
diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
index a8665a7611c2..8bd95971fe2d 100644
--- a/arch/mips/include/asm/dec/ioasic_addrs.h
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -40,7 +40,7 @@
40#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ 40#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
41#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 41#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
42#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ 42#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
43#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ 43#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
44#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 44#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
45 45
46 46
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 0eb3241de706..88d9ffd74258 100644
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -57,12 +57,12 @@
57/* 57/*
58 * System Control & Status Register bits. 58 * System Control & Status Register bits.
59 */ 59 */
60#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ 60#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
61#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ 61#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
62#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ 62#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
63#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ 63#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
64#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ 64#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
65#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ 65#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
66#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ 66#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
67#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ 67#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
68#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ 68#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
index 69dc2a9a2d0f..92c0fe256099 100644
--- a/arch/mips/include/asm/dec/kn02ca.h
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -68,7 +68,7 @@
68#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ 68#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
69 69
70#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ 70#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
71#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ 71#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
72#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ 72#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
73#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ 73#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
74#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ 74#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index 446577712bee..c0ead6313845 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -49,7 +49,7 @@
49 49
50#ifdef CONFIG_64BIT 50#ifdef CONFIG_64BIT
51 51
52#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ 52#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
53 53
54#else /* !CONFIG_64BIT */ 54#else /* !CONFIG_64BIT */
55 55
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index cf3ae2480b1d..a66359ef4ece 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -331,6 +331,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
331#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 331#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
332 dump_task_fpu(tsk, elf_fpregs) 332 dump_task_fpu(tsk, elf_fpregs)
333 333
334#define CORE_DUMP_USE_REGSET
334#define ELF_EXEC_PAGESIZE PAGE_SIZE 335#define ELF_EXEC_PAGESIZE PAGE_SIZE
335 336
336/* This yields a mask that user programs can use to figure out what 337/* This yields a mask that user programs can use to figure out what
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
deleted file mode 100644
index 6cb30f2b7198..000000000000
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
new file mode 100644
index 000000000000..00867dd05a69
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -0,0 +1,110 @@
1#ifndef __BCM47XX_BOARD_H
2#define __BCM47XX_BOARD_H
3
4enum bcm47xx_board {
5 BCM47XX_BOARD_ASUS_RTAC66U,
6 BCM47XX_BOARD_ASUS_RTN10,
7 BCM47XX_BOARD_ASUS_RTN10D,
8 BCM47XX_BOARD_ASUS_RTN10U,
9 BCM47XX_BOARD_ASUS_RTN12,
10 BCM47XX_BOARD_ASUS_RTN12B1,
11 BCM47XX_BOARD_ASUS_RTN12C1,
12 BCM47XX_BOARD_ASUS_RTN12D1,
13 BCM47XX_BOARD_ASUS_RTN12HP,
14 BCM47XX_BOARD_ASUS_RTN15U,
15 BCM47XX_BOARD_ASUS_RTN16,
16 BCM47XX_BOARD_ASUS_RTN53,
17 BCM47XX_BOARD_ASUS_RTN66U,
18 BCM47XX_BOARD_ASUS_WL300G,
19 BCM47XX_BOARD_ASUS_WL320GE,
20 BCM47XX_BOARD_ASUS_WL330GE,
21 BCM47XX_BOARD_ASUS_WL500GD,
22 BCM47XX_BOARD_ASUS_WL500GPV1,
23 BCM47XX_BOARD_ASUS_WL500GPV2,
24 BCM47XX_BOARD_ASUS_WL500W,
25 BCM47XX_BOARD_ASUS_WL520GC,
26 BCM47XX_BOARD_ASUS_WL520GU,
27 BCM47XX_BOARD_ASUS_WL700GE,
28 BCM47XX_BOARD_ASUS_WLHDD,
29
30 BCM47XX_BOARD_BELKIN_F7D4301,
31
32 BCM47XX_BOARD_BUFFALO_WBR2_G54,
33 BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
34 BCM47XX_BOARD_BUFFALO_WHR_G125,
35 BCM47XX_BOARD_BUFFALO_WHR_G54S,
36 BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
37 BCM47XX_BOARD_BUFFALO_WLA2_G54L,
38 BCM47XX_BOARD_BUFFALO_WZR_G300N,
39 BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
40 BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
41
42 BCM47XX_BOARD_CISCO_M10V1,
43 BCM47XX_BOARD_CISCO_M20V1,
44
45 BCM47XX_BOARD_DELL_TM2300,
46
47 BCM47XX_BOARD_DLINK_DIR130,
48 BCM47XX_BOARD_DLINK_DIR330,
49
50 BCM47XX_BOARD_HUAWEI_E970,
51
52 BCM47XX_BOARD_LINKSYS_E900V1,
53 BCM47XX_BOARD_LINKSYS_E1000V1,
54 BCM47XX_BOARD_LINKSYS_E1000V2,
55 BCM47XX_BOARD_LINKSYS_E1000V21,
56 BCM47XX_BOARD_LINKSYS_E1200V2,
57 BCM47XX_BOARD_LINKSYS_E2000V1,
58 BCM47XX_BOARD_LINKSYS_E3000V1,
59 BCM47XX_BOARD_LINKSYS_E3200V1,
60 BCM47XX_BOARD_LINKSYS_E4200V1,
61 BCM47XX_BOARD_LINKSYS_WRT150NV1,
62 BCM47XX_BOARD_LINKSYS_WRT150NV11,
63 BCM47XX_BOARD_LINKSYS_WRT160NV1,
64 BCM47XX_BOARD_LINKSYS_WRT160NV3,
65 BCM47XX_BOARD_LINKSYS_WRT300NV11,
66 BCM47XX_BOARD_LINKSYS_WRT310NV1,
67 BCM47XX_BOARD_LINKSYS_WRT310NV2,
68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
69 BCM47XX_BOARD_LINKSYS_WRT610NV1,
70 BCM47XX_BOARD_LINKSYS_WRT610NV2,
71 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
72
73 BCM47XX_BOARD_MOTOROLA_WE800G,
74 BCM47XX_BOARD_MOTOROLA_WR850GP,
75 BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
76
77 BCM47XX_BOARD_NETGEAR_WGR614V8,
78 BCM47XX_BOARD_NETGEAR_WGR614V9,
79 BCM47XX_BOARD_NETGEAR_WNDR3300,
80 BCM47XX_BOARD_NETGEAR_WNDR3400V1,
81 BCM47XX_BOARD_NETGEAR_WNDR3400V2,
82 BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
83 BCM47XX_BOARD_NETGEAR_WNDR3700V3,
84 BCM47XX_BOARD_NETGEAR_WNDR4000,
85 BCM47XX_BOARD_NETGEAR_WNDR4500V1,
86 BCM47XX_BOARD_NETGEAR_WNDR4500V2,
87 BCM47XX_BOARD_NETGEAR_WNR2000,
88 BCM47XX_BOARD_NETGEAR_WNR3500L,
89 BCM47XX_BOARD_NETGEAR_WNR3500U,
90 BCM47XX_BOARD_NETGEAR_WNR3500V2,
91 BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
92 BCM47XX_BOARD_NETGEAR_WNR834BV2,
93
94 BCM47XX_BOARD_PHICOMM_M1,
95
96 BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
97
98 BCM47XX_BOARD_ZTE_H218N,
99
100 BCM47XX_BOARD_UNKNOWN,
101 BCM47XX_BOARD_NO,
102};
103
104#define BCM47XX_BOARD_MAX_NAME 30
105
106void bcm47xx_board_detect(void);
107enum bcm47xx_board bcm47xx_board_get(void);
108const char *bcm47xx_board_get_name(void);
109
110#endif /* __BCM47XX_BOARD_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index b8e7be8f34dd..36a3fc1aa3ae 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -48,4 +48,6 @@ static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf); 48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
49} 49}
50 50
51int bcm47xx_nvram_gpio_pin(const char *name);
52
51#endif /* __BCM47XX_NVRAM_H */ 53#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 47fb247f9663..f9f448650505 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -52,23 +52,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
52 return 0; 52 return 0;
53} 53}
54 54
55static inline void plat_extra_sync_for_device(struct device *dev)
56{
57 BUG();
58}
59
60static inline int plat_device_is_coherent(struct device *dev) 55static inline int plat_device_is_coherent(struct device *dev)
61{ 56{
62 return 1; 57 return 1;
63} 58}
64 59
65static inline int plat_dma_mapping_error(struct device *dev,
66 dma_addr_t dma_addr)
67{
68 BUG();
69 return 0;
70}
71
72dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 60dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
73phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); 61phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
74 62
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
new file mode 100644
index 000000000000..acce27fd2bb8
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -0,0 +1,87 @@
1/*
2 * CPU feature overrides for DECstation systems. Two variations
3 * are generally applicable.
4 *
5 * Copyright (C) 2013 Maciej W. Rozycki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
13#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
14
15/* Generic ones first. */
16#define cpu_has_tlb 1
17#define cpu_has_tx39_cache 0
18#define cpu_has_fpu 1
19#define cpu_has_divec 0
20#define cpu_has_prefetch 0
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23#define cpu_has_mips16 0
24#define cpu_has_mdmx 0
25#define cpu_has_mips3d 0
26#define cpu_has_smartmips 0
27#define cpu_has_rixi 0
28#define cpu_has_vtag_icache 0
29#define cpu_has_ic_fills_f_dc 0
30#define cpu_has_pindexed_dcache 0
31#define cpu_has_local_ebase 0
32#define cpu_icache_snoops_remote_store 1
33#define cpu_has_mips_4 0
34#define cpu_has_mips_5 0
35#define cpu_has_mips32r1 0
36#define cpu_has_mips32r2 0
37#define cpu_has_mips64r1 0
38#define cpu_has_mips64r2 0
39#define cpu_has_dsp 0
40#define cpu_has_mipsmt 0
41#define cpu_has_userlocal 0
42
43/* R3k-specific ones. */
44#ifdef CONFIG_CPU_R3000
45#define cpu_has_4kex 0
46#define cpu_has_3k_cache 1
47#define cpu_has_4k_cache 0
48#define cpu_has_32fpr 0
49#define cpu_has_counter 0
50#define cpu_has_watch 0
51#define cpu_has_vce 0
52#define cpu_has_cache_cdex_p 0
53#define cpu_has_cache_cdex_s 0
54#define cpu_has_llsc 0
55#define cpu_has_dc_aliases 0
56#define cpu_has_mips_2 0
57#define cpu_has_mips_3 0
58#define cpu_has_nofpuex 1
59#define cpu_has_inclusive_pcaches 0
60#define cpu_dcache_line_size() 4
61#define cpu_icache_line_size() 4
62#define cpu_scache_line_size() 0
63#endif /* CONFIG_CPU_R3000 */
64
65/* R4k-specific ones. */
66#ifdef CONFIG_CPU_R4X00
67#define cpu_has_4kex 1
68#define cpu_has_3k_cache 0
69#define cpu_has_4k_cache 1
70#define cpu_has_32fpr 1
71#define cpu_has_counter 1
72#define cpu_has_watch 1
73#define cpu_has_vce 1
74#define cpu_has_cache_cdex_p 1
75#define cpu_has_cache_cdex_s 1
76#define cpu_has_llsc 1
77#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
78#define cpu_has_mips_2 1
79#define cpu_has_mips_3 1
80#define cpu_has_nofpuex 0
81#define cpu_has_inclusive_pcaches 1
82#define cpu_dcache_line_size() 16
83#define cpu_icache_line_size() 16
84#define cpu_scache_line_size() 32
85#endif /* CONFIG_CPU_R4X00 */
86
87#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 74cb99257d5b..a9e8f6b62b0b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -47,16 +47,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
47 return 1; 47 return 1;
48} 48}
49 49
50static inline void plat_extra_sync_for_device(struct device *dev)
51{
52}
53
54static inline int plat_dma_mapping_error(struct device *dev,
55 dma_addr_t dma_addr)
56{
57 return 0;
58}
59
60static inline int plat_device_is_coherent(struct device *dev) 50static inline int plat_device_is_coherent(struct device *dev)
61{ 51{
62#ifdef CONFIG_DMA_COHERENT 52#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 06c441968e6e..4ffddfdb5062 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -58,16 +58,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
58 return 1; 58 return 1;
59} 59}
60 60
61static inline void plat_extra_sync_for_device(struct device *dev)
62{
63}
64
65static inline int plat_dma_mapping_error(struct device *dev,
66 dma_addr_t dma_addr)
67{
68 return 0;
69}
70
71static inline int plat_device_is_coherent(struct device *dev) 61static inline int plat_device_is_coherent(struct device *dev)
72{ 62{
73 return 1; /* IP27 non-cohernet mode is unsupported */ 63 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 073f0c4760ba..104cfbc3ed63 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -80,17 +80,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
80 return 1; 80 return 1;
81} 81}
82 82
83static inline void plat_extra_sync_for_device(struct device *dev)
84{
85 return;
86}
87
88static inline int plat_dma_mapping_error(struct device *dev,
89 dma_addr_t dma_addr)
90{
91 return 0;
92}
93
94static inline int plat_device_is_coherent(struct device *dev) 83static inline int plat_device_is_coherent(struct device *dev)
95{ 84{
96 return 0; /* IP32 is non-cohernet */ 85 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 9fc1e9ad7038..949003ef97b3 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -48,16 +48,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
48 return 1; 48 return 1;
49} 49}
50 50
51static inline void plat_extra_sync_for_device(struct device *dev)
52{
53}
54
55static inline int plat_dma_mapping_error(struct device *dev,
56 dma_addr_t dma_addr)
57{
58 return 0;
59}
60
61static inline int plat_device_is_coherent(struct device *dev) 51static inline int plat_device_is_coherent(struct device *dev)
62{ 52{
63 return 0; 53 return 0;
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index e1433055fe98..aeb2c05d6145 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -53,16 +53,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
53 return 1; 53 return 1;
54} 54}
55 55
56static inline void plat_extra_sync_for_device(struct device *dev)
57{
58}
59
60static inline int plat_dma_mapping_error(struct device *dev,
61 dma_addr_t dma_addr)
62{
63 return 0;
64}
65
66static inline int plat_device_is_coherent(struct device *dev) 56static inline int plat_device_is_coherent(struct device *dev)
67{ 57{
68 return 0; 58 return 0;
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
deleted file mode 100644
index b341108d12f1..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <asm/mach-powertv/asic_regs.h>
25
26#define DVR_CAPABLE (1<<0)
27#define PCIE_CAPABLE (1<<1)
28#define FFS_CAPABLE (1<<2)
29#define DISPLAY_CAPABLE (1<<3)
30
31/* Platform Family types
32 * For compitability, the new value must be added in the end */
33enum family_type {
34 FAMILY_8500,
35 FAMILY_8500RNG,
36 FAMILY_4500,
37 FAMILY_1500,
38 FAMILY_8600,
39 FAMILY_4600,
40 FAMILY_4600VZA,
41 FAMILY_8600VZB,
42 FAMILY_1500VZE,
43 FAMILY_1500VZF,
44 FAMILY_8700,
45 FAMILIES
46};
47
48/* Register maps for each ASIC */
49extern const struct register_map calliope_register_map;
50extern const struct register_map cronus_register_map;
51extern const struct register_map gaia_register_map;
52extern const struct register_map zeus_register_map;
53
54extern struct resource dvr_cronus_resources[];
55extern struct resource dvr_gaia_resources[];
56extern struct resource dvr_zeus_resources[];
57extern struct resource non_dvr_calliope_resources[];
58extern struct resource non_dvr_cronus_resources[];
59extern struct resource non_dvr_cronuslite_resources[];
60extern struct resource non_dvr_gaia_resources[];
61extern struct resource non_dvr_vz_calliope_resources[];
62extern struct resource non_dvr_vze_calliope_resources[];
63extern struct resource non_dvr_vzf_calliope_resources[];
64extern struct resource non_dvr_zeus_resources[];
65
66extern void powertv_platform_init(void);
67extern void platform_alloc_bootmem(void);
68extern enum asic_type platform_get_asic(void);
69extern enum family_type platform_get_family(void);
70extern int platform_supports_dvr(void);
71extern int platform_supports_ffs(void);
72extern int platform_supports_pcie(void);
73extern int platform_supports_display(void);
74extern void configure_platform(void);
75
76/* Platform Resources */
77#define ASIC_RESOURCE_GET_EXISTS 1
78extern struct resource *asic_resource_get(const char *name);
79extern void platform_release_memory(void *baddr, int size);
80
81/* USB configuration */
82struct usb_hcd; /* Forward reference */
83extern void platform_configure_usb_ehci(void);
84extern void platform_unconfigure_usb_ehci(void);
85extern void platform_configure_usb_ohci(void);
86extern void platform_unconfigure_usb_ohci(void);
87
88/* Resource for ASIC registers */
89extern struct resource asic_resource;
90extern int platform_usb_devices_init(struct platform_device **echi_dev,
91 struct platform_device **ohci_dev);
92
93/* Reboot Cause */
94extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
95extern void set_locked_reboot_cause(char code, unsigned int data,
96 unsigned int data2);
97
98enum sys_reboot_type {
99 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
100 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
101 * mode */
102 sys_user_reboot = 0x02, /* Reboot initiated by user */
103 sys_system_reboot = 0x03, /* Reboot initiated by OS */
104 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
105 sys_silent_reboot = 0x05, /* Silent reboot */
106 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
107 sys_power_up_reboot = 0x07, /* Power on bootup. Older
108 * drivers may report as
109 * userReboot. */
110 sys_code_change = 0x08, /* Reboot to take code change.
111 * Older drivers may report as
112 * userReboot. */
113 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
114 * reset button reset. Older
115 * drivers may report as
116 * userReboot. */
117 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
118};
119
120#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
deleted file mode 100644
index 20348e817b09..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
deleted file mode 100644
index 06712abb3e55..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASIC_GAIA,
31 ASICS /* Number of supported ASICs */
32};
33
34/* hardcoded values read from Chip Version registers */
35#define CRONUS_10 0x0B4C1C20
36#define CRONUS_11 0x0B4C1C21
37#define CRONUSLITE_10 0x0B4C1C40
38
39#define NAND_FLASH_BASE 0x03000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define GAIA_IO_BASE 0x09000000
42#define CRONUS_IO_BASE 0x09000000
43#define ZEUS_IO_BASE 0x09000000
44
45#define ASIC_IO_SIZE 0x01000000
46
47/* Definitions for backward compatibility */
48#define UART1_INTSTAT uart1_intstat
49#define UART1_INTEN uart1_inten
50#define UART1_CONFIG1 uart1_config1
51#define UART1_CONFIG2 uart1_config2
52#define UART1_DIVISORHI uart1_divisorhi
53#define UART1_DIVISORLO uart1_divisorlo
54#define UART1_DATA uart1_data
55#define UART1_STATUS uart1_status
56
57/* ASIC register enumeration */
58union register_map_entry {
59 unsigned long phys;
60 u32 *virt;
61};
62
63#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
64struct register_map {
65#include <asm/mach-powertv/asic_reg_map.h>
66};
67#undef REGISTER_MAP_ELEMENT
68
69/**
70 * register_map_offset_phys - add an offset to the physical address
71 * @map: Pointer to the &struct register_map
72 * @offset: Value to add
73 *
74 * Only adds the base to non-zero physical addresses
75 */
76static inline void register_map_offset_phys(struct register_map *map,
77 unsigned long offset)
78{
79#define REGISTER_MAP_ELEMENT(x) do { \
80 if (map->x.phys != 0) \
81 map->x.phys += offset; \
82 } while (false);
83
84#include <asm/mach-powertv/asic_reg_map.h>
85#undef REGISTER_MAP_ELEMENT
86}
87
88/**
89 * register_map_virtualize - Convert &register_map to virtual addresses
90 * @map: Pointer to &register_map to virtualize
91 */
92static inline void register_map_virtualize(struct register_map *map)
93{
94#define REGISTER_MAP_ELEMENT(x) do { \
95 map->x.virt = (!map->x.phys) ? NULL : \
96 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
97 } while (false);
98
99#include <asm/mach-powertv/asic_reg_map.h>
100#undef REGISTER_MAP_ELEMENT
101}
102
103extern struct register_map _asic_register_map;
104extern unsigned long asic_phy_base;
105
106/*
107 * Macros to interface to registers through their ioremapped address
108 * asic_reg_phys_addr Returns the physical address of the given register
109 * asic_reg_addr Returns the iomapped virtual address of the given
110 * register.
111 */
112#define asic_reg_addr(x) (_asic_register_map.x.virt)
113#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
114 (unsigned long) asic_reg_addr(x))))
115
116/*
117 * The asic_reg macro is gone. It should be replaced by either asic_read or
118 * asic_write, as appropriate.
119 */
120
121#define asic_read(x) readl(asic_reg_addr(x))
122#define asic_write(v, x) writel(v, asic_reg_addr(x))
123
124extern void asic_irq_init(void);
125#endif
diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
deleted file mode 100644
index 58c76ec32a19..000000000000
--- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 2010 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
20#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
21#define cpu_has_tlb 1
22#define cpu_has_4kex 1
23#define cpu_has_3k_cache 0
24#define cpu_has_4k_cache 1
25#define cpu_has_tx39_cache 0
26#define cpu_has_fpu 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30#define cpu_has_vce 0
31#define cpu_has_cache_cdex_p 0
32#define cpu_has_cache_cdex_s 0
33#define cpu_has_mcheck 1
34#define cpu_has_ejtag 1
35#define cpu_has_llsc 1
36#define cpu_has_mips16 0
37#define cpu_has_mdmx 0
38#define cpu_has_mips3d 0
39#define cpu_has_smartmips 0
40#define cpu_has_vtag_icache 0
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 1
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47#define cpu_has_dsp 0
48#define cpu_has_dsp2 0
49#define cpu_has_mipsmt 0
50#define cpu_has_userlocal 0
51#define cpu_has_nofpuex 0
52#define cpu_has_64bits 0
53#define cpu_has_64bit_zero_reg 0
54#define cpu_has_vint 1
55#define cpu_has_veic 1
56#define cpu_has_inclusive_pcaches 0
57
58#define cpu_dcache_line_size() 32
59#define cpu_icache_line_size() 32
60#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
deleted file mode 100644
index f8316720a218..000000000000
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/device.h>
17#include <asm/mach-powertv/asic.h>
18
19static inline bool is_kseg2(void *addr)
20{
21 return (unsigned long)addr >= KSEG2;
22}
23
24static inline unsigned long virt_to_phys_from_pte(void *addr)
25{
26 pgd_t *pgd;
27 pud_t *pud;
28 pmd_t *pmd;
29 pte_t *ptep, pte;
30
31 unsigned long virt_addr = (unsigned long)addr;
32 unsigned long phys_addr = 0UL;
33
34 /* get the page global directory. */
35 pgd = pgd_offset_k(virt_addr);
36
37 if (!pgd_none(*pgd)) {
38 /* get the page upper directory */
39 pud = pud_offset(pgd, virt_addr);
40 if (!pud_none(*pud)) {
41 /* get the page middle directory */
42 pmd = pmd_offset(pud, virt_addr);
43 if (!pmd_none(*pmd)) {
44 /* get a pointer to the page table entry */
45 ptep = pte_offset(pmd, virt_addr);
46 pte = *ptep;
47 /* check for a valid page */
48 if (pte_present(pte)) {
49 /* get the physical address the page is
50 * referring to */
51 phys_addr = (unsigned long)
52 page_to_phys(pte_page(pte));
53 /* add the offset within the page */
54 phys_addr |= (virt_addr & ~PAGE_MASK);
55 }
56 }
57 }
58 }
59
60 return phys_addr;
61}
62
63static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
64 size_t size)
65{
66 if (is_kseg2(addr))
67 return phys_to_dma(virt_to_phys_from_pte(addr));
68 else
69 return phys_to_dma(virt_to_phys(addr));
70}
71
72static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
73 struct page *page)
74{
75 return phys_to_dma(page_to_phys(page));
76}
77
78static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
79 dma_addr_t dma_addr)
80{
81 return dma_to_phys(dma_addr);
82}
83
84static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
85 size_t size, enum dma_data_direction direction)
86{
87}
88
89static inline int plat_dma_supported(struct device *dev, u64 mask)
90{
91 /*
92 * we fall back to GFP_DMA when the mask isn't all 1s,
93 * so we can't guarantee allocations that must be
94 * within a tighter range than GFP_DMA..
95 */
96 if (mask < DMA_BIT_MASK(24))
97 return 0;
98
99 return 1;
100}
101
102static inline void plat_extra_sync_for_device(struct device *dev)
103{
104}
105
106static inline int plat_dma_mapping_error(struct device *dev,
107 dma_addr_t dma_addr)
108{
109 return 0;
110}
111
112static inline int plat_device_is_coherent(struct device *dev)
113{
114 return 0;
115}
116
117#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
deleted file mode 100644
index 6c463be62156..000000000000
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
deleted file mode 100644
index c86ef094ec37..000000000000
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13#include <linux/log2.h>
14#include <linux/compiler.h>
15
16#include <asm/pgtable-bits.h>
17#include <asm/addrspace.h>
18
19/* We're going to mess with bits, so get sizes */
20#define IOR_BPC 8 /* Bits per char */
21#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
22#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
23
24/*
25 * Define the granularity of physical/DMA mapping in terms of the number
26 * of bits that defines the offset within a grain. These will be the
27 * least significant bits of the address. The rest of a physical or DMA
28 * address will be used to index into an appropriate table to find the
29 * offset to add to the address to yield the corresponding DMA or physical
30 * address, respectively.
31 */
32#define IOR_LSBITS 22 /* Bits in a grain */
33
34/*
35 * Compute the number of most significant address bits after removing those
36 * used for the offset within a grain and then compute the number of table
37 * entries for the conversion.
38 */
39#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
40#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
41
42#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
43#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
44
45/*
46 * Define data structures used as elements in the arrays for the conversion
47 * between physical and DMA addresses. We do some slightly fancy math to
48 * compute the width of the offset element of the conversion tables so
49 * that we can have the smallest conversion tables. Next, round up the
50 * sizes to the next higher power of two, i.e. the offset element will have
51 * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
52 * bits. Finally, we compute a shift value that puts the most significant
53 * bits of the offset into the most significant bits of the offset element.
54 * This makes it more efficient on processors without barrel shifters and
55 * easier to see the values if the conversion table is dumped in binary.
56 */
57#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
58#define IOR_OFFSET_WIDTH(n) \
59 (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
60
61#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
62#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
63
64#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
65#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
66
67struct ior_phys_to_dma {
68 dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
69 __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
70};
71
72struct ior_dma_to_phys {
73 dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
74 __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
75};
76
77extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
78extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
79
80static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
81{
82 return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
83}
84
85static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
86{
87 return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
88}
89
90/* These are not portable and should not be used in drivers. Drivers should
91 * be using ioremap() and friends to map physical addresses to virtual
92 * addresses and dma_map*() and friends to map virtual addresses into DMA
93 * addresses and back.
94 */
95static inline dma_addr_t phys_to_dma(phys_addr_t phys)
96{
97 return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
98}
99
100static inline phys_addr_t dma_to_phys(dma_addr_t dma)
101{
102 return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
103}
104
105extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
106 dma_addr_t size);
107
108/*
109 * Allow physical addresses to be fixed up to help peripherals located
110 * outside the low 32-bit range -- generic pass-through version.
111 */
112static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
113{
114 return phys_addr;
115}
116
117/*
118 * Handle the special case of addresses the area aliased into the first
119 * 512 MiB of the processor's physical address space. These turn into either
120 * kseg0 or kseg1 addresses, depending on flags.
121 */
122static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
123 unsigned long flags)
124{
125 phys_addr_t start_offset;
126 void __iomem *result = NULL;
127
128 /* Start by checking to see whether this is an aliased address */
129 start_offset = _dma_to_phys_offset_raw(start);
130
131 /*
132 * If:
133 * o the memory is aliased into the first 512 MiB, and
134 * o the start and end are in the same RAM bank, and
135 * o we don't have a zero size or wrap around, and
136 * o we are supposed to create an uncached mapping,
137 * handle this is a kseg0 or kseg1 address
138 */
139 if (start_offset != 0) {
140 phys_addr_t last;
141 dma_addr_t dma_to_phys_offset;
142
143 last = start + size - 1;
144 dma_to_phys_offset =
145 _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
146
147 if (dma_to_phys_offset == start_offset &&
148 size != 0 && start <= last) {
149 phys_t adjusted_start;
150 adjusted_start = start + start_offset;
151 if (flags == _CACHE_UNCACHED)
152 result = (void __iomem *) (unsigned long)
153 CKSEG1ADDR(adjusted_start);
154 else
155 result = (void __iomem *) (unsigned long)
156 CKSEG0ADDR(adjusted_start);
157 }
158 }
159
160 return result;
161}
162
163static inline int plat_iounmap(const volatile void __iomem *addr)
164{
165 return 0;
166}
167#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
deleted file mode 100644
index 4bd5d0c61a91..000000000000
--- a/arch/mips/include/asm/mach-powertv/irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
deleted file mode 100644
index 6f3e9a0fcf8c..000000000000
--- a/arch/mips/include/asm/mach-powertv/powertv-clock.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
deleted file mode 100644
index c5651c8e58d1..000000000000
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
10 */
11#ifndef __ASM_MACH_POWERTV_WAR_H
12#define __ASM_MACH_POWERTV_WAR_H
13
14#define R4600_V1_INDEX_ICACHEOP_WAR 0
15#define R4600_V1_HIT_CACHEOP_WAR 0
16#define R4600_V2_HIT_CACHEOP_WAR 0
17#define R5432_CP0_INTERRUPT_WAR 0
18#define BCM1250_M3_WAR 0
19#define SIBYTE_1956_WAR 0
20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define ICACHE_REFILLS_WORKAROUND_WAR 1
24#define R10000_LLSC_WAR 0
25#define MIPS34K_MISSED_ITLB_WAR 0
26
27#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index a02596cf1abd..e33227998713 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2013 Imagination Technologies Ltd.
4 * 5 *
5 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -20,61 +21,26 @@
20#ifndef __ASM_MIPS_BOARDS_PIIX4_H 21#ifndef __ASM_MIPS_BOARDS_PIIX4_H
21#define __ASM_MIPS_BOARDS_PIIX4_H 22#define __ASM_MIPS_BOARDS_PIIX4_H
22 23
23/************************************************************************ 24/* PIRQX Route Control */
24 * IO register offsets 25#define PIIX4_FUNC0_PIRQRC 0x60
25 ************************************************************************/ 26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
26#define PIIX4_ICTLR1_ICW1 0x20 27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
27#define PIIX4_ICTLR1_ICW2 0x21 28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
28#define PIIX4_ICTLR1_ICW3 0x21 29/* Top Of Memory */
29#define PIIX4_ICTLR1_ICW4 0x21 30#define PIIX4_FUNC0_TOM 0x69
30#define PIIX4_ICTLR2_ICW1 0xa0 31#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
31#define PIIX4_ICTLR2_ICW2 0xa1 32/* Deterministic Latency Control */
32#define PIIX4_ICTLR2_ICW3 0xa1 33#define PIIX4_FUNC0_DLC 0x82
33#define PIIX4_ICTLR2_ICW4 0xa1 34#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
34#define PIIX4_ICTLR1_OCW1 0x21 35#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
35#define PIIX4_ICTLR1_OCW2 0x20 36#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
36#define PIIX4_ICTLR1_OCW3 0x20 37
37#define PIIX4_ICTLR1_OCW4 0x20 38/* IDE Timing */
38#define PIIX4_ICTLR2_OCW1 0xa1 39#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
39#define PIIX4_ICTLR2_OCW2 0xa0 40#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
40#define PIIX4_ICTLR2_OCW3 0xa0 41#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
41#define PIIX4_ICTLR2_OCW4 0xa0 42#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
42 43#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
43 44#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
44/************************************************************************
45 * Register encodings.
46 ************************************************************************/
47#define PIIX4_OCW2_NSEOI (0x1 << 5)
48#define PIIX4_OCW2_SEOI (0x3 << 5)
49#define PIIX4_OCW2_RNSEOI (0x5 << 5)
50#define PIIX4_OCW2_RAEOIS (0x4 << 5)
51#define PIIX4_OCW2_RAEOIC (0x0 << 5)
52#define PIIX4_OCW2_RSEOI (0x7 << 5)
53#define PIIX4_OCW2_SP (0x6 << 5)
54#define PIIX4_OCW2_NOP (0x2 << 5)
55
56#define PIIX4_OCW2_SEL (0x0 << 3)
57
58#define PIIX4_OCW2_ILS_0 0
59#define PIIX4_OCW2_ILS_1 1
60#define PIIX4_OCW2_ILS_2 2
61#define PIIX4_OCW2_ILS_3 3
62#define PIIX4_OCW2_ILS_4 4
63#define PIIX4_OCW2_ILS_5 5
64#define PIIX4_OCW2_ILS_6 6
65#define PIIX4_OCW2_ILS_7 7
66#define PIIX4_OCW2_ILS_8 0
67#define PIIX4_OCW2_ILS_9 1
68#define PIIX4_OCW2_ILS_10 2
69#define PIIX4_OCW2_ILS_11 3
70#define PIIX4_OCW2_ILS_12 4
71#define PIIX4_OCW2_ILS_13 5
72#define PIIX4_OCW2_ILS_14 6
73#define PIIX4_OCW2_ILS_15 7
74
75#define PIIX4_OCW3_SEL (0x1 << 3)
76
77#define PIIX4_OCW3_IRR 0x2
78#define PIIX4_OCW3_ISR 0x3
79 45
80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 46#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 3b29079b5424..e277bbad2871 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,21 +24,21 @@
24#endif /* SMTC */ 24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 27#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30do { \ 28do { \
31 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 29 extern void tlbmiss_handler_setup_pgd(unsigned long); \
32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
33} while (0) 31} while (0)
34 32
33#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
35#define TLBMISS_HANDLER_SETUP() \ 34#define TLBMISS_HANDLER_SETUP() \
36 do { \ 35 do { \
37 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
38 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 37 write_c0_xcontext((unsigned long) smp_processor_id() << \
38 SMP_CPUID_REGSHIFT); \
39 } while (0) 39 } while (0)
40 40
41#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 41#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
42 42
43/* 43/*
44 * For the fast tlb miss handlers, we keep a per cpu array of pointers 44 * For the fast tlb miss handlers, we keep a per cpu array of pointers
@@ -47,21 +47,11 @@ do { \
47 */ 47 */
48extern unsigned long pgd_current[]; 48extern unsigned long pgd_current[];
49 49
50#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
51 pgd_current[smp_processor_id()] = (unsigned long)(pgd)
52
53#ifdef CONFIG_32BIT
54#define TLBMISS_HANDLER_SETUP() \ 50#define TLBMISS_HANDLER_SETUP() \
55 write_c0_context((unsigned long) smp_processor_id() << 25); \ 51 write_c0_context((unsigned long) smp_processor_id() << \
52 SMP_CPUID_REGSHIFT); \
56 back_to_back_c0_hazard(); \ 53 back_to_back_c0_hazard(); \
57 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
58#endif
59#ifdef CONFIG_64BIT
60#define TLBMISS_HANDLER_SETUP() \
61 write_c0_context((unsigned long) smp_processor_id() << 26); \
62 back_to_back_c0_hazard(); \
63 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
64#endif
65#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 55#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
66#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 56#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
67 57
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 5e6cd0947393..7bba9da110af 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -81,7 +81,6 @@ static inline long regs_return_value(struct pt_regs *regs)
81 81
82#define instruction_pointer(regs) ((regs)->cp0_epc) 82#define instruction_pointer(regs) ((regs)->cp0_epc)
83#define profile_pc(regs) instruction_pointer(regs) 83#define profile_pc(regs) instruction_pointer(regs)
84#define user_stack_pointer(r) ((r)->regs[29])
85 84
86extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); 85extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
87extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); 86extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
@@ -100,4 +99,17 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
100 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \ 99 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \
101}) 100})
102 101
102/* Helpers for working with the user stack pointer */
103
104static inline unsigned long user_stack_pointer(struct pt_regs *regs)
105{
106 return regs->regs[29];
107}
108
109static inline void user_stack_pointer_set(struct pt_regs *regs,
110 unsigned long val)
111{
112 regs->regs[29] = val;
113}
114
103#endif /* _ASM_PTRACE_H */ 115#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index a0b2650516ac..34d1a1917125 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -15,6 +15,7 @@
15#include <asm/asm.h> 15#include <asm/asm.h>
16#include <asm/cacheops.h> 16#include <asm/cacheops.h>
17#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/cpu-type.h>
18#include <asm/mipsmtregs.h> 19#include <asm/mipsmtregs.h>
19 20
20/* 21/*
@@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr)
162static inline void flush_icache_line(unsigned long addr) 163static inline void flush_icache_line(unsigned long addr)
163{ 164{
164 __iflush_prologue 165 __iflush_prologue
165 cache_op(Hit_Invalidate_I, addr); 166 switch (boot_cpu_type()) {
167 case CPU_LOONGSON2:
168 cache_op(Hit_Invalidate_I_Loongson23, addr);
169 break;
170
171 default:
172 cache_op(Hit_Invalidate_I, addr);
173 break;
174 }
166 __iflush_epilogue 175 __iflush_epilogue
167} 176}
168 177
@@ -208,7 +217,15 @@ static inline void flush_scache_line(unsigned long addr)
208 */ 217 */
209static inline void protected_flush_icache_line(unsigned long addr) 218static inline void protected_flush_icache_line(unsigned long addr)
210{ 219{
211 protected_cache_op(Hit_Invalidate_I, addr); 220 switch (boot_cpu_type()) {
221 case CPU_LOONGSON2:
222 protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
223 break;
224
225 default:
226 protected_cache_op(Hit_Invalidate_I, addr);
227 break;
228 }
212} 229}
213 230
214/* 231/*
@@ -412,8 +429,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64
412__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) 429__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
413 430
414/* build blast_xxx_range, protected_blast_xxx_range */ 431/* build blast_xxx_range, protected_blast_xxx_range */
415#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 432#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
416static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 433static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
417 unsigned long end) \ 434 unsigned long end) \
418{ \ 435{ \
419 unsigned long lsize = cpu_##desc##_line_size(); \ 436 unsigned long lsize = cpu_##desc##_line_size(); \
@@ -432,13 +449,15 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
432 __##pfx##flush_epilogue \ 449 __##pfx##flush_epilogue \
433} 450}
434 451
435__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) 452__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
436__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) 453__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
437__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) 454__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
438__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) 455__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
439__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) 456 protected_, loongson23_)
457__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
458__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
440/* blast_inv_dcache_range */ 459/* blast_inv_dcache_range */
441__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) 460__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
442__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) 461__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
443 462
444#endif /* _ASM_R4KCACHE_H */ 463#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e26589ef36ee..d7bfdeba9e84 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -5,6 +5,14 @@
5 5
6extern void setup_early_printk(void); 6extern void setup_early_printk(void);
7 7
8#ifdef CONFIG_EARLY_PRINTK_8250
9extern void setup_8250_early_printk_port(unsigned long base,
10 unsigned int reg_shift, unsigned int timeout);
11#else
12static inline void setup_8250_early_printk_port(unsigned long base,
13 unsigned int reg_shift, unsigned int timeout) {}
14#endif
15
8extern void set_handler(unsigned long offset, void *addr, unsigned long len); 16extern void set_handler(unsigned long offset, void *addr, unsigned long len);
9extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); 17extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
10 18
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 23fc95e65673..4857e2c8df5a 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -17,6 +17,7 @@
17#include <asm/asmmacro.h> 17#include <asm/asmmacro.h>
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h>
20 21
21/* 22/*
22 * For SMTC kernel, global IE should be left set, and interrupts 23 * For SMTC kernel, global IE should be left set, and interrupts
@@ -93,21 +94,8 @@
93 .endm 94 .endm
94 95
95#ifdef CONFIG_SMP 96#ifdef CONFIG_SMP
96#ifdef CONFIG_MIPS_MT_SMTC
97#define PTEBASE_SHIFT 19 /* TCBIND */
98#define CPU_ID_REG CP0_TCBIND
99#define CPU_ID_MFC0 mfc0
100#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
101#define PTEBASE_SHIFT 48 /* XCONTEXT */
102#define CPU_ID_REG CP0_XCONTEXT
103#define CPU_ID_MFC0 MFC0
104#else
105#define PTEBASE_SHIFT 23 /* CONTEXT */
106#define CPU_ID_REG CP0_CONTEXT
107#define CPU_ID_MFC0 MFC0
108#endif
109 .macro get_saved_sp /* SMP variation */ 97 .macro get_saved_sp /* SMP variation */
110 CPU_ID_MFC0 k0, CPU_ID_REG 98 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
111#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 99#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
112 lui k1, %hi(kernelsp) 100 lui k1, %hi(kernelsp)
113#else 101#else
@@ -117,17 +105,17 @@
117 daddiu k1, %hi(kernelsp) 105 daddiu k1, %hi(kernelsp)
118 dsll k1, 16 106 dsll k1, 16
119#endif 107#endif
120 LONG_SRL k0, PTEBASE_SHIFT 108 LONG_SRL k0, SMP_CPUID_PTRSHIFT
121 LONG_ADDU k1, k0 109 LONG_ADDU k1, k0
122 LONG_L k1, %lo(kernelsp)(k1) 110 LONG_L k1, %lo(kernelsp)(k1)
123 .endm 111 .endm
124 112
125 .macro set_saved_sp stackp temp temp2 113 .macro set_saved_sp stackp temp temp2
126 CPU_ID_MFC0 \temp, CPU_ID_REG 114 ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
127 LONG_SRL \temp, PTEBASE_SHIFT 115 LONG_SRL \temp, SMP_CPUID_PTRSHIFT
128 LONG_S \stackp, kernelsp(\temp) 116 LONG_S \stackp, kernelsp(\temp)
129 .endm 117 .endm
130#else 118#else /* !CONFIG_SMP */
131 .macro get_saved_sp /* Uniprocessor variation */ 119 .macro get_saved_sp /* Uniprocessor variation */
132#ifdef CONFIG_CPU_JUMP_WORKAROUNDS 120#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
133 /* 121 /*
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
new file mode 100644
index 000000000000..81c89132c59d
--- /dev/null
+++ b/arch/mips/include/asm/syscall.h
@@ -0,0 +1,116 @@
1/*
2 * Access to user system call parameters and results
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * See asm-generic/syscall.h for descriptions of what we must do here.
9 *
10 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
11 */
12
13#ifndef __ASM_MIPS_SYSCALL_H
14#define __ASM_MIPS_SYSCALL_H
15
16#include <linux/audit.h>
17#include <linux/elf-em.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/uaccess.h>
21#include <asm/ptrace.h>
22
23static inline long syscall_get_nr(struct task_struct *task,
24 struct pt_regs *regs)
25{
26 return regs->regs[2];
27}
28
29static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
30 struct task_struct *task, struct pt_regs *regs, unsigned int n)
31{
32 unsigned long usp = regs->regs[29];
33
34 switch (n) {
35 case 0: case 1: case 2: case 3:
36 *arg = regs->regs[4 + n];
37
38 return 0;
39
40#ifdef CONFIG_32BIT
41 case 4: case 5: case 6: case 7:
42 return get_user(*arg, (int *)usp + 4 * n);
43#endif
44
45#ifdef CONFIG_64BIT
46 case 4: case 5: case 6: case 7:
47#ifdef CONFIG_MIPS32_O32
48 if (test_thread_flag(TIF_32BIT_REGS))
49 return get_user(*arg, (int *)usp + 4 * n);
50 else
51#endif
52 *arg = regs->regs[4 + n];
53
54 return 0;
55#endif
56
57 default:
58 BUG();
59 }
60}
61
62static inline long syscall_get_return_value(struct task_struct *task,
63 struct pt_regs *regs)
64{
65 return regs->regs[2];
66}
67
68static inline void syscall_set_return_value(struct task_struct *task,
69 struct pt_regs *regs,
70 int error, long val)
71{
72 if (error) {
73 regs->regs[2] = -error;
74 regs->regs[7] = -1;
75 } else {
76 regs->regs[2] = val;
77 regs->regs[7] = 0;
78 }
79}
80
81static inline void syscall_get_arguments(struct task_struct *task,
82 struct pt_regs *regs,
83 unsigned int i, unsigned int n,
84 unsigned long *args)
85{
86 unsigned long arg;
87 int ret;
88
89 while (n--)
90 ret |= mips_get_syscall_arg(&arg, task, regs, i++);
91
92 /*
93 * No way to communicate an error because this is a void function.
94 */
95#if 0
96 return ret;
97#endif
98}
99
100extern const unsigned long sys_call_table[];
101extern const unsigned long sys32_call_table[];
102extern const unsigned long sysn32_call_table[];
103
104static inline int __syscall_get_arch(void)
105{
106 int arch = EM_MIPS;
107#ifdef CONFIG_64BIT
108 arch |= __AUDIT_ARCH_64BIT;
109#endif
110#if defined(__LITTLE_ENDIAN)
111 arch |= __AUDIT_ARCH_LE;
112#endif
113 return arch;
114}
115
116#endif /* __ASM_MIPS_SYSCALL_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 61215a34acc6..f9b24bfbdbae 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void)
116#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 116#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
117#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 117#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
118#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 118#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
119#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
119#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 120#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
120 121
121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 122#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -132,21 +133,54 @@ static inline struct thread_info *current_thread_info(void)
132#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 133#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 134#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 135#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
136#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
135 137
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 138#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
137 _TIF_SYSCALL_AUDIT) 139 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
138 140
139/* work to do in syscall_trace_leave() */ 141/* work to do in syscall_trace_leave() */
140#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 142#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
141 _TIF_SYSCALL_AUDIT) 143 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
142 144
143/* work to do on interrupt/exception return */ 145/* work to do on interrupt/exception return */
144#define _TIF_WORK_MASK \ 146#define _TIF_WORK_MASK \
145 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) 147 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
146/* work to do on any return to u-space */ 148/* work to do on any return to u-space */
147#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ 149#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
148 _TIF_WORK_SYSCALL_EXIT) 150 _TIF_WORK_SYSCALL_EXIT | \
151 _TIF_SYSCALL_TRACEPOINT)
149 152
150#endif /* __KERNEL__ */ 153/*
154 * We stash processor id into a COP0 register to retrieve it fast
155 * at kernel exception entry.
156 */
157#if defined(CONFIG_MIPS_MT_SMTC)
158#define SMP_CPUID_REG 2, 2 /* TCBIND */
159#define ASM_SMP_CPUID_REG $2, 2
160#define SMP_CPUID_PTRSHIFT 19
161#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
162#define SMP_CPUID_REG 20, 0 /* XCONTEXT */
163#define ASM_SMP_CPUID_REG $20
164#define SMP_CPUID_PTRSHIFT 48
165#else
166#define SMP_CPUID_REG 4, 0 /* CONTEXT */
167#define ASM_SMP_CPUID_REG $4
168#define SMP_CPUID_PTRSHIFT 23
169#endif
151 170
171#ifdef CONFIG_64BIT
172#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3)
173#else
174#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2)
175#endif
176
177#ifdef CONFIG_MIPS_MT_SMTC
178#define ASM_CPUID_MFC0 mfc0
179#define UASM_i_CPUID_MFC0 uasm_i_mfc0
180#else
181#define ASM_CPUID_MFC0 MFC0
182#define UASM_i_CPUID_MFC0 UASM_i_MFC0
183#endif
184
185#endif /* __KERNEL__ */
152#endif /* _ASM_THREAD_INFO_H */ 186#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 2d7b9df4542d..24f534a7fbc3 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
75 75
76static inline int init_mips_clocksource(void) 76static inline int init_mips_clocksource(void)
77{ 77{
78#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC) 78#ifdef CONFIG_CSRC_R4K
79 return init_r4k_clocksource(); 79 return init_r4k_clocksource();
80#else 80#else
81 return 0; 81 return 0;
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 63c9c886173a..4d3b92886665 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -14,6 +14,13 @@
14 14
15#include <uapi/asm/unistd.h> 15#include <uapi/asm/unistd.h>
16 16
17#ifdef CONFIG_MIPS32_N32
18#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls)
19#elif defined(CONFIG_64BIT)
20#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls)
21#else
22#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls)
23#endif
17 24
18#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
19 26
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 88e292b7719e..e81174432bab 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -33,6 +33,8 @@ struct siginfo;
33#error _MIPS_SZLONG neither 32 nor 64 33#error _MIPS_SZLONG neither 32 nor 64
34#endif 34#endif
35 35
36#define __ARCH_SIGSYS
37
36#include <asm-generic/siginfo.h> 38#include <asm-generic/siginfo.h>
37 39
38typedef struct siginfo { 40typedef struct siginfo {
@@ -97,6 +99,13 @@ typedef struct siginfo {
97 __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ 99 __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
98 int _fd; 100 int _fd;
99 } _sigpoll; 101 } _sigpoll;
102
103 /* SIGSYS */
104 struct {
105 void __user *_call_addr; /* calling user insn */
106 int _syscall; /* triggering system call number */
107 unsigned int _arch; /* AUDIT_ARCH_* of syscall */
108 } _sigsys;
100 } _sifields; 109 } _sifields;
101} siginfo_t; 110} siginfo_t;
102 111
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 423d871a946b..1c1b71752c84 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
26obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 26obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
27obj-$(CONFIG_CSRC_GIC) += csrc-gic.o 27obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
28obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 28obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
29obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
30obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 29obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
31obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 30obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
32obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 31obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@@ -35,6 +34,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o
35obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 34obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
36obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o 35obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
37 36
37obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
38obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o 38obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
39 39
40obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o 40obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
@@ -84,6 +84,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o
84obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o 84obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o
85obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 85obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
86obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 86obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
87obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o
87obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o 88obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
88obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o 89obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
89 90
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5465dc183e5a..c814287bdf5d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -376,13 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
376 __cpu_name[cpu] = "R4000PC"; 376 __cpu_name[cpu] = "R4000PC";
377 } 377 }
378 } else { 378 } else {
379 int cca = read_c0_config() & CONF_CM_CMASK;
380 int mc;
381
382 /*
383 * SC and MC versions can't be reliably told apart,
384 * but only the latter support coherent caching
385 * modes so assume the firmware has set the KSEG0
386 * coherency attribute reasonably (if uncached, we
387 * assume SC).
388 */
389 switch (cca) {
390 case CONF_CM_CACHABLE_CE:
391 case CONF_CM_CACHABLE_COW:
392 case CONF_CM_CACHABLE_CUW:
393 mc = 1;
394 break;
395 default:
396 mc = 0;
397 break;
398 }
379 if ((c->processor_id & PRID_REV_MASK) >= 399 if ((c->processor_id & PRID_REV_MASK) >=
380 PRID_REV_R4400) { 400 PRID_REV_R4400) {
381 c->cputype = CPU_R4400SC; 401 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
382 __cpu_name[cpu] = "R4400SC"; 402 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
383 } else { 403 } else {
384 c->cputype = CPU_R4000SC; 404 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
385 __cpu_name[cpu] = "R4000SC"; 405 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
386 } 406 }
387 } 407 }
388 408
@@ -1079,8 +1099,8 @@ void cpu_report(void)
1079{ 1099{
1080 struct cpuinfo_mips *c = &current_cpu_data; 1100 struct cpuinfo_mips *c = &current_cpu_data;
1081 1101
1082 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1102 pr_info("CPU%d revision is: %08x (%s)\n",
1083 c->processor_id, cpu_name_string()); 1103 smp_processor_id(), c->processor_id, cpu_name_string());
1084 if (c->options & MIPS_CPU_FPU) 1104 if (c->options & MIPS_CPU_FPU)
1085 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1105 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1086} 1106}
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
deleted file mode 100644
index abd99ea911ae..000000000000
--- a/arch/mips/kernel/csrc-powertv.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Copyright (C) 2008 Scientific-Atlanta, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18/*
19 * The file comes from kernel/csrc-r4k.c
20 */
21#include <linux/clocksource.h>
22#include <linux/init.h>
23
24#include <asm/time.h> /* Not included in linux/time.h */
25
26#include <asm/mach-powertv/asic_regs.h>
27#include "powertv-clock.h"
28
29/* MIPS PLL Register Definitions */
30#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
31#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
32#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
33
34/*
35 * returns: Clock frequency in kHz
36 */
37unsigned int __init mips_get_pll_freq(void)
38{
39 unsigned int pll_reg, m, n, p;
40 unsigned int fin = 54000; /* Base frequency in kHz */
41 unsigned int fout;
42
43 /* Read PLL register setting */
44 pll_reg = asic_read(mips_pll_setup);
45 m = PLL_GET_M(pll_reg);
46 n = PLL_GET_N(pll_reg);
47 p = PLL_GET_P(pll_reg);
48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49
50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51 fout = ((2 * n * fin) / (m * (0x01 << p)));
52
53 pr_info("MIPS Clock Freq=%d kHz\n", fout);
54
55 return fout;
56}
57
58static cycle_t c0_hpt_read(struct clocksource *cs)
59{
60 return read_c0_count();
61}
62
63static struct clocksource clocksource_mips = {
64 .name = "powertv-counter",
65 .read = c0_hpt_read,
66 .mask = CLOCKSOURCE_MASK(32),
67 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
68};
69
70static void __init powertv_c0_hpt_clocksource_init(void)
71{
72 unsigned int pll_freq = mips_get_pll_freq();
73
74 pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75 (pll_freq % 1000) * 100 / 1000);
76
77 mips_hpt_frequency = pll_freq / 2 * 1000;
78
79 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80
81 clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
82}
83
84/**
85 * struct tim_c - free running counter
86 * @hi: High 16 bits of the counter
87 * @lo: Low 32 bits of the counter
88 *
89 * Lays out the structure of the free running counter in memory. This counter
90 * increments at a rate of 27 MHz/8 on all platforms.
91 */
92struct tim_c {
93 unsigned int hi;
94 unsigned int lo;
95};
96
97static struct tim_c *tim_c;
98
99static cycle_t tim_c_read(struct clocksource *cs)
100{
101 unsigned int hi;
102 unsigned int next_hi;
103 unsigned int lo;
104
105 hi = readl(&tim_c->hi);
106
107 for (;;) {
108 lo = readl(&tim_c->lo);
109 next_hi = readl(&tim_c->hi);
110 if (next_hi == hi)
111 break;
112 hi = next_hi;
113 }
114
115pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
116 return ((u64) hi << 32) | lo;
117}
118
119#define TIM_C_SIZE 48 /* # bits in the timer */
120
121static struct clocksource clocksource_tim_c = {
122 .name = "powertv-tim_c",
123 .read = tim_c_read,
124 .mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
125 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
126};
127
128/**
129 * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
130 *
131 * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
132 * 1 / (27,000,000/8) seconds.
133 */
134static void __init powertv_tim_c_clocksource_init(void)
135{
136 const unsigned long counts_per_second = 27000000 / 8;
137
138 clocksource_tim_c.rating = 200;
139
140 clocksource_register_hz(&clocksource_tim_c, counts_per_second);
141 tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
142}
143
144/**
145 powertv_clocksource_init - initialize all clocksources
146 */
147void __init powertv_clocksource_init(void)
148{
149 powertv_c0_hpt_clocksource_init();
150 powertv_tim_c_clocksource_init();
151}
diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c
new file mode 100644
index 000000000000..83cea3767556
--- /dev/null
+++ b/arch/mips/kernel/early_printk_8250.c
@@ -0,0 +1,66 @@
1/*
2 * 8250/16550-type serial ports prom_putchar()
3 *
4 * Copyright (C) 2010 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/io.h>
21#include <linux/serial_core.h>
22#include <linux/serial_reg.h>
23
24static void __iomem *serial8250_base;
25static unsigned int serial8250_reg_shift;
26static unsigned int serial8250_tx_timeout;
27
28void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift,
29 unsigned int timeout)
30{
31 serial8250_base = (void __iomem *)base;
32 serial8250_reg_shift = reg_shift;
33 serial8250_tx_timeout = timeout;
34}
35
36static inline u8 serial_in(int offset)
37{
38 return readb(serial8250_base + (offset << serial8250_reg_shift));
39}
40
41static inline void serial_out(int offset, char value)
42{
43 writeb(value, serial8250_base + (offset << serial8250_reg_shift));
44}
45
46void prom_putchar(char c)
47{
48 unsigned int timeout;
49 int status, bits;
50
51 if (!serial8250_base)
52 return;
53
54 timeout = serial8250_tx_timeout;
55 bits = UART_LSR_TEMT | UART_LSR_THRE;
56
57 do {
58 status = serial_in(UART_LSR);
59
60 if (--timeout == 0)
61 break;
62 } while ((status & bits) != bits);
63
64 if (timeout)
65 serial_out(UART_TX, c);
66}
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index dba90ec0dc38..185ba258361b 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -11,11 +11,14 @@
11#include <linux/uaccess.h> 11#include <linux/uaccess.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/ftrace.h> 13#include <linux/ftrace.h>
14#include <linux/syscalls.h>
14 15
15#include <asm/asm.h> 16#include <asm/asm.h>
16#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
17#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/syscall.h>
18#include <asm/uasm.h> 20#include <asm/uasm.h>
21#include <asm/unistd.h>
19 22
20#include <asm-generic/sections.h> 23#include <asm-generic/sections.h>
21 24
@@ -364,3 +367,33 @@ out:
364 WARN_ON(1); 367 WARN_ON(1);
365} 368}
366#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ 369#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
370
371#ifdef CONFIG_FTRACE_SYSCALLS
372
373#ifdef CONFIG_32BIT
374unsigned long __init arch_syscall_addr(int nr)
375{
376 return (unsigned long)sys_call_table[nr - __NR_O32_Linux];
377}
378#endif
379
380#ifdef CONFIG_64BIT
381
382unsigned long __init arch_syscall_addr(int nr)
383{
384#ifdef CONFIG_MIPS32_N32
385 if (nr >= __NR_N32_Linux && nr <= __NR_N32_Linux + __NR_N32_Linux_syscalls)
386 return (unsigned long)sysn32_call_table[nr - __NR_N32_Linux];
387#endif
388 if (nr >= __NR_64_Linux && nr <= __NR_64_Linux + __NR_64_Linux_syscalls)
389 return (unsigned long)sys_call_table[nr - __NR_64_Linux];
390#ifdef CONFIG_MIPS32_O32
391 if (nr >= __NR_O32_Linux && nr <= __NR_O32_Linux + __NR_O32_Linux_syscalls)
392 return (unsigned long)sys32_call_table[nr - __NR_O32_Linux];
393#endif
394
395 return (unsigned long) &sys_ni_syscall;
396}
397#endif
398
399#endif /* CONFIG_FTRACE_SYSCALLS */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 31fa856829cb..47d7583cd67f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -374,12 +374,20 @@ NESTED(except_vec_nmi, 0, sp)
374NESTED(nmi_handler, PT_SIZE, sp) 374NESTED(nmi_handler, PT_SIZE, sp)
375 .set push 375 .set push
376 .set noat 376 .set noat
377 /*
378 * Clear ERL - restore segment mapping
379 * Clear BEV - required for page fault exception handler to work
380 */
381 mfc0 k0, CP0_STATUS
382 ori k0, k0, ST0_EXL
383 li k1, ~(ST0_BEV | ST0_ERL)
384 and k0, k0, k1
385 mtc0 k0, CP0_STATUS
386 _ehb
377 SAVE_ALL 387 SAVE_ALL
378 move a0, sp 388 move a0, sp
379 jal nmi_exception_handler 389 jal nmi_exception_handler
380 RESTORE_ALL 390 /* nmi_exception_handler never returns */
381 .set mips3
382 eret
383 .set pop 391 .set pop
384 END(nmi_handler) 392 END(nmi_handler)
385 393
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 72ef2d25cbf2..e498f2b3646a 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -150,7 +150,7 @@ int __init mips_cpu_intc_init(struct device_node *of_node,
150 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, 150 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
151 &mips_cpu_intc_irq_domain_ops, NULL); 151 &mips_cpu_intc_irq_domain_ops, NULL);
152 if (!domain) 152 if (!domain)
153 panic("Failed to add irqdomain for MIPS CPU\n"); 153 panic("Failed to add irqdomain for MIPS CPU");
154 154
155 return 0; 155 return 0;
156} 156}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 977a623d9253..2a52568dbcd6 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -23,6 +23,7 @@
23#include <linux/moduleloader.h> 23#include <linux/moduleloader.h>
24#include <linux/elf.h> 24#include <linux/elf.h>
25#include <linux/mm.h> 25#include <linux/mm.h>
26#include <linux/numa.h>
26#include <linux/vmalloc.h> 27#include <linux/vmalloc.h>
27#include <linux/slab.h> 28#include <linux/slab.h>
28#include <linux/fs.h> 29#include <linux/fs.h>
@@ -46,7 +47,7 @@ static DEFINE_SPINLOCK(dbe_lock);
46void *module_alloc(unsigned long size) 47void *module_alloc(unsigned long size)
47{ 48{
48 return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, 49 return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
49 GFP_KERNEL, PAGE_KERNEL, -1, 50 GFP_KERNEL, PAGE_KERNEL, NUMA_NO_NODE,
50 __builtin_return_address(0)); 51 __builtin_return_address(0));
51} 52}
52#endif 53#endif
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 8ae1ebef8b71..b52e1d2b33e0 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -16,16 +16,20 @@
16 */ 16 */
17#include <linux/compiler.h> 17#include <linux/compiler.h>
18#include <linux/context_tracking.h> 18#include <linux/context_tracking.h>
19#include <linux/elf.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/sched.h> 21#include <linux/sched.h>
21#include <linux/mm.h> 22#include <linux/mm.h>
22#include <linux/errno.h> 23#include <linux/errno.h>
23#include <linux/ptrace.h> 24#include <linux/ptrace.h>
25#include <linux/regset.h>
24#include <linux/smp.h> 26#include <linux/smp.h>
25#include <linux/user.h> 27#include <linux/user.h>
26#include <linux/security.h> 28#include <linux/security.h>
29#include <linux/tracehook.h>
27#include <linux/audit.h> 30#include <linux/audit.h>
28#include <linux/seccomp.h> 31#include <linux/seccomp.h>
32#include <linux/ftrace.h>
29 33
30#include <asm/byteorder.h> 34#include <asm/byteorder.h>
31#include <asm/cpu.h> 35#include <asm/cpu.h>
@@ -35,10 +39,14 @@
35#include <asm/mipsmtregs.h> 39#include <asm/mipsmtregs.h>
36#include <asm/pgtable.h> 40#include <asm/pgtable.h>
37#include <asm/page.h> 41#include <asm/page.h>
42#include <asm/syscall.h>
38#include <asm/uaccess.h> 43#include <asm/uaccess.h>
39#include <asm/bootinfo.h> 44#include <asm/bootinfo.h>
40#include <asm/reg.h> 45#include <asm/reg.h>
41 46
47#define CREATE_TRACE_POINTS
48#include <trace/events/syscalls.h>
49
42/* 50/*
43 * Called by kernel/ptrace.c when detaching.. 51 * Called by kernel/ptrace.c when detaching..
44 * 52 *
@@ -255,6 +263,133 @@ int ptrace_set_watch_regs(struct task_struct *child,
255 return 0; 263 return 0;
256} 264}
257 265
266/* regset get/set implementations */
267
268static int gpr_get(struct task_struct *target,
269 const struct user_regset *regset,
270 unsigned int pos, unsigned int count,
271 void *kbuf, void __user *ubuf)
272{
273 struct pt_regs *regs = task_pt_regs(target);
274
275 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
276 regs, 0, sizeof(*regs));
277}
278
279static int gpr_set(struct task_struct *target,
280 const struct user_regset *regset,
281 unsigned int pos, unsigned int count,
282 const void *kbuf, const void __user *ubuf)
283{
284 struct pt_regs newregs;
285 int ret;
286
287 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
288 &newregs,
289 0, sizeof(newregs));
290 if (ret)
291 return ret;
292
293 *task_pt_regs(target) = newregs;
294
295 return 0;
296}
297
298static int fpr_get(struct task_struct *target,
299 const struct user_regset *regset,
300 unsigned int pos, unsigned int count,
301 void *kbuf, void __user *ubuf)
302{
303 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
304 &target->thread.fpu,
305 0, sizeof(elf_fpregset_t));
306 /* XXX fcr31 */
307}
308
309static int fpr_set(struct task_struct *target,
310 const struct user_regset *regset,
311 unsigned int pos, unsigned int count,
312 const void *kbuf, const void __user *ubuf)
313{
314 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
315 &target->thread.fpu,
316 0, sizeof(elf_fpregset_t));
317 /* XXX fcr31 */
318}
319
320enum mips_regset {
321 REGSET_GPR,
322 REGSET_FPR,
323};
324
325static const struct user_regset mips_regsets[] = {
326 [REGSET_GPR] = {
327 .core_note_type = NT_PRSTATUS,
328 .n = ELF_NGREG,
329 .size = sizeof(unsigned int),
330 .align = sizeof(unsigned int),
331 .get = gpr_get,
332 .set = gpr_set,
333 },
334 [REGSET_FPR] = {
335 .core_note_type = NT_PRFPREG,
336 .n = ELF_NFPREG,
337 .size = sizeof(elf_fpreg_t),
338 .align = sizeof(elf_fpreg_t),
339 .get = fpr_get,
340 .set = fpr_set,
341 },
342};
343
344static const struct user_regset_view user_mips_view = {
345 .name = "mips",
346 .e_machine = ELF_ARCH,
347 .ei_osabi = ELF_OSABI,
348 .regsets = mips_regsets,
349 .n = ARRAY_SIZE(mips_regsets),
350};
351
352static const struct user_regset mips64_regsets[] = {
353 [REGSET_GPR] = {
354 .core_note_type = NT_PRSTATUS,
355 .n = ELF_NGREG,
356 .size = sizeof(unsigned long),
357 .align = sizeof(unsigned long),
358 .get = gpr_get,
359 .set = gpr_set,
360 },
361 [REGSET_FPR] = {
362 .core_note_type = NT_PRFPREG,
363 .n = ELF_NFPREG,
364 .size = sizeof(elf_fpreg_t),
365 .align = sizeof(elf_fpreg_t),
366 .get = fpr_get,
367 .set = fpr_set,
368 },
369};
370
371static const struct user_regset_view user_mips64_view = {
372 .name = "mips",
373 .e_machine = ELF_ARCH,
374 .ei_osabi = ELF_OSABI,
375 .regsets = mips64_regsets,
376 .n = ARRAY_SIZE(mips_regsets),
377};
378
379const struct user_regset_view *task_user_regset_view(struct task_struct *task)
380{
381#ifdef CONFIG_32BIT
382 return &user_mips_view;
383#endif
384
385#ifdef CONFIG_MIPS32_O32
386 if (test_thread_flag(TIF_32BIT_REGS))
387 return &user_mips_view;
388#endif
389
390 return &user_mips64_view;
391}
392
258long arch_ptrace(struct task_struct *child, long request, 393long arch_ptrace(struct task_struct *child, long request,
259 unsigned long addr, unsigned long data) 394 unsigned long addr, unsigned long data)
260{ 395{
@@ -517,52 +652,27 @@ long arch_ptrace(struct task_struct *child, long request,
517 return ret; 652 return ret;
518} 653}
519 654
520static inline int audit_arch(void)
521{
522 int arch = EM_MIPS;
523#ifdef CONFIG_64BIT
524 arch |= __AUDIT_ARCH_64BIT;
525#endif
526#if defined(__LITTLE_ENDIAN)
527 arch |= __AUDIT_ARCH_LE;
528#endif
529 return arch;
530}
531
532/* 655/*
533 * Notification of system call entry/exit 656 * Notification of system call entry/exit
534 * - triggered by current->work.syscall_trace 657 * - triggered by current->work.syscall_trace
535 */ 658 */
536asmlinkage void syscall_trace_enter(struct pt_regs *regs) 659asmlinkage void syscall_trace_enter(struct pt_regs *regs)
537{ 660{
661 long ret = 0;
538 user_exit(); 662 user_exit();
539 663
540 /* do the secure computing check first */ 664 /* do the secure computing check first */
541 secure_computing_strict(regs->regs[2]); 665 secure_computing_strict(regs->regs[2]);
542 666
543 if (!(current->ptrace & PT_PTRACED)) 667 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
544 goto out; 668 tracehook_report_syscall_entry(regs))
545 669 ret = -1;
546 if (!test_thread_flag(TIF_SYSCALL_TRACE))
547 goto out;
548 670
549 /* The 0x80 provides a way for the tracing parent to distinguish 671 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
550 between a syscall stop and SIGTRAP delivery */ 672 trace_sys_enter(regs, regs->regs[2]);
551 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
552 0x80 : 0));
553
554 /*
555 * this isn't the same as continuing with a signal, but it will do
556 * for normal use. strace only continues with a signal if the
557 * stopping signal is not SIGTRAP. -brl
558 */
559 if (current->exit_code) {
560 send_sig(current->exit_code, current, 1);
561 current->exit_code = 0;
562 }
563 673
564out: 674 audit_syscall_entry(__syscall_get_arch(),
565 audit_syscall_entry(audit_arch(), regs->regs[2], 675 regs->regs[2],
566 regs->regs[4], regs->regs[5], 676 regs->regs[4], regs->regs[5],
567 regs->regs[6], regs->regs[7]); 677 regs->regs[6], regs->regs[7]);
568} 678}
@@ -582,26 +692,11 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
582 692
583 audit_syscall_exit(regs); 693 audit_syscall_exit(regs);
584 694
585 if (!(current->ptrace & PT_PTRACED)) 695 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
586 return; 696 trace_sys_exit(regs, regs->regs[2]);
587
588 if (!test_thread_flag(TIF_SYSCALL_TRACE))
589 return;
590
591 /* The 0x80 provides a way for the tracing parent to distinguish
592 between a syscall stop and SIGTRAP delivery */
593 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
594 0x80 : 0));
595 697
596 /* 698 if (test_thread_flag(TIF_SYSCALL_TRACE))
597 * this isn't the same as continuing with a signal, but it will do 699 tracehook_report_syscall_exit(regs, 0);
598 * for normal use. strace only continues with a signal if the
599 * stopping signal is not SIGTRAP. -brl
600 */
601 if (current->exit_code) {
602 send_sig(current->exit_code, current, 1);
603 current->exit_code = 0;
604 }
605 700
606 user_enter(); 701 user_enter();
607} 702}
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index e774bb1088b5..e8e541b40d86 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -40,17 +40,58 @@ NESTED(handle_sys, PT_SIZE, sp)
40 sw t1, PT_EPC(sp) 40 sw t1, PT_EPC(sp)
41 beqz t0, illegal_syscall 41 beqz t0, illegal_syscall
42 42
43 sll t0, v0, 3 43 sll t0, v0, 2
44 la t1, sys_call_table 44 la t1, sys_call_table
45 addu t1, t0 45 addu t1, t0
46 lw t2, (t1) # syscall routine 46 lw t2, (t1) # syscall routine
47 lw t3, 4(t1) # >= 0 if we need stack arguments
48 beqz t2, illegal_syscall 47 beqz t2, illegal_syscall
49 48
50 sw a3, PT_R26(sp) # save a3 for syscall restarting 49 sw a3, PT_R26(sp) # save a3 for syscall restarting
51 bgez t3, stackargs
52 50
53stack_done: 51 /*
52 * More than four arguments. Try to deal with it by copying the
53 * stack arguments from the user stack to the kernel stack.
54 * This Sucks (TM).
55 */
56 lw t0, PT_R29(sp) # get old user stack pointer
57
58 /*
59 * We intentionally keep the kernel stack a little below the top of
60 * userspace so we don't have to do a slower byte accurate check here.
61 */
62 lw t5, TI_ADDR_LIMIT($28)
63 addu t4, t0, 32
64 and t5, t4
65 bltz t5, bad_stack # -> sp is bad
66
67 /*
68 * Ok, copy the args from the luser stack to the kernel stack.
69 * t3 is the precomputed number of instruction bytes needed to
70 * load or store arguments 6-8.
71 */
72
73 .set push
74 .set noreorder
75 .set nomacro
76
771: lw t5, 16(t0) # argument #5 from usp
784: lw t6, 20(t0) # argument #6 from usp
793: lw t7, 24(t0) # argument #7 from usp
802: lw t8, 28(t0) # argument #8 from usp
81
82 sw t5, 16(sp) # argument #5 to ksp
83 sw t6, 20(sp) # argument #6 to ksp
84 sw t7, 24(sp) # argument #7 to ksp
85 sw t8, 28(sp) # argument #8 to ksp
86 .set pop
87
88 .section __ex_table,"a"
89 PTR 1b,bad_stack
90 PTR 2b,bad_stack
91 PTR 3b,bad_stack
92 PTR 4b,bad_stack
93 .previous
94
54 lw t0, TI_FLAGS($28) # syscall tracing enabled? 95 lw t0, TI_FLAGS($28) # syscall tracing enabled?
55 li t1, _TIF_WORK_SYSCALL_ENTRY 96 li t1, _TIF_WORK_SYSCALL_ENTRY
56 and t0, t1 97 and t0, t1
@@ -102,66 +143,6 @@ syscall_trace_entry:
102/* ------------------------------------------------------------------------ */ 143/* ------------------------------------------------------------------------ */
103 144
104 /* 145 /*
105 * More than four arguments. Try to deal with it by copying the
106 * stack arguments from the user stack to the kernel stack.
107 * This Sucks (TM).
108 */
109stackargs:
110 lw t0, PT_R29(sp) # get old user stack pointer
111
112 /*
113 * We intentionally keep the kernel stack a little below the top of
114 * userspace so we don't have to do a slower byte accurate check here.
115 */
116 lw t5, TI_ADDR_LIMIT($28)
117 addu t4, t0, 32
118 and t5, t4
119 bltz t5, bad_stack # -> sp is bad
120
121 /* Ok, copy the args from the luser stack to the kernel stack.
122 * t3 is the precomputed number of instruction bytes needed to
123 * load or store arguments 6-8.
124 */
125
126 la t1, 5f # load up to 3 arguments
127 subu t1, t3
1281: lw t5, 16(t0) # argument #5 from usp
129 .set push
130 .set noreorder
131 .set nomacro
132 jr t1
133 addiu t1, 6f - 5f
134
1352: lw t8, 28(t0) # argument #8 from usp
1363: lw t7, 24(t0) # argument #7 from usp
1374: lw t6, 20(t0) # argument #6 from usp
1385: jr t1
139 sw t5, 16(sp) # argument #5 to ksp
140
141#ifdef CONFIG_CPU_MICROMIPS
142 sw t8, 28(sp) # argument #8 to ksp
143 nop
144 sw t7, 24(sp) # argument #7 to ksp
145 nop
146 sw t6, 20(sp) # argument #6 to ksp
147 nop
148#else
149 sw t8, 28(sp) # argument #8 to ksp
150 sw t7, 24(sp) # argument #7 to ksp
151 sw t6, 20(sp) # argument #6 to ksp
152#endif
1536: j stack_done # go back
154 nop
155 .set pop
156
157 .section __ex_table,"a"
158 PTR 1b,bad_stack
159 PTR 2b,bad_stack
160 PTR 3b,bad_stack
161 PTR 4b,bad_stack
162 .previous
163
164 /*
165 * The stackpointer for a call with more than 4 arguments is bad. 146 * The stackpointer for a call with more than 4 arguments is bad.
166 * We probably should handle this case a bit more drastic. 147 * We probably should handle this case a bit more drastic.
167 */ 148 */
@@ -187,7 +168,7 @@ illegal_syscall:
187 subu t0, a0, __NR_O32_Linux # check syscall number 168 subu t0, a0, __NR_O32_Linux # check syscall number
188 sltiu v0, t0, __NR_O32_Linux_syscalls + 1 169 sltiu v0, t0, __NR_O32_Linux_syscalls + 1
189 beqz t0, einval # do not recurse 170 beqz t0, einval # do not recurse
190 sll t1, t0, 3 171 sll t1, t0, 2
191 beqz v0, einval 172 beqz v0, einval
192 lw t2, sys_call_table(t1) # syscall routine 173 lw t2, sys_call_table(t1) # syscall routine
193 174
@@ -218,260 +199,248 @@ einval: li v0, -ENOSYS
218 jr ra 199 jr ra
219 END(sys_syscall) 200 END(sys_syscall)
220 201
221 .macro fifty ptr, nargs, from=1, to=50 202 .align 2
222 sys \ptr \nargs 203 .type sys_call_table, @object
223 .if \to-\from 204EXPORT(sys_call_table)
224 fifty \ptr,\nargs,"(\from+1)",\to 205 PTR sys_syscall /* 4000 */
225 .endif 206 PTR sys_exit
226 .endm 207 PTR __sys_fork
227 208 PTR sys_read
228 .macro mille ptr, nargs, from=1, to=20 209 PTR sys_write
229 fifty \ptr,\nargs 210 PTR sys_open /* 4005 */
230 .if \to-\from 211 PTR sys_close
231 mille \ptr,\nargs,"(\from+1)",\to 212 PTR sys_waitpid
232 .endif 213 PTR sys_creat
233 .endm 214 PTR sys_link
234 215 PTR sys_unlink /* 4010 */
235 .macro syscalltable 216 PTR sys_execve
236 sys sys_syscall 8 /* 4000 */ 217 PTR sys_chdir
237 sys sys_exit 1 218 PTR sys_time
238 sys __sys_fork 0 219 PTR sys_mknod
239 sys sys_read 3 220 PTR sys_chmod /* 4015 */
240 sys sys_write 3 221 PTR sys_lchown
241 sys sys_open 3 /* 4005 */ 222 PTR sys_ni_syscall
242 sys sys_close 1 223 PTR sys_ni_syscall /* was sys_stat */
243 sys sys_waitpid 3 224 PTR sys_lseek
244 sys sys_creat 2 225 PTR sys_getpid /* 4020 */
245 sys sys_link 2 226 PTR sys_mount
246 sys sys_unlink 1 /* 4010 */ 227 PTR sys_oldumount
247 sys sys_execve 0 228 PTR sys_setuid
248 sys sys_chdir 1 229 PTR sys_getuid
249 sys sys_time 1 230 PTR sys_stime /* 4025 */
250 sys sys_mknod 3 231 PTR sys_ptrace
251 sys sys_chmod 2 /* 4015 */ 232 PTR sys_alarm
252 sys sys_lchown 3 233 PTR sys_ni_syscall /* was sys_fstat */
253 sys sys_ni_syscall 0 234 PTR sys_pause
254 sys sys_ni_syscall 0 /* was sys_stat */ 235 PTR sys_utime /* 4030 */
255 sys sys_lseek 3 236 PTR sys_ni_syscall
256 sys sys_getpid 0 /* 4020 */ 237 PTR sys_ni_syscall
257 sys sys_mount 5 238 PTR sys_access
258 sys sys_oldumount 1 239 PTR sys_nice
259 sys sys_setuid 1 240 PTR sys_ni_syscall /* 4035 */
260 sys sys_getuid 0 241 PTR sys_sync
261 sys sys_stime 1 /* 4025 */ 242 PTR sys_kill
262 sys sys_ptrace 4 243 PTR sys_rename
263 sys sys_alarm 1 244 PTR sys_mkdir
264 sys sys_ni_syscall 0 /* was sys_fstat */ 245 PTR sys_rmdir /* 4040 */
265 sys sys_pause 0 246 PTR sys_dup
266 sys sys_utime 2 /* 4030 */ 247 PTR sysm_pipe
267 sys sys_ni_syscall 0 248 PTR sys_times
268 sys sys_ni_syscall 0 249 PTR sys_ni_syscall
269 sys sys_access 2 250 PTR sys_brk /* 4045 */
270 sys sys_nice 1 251 PTR sys_setgid
271 sys sys_ni_syscall 0 /* 4035 */ 252 PTR sys_getgid
272 sys sys_sync 0 253 PTR sys_ni_syscall /* was signal(2) */
273 sys sys_kill 2 254 PTR sys_geteuid
274 sys sys_rename 2 255 PTR sys_getegid /* 4050 */
275 sys sys_mkdir 2 256 PTR sys_acct
276 sys sys_rmdir 1 /* 4040 */ 257 PTR sys_umount
277 sys sys_dup 1 258 PTR sys_ni_syscall
278 sys sysm_pipe 0 259 PTR sys_ioctl
279 sys sys_times 1 260 PTR sys_fcntl /* 4055 */
280 sys sys_ni_syscall 0 261 PTR sys_ni_syscall
281 sys sys_brk 1 /* 4045 */ 262 PTR sys_setpgid
282 sys sys_setgid 1 263 PTR sys_ni_syscall
283 sys sys_getgid 0 264 PTR sys_olduname
284 sys sys_ni_syscall 0 /* was signal(2) */ 265 PTR sys_umask /* 4060 */
285 sys sys_geteuid 0 266 PTR sys_chroot
286 sys sys_getegid 0 /* 4050 */ 267 PTR sys_ustat
287 sys sys_acct 1 268 PTR sys_dup2
288 sys sys_umount 2 269 PTR sys_getppid
289 sys sys_ni_syscall 0 270 PTR sys_getpgrp /* 4065 */
290 sys sys_ioctl 3 271 PTR sys_setsid
291 sys sys_fcntl 3 /* 4055 */ 272 PTR sys_sigaction
292 sys sys_ni_syscall 2 273 PTR sys_sgetmask
293 sys sys_setpgid 2 274 PTR sys_ssetmask
294 sys sys_ni_syscall 0 275 PTR sys_setreuid /* 4070 */
295 sys sys_olduname 1 276 PTR sys_setregid
296 sys sys_umask 1 /* 4060 */ 277 PTR sys_sigsuspend
297 sys sys_chroot 1 278 PTR sys_sigpending
298 sys sys_ustat 2 279 PTR sys_sethostname
299 sys sys_dup2 2 280 PTR sys_setrlimit /* 4075 */
300 sys sys_getppid 0 281 PTR sys_getrlimit
301 sys sys_getpgrp 0 /* 4065 */ 282 PTR sys_getrusage
302 sys sys_setsid 0 283 PTR sys_gettimeofday
303 sys sys_sigaction 3 284 PTR sys_settimeofday
304 sys sys_sgetmask 0 285 PTR sys_getgroups /* 4080 */
305 sys sys_ssetmask 1 286 PTR sys_setgroups
306 sys sys_setreuid 2 /* 4070 */ 287 PTR sys_ni_syscall /* old_select */
307 sys sys_setregid 2 288 PTR sys_symlink
308 sys sys_sigsuspend 0 289 PTR sys_ni_syscall /* was sys_lstat */
309 sys sys_sigpending 1 290 PTR sys_readlink /* 4085 */
310 sys sys_sethostname 2 291 PTR sys_uselib
311 sys sys_setrlimit 2 /* 4075 */ 292 PTR sys_swapon
312 sys sys_getrlimit 2 293 PTR sys_reboot
313 sys sys_getrusage 2 294 PTR sys_old_readdir
314 sys sys_gettimeofday 2 295 PTR sys_mips_mmap /* 4090 */
315 sys sys_settimeofday 2 296 PTR sys_munmap
316 sys sys_getgroups 2 /* 4080 */ 297 PTR sys_truncate
317 sys sys_setgroups 2 298 PTR sys_ftruncate
318 sys sys_ni_syscall 0 /* old_select */ 299 PTR sys_fchmod
319 sys sys_symlink 2 300 PTR sys_fchown /* 4095 */
320 sys sys_ni_syscall 0 /* was sys_lstat */ 301 PTR sys_getpriority
321 sys sys_readlink 3 /* 4085 */ 302 PTR sys_setpriority
322 sys sys_uselib 1 303 PTR sys_ni_syscall
323 sys sys_swapon 2 304 PTR sys_statfs
324 sys sys_reboot 3 305 PTR sys_fstatfs /* 4100 */
325 sys sys_old_readdir 3 306 PTR sys_ni_syscall /* was ioperm(2) */
326 sys sys_mips_mmap 6 /* 4090 */ 307 PTR sys_socketcall
327 sys sys_munmap 2 308 PTR sys_syslog
328 sys sys_truncate 2 309 PTR sys_setitimer
329 sys sys_ftruncate 2 310 PTR sys_getitimer /* 4105 */
330 sys sys_fchmod 2 311 PTR sys_newstat
331 sys sys_fchown 3 /* 4095 */ 312 PTR sys_newlstat
332 sys sys_getpriority 2 313 PTR sys_newfstat
333 sys sys_setpriority 3 314 PTR sys_uname
334 sys sys_ni_syscall 0 315 PTR sys_ni_syscall /* 4110 was iopl(2) */
335 sys sys_statfs 2 316 PTR sys_vhangup
336 sys sys_fstatfs 2 /* 4100 */ 317 PTR sys_ni_syscall /* was sys_idle() */
337 sys sys_ni_syscall 0 /* was ioperm(2) */ 318 PTR sys_ni_syscall /* was sys_vm86 */
338 sys sys_socketcall 2 319 PTR sys_wait4
339 sys sys_syslog 3 320 PTR sys_swapoff /* 4115 */
340 sys sys_setitimer 3 321 PTR sys_sysinfo
341 sys sys_getitimer 2 /* 4105 */ 322 PTR sys_ipc
342 sys sys_newstat 2 323 PTR sys_fsync
343 sys sys_newlstat 2 324 PTR sys_sigreturn
344 sys sys_newfstat 2 325 PTR __sys_clone /* 4120 */
345 sys sys_uname 1 326 PTR sys_setdomainname
346 sys sys_ni_syscall 0 /* 4110 was iopl(2) */ 327 PTR sys_newuname
347 sys sys_vhangup 0 328 PTR sys_ni_syscall /* sys_modify_ldt */
348 sys sys_ni_syscall 0 /* was sys_idle() */ 329 PTR sys_adjtimex
349 sys sys_ni_syscall 0 /* was sys_vm86 */ 330 PTR sys_mprotect /* 4125 */
350 sys sys_wait4 4 331 PTR sys_sigprocmask
351 sys sys_swapoff 1 /* 4115 */ 332 PTR sys_ni_syscall /* was create_module */
352 sys sys_sysinfo 1 333 PTR sys_init_module
353 sys sys_ipc 6 334 PTR sys_delete_module
354 sys sys_fsync 1 335 PTR sys_ni_syscall /* 4130 was get_kernel_syms */
355 sys sys_sigreturn 0 336 PTR sys_quotactl
356 sys __sys_clone 6 /* 4120 */ 337 PTR sys_getpgid
357 sys sys_setdomainname 2 338 PTR sys_fchdir
358 sys sys_newuname 1 339 PTR sys_bdflush
359 sys sys_ni_syscall 0 /* sys_modify_ldt */ 340 PTR sys_sysfs /* 4135 */
360 sys sys_adjtimex 1 341 PTR sys_personality
361 sys sys_mprotect 3 /* 4125 */ 342 PTR sys_ni_syscall /* for afs_syscall */
362 sys sys_sigprocmask 3 343 PTR sys_setfsuid
363 sys sys_ni_syscall 0 /* was create_module */ 344 PTR sys_setfsgid
364 sys sys_init_module 5 345 PTR sys_llseek /* 4140 */
365 sys sys_delete_module 1 346 PTR sys_getdents
366 sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */ 347 PTR sys_select
367 sys sys_quotactl 4 348 PTR sys_flock
368 sys sys_getpgid 1 349 PTR sys_msync
369 sys sys_fchdir 1 350 PTR sys_readv /* 4145 */
370 sys sys_bdflush 2 351 PTR sys_writev
371 sys sys_sysfs 3 /* 4135 */ 352 PTR sys_cacheflush
372 sys sys_personality 1 353 PTR sys_cachectl
373 sys sys_ni_syscall 0 /* for afs_syscall */ 354 PTR sys_sysmips
374 sys sys_setfsuid 1 355 PTR sys_ni_syscall /* 4150 */
375 sys sys_setfsgid 1 356 PTR sys_getsid
376 sys sys_llseek 5 /* 4140 */ 357 PTR sys_fdatasync
377 sys sys_getdents 3 358 PTR sys_sysctl
378 sys sys_select 5 359 PTR sys_mlock
379 sys sys_flock 2 360 PTR sys_munlock /* 4155 */
380 sys sys_msync 3 361 PTR sys_mlockall
381 sys sys_readv 3 /* 4145 */ 362 PTR sys_munlockall
382 sys sys_writev 3 363 PTR sys_sched_setparam
383 sys sys_cacheflush 3 364 PTR sys_sched_getparam
384 sys sys_cachectl 3 365 PTR sys_sched_setscheduler /* 4160 */
385 sys sys_sysmips 4 366 PTR sys_sched_getscheduler
386 sys sys_ni_syscall 0 /* 4150 */ 367 PTR sys_sched_yield
387 sys sys_getsid 1 368 PTR sys_sched_get_priority_max
388 sys sys_fdatasync 1 369 PTR sys_sched_get_priority_min
389 sys sys_sysctl 1 370 PTR sys_sched_rr_get_interval /* 4165 */
390 sys sys_mlock 2 371 PTR sys_nanosleep
391 sys sys_munlock 2 /* 4155 */ 372 PTR sys_mremap
392 sys sys_mlockall 1 373 PTR sys_accept
393 sys sys_munlockall 0 374 PTR sys_bind
394 sys sys_sched_setparam 2 375 PTR sys_connect /* 4170 */
395 sys sys_sched_getparam 2 376 PTR sys_getpeername
396 sys sys_sched_setscheduler 3 /* 4160 */ 377 PTR sys_getsockname
397 sys sys_sched_getscheduler 1 378 PTR sys_getsockopt
398 sys sys_sched_yield 0 379 PTR sys_listen
399 sys sys_sched_get_priority_max 1 380 PTR sys_recv /* 4175 */
400 sys sys_sched_get_priority_min 1 381 PTR sys_recvfrom
401 sys sys_sched_rr_get_interval 2 /* 4165 */ 382 PTR sys_recvmsg
402 sys sys_nanosleep, 2 383 PTR sys_send
403 sys sys_mremap, 5 384 PTR sys_sendmsg
404 sys sys_accept 3 385 PTR sys_sendto /* 4180 */
405 sys sys_bind 3 386 PTR sys_setsockopt
406 sys sys_connect 3 /* 4170 */ 387 PTR sys_shutdown
407 sys sys_getpeername 3 388 PTR sys_socket
408 sys sys_getsockname 3 389 PTR sys_socketpair
409 sys sys_getsockopt 5 390 PTR sys_setresuid /* 4185 */
410 sys sys_listen 2 391 PTR sys_getresuid
411 sys sys_recv 4 /* 4175 */ 392 PTR sys_ni_syscall /* was sys_query_module */
412 sys sys_recvfrom 6 393 PTR sys_poll
413 sys sys_recvmsg 3 394 PTR sys_ni_syscall /* was nfsservctl */
414 sys sys_send 4 395 PTR sys_setresgid /* 4190 */
415 sys sys_sendmsg 3 396 PTR sys_getresgid
416 sys sys_sendto 6 /* 4180 */ 397 PTR sys_prctl
417 sys sys_setsockopt 5 398 PTR sys_rt_sigreturn
418 sys sys_shutdown 2 399 PTR sys_rt_sigaction
419 sys sys_socket 3 400 PTR sys_rt_sigprocmask /* 4195 */
420 sys sys_socketpair 4 401 PTR sys_rt_sigpending
421 sys sys_setresuid 3 /* 4185 */ 402 PTR sys_rt_sigtimedwait
422 sys sys_getresuid 3 403 PTR sys_rt_sigqueueinfo
423 sys sys_ni_syscall 0 /* was sys_query_module */ 404 PTR sys_rt_sigsuspend
424 sys sys_poll 3 405 PTR sys_pread64 /* 4200 */
425 sys sys_ni_syscall 0 /* was nfsservctl */ 406 PTR sys_pwrite64
426 sys sys_setresgid 3 /* 4190 */ 407 PTR sys_chown
427 sys sys_getresgid 3 408 PTR sys_getcwd
428 sys sys_prctl 5 409 PTR sys_capget
429 sys sys_rt_sigreturn 0 410 PTR sys_capset /* 4205 */
430 sys sys_rt_sigaction 4 411 PTR sys_sigaltstack
431 sys sys_rt_sigprocmask 4 /* 4195 */ 412 PTR sys_sendfile
432 sys sys_rt_sigpending 2 413 PTR sys_ni_syscall
433 sys sys_rt_sigtimedwait 4 414 PTR sys_ni_syscall
434 sys sys_rt_sigqueueinfo 3 415 PTR sys_mips_mmap2 /* 4210 */
435 sys sys_rt_sigsuspend 0 416 PTR sys_truncate64
436 sys sys_pread64 6 /* 4200 */ 417 PTR sys_ftruncate64
437 sys sys_pwrite64 6 418 PTR sys_stat64
438 sys sys_chown 3 419 PTR sys_lstat64
439 sys sys_getcwd 2 420 PTR sys_fstat64 /* 4215 */
440 sys sys_capget 2 421 PTR sys_pivot_root
441 sys sys_capset 2 /* 4205 */ 422 PTR sys_mincore
442 sys sys_sigaltstack 0 423 PTR sys_madvise
443 sys sys_sendfile 4 424 PTR sys_getdents64
444 sys sys_ni_syscall 0 425 PTR sys_fcntl64 /* 4220 */
445 sys sys_ni_syscall 0 426 PTR sys_ni_syscall
446 sys sys_mips_mmap2 6 /* 4210 */ 427 PTR sys_gettid
447 sys sys_truncate64 4 428 PTR sys_readahead
448 sys sys_ftruncate64 4 429 PTR sys_setxattr
449 sys sys_stat64 2 430 PTR sys_lsetxattr /* 4225 */
450 sys sys_lstat64 2 431 PTR sys_fsetxattr
451 sys sys_fstat64 2 /* 4215 */ 432 PTR sys_getxattr
452 sys sys_pivot_root 2 433 PTR sys_lgetxattr
453 sys sys_mincore 3 434 PTR sys_fgetxattr
454 sys sys_madvise 3 435 PTR sys_listxattr /* 4230 */
455 sys sys_getdents64 3 436 PTR sys_llistxattr
456 sys sys_fcntl64 3 /* 4220 */ 437 PTR sys_flistxattr
457 sys sys_ni_syscall 0 438 PTR sys_removexattr
458 sys sys_gettid 0 439 PTR sys_lremovexattr
459 sys sys_readahead 5 440 PTR sys_fremovexattr /* 4235 */
460 sys sys_setxattr 5 441 PTR sys_tkill
461 sys sys_lsetxattr 5 /* 4225 */ 442 PTR sys_sendfile64
462 sys sys_fsetxattr 5 443 PTR sys_futex
463 sys sys_getxattr 4
464 sys sys_lgetxattr 4
465 sys sys_fgetxattr 4
466 sys sys_listxattr 3 /* 4230 */
467 sys sys_llistxattr 3
468 sys sys_flistxattr 3
469 sys sys_removexattr 2
470 sys sys_lremovexattr 2
471 sys sys_fremovexattr 2 /* 4235 */
472 sys sys_tkill 2
473 sys sys_sendfile64 5
474 sys sys_futex 6
475#ifdef CONFIG_MIPS_MT_FPAFF 444#ifdef CONFIG_MIPS_MT_FPAFF
476 /* 445 /*
477 * For FPU affinity scheduling on MIPS MT processors, we need to 446 * For FPU affinity scheduling on MIPS MT processors, we need to
@@ -480,132 +449,117 @@ einval: li v0, -ENOSYS
480 * these hooks for the 32-bit kernel - there is no MIPS64 MT processor 449 * these hooks for the 32-bit kernel - there is no MIPS64 MT processor
481 * atm. 450 * atm.
482 */ 451 */
483 sys mipsmt_sys_sched_setaffinity 3 452 PTR mipsmt_sys_sched_setaffinity
484 sys mipsmt_sys_sched_getaffinity 3 453 PTR mipsmt_sys_sched_getaffinity
485#else 454#else
486 sys sys_sched_setaffinity 3 455 PTR sys_sched_setaffinity
487 sys sys_sched_getaffinity 3 /* 4240 */ 456 PTR sys_sched_getaffinity /* 4240 */
488#endif /* CONFIG_MIPS_MT_FPAFF */ 457#endif /* CONFIG_MIPS_MT_FPAFF */
489 sys sys_io_setup 2 458 PTR sys_io_setup
490 sys sys_io_destroy 1 459 PTR sys_io_destroy
491 sys sys_io_getevents 5 460 PTR sys_io_getevents
492 sys sys_io_submit 3 461 PTR sys_io_submit
493 sys sys_io_cancel 3 /* 4245 */ 462 PTR sys_io_cancel /* 4245 */
494 sys sys_exit_group 1 463 PTR sys_exit_group
495 sys sys_lookup_dcookie 4 464 PTR sys_lookup_dcookie
496 sys sys_epoll_create 1 465 PTR sys_epoll_create
497 sys sys_epoll_ctl 4 466 PTR sys_epoll_ctl
498 sys sys_epoll_wait 4 /* 4250 */ 467 PTR sys_epoll_wait /* 4250 */
499 sys sys_remap_file_pages 5 468 PTR sys_remap_file_pages
500 sys sys_set_tid_address 1 469 PTR sys_set_tid_address
501 sys sys_restart_syscall 0 470 PTR sys_restart_syscall
502 sys sys_fadvise64_64 7 471 PTR sys_fadvise64_64
503 sys sys_statfs64 3 /* 4255 */ 472 PTR sys_statfs64 /* 4255 */
504 sys sys_fstatfs64 2 473 PTR sys_fstatfs64
505 sys sys_timer_create 3 474 PTR sys_timer_create
506 sys sys_timer_settime 4 475 PTR sys_timer_settime
507 sys sys_timer_gettime 2 476 PTR sys_timer_gettime
508 sys sys_timer_getoverrun 1 /* 4260 */ 477 PTR sys_timer_getoverrun /* 4260 */
509 sys sys_timer_delete 1 478 PTR sys_timer_delete
510 sys sys_clock_settime 2 479 PTR sys_clock_settime
511 sys sys_clock_gettime 2 480 PTR sys_clock_gettime
512 sys sys_clock_getres 2 481 PTR sys_clock_getres
513 sys sys_clock_nanosleep 4 /* 4265 */ 482 PTR sys_clock_nanosleep /* 4265 */
514 sys sys_tgkill 3 483 PTR sys_tgkill
515 sys sys_utimes 2 484 PTR sys_utimes
516 sys sys_mbind 4 485 PTR sys_mbind
517 sys sys_ni_syscall 0 /* sys_get_mempolicy */ 486 PTR sys_ni_syscall /* sys_get_mempolicy */
518 sys sys_ni_syscall 0 /* 4270 sys_set_mempolicy */ 487 PTR sys_ni_syscall /* 4270 sys_set_mempolicy */
519 sys sys_mq_open 4 488 PTR sys_mq_open
520 sys sys_mq_unlink 1 489 PTR sys_mq_unlink
521 sys sys_mq_timedsend 5 490 PTR sys_mq_timedsend
522 sys sys_mq_timedreceive 5 491 PTR sys_mq_timedreceive
523 sys sys_mq_notify 2 /* 4275 */ 492 PTR sys_mq_notify /* 4275 */
524 sys sys_mq_getsetattr 3 493 PTR sys_mq_getsetattr
525 sys sys_ni_syscall 0 /* sys_vserver */ 494 PTR sys_ni_syscall /* sys_vserver */
526 sys sys_waitid 5 495 PTR sys_waitid
527 sys sys_ni_syscall 0 /* available, was setaltroot */ 496 PTR sys_ni_syscall /* available, was setaltroot */
528 sys sys_add_key 5 /* 4280 */ 497 PTR sys_add_key /* 4280 */
529 sys sys_request_key 4 498 PTR sys_request_key
530 sys sys_keyctl 5 499 PTR sys_keyctl
531 sys sys_set_thread_area 1 500 PTR sys_set_thread_area
532 sys sys_inotify_init 0 501 PTR sys_inotify_init
533 sys sys_inotify_add_watch 3 /* 4285 */ 502 PTR sys_inotify_add_watch /* 4285 */
534 sys sys_inotify_rm_watch 2 503 PTR sys_inotify_rm_watch
535 sys sys_migrate_pages 4 504 PTR sys_migrate_pages
536 sys sys_openat 4 505 PTR sys_openat
537 sys sys_mkdirat 3 506 PTR sys_mkdirat
538 sys sys_mknodat 4 /* 4290 */ 507 PTR sys_mknodat /* 4290 */
539 sys sys_fchownat 5 508 PTR sys_fchownat
540 sys sys_futimesat 3 509 PTR sys_futimesat
541 sys sys_fstatat64 4 510 PTR sys_fstatat64
542 sys sys_unlinkat 3 511 PTR sys_unlinkat
543 sys sys_renameat 4 /* 4295 */ 512 PTR sys_renameat /* 4295 */
544 sys sys_linkat 5 513 PTR sys_linkat
545 sys sys_symlinkat 3 514 PTR sys_symlinkat
546 sys sys_readlinkat 4 515 PTR sys_readlinkat
547 sys sys_fchmodat 3 516 PTR sys_fchmodat
548 sys sys_faccessat 3 /* 4300 */ 517 PTR sys_faccessat /* 4300 */
549 sys sys_pselect6 6 518 PTR sys_pselect6
550 sys sys_ppoll 5 519 PTR sys_ppoll
551 sys sys_unshare 1 520 PTR sys_unshare
552 sys sys_splice 6 521 PTR sys_splice
553 sys sys_sync_file_range 7 /* 4305 */ 522 PTR sys_sync_file_range /* 4305 */
554 sys sys_tee 4 523 PTR sys_tee
555 sys sys_vmsplice 4 524 PTR sys_vmsplice
556 sys sys_move_pages 6 525 PTR sys_move_pages
557 sys sys_set_robust_list 2 526 PTR sys_set_robust_list
558 sys sys_get_robust_list 3 /* 4310 */ 527 PTR sys_get_robust_list /* 4310 */
559 sys sys_kexec_load 4 528 PTR sys_kexec_load
560 sys sys_getcpu 3 529 PTR sys_getcpu
561 sys sys_epoll_pwait 6 530 PTR sys_epoll_pwait
562 sys sys_ioprio_set 3 531 PTR sys_ioprio_set
563 sys sys_ioprio_get 2 /* 4315 */ 532 PTR sys_ioprio_get /* 4315 */
564 sys sys_utimensat 4 533 PTR sys_utimensat
565 sys sys_signalfd 3 534 PTR sys_signalfd
566 sys sys_ni_syscall 0 /* was timerfd */ 535 PTR sys_ni_syscall /* was timerfd */
567 sys sys_eventfd 1 536 PTR sys_eventfd
568 sys sys_fallocate 6 /* 4320 */ 537 PTR sys_fallocate /* 4320 */
569 sys sys_timerfd_create 2 538 PTR sys_timerfd_create
570 sys sys_timerfd_gettime 2 539 PTR sys_timerfd_gettime
571 sys sys_timerfd_settime 4 540 PTR sys_timerfd_settime
572 sys sys_signalfd4 4 541 PTR sys_signalfd4
573 sys sys_eventfd2 2 /* 4325 */ 542 PTR sys_eventfd2 /* 4325 */
574 sys sys_epoll_create1 1 543 PTR sys_epoll_create1
575 sys sys_dup3 3 544 PTR sys_dup3
576 sys sys_pipe2 2 545 PTR sys_pipe2
577 sys sys_inotify_init1 1 546 PTR sys_inotify_init1
578 sys sys_preadv 6 /* 4330 */ 547 PTR sys_preadv /* 4330 */
579 sys sys_pwritev 6 548 PTR sys_pwritev
580 sys sys_rt_tgsigqueueinfo 4 549 PTR sys_rt_tgsigqueueinfo
581 sys sys_perf_event_open 5 550 PTR sys_perf_event_open
582 sys sys_accept4 4 551 PTR sys_accept4
583 sys sys_recvmmsg 5 /* 4335 */ 552 PTR sys_recvmmsg /* 4335 */
584 sys sys_fanotify_init 2 553 PTR sys_fanotify_init
585 sys sys_fanotify_mark 6 554 PTR sys_fanotify_mark
586 sys sys_prlimit64 4 555 PTR sys_prlimit64
587 sys sys_name_to_handle_at 5 556 PTR sys_name_to_handle_at
588 sys sys_open_by_handle_at 3 /* 4340 */ 557 PTR sys_open_by_handle_at /* 4340 */
589 sys sys_clock_adjtime 2 558 PTR sys_clock_adjtime
590 sys sys_syncfs 1 559 PTR sys_syncfs
591 sys sys_sendmmsg 4 560 PTR sys_sendmmsg
592 sys sys_setns 2 561 PTR sys_setns
593 sys sys_process_vm_readv 6 /* 4345 */ 562 PTR sys_process_vm_readv /* 4345 */
594 sys sys_process_vm_writev 6 563 PTR sys_process_vm_writev
595 sys sys_kcmp 5 564 PTR sys_kcmp
596 sys sys_finit_module 3 565 PTR sys_finit_module
597 .endm
598
599 /* We pre-compute the number of _instruction_ bytes needed to
600 load or store the arguments 6-8. Negative values are ignored. */
601
602 .macro sys function, nargs
603 PTR \function
604 LONG (\nargs << 2) - (5 << 2)
605 .endm
606
607 .align 3
608 .type sys_call_table,@object
609EXPORT(sys_call_table)
610 syscalltable
611 .size sys_call_table, . - sys_call_table
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index be6627ead619..57e3742fec59 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -114,7 +114,8 @@ illegal_syscall:
114 END(handle_sys64) 114 END(handle_sys64)
115 115
116 .align 3 116 .align 3
117sys_call_table: 117 .type sys_call_table, @object
118EXPORT(sys_call_table)
118 PTR sys_read /* 5000 */ 119 PTR sys_read /* 5000 */
119 PTR sys_write 120 PTR sys_write
120 PTR sys_open 121 PTR sys_open
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index cab150789c8d..2f48f5934399 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -103,6 +103,7 @@ not_n32_scall:
103 103
104 END(handle_sysn32) 104 END(handle_sysn32)
105 105
106 .type sysn32_call_table, @object
106EXPORT(sysn32_call_table) 107EXPORT(sysn32_call_table)
107 PTR sys_read /* 6000 */ 108 PTR sys_read /* 6000 */
108 PTR sys_write 109 PTR sys_write
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 37605dc8eef7..f1acdb429f4f 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp)
53 sll a3, a3, 0 53 sll a3, a3, 0
54 54
55 dsll t0, v0, 3 # offset into table 55 dsll t0, v0, 3 # offset into table
56 ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) 56 ld t2, (sys32_call_table - (__NR_O32_Linux * 8))(t0)
57 57
58 sd a3, PT_R26(sp) # save a3 for syscall restarting 58 sd a3, PT_R26(sp) # save a3 for syscall restarting
59 59
@@ -168,7 +168,7 @@ LEAF(sys32_syscall)
168 beqz t0, einval # do not recurse 168 beqz t0, einval # do not recurse
169 dsll t1, t0, 3 169 dsll t1, t0, 3
170 beqz v0, einval 170 beqz v0, einval
171 ld t2, sys_call_table(t1) # syscall routine 171 ld t2, sys32_call_table(t1) # syscall routine
172 172
173 move a0, a1 # shift argument registers 173 move a0, a1 # shift argument registers
174 move a1, a2 174 move a1, a2
@@ -190,8 +190,8 @@ einval: li v0, -ENOSYS
190 END(sys32_syscall) 190 END(sys32_syscall)
191 191
192 .align 3 192 .align 3
193 .type sys_call_table,@object 193 .type sys32_call_table,@object
194sys_call_table: 194EXPORT(sys32_call_table)
195 PTR sys32_syscall /* 4000 */ 195 PTR sys32_syscall /* 4000 */
196 PTR sys_exit 196 PTR sys_exit
197 PTR __sys_fork 197 PTR __sys_fork
@@ -541,4 +541,4 @@ sys_call_table:
541 PTR compat_sys_process_vm_writev 541 PTR compat_sys_process_vm_writev
542 PTR sys_kcmp 542 PTR sys_kcmp
543 PTR sys_finit_module 543 PTR sys_finit_module
544 .size sys_call_table,.-sys_call_table 544 .size sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c538d6e01b7b..a842154d57dc 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -300,12 +300,13 @@ static void __init bootmem_init(void)
300 int i; 300 int i;
301 301
302 /* 302 /*
303 * Init any data related to initrd. It's a nop if INITRD is 303 * Sanity check any INITRD first. We don't take it into account
304 * not selected. Once that done we can determine the low bound 304 * for bootmem setup initially, rely on the end-of-kernel-code
305 * of usable memory. 305 * as our memory range starting point. Once bootmem is inited we
306 * will reserve the area used for the initrd.
306 */ 307 */
307 reserved_end = max(init_initrd(), 308 init_initrd();
308 (unsigned long) PFN_UP(__pa_symbol(&_end))); 309 reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end));
309 310
310 /* 311 /*
311 * max_low_pfn is not a number of pages. The number of pages 312 * max_low_pfn is not a number of pages. The number of pages
@@ -362,6 +363,14 @@ static void __init bootmem_init(void)
362 max_low_pfn = PFN_DOWN(HIGHMEM_START); 363 max_low_pfn = PFN_DOWN(HIGHMEM_START);
363 } 364 }
364 365
366#ifdef CONFIG_BLK_DEV_INITRD
367 /*
368 * mapstart should be after initrd_end
369 */
370 if (initrd_end)
371 mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end)));
372#endif
373
365 /* 374 /*
366 * Initialize the boot-time allocator with low memory only. 375 * Initialize the boot-time allocator with low memory only.
367 */ 376 */
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 126da74d4c55..2362665ba496 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -136,10 +136,10 @@ static void bmips_prepare_cpus(unsigned int max_cpus)
136{ 136{
137 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 137 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
138 "smp_ipi0", NULL)) 138 "smp_ipi0", NULL))
139 panic("Can't request IPI0 interrupt\n"); 139 panic("Can't request IPI0 interrupt");
140 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 140 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
141 "smp_ipi1", NULL)) 141 "smp_ipi1", NULL))
142 panic("Can't request IPI1 interrupt\n"); 142 panic("Can't request IPI1 interrupt");
143} 143}
144 144
145/* 145/*
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 5c208ed8f856..0a022ee33b2a 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -150,7 +150,6 @@ asmlinkage void start_secondary(void)
150void __irq_entry smp_call_function_interrupt(void) 150void __irq_entry smp_call_function_interrupt(void)
151{ 151{
152 irq_enter(); 152 irq_enter();
153 generic_smp_call_function_single_interrupt();
154 generic_smp_call_function_interrupt(); 153 generic_smp_call_function_interrupt();
155 irq_exit(); 154 irq_exit();
156} 155}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 524841f02803..f9c8746be8d6 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -330,6 +330,7 @@ void show_regs(struct pt_regs *regs)
330void show_registers(struct pt_regs *regs) 330void show_registers(struct pt_regs *regs)
331{ 331{
332 const int field = 2 * sizeof(unsigned long); 332 const int field = 2 * sizeof(unsigned long);
333 mm_segment_t old_fs = get_fs();
333 334
334 __show_regs(regs); 335 __show_regs(regs);
335 print_modules(); 336 print_modules();
@@ -344,9 +345,13 @@ void show_registers(struct pt_regs *regs)
344 printk("*HwTLS: %0*lx\n", field, tls); 345 printk("*HwTLS: %0*lx\n", field, tls);
345 } 346 }
346 347
348 if (!user_mode(regs))
349 /* Necessary for getting the correct stack content */
350 set_fs(KERNEL_DS);
347 show_stacktrace(current, regs); 351 show_stacktrace(current, regs);
348 show_code((unsigned int __user *) regs->cp0_epc); 352 show_code((unsigned int __user *) regs->cp0_epc);
349 printk("\n"); 353 printk("\n");
354 set_fs(old_fs);
350} 355}
351 356
352static int regs_to_trapnr(struct pt_regs *regs) 357static int regs_to_trapnr(struct pt_regs *regs)
@@ -366,7 +371,8 @@ void __noreturn die(const char *str, struct pt_regs *regs)
366 371
367 oops_enter(); 372 oops_enter();
368 373
369 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) 374 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
375 SIGSEGV) == NOTIFY_STOP)
370 sig = 0; 376 sig = 0;
371 377
372 console_verbose(); 378 console_verbose();
@@ -457,8 +463,8 @@ asmlinkage void do_be(struct pt_regs *regs)
457 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 463 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
458 data ? "Data" : "Instruction", 464 data ? "Data" : "Instruction",
459 field, regs->cp0_epc, field, regs->regs[31]); 465 field, regs->cp0_epc, field, regs->regs[31]);
460 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) 466 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
461 == NOTIFY_STOP) 467 SIGBUS) == NOTIFY_STOP)
462 goto out; 468 goto out;
463 469
464 die_if_kernel("Oops", regs); 470 die_if_kernel("Oops", regs);
@@ -727,8 +733,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
727 siginfo_t info = {0}; 733 siginfo_t info = {0};
728 734
729 prev_state = exception_enter(); 735 prev_state = exception_enter();
730 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 736 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
731 == NOTIFY_STOP) 737 SIGFPE) == NOTIFY_STOP)
732 goto out; 738 goto out;
733 die_if_kernel("FP exception in kernel code", regs); 739 die_if_kernel("FP exception in kernel code", regs);
734 740
@@ -798,7 +804,8 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
798 return; 804 return;
799#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 805#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
800 806
801 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 807 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
808 SIGTRAP) == NOTIFY_STOP)
802 return; 809 return;
803 810
804 /* 811 /*
@@ -892,12 +899,14 @@ asmlinkage void do_bp(struct pt_regs *regs)
892 */ 899 */
893 switch (bcode) { 900 switch (bcode) {
894 case BRK_KPROBE_BP: 901 case BRK_KPROBE_BP:
895 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 902 if (notify_die(DIE_BREAK, "debug", regs, bcode,
903 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
896 goto out; 904 goto out;
897 else 905 else
898 break; 906 break;
899 case BRK_KPROBE_SSTEPBP: 907 case BRK_KPROBE_SSTEPBP:
900 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 908 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
909 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
901 goto out; 910 goto out;
902 else 911 else
903 break; 912 break;
@@ -961,8 +970,8 @@ asmlinkage void do_ri(struct pt_regs *regs)
961 int status = -1; 970 int status = -1;
962 971
963 prev_state = exception_enter(); 972 prev_state = exception_enter();
964 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) 973 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
965 == NOTIFY_STOP) 974 SIGILL) == NOTIFY_STOP)
966 goto out; 975 goto out;
967 976
968 die_if_kernel("Reserved instruction in kernel code", regs); 977 die_if_kernel("Reserved instruction in kernel code", regs);
@@ -1488,10 +1497,14 @@ int register_nmi_notifier(struct notifier_block *nb)
1488 1497
1489void __noreturn nmi_exception_handler(struct pt_regs *regs) 1498void __noreturn nmi_exception_handler(struct pt_regs *regs)
1490{ 1499{
1500 char str[100];
1501
1491 raw_notifier_call_chain(&nmi_chain, 0, regs); 1502 raw_notifier_call_chain(&nmi_chain, 0, regs);
1492 bust_spinlocks(1); 1503 bust_spinlocks(1);
1493 printk("NMI taken!!!!\n"); 1504 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1494 die("NMI", regs); 1505 smp_processor_id(), regs->cp0_epc);
1506 regs->cp0_epc = read_c0_errorepc();
1507 die(str, regs);
1495} 1508}
1496 1509
1497#define VECTORSPACING 0x100 /* for EI/VI mode */ 1510#define VECTORSPACING 0x100 /* for EI/VI mode */
@@ -1554,7 +1567,6 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1554 unsigned char *b; 1567 unsigned char *b;
1555 1568
1556 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1569 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1557 BUG_ON((n < 0) && (n > 9));
1558 1570
1559 if (addr == NULL) { 1571 if (addr == NULL) {
1560 handler = (unsigned long) do_default_vi; 1572 handler = (unsigned long) do_default_vi;
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index eb3e18659630..85685e1cdb89 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -390,7 +390,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
390 ret = of_irq_to_resource_table(eiu_node, 390 ret = of_irq_to_resource_table(eiu_node,
391 ltq_eiu_irq, exin_avail); 391 ltq_eiu_irq, exin_avail);
392 if (ret != exin_avail) 392 if (ret != exin_avail)
393 panic("failed to load external irq resources\n"); 393 panic("failed to load external irq resources");
394 394
395 if (request_mem_region(res.start, resource_size(&res), 395 if (request_mem_region(res.start, resource_size(&res),
396 res.name) < 0) 396 res.name) < 0)
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index c24924fe087d..51804b10a036 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -128,7 +128,7 @@ static int pmu_enable(struct clk *clk)
128 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); 128 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
129 129
130 if (!retry) 130 if (!retry)
131 panic("activating PMU module failed!\n"); 131 panic("activating PMU module failed!");
132 132
133 return 0; 133 return 0;
134} 134}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bc6f96fcb529..62ffd20ea869 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -346,14 +346,8 @@ static void r4k_blast_scache_setup(void)
346 346
347static inline void local_r4k___flush_cache_all(void * args) 347static inline void local_r4k___flush_cache_all(void * args)
348{ 348{
349#if defined(CONFIG_CPU_LOONGSON2)
350 r4k_blast_scache();
351 return;
352#endif
353 r4k_blast_dcache();
354 r4k_blast_icache();
355
356 switch (current_cpu_type()) { 349 switch (current_cpu_type()) {
350 case CPU_LOONGSON2:
357 case CPU_R4000SC: 351 case CPU_R4000SC:
358 case CPU_R4000MC: 352 case CPU_R4000MC:
359 case CPU_R4400SC: 353 case CPU_R4400SC:
@@ -361,7 +355,18 @@ static inline void local_r4k___flush_cache_all(void * args)
361 case CPU_R10000: 355 case CPU_R10000:
362 case CPU_R12000: 356 case CPU_R12000:
363 case CPU_R14000: 357 case CPU_R14000:
358 /*
359 * These caches are inclusive caches, that is, if something
360 * is not cached in the S-cache, we know it also won't be
361 * in one of the primary caches.
362 */
364 r4k_blast_scache(); 363 r4k_blast_scache();
364 break;
365
366 default:
367 r4k_blast_dcache();
368 r4k_blast_icache();
369 break;
365 } 370 }
366} 371}
367 372
@@ -572,8 +577,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
572 577
573 if (end - start > icache_size) 578 if (end - start > icache_size)
574 r4k_blast_icache(); 579 r4k_blast_icache();
575 else 580 else {
576 protected_blast_icache_range(start, end); 581 switch (boot_cpu_type()) {
582 case CPU_LOONGSON2:
583 protected_blast_icache_range(start, end);
584 break;
585
586 default:
587 protected_loongson23_blast_icache_range(start, end);
588 break;
589 }
590 }
577} 591}
578 592
579static inline void local_r4k_flush_icache_range_ipi(void *args) 593static inline void local_r4k_flush_icache_range_ipi(void *args)
@@ -1109,15 +1123,14 @@ static void probe_pcache(void)
1109 case CPU_ALCHEMY: 1123 case CPU_ALCHEMY:
1110 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1124 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1111 break; 1125 break;
1112 }
1113 1126
1114#ifdef CONFIG_CPU_LOONGSON2 1127 case CPU_LOONGSON2:
1115 /* 1128 /*
1116 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1129 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1117 * one op will act on all 4 ways 1130 * one op will act on all 4 ways
1118 */ 1131 */
1119 c->icache.ways = 1; 1132 c->icache.ways = 1;
1120#endif 1133 }
1121 1134
1122 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1135 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1123 icache_size >> 10, 1136 icache_size >> 10,
@@ -1193,7 +1206,6 @@ static int probe_scache(void)
1193 return 1; 1206 return 1;
1194} 1207}
1195 1208
1196#if defined(CONFIG_CPU_LOONGSON2)
1197static void __init loongson2_sc_init(void) 1209static void __init loongson2_sc_init(void)
1198{ 1210{
1199 struct cpuinfo_mips *c = &current_cpu_data; 1211 struct cpuinfo_mips *c = &current_cpu_data;
@@ -1209,7 +1221,6 @@ static void __init loongson2_sc_init(void)
1209 1221
1210 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1222 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1211} 1223}
1212#endif
1213 1224
1214extern int r5k_sc_init(void); 1225extern int r5k_sc_init(void);
1215extern int rm7k_sc_init(void); 1226extern int rm7k_sc_init(void);
@@ -1259,11 +1270,10 @@ static void setup_scache(void)
1259#endif 1270#endif
1260 return; 1271 return;
1261 1272
1262#if defined(CONFIG_CPU_LOONGSON2)
1263 case CPU_LOONGSON2: 1273 case CPU_LOONGSON2:
1264 loongson2_sc_init(); 1274 loongson2_sc_init();
1265 return; 1275 return;
1266#endif 1276
1267 case CPU_XLP: 1277 case CPU_XLP:
1268 /* don't need to worry about L2, fully coherent */ 1278 /* don't need to worry about L2, fully coherent */
1269 return; 1279 return;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 5f8b95512580..2e9418562258 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -297,7 +297,6 @@ static void mips_dma_sync_single_for_cpu(struct device *dev,
297static void mips_dma_sync_single_for_device(struct device *dev, 297static void mips_dma_sync_single_for_device(struct device *dev,
298 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) 298 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
299{ 299{
300 plat_extra_sync_for_device(dev);
301 if (!plat_device_is_coherent(dev)) 300 if (!plat_device_is_coherent(dev))
302 __dma_sync(dma_addr_to_page(dev, dma_handle), 301 __dma_sync(dma_addr_to_page(dev, dma_handle),
303 dma_handle & ~PAGE_MASK, size, direction); 302 dma_handle & ~PAGE_MASK, size, direction);
@@ -327,7 +326,7 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
327 326
328int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 327int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
329{ 328{
330 return plat_dma_mapping_error(dev, dma_addr); 329 return 0;
331} 330}
332 331
333int mips_dma_supported(struct device *dev, u64 mask) 332int mips_dma_supported(struct device *dev, u64 mask)
@@ -340,7 +339,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
340{ 339{
341 BUG_ON(direction == DMA_NONE); 340 BUG_ON(direction == DMA_NONE);
342 341
343 plat_extra_sync_for_device(dev);
344 if (!plat_device_is_coherent(dev)) 342 if (!plat_device_is_coherent(dev))
345 __dma_sync_virtual(vaddr, size, direction); 343 __dma_sync_virtual(vaddr, size, direction);
346} 344}
diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S
index 79bca3130bd1..30a494db99c2 100644
--- a/arch/mips/mm/tlb-funcs.S
+++ b/arch/mips/mm/tlb-funcs.S
@@ -16,12 +16,10 @@
16 16
17#define FASTPATH_SIZE 128 17#define FASTPATH_SIZE 128
18 18
19#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
20LEAF(tlbmiss_handler_setup_pgd) 19LEAF(tlbmiss_handler_setup_pgd)
21 .space 16 * 4 20 .space 16 * 4
22END(tlbmiss_handler_setup_pgd) 21END(tlbmiss_handler_setup_pgd)
23EXPORT(tlbmiss_handler_setup_pgd_end) 22EXPORT(tlbmiss_handler_setup_pgd_end)
24#endif
25 23
26LEAF(handle_tlbm) 24LEAF(handle_tlbm)
27 .space FASTPATH_SIZE * 4 25 .space FASTPATH_SIZE * 4
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index bb3a5f643e97..da3b0b9c9eae 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -52,21 +52,26 @@ extern void build_tlb_refill_handler(void);
52 52
53#endif /* CONFIG_MIPS_MT_SMTC */ 53#endif /* CONFIG_MIPS_MT_SMTC */
54 54
55#if defined(CONFIG_CPU_LOONGSON2)
56/* 55/*
57 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, 56 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
58 * unfortrunately, itlb is not totally transparent to software. 57 * unfortrunately, itlb is not totally transparent to software.
59 */ 58 */
60#define FLUSH_ITLB write_c0_diag(4); 59static inline void flush_itlb(void)
61 60{
62#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } 61 switch (current_cpu_type()) {
63 62 case CPU_LOONGSON2:
64#else 63 write_c0_diag(4);
65 64 break;
66#define FLUSH_ITLB 65 default:
67#define FLUSH_ITLB_VM(vma) 66 break;
67 }
68}
68 69
69#endif 70static inline void flush_itlb_vm(struct vm_area_struct *vma)
71{
72 if (vma->vm_flags & VM_EXEC)
73 flush_itlb();
74}
70 75
71void local_flush_tlb_all(void) 76void local_flush_tlb_all(void)
72{ 77{
@@ -93,7 +98,7 @@ void local_flush_tlb_all(void)
93 } 98 }
94 tlbw_use_hazard(); 99 tlbw_use_hazard();
95 write_c0_entryhi(old_ctx); 100 write_c0_entryhi(old_ctx);
96 FLUSH_ITLB; 101 flush_itlb();
97 EXIT_CRITICAL(flags); 102 EXIT_CRITICAL(flags);
98} 103}
99EXPORT_SYMBOL(local_flush_tlb_all); 104EXPORT_SYMBOL(local_flush_tlb_all);
@@ -155,7 +160,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
155 } else { 160 } else {
156 drop_mmu_context(mm, cpu); 161 drop_mmu_context(mm, cpu);
157 } 162 }
158 FLUSH_ITLB; 163 flush_itlb();
159 EXIT_CRITICAL(flags); 164 EXIT_CRITICAL(flags);
160 } 165 }
161} 166}
@@ -197,7 +202,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
197 } else { 202 } else {
198 local_flush_tlb_all(); 203 local_flush_tlb_all();
199 } 204 }
200 FLUSH_ITLB; 205 flush_itlb();
201 EXIT_CRITICAL(flags); 206 EXIT_CRITICAL(flags);
202} 207}
203 208
@@ -230,7 +235,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
230 235
231 finish: 236 finish:
232 write_c0_entryhi(oldpid); 237 write_c0_entryhi(oldpid);
233 FLUSH_ITLB_VM(vma); 238 flush_itlb_vm(vma);
234 EXIT_CRITICAL(flags); 239 EXIT_CRITICAL(flags);
235 } 240 }
236} 241}
@@ -262,7 +267,7 @@ void local_flush_tlb_one(unsigned long page)
262 tlbw_use_hazard(); 267 tlbw_use_hazard();
263 } 268 }
264 write_c0_entryhi(oldpid); 269 write_c0_entryhi(oldpid);
265 FLUSH_ITLB; 270 flush_itlb();
266 EXIT_CRITICAL(flags); 271 EXIT_CRITICAL(flags);
267} 272}
268 273
@@ -335,7 +340,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
335 tlb_write_indexed(); 340 tlb_write_indexed();
336 } 341 }
337 tlbw_use_hazard(); 342 tlbw_use_hazard();
338 FLUSH_ITLB_VM(vma); 343 flush_itlb_vm(vma);
339 EXIT_CRITICAL(flags); 344 EXIT_CRITICAL(flags);
340} 345}
341 346
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9bb3a9363b06..183f2b583e4d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -340,10 +340,6 @@ static struct work_registers build_get_work_registers(u32 **p)
340{ 340{
341 struct work_registers r; 341 struct work_registers r;
342 342
343 int smp_processor_id_reg;
344 int smp_processor_id_sel;
345 int smp_processor_id_shift;
346
347 if (scratch_reg >= 0) { 343 if (scratch_reg >= 0) {
348 /* Save in CPU local C0_KScratch? */ 344 /* Save in CPU local C0_KScratch? */
349 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 345 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
@@ -354,25 +350,9 @@ static struct work_registers build_get_work_registers(u32 **p)
354 } 350 }
355 351
356 if (num_possible_cpus() > 1) { 352 if (num_possible_cpus() > 1) {
357#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
358 smp_processor_id_shift = 51;
359 smp_processor_id_reg = 20; /* XContext */
360 smp_processor_id_sel = 0;
361#else
362# ifdef CONFIG_32BIT
363 smp_processor_id_shift = 25;
364 smp_processor_id_reg = 4; /* Context */
365 smp_processor_id_sel = 0;
366# endif
367# ifdef CONFIG_64BIT
368 smp_processor_id_shift = 26;
369 smp_processor_id_reg = 4; /* Context */
370 smp_processor_id_sel = 0;
371# endif
372#endif
373 /* Get smp_processor_id */ 353 /* Get smp_processor_id */
374 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); 354 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
375 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); 355 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
376 356
377 /* handler_reg_save index in K0 */ 357 /* handler_reg_save index in K0 */
378 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 358 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
@@ -819,11 +799,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
819 } 799 }
820 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 800 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
821 801
822#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
823 if (pgd_reg != -1) { 802 if (pgd_reg != -1) {
824 /* pgd is in pgd_reg */ 803 /* pgd is in pgd_reg */
825 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 804 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
826 } else { 805 } else {
806#if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
827 /* 807 /*
828 * &pgd << 11 stored in CONTEXT [23..63]. 808 * &pgd << 11 stored in CONTEXT [23..63].
829 */ 809 */
@@ -835,30 +815,18 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
835 /* 1 0 1 0 1 << 6 xkphys cached */ 815 /* 1 0 1 0 1 << 6 xkphys cached */
836 uasm_i_ori(p, ptr, ptr, 0x540); 816 uasm_i_ori(p, ptr, ptr, 0x540);
837 uasm_i_drotr(p, ptr, ptr, 11); 817 uasm_i_drotr(p, ptr, ptr, 11);
838 }
839#elif defined(CONFIG_SMP) 818#elif defined(CONFIG_SMP)
840# ifdef CONFIG_MIPS_MT_SMTC 819 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
841 /* 820 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
842 * SMTC uses TCBind value as "CPU" index 821 UASM_i_LA_mostly(p, tmp, pgdc);
843 */ 822 uasm_i_daddu(p, ptr, ptr, tmp);
844 uasm_i_mfc0(p, ptr, C0_TCBIND); 823 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
845 uasm_i_dsrl_safe(p, ptr, ptr, 19); 824 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
846# else
847 /*
848 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
849 * stored in CONTEXT.
850 */
851 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
852 uasm_i_dsrl_safe(p, ptr, ptr, 23);
853# endif
854 UASM_i_LA_mostly(p, tmp, pgdc);
855 uasm_i_daddu(p, ptr, ptr, tmp);
856 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
858#else 825#else
859 UASM_i_LA_mostly(p, ptr, pgdc); 826 UASM_i_LA_mostly(p, ptr, pgdc);
860 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 827 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
861#endif 828#endif
829 }
862 830
863 uasm_l_vmalloc_done(l, *p); 831 uasm_l_vmalloc_done(l, *p);
864 832
@@ -953,31 +921,25 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
953static void __maybe_unused 921static void __maybe_unused
954build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 922build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
955{ 923{
956 long pgdc = (long)pgd_current; 924 if (pgd_reg != -1) {
925 /* pgd is in pgd_reg */
926 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
927 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
928 } else {
929 long pgdc = (long)pgd_current;
957 930
958 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 931 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
959#ifdef CONFIG_SMP 932#ifdef CONFIG_SMP
960#ifdef CONFIG_MIPS_MT_SMTC 933 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
961 /* 934 UASM_i_LA_mostly(p, tmp, pgdc);
962 * SMTC uses TCBind value as "CPU" index 935 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
963 */ 936 uasm_i_addu(p, ptr, tmp, ptr);
964 uasm_i_mfc0(p, ptr, C0_TCBIND);
965 UASM_i_LA_mostly(p, tmp, pgdc);
966 uasm_i_srl(p, ptr, ptr, 19);
967#else
968 /*
969 * smp_processor_id() << 2 is stored in CONTEXT.
970 */
971 uasm_i_mfc0(p, ptr, C0_CONTEXT);
972 UASM_i_LA_mostly(p, tmp, pgdc);
973 uasm_i_srl(p, ptr, ptr, 23);
974#endif
975 uasm_i_addu(p, ptr, tmp, ptr);
976#else 937#else
977 UASM_i_LA_mostly(p, ptr, pgdc); 938 UASM_i_LA_mostly(p, ptr, pgdc);
978#endif 939#endif
979 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 940 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
980 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 941 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
942 }
981 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 943 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
982 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 944 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
983 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 945 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
@@ -1349,95 +1311,100 @@ static void build_r4000_tlb_refill_handler(void)
1349 * need three, with the second nop'ed and the third being 1311 * need three, with the second nop'ed and the third being
1350 * unused. 1312 * unused.
1351 */ 1313 */
1352 /* Loongson2 ebase is different than r4k, we have more space */ 1314 switch (boot_cpu_type()) {
1353#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) 1315 default:
1354 if ((p - tlb_handler) > 64) 1316 if (sizeof(long) == 4) {
1355 panic("TLB refill handler space exceeded"); 1317 case CPU_LOONGSON2:
1356#else 1318 /* Loongson2 ebase is different than r4k, we have more space */
1357 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1319 if ((p - tlb_handler) > 64)
1358 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1320 panic("TLB refill handler space exceeded");
1359 && uasm_insn_has_bdelay(relocs,
1360 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1361 panic("TLB refill handler space exceeded");
1362#endif
1363
1364 /*
1365 * Now fold the handler in the TLB refill handler space.
1366 */
1367#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1368 f = final_handler;
1369 /* Simplest case, just copy the handler. */
1370 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1371 final_len = p - tlb_handler;
1372#else /* CONFIG_64BIT */
1373 f = final_handler + MIPS64_REFILL_INSNS;
1374 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1375 /* Just copy the handler. */
1376 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1377 final_len = p - tlb_handler;
1378 } else {
1379#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1380 const enum label_id ls = label_tlb_huge_update;
1381#else
1382 const enum label_id ls = label_vmalloc;
1383#endif
1384 u32 *split;
1385 int ov = 0;
1386 int i;
1387
1388 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1389 ;
1390 BUG_ON(i == ARRAY_SIZE(labels));
1391 split = labels[i].addr;
1392
1393 /*
1394 * See if we have overflown one way or the other.
1395 */
1396 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1397 split < p - MIPS64_REFILL_INSNS)
1398 ov = 1;
1399
1400 if (ov) {
1401 /* 1321 /*
1402 * Split two instructions before the end. One 1322 * Now fold the handler in the TLB refill handler space.
1403 * for the branch and one for the instruction
1404 * in the delay slot.
1405 */ 1323 */
1406 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1324 f = final_handler;
1407 1325 /* Simplest case, just copy the handler. */
1326 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1327 final_len = p - tlb_handler;
1328 break;
1329 } else {
1330 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1331 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1332 && uasm_insn_has_bdelay(relocs,
1333 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1334 panic("TLB refill handler space exceeded");
1408 /* 1335 /*
1409 * If the branch would fall in a delay slot, 1336 * Now fold the handler in the TLB refill handler space.
1410 * we must back up an additional instruction
1411 * so that it is no longer in a delay slot.
1412 */ 1337 */
1413 if (uasm_insn_has_bdelay(relocs, split - 1)) 1338 f = final_handler + MIPS64_REFILL_INSNS;
1414 split--; 1339 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1415 } 1340 /* Just copy the handler. */
1416 /* Copy first part of the handler. */ 1341 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1417 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1342 final_len = p - tlb_handler;
1418 f += split - tlb_handler; 1343 } else {
1419 1344#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1420 if (ov) { 1345 const enum label_id ls = label_tlb_huge_update;
1421 /* Insert branch. */ 1346#else
1422 uasm_l_split(&l, final_handler); 1347 const enum label_id ls = label_vmalloc;
1423 uasm_il_b(&f, &r, label_split); 1348#endif
1424 if (uasm_insn_has_bdelay(relocs, split)) 1349 u32 *split;
1425 uasm_i_nop(&f); 1350 int ov = 0;
1426 else { 1351 int i;
1427 uasm_copy_handler(relocs, labels, 1352
1428 split, split + 1, f); 1353 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1429 uasm_move_labels(labels, f, f + 1, -1); 1354 ;
1430 f++; 1355 BUG_ON(i == ARRAY_SIZE(labels));
1431 split++; 1356 split = labels[i].addr;
1357
1358 /*
1359 * See if we have overflown one way or the other.
1360 */
1361 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1362 split < p - MIPS64_REFILL_INSNS)
1363 ov = 1;
1364
1365 if (ov) {
1366 /*
1367 * Split two instructions before the end. One
1368 * for the branch and one for the instruction
1369 * in the delay slot.
1370 */
1371 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1372
1373 /*
1374 * If the branch would fall in a delay slot,
1375 * we must back up an additional instruction
1376 * so that it is no longer in a delay slot.
1377 */
1378 if (uasm_insn_has_bdelay(relocs, split - 1))
1379 split--;
1380 }
1381 /* Copy first part of the handler. */
1382 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1383 f += split - tlb_handler;
1384
1385 if (ov) {
1386 /* Insert branch. */
1387 uasm_l_split(&l, final_handler);
1388 uasm_il_b(&f, &r, label_split);
1389 if (uasm_insn_has_bdelay(relocs, split))
1390 uasm_i_nop(&f);
1391 else {
1392 uasm_copy_handler(relocs, labels,
1393 split, split + 1, f);
1394 uasm_move_labels(labels, f, f + 1, -1);
1395 f++;
1396 split++;
1397 }
1398 }
1399
1400 /* Copy the rest of the handler. */
1401 uasm_copy_handler(relocs, labels, split, p, final_handler);
1402 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1403 (p - split);
1432 } 1404 }
1433 } 1405 }
1434 1406 break;
1435 /* Copy the rest of the handler. */
1436 uasm_copy_handler(relocs, labels, split, p, final_handler);
1437 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1438 (p - split);
1439 } 1407 }
1440#endif /* CONFIG_64BIT */
1441 1408
1442 uasm_resolve_relocs(relocs, labels); 1409 uasm_resolve_relocs(relocs, labels);
1443 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1410 pr_debug("Wrote TLB refill handler (%u instructions).\n",
@@ -1451,28 +1418,30 @@ static void build_r4000_tlb_refill_handler(void)
1451extern u32 handle_tlbl[], handle_tlbl_end[]; 1418extern u32 handle_tlbl[], handle_tlbl_end[];
1452extern u32 handle_tlbs[], handle_tlbs_end[]; 1419extern u32 handle_tlbs[], handle_tlbs_end[];
1453extern u32 handle_tlbm[], handle_tlbm_end[]; 1420extern u32 handle_tlbm[], handle_tlbm_end[];
1454
1455#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1456extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; 1421extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[];
1457 1422
1458static void build_r4000_setup_pgd(void) 1423static void build_setup_pgd(void)
1459{ 1424{
1460 const int a0 = 4; 1425 const int a0 = 4;
1461 const int a1 = 5; 1426 const int __maybe_unused a1 = 5;
1427 const int __maybe_unused a2 = 6;
1462 u32 *p = tlbmiss_handler_setup_pgd; 1428 u32 *p = tlbmiss_handler_setup_pgd;
1463 const int tlbmiss_handler_setup_pgd_size = 1429 const int tlbmiss_handler_setup_pgd_size =
1464 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; 1430 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd;
1465 struct uasm_label *l = labels; 1431#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1466 struct uasm_reloc *r = relocs; 1432 long pgdc = (long)pgd_current;
1433#endif
1467 1434
1468 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * 1435 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1469 sizeof(tlbmiss_handler_setup_pgd[0])); 1436 sizeof(tlbmiss_handler_setup_pgd[0]));
1470 memset(labels, 0, sizeof(labels)); 1437 memset(labels, 0, sizeof(labels));
1471 memset(relocs, 0, sizeof(relocs)); 1438 memset(relocs, 0, sizeof(relocs));
1472
1473 pgd_reg = allocate_kscratch(); 1439 pgd_reg = allocate_kscratch();
1474 1440#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1475 if (pgd_reg == -1) { 1441 if (pgd_reg == -1) {
1442 struct uasm_label *l = labels;
1443 struct uasm_reloc *r = relocs;
1444
1476 /* PGD << 11 in c0_Context */ 1445 /* PGD << 11 in c0_Context */
1477 /* 1446 /*
1478 * If it is a ckseg0 address, convert to a physical 1447 * If it is a ckseg0 address, convert to a physical
@@ -1494,6 +1463,26 @@ static void build_r4000_setup_pgd(void)
1494 uasm_i_jr(&p, 31); 1463 uasm_i_jr(&p, 31);
1495 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1464 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1496 } 1465 }
1466#else
1467#ifdef CONFIG_SMP
1468 /* Save PGD to pgd_current[smp_processor_id()] */
1469 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1470 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1471 UASM_i_LA_mostly(&p, a2, pgdc);
1472 UASM_i_ADDU(&p, a2, a2, a1);
1473 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1474#else
1475 UASM_i_LA_mostly(&p, a2, pgdc);
1476 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1477#endif /* SMP */
1478 uasm_i_jr(&p, 31);
1479
1480 /* if pgd_reg is allocated, save PGD also to scratch register */
1481 if (pgd_reg != -1)
1482 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1483 else
1484 uasm_i_nop(&p);
1485#endif
1497 if (p >= tlbmiss_handler_setup_pgd_end) 1486 if (p >= tlbmiss_handler_setup_pgd_end)
1498 panic("tlbmiss_handler_setup_pgd space exceeded"); 1487 panic("tlbmiss_handler_setup_pgd space exceeded");
1499 1488
@@ -1504,7 +1493,6 @@ static void build_r4000_setup_pgd(void)
1504 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1493 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1505 tlbmiss_handler_setup_pgd_size); 1494 tlbmiss_handler_setup_pgd_size);
1506} 1495}
1507#endif
1508 1496
1509static void 1497static void
1510iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1498iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
@@ -2197,10 +2185,8 @@ static void flush_tlb_handlers(void)
2197 (unsigned long)handle_tlbs_end); 2185 (unsigned long)handle_tlbs_end);
2198 local_flush_icache_range((unsigned long)handle_tlbm, 2186 local_flush_icache_range((unsigned long)handle_tlbm,
2199 (unsigned long)handle_tlbm_end); 2187 (unsigned long)handle_tlbm_end);
2200#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2201 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2188 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2202 (unsigned long)tlbmiss_handler_setup_pgd_end); 2189 (unsigned long)tlbmiss_handler_setup_pgd_end);
2203#endif
2204} 2190}
2205 2191
2206void build_tlb_refill_handler(void) 2192void build_tlb_refill_handler(void)
@@ -2232,6 +2218,7 @@ void build_tlb_refill_handler(void)
2232 if (!run_once) { 2218 if (!run_once) {
2233 if (!cpu_has_local_ebase) 2219 if (!cpu_has_local_ebase)
2234 build_r3000_tlb_refill_handler(); 2220 build_r3000_tlb_refill_handler();
2221 build_setup_pgd();
2235 build_r3000_tlb_load_handler(); 2222 build_r3000_tlb_load_handler();
2236 build_r3000_tlb_store_handler(); 2223 build_r3000_tlb_store_handler();
2237 build_r3000_tlb_modify_handler(); 2224 build_r3000_tlb_modify_handler();
@@ -2255,9 +2242,7 @@ void build_tlb_refill_handler(void)
2255 default: 2242 default:
2256 if (!run_once) { 2243 if (!run_once) {
2257 scratch_reg = allocate_kscratch(); 2244 scratch_reg = allocate_kscratch();
2258#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 2245 build_setup_pgd();
2259 build_r4000_setup_pgd();
2260#endif
2261 build_r4000_tlb_load_handler(); 2246 build_r4000_tlb_load_handler();
2262 build_r4000_tlb_store_handler(); 2247 build_r4000_tlb_store_handler();
2263 build_r4000_tlb_modify_handler(); 2248 build_r4000_tlb_modify_handler();
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 5b28e81d94a0..0892575f829d 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -37,7 +37,6 @@
37#include <asm/irq_regs.h> 37#include <asm/irq_regs.h>
38#include <asm/mips-boards/malta.h> 38#include <asm/mips-boards/malta.h>
39#include <asm/mips-boards/maltaint.h> 39#include <asm/mips-boards/maltaint.h>
40#include <asm/mips-boards/piix4.h>
41#include <asm/gt64120.h> 40#include <asm/gt64120.h>
42#include <asm/mips-boards/generic.h> 41#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/msc01_pci.h> 42#include <asm/mips-boards/msc01_pci.h>
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 6f8feb9efcff..c0eded01fde9 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -245,7 +245,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
245 return threadmode; 245 return threadmode;
246 246
247unsupp: 247unsupp:
248 panic("Unsupported CPU mask %lx\n", 248 panic("Unsupported CPU mask %lx",
249 (unsigned long)cpumask_bits(wakeup_mask)[0]); 249 (unsigned long)cpumask_bits(wakeup_mask)[0]);
250 return 0; 250 return 0;
251} 251}
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 07ada7f8441e..df36e2327c54 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -1,5 +1,6 @@
1#include <linux/init.h> 1#include <linux/init.h>
2#include <linux/pci.h> 2#include <linux/pci.h>
3#include <asm/mips-boards/piix4.h>
3 4
4/* PCI interrupt pins */ 5/* PCI interrupt pins */
5#define PCIA 1 6#define PCIA 1
@@ -53,7 +54,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
53static void malta_piix_func0_fixup(struct pci_dev *pdev) 54static void malta_piix_func0_fixup(struct pci_dev *pdev)
54{ 55{
55 unsigned char reg_val; 56 unsigned char reg_val;
56 static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */ 57 /* PIIX PIRQC[A:D] irq mappings */
58 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
57 0, 0, 0, 3, 59 0, 0, 0, 3,
58 4, 5, 6, 7, 60 4, 5, 6, 7,
59 0, 9, 10, 11, 61 0, 9, 10, 11,
@@ -63,11 +65,12 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
63 65
64 /* Interrogate PIIX4 to get PCI IRQ mapping */ 66 /* Interrogate PIIX4 to get PCI IRQ mapping */
65 for (i = 0; i <= 3; i++) { 67 for (i = 0; i <= 3; i++) {
66 pci_read_config_byte(pdev, 0x60+i, &reg_val); 68 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
67 if (reg_val & 0x80) 69 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
68 pci_irq[PCIA+i] = 0; /* Disabled */ 70 pci_irq[PCIA+i] = 0; /* Disabled */
69 else 71 else
70 pci_irq[PCIA+i] = piixirqmap[reg_val & 15]; 72 pci_irq[PCIA+i] = piixirqmap[reg_val &
73 PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
71 } 74 }
72 75
73 /* Done by YAMON 2.00 onwards */ 76 /* Done by YAMON 2.00 onwards */
@@ -76,8 +79,9 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
76 * Set top of main memory accessible by ISA or DMA 79 * Set top of main memory accessible by ISA or DMA
77 * devices to 16 Mb. 80 * devices to 16 Mb.
78 */ 81 */
79 pci_read_config_byte(pdev, 0x69, &reg_val); 82 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
80 pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); 83 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
84 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
81 } 85 }
82} 86}
83 87
@@ -93,10 +97,14 @@ static void malta_piix_func1_fixup(struct pci_dev *pdev)
93 /* 97 /*
94 * IDE Decode enable. 98 * IDE Decode enable.
95 */ 99 */
96 pci_read_config_byte(pdev, 0x41, &reg_val); 100 pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
97 pci_write_config_byte(pdev, 0x41, reg_val|0x80); 101 &reg_val);
98 pci_read_config_byte(pdev, 0x43, &reg_val); 102 pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
99 pci_write_config_byte(pdev, 0x43, reg_val|0x80); 103 reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
104 pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
105 &reg_val);
106 pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
107 reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
100 } 108 }
101} 109}
102 110
@@ -108,10 +116,12 @@ static void quirk_dlcsetup(struct pci_dev *dev)
108{ 116{
109 u8 odlc, ndlc; 117 u8 odlc, ndlc;
110 118
111 (void) pci_read_config_byte(dev, 0x82, &odlc); 119 (void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
112 /* Enable passive releases and delayed transaction */ 120 /* Enable passive releases and delayed transaction */
113 ndlc = odlc | 7; 121 ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
114 (void) pci_write_config_byte(dev, 0x82, ndlc); 122 PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
123 PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
124 (void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
115} 125}
116 126
117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, 127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c
index 18517dd0f709..d471a26dd5f8 100644
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -363,9 +363,6 @@ static int ar71xx_pci_probe(struct platform_device *pdev)
363 spin_lock_init(&apc->lock); 363 spin_lock_init(&apc->lock);
364 364
365 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); 365 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
366 if (!res)
367 return -EINVAL;
368
369 apc->cfg_base = devm_ioremap_resource(&pdev->dev, res); 366 apc->cfg_base = devm_ioremap_resource(&pdev->dev, res);
370 if (IS_ERR(apc->cfg_base)) 367 if (IS_ERR(apc->cfg_base))
371 return PTR_ERR(apc->cfg_base); 368 return PTR_ERR(apc->cfg_base);
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index 65ec032fa0b4..785b2659b519 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -362,25 +362,16 @@ static int ar724x_pci_probe(struct platform_device *pdev)
362 return -ENOMEM; 362 return -ENOMEM;
363 363
364 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); 364 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
365 if (!res)
366 return -EINVAL;
367
368 apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res); 365 apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
369 if (IS_ERR(apc->ctrl_base)) 366 if (IS_ERR(apc->ctrl_base))
370 return PTR_ERR(apc->ctrl_base); 367 return PTR_ERR(apc->ctrl_base);
371 368
372 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); 369 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
373 if (!res)
374 return -EINVAL;
375
376 apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res); 370 apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res);
377 if (IS_ERR(apc->devcfg_base)) 371 if (IS_ERR(apc->devcfg_base))
378 return PTR_ERR(apc->devcfg_base); 372 return PTR_ERR(apc->devcfg_base);
379 373
380 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base"); 374 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
381 if (!res)
382 return -EINVAL;
383
384 apc->crp_base = devm_ioremap_resource(&pdev->dev, res); 375 apc->crp_base = devm_ioremap_resource(&pdev->dev, res);
385 if (IS_ERR(apc->crp_base)) 376 if (IS_ERR(apc->crp_base))
386 return PTR_ERR(apc->crp_base); 377 return PTR_ERR(apc->crp_base);
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 33e7aa52d9c4..1bf60b127377 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -120,51 +120,37 @@ static void pcibios_scanbus(struct pci_controller *hose)
120#ifdef CONFIG_OF 120#ifdef CONFIG_OF
121void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 121void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
122{ 122{
123 const __be32 *ranges; 123 struct of_pci_range range;
124 int rlen; 124 struct of_pci_range_parser parser;
125 int pna = of_n_addr_cells(node);
126 int np = pna + 5;
127 125
128 pr_info("PCI host bridge %s ranges:\n", node->full_name); 126 pr_info("PCI host bridge %s ranges:\n", node->full_name);
129 ranges = of_get_property(node, "ranges", &rlen);
130 if (ranges == NULL)
131 return;
132 hose->of_node = node; 127 hose->of_node = node;
133 128
134 while ((rlen -= np * 4) >= 0) { 129 if (of_pci_range_parser_init(&parser, node))
135 u32 pci_space; 130 return;
131
132 for_each_of_pci_range(&parser, &range) {
136 struct resource *res = NULL; 133 struct resource *res = NULL;
137 u64 addr, size; 134
138 135 switch (range.flags & IORESOURCE_TYPE_BITS) {
139 pci_space = be32_to_cpup(&ranges[0]); 136 case IORESOURCE_IO:
140 addr = of_translate_address(node, ranges + 3);
141 size = of_read_number(ranges + pna + 3, 2);
142 ranges += np;
143 switch ((pci_space >> 24) & 0x3) {
144 case 1: /* PCI IO space */
145 pr_info(" IO 0x%016llx..0x%016llx\n", 137 pr_info(" IO 0x%016llx..0x%016llx\n",
146 addr, addr + size - 1); 138 range.cpu_addr,
139 range.cpu_addr + range.size - 1);
147 hose->io_map_base = 140 hose->io_map_base =
148 (unsigned long)ioremap(addr, size); 141 (unsigned long)ioremap(range.cpu_addr,
142 range.size);
149 res = hose->io_resource; 143 res = hose->io_resource;
150 res->flags = IORESOURCE_IO;
151 break; 144 break;
152 case 2: /* PCI Memory space */ 145 case IORESOURCE_MEM:
153 case 3: /* PCI 64 bits Memory space */
154 pr_info(" MEM 0x%016llx..0x%016llx\n", 146 pr_info(" MEM 0x%016llx..0x%016llx\n",
155 addr, addr + size - 1); 147 range.cpu_addr,
148 range.cpu_addr + range.size - 1);
156 res = hose->mem_resource; 149 res = hose->mem_resource;
157 res->flags = IORESOURCE_MEM;
158 break; 150 break;
159 } 151 }
160 if (res != NULL) { 152 if (res != NULL)
161 res->start = addr; 153 of_pci_range_to_resource(&range, node, res);
162 res->name = node->full_name;
163 res->end = res->start + size - 1;
164 res->parent = NULL;
165 res->sibling = NULL;
166 res->child = NULL;
167 }
168 } 154 }
169} 155}
170 156
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
deleted file mode 100644
index dd91fbacbcba..000000000000
--- a/arch/mips/powertv/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
1config BOOTLOADER_FAMILY
2 string "POWERTV Bootloader Family string"
3 default "85"
4 depends on POWERTV
5 help
6 This value should be specified when the bootloader driver is disabled
7 and must be exactly two characters long. Families supported are:
8 R1 - RNG-100 R2 - RNG-200
9 A1 - Class A B1 - Class B
10 E1 - Class E F1 - Class F
11 44 - 45xx 46 - 46xx
12 85 - 85xx 86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
deleted file mode 100644
index 39ca9f8d63ae..000000000000
--- a/arch/mips/powertv/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# Carsten Langgaard, carstenl@mips.com
6# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
7# Portions copyright (C) 2009 Cisco Systems, Inc.
8#
9# This program is free software; you can distribute it and/or modify it
10# under the terms of the GNU General Public License (Version 2) as
11# published by the Free Software Foundation.
12#
13# This program is distributed in the hope it will be useful, but WITHOUT
14# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16# for more details.
17#
18# You should have received a copy of the GNU General Public License along
19# with this program; if not, write to the Free Software Foundation, Inc.,
20# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21#
22# Makefile for the Cisco PowerTV-specific kernel interface routines
23# under Linux.
24#
25
26obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
27 asic/ pci/
28
29obj-$(CONFIG_USB) += powertv-usb.o
diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform
deleted file mode 100644
index 4eb5af1d8eea..000000000000
--- a/arch/mips/powertv/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Cisco PowerTV Platform
3#
4platform-$(CONFIG_POWERTV) += powertv/
5cflags-$(CONFIG_POWERTV) += \
6 -I$(srctree)/arch/mips/include/asm/mach-powertv
7load-$(CONFIG_POWERTV) += 0xffffffff90800000
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
deleted file mode 100644
index 35dcc53eb25f..000000000000
--- a/arch/mips/powertv/asic/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \
20 asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \
21 prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
deleted file mode 100644
index 2f539b43f56b..000000000000
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Calliope ASIC.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
30
31const struct register_map calliope_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
33 .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
34 .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
36 .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37 .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38 .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39 .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
43 .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
44 .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
45 .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
46 .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
47 .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
48 .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
49 .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
50
51 .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
52 .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
53 .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
54 .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
55 .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
56 .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
57 .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
58 .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
59 .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
60 .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
61 .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
62 .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
63 .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
64 .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
65 .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
66 .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
67 .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
68 .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
69 .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
70 .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
71 .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
72 .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
73 .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
74 .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
75 .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
76 .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
78
79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80 .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
84 .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
85 .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
86 .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
87 .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
88 .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
89 .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
90 .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
91 .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
92
93 .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
94 .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
95 .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
96 .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
97 .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
98 .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
99 .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
100 .front_panel = {.phys = 0x000000}, /* -not used- */
101};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
deleted file mode 100644
index 7f8f3429b35a..000000000000
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Cronus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
30
31const struct register_map cronus_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
36 .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37 .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38 .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39 .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
43 .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
44 .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
45 .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
46 .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
47 .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
48 .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
49 .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
50
51 .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
52 .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
53 .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
54 .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
55 .int_config = {.phys = CRONUS_ADDR(0x2A2810)},
56 .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
57 .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
58 .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
59 .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
60 .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
61 .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
62 .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
63 .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
64 .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
65 .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
66 .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
67 .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
68 .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
69 .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
70 .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
71 .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
72 .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
73 .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
74 .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
75 .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
76 .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
78
79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80 .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
90 .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
91 .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
92
93 .pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
94 .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
95 .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
96 .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
97 .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
98 .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
99 .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
100 .front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
101};
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
deleted file mode 100644
index 1265b49012e6..000000000000
--- a/arch/mips/powertv/asic/asic-gaia.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Locations of devices in the Gaia ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26const struct register_map gaia_register_map __initconst = {
27 .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
28 .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
29 .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
30
31 .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800},
32 .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804},
33 .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808},
34 .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C},
35
36 /* The registers of IRBlaster */
37 .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800},
38 .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804},
39 .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808},
40 .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C},
41 .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810},
42 .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814},
43 .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818},
44 .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C},
45
46 .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800},
47 .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804},
48 .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808},
49 .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C},
50 .int_config = {.phys = GAIA_IO_BASE + 0x2A2810},
51 .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818},
52 .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830},
53 .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834},
54 .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838},
55 .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C},
56 .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880},
57 .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884},
58 .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888},
59 .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C},
60 .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890},
61 .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894},
62 .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898},
63 .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C},
64 .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0},
65 .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4},
66 .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8},
67 .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC},
68 .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0},
69 .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4},
70 .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8},
71 .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC},
72 .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4},
73
74 .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000},
75 .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024},
76 .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC},
77 .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108},
78 .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C},
79 .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014},
80 .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00},
81 .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00},
82 .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004},
83 .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C},
84 .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00},
85 .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04},
86 .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08},
87
88 .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000},
89 .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10},
90 .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14},
91 .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20},
92 .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24},
93 .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C},
94 .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30},
95 .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800},
96};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
deleted file mode 100644
index 14e7de137e03..000000000000
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Locations of devices in the Zeus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
30
31const struct register_map zeus_register_map __initconst = {
32 .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
35
36 .chipver3 = {.phys = ZEUS_ADDR(0x280800)},
37 .chipver2 = {.phys = ZEUS_ADDR(0x280804)},
38 .chipver1 = {.phys = ZEUS_ADDR(0x280808)},
39 .chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
43 .uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
44 .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
45 .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
46 .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
47 .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
48 .uart1_data = {.phys = ZEUS_ADDR(0x281818)},
49 .uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
50
51 .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
52 .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
53 .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
54 .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
55 .int_config = {.phys = ZEUS_ADDR(0x282810)},
56 .int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
57 .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
58 .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
59 .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
60 .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
61 .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
62 .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
63 .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
64 .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
65 .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
66 .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
67 .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
68 .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
69 .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
70 .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
71 .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
72 .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
73 .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
74 .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
75 .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
76 .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
78
79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80 .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
84 .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
85 .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
86 .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
87 .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
88 .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
89 .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
90 .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
91 .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
92
93 .pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
94 .tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
95 .tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
96 .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
97 .gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
98 .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
99 .watchdog = {.phys = ZEUS_ADDR(0x282c30)},
100 .front_panel = {.phys = ZEUS_ADDR(0x283800)},
101};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
deleted file mode 100644
index 8380605d597d..000000000000
--- a/arch/mips/powertv/asic/asic_devices.c
+++ /dev/null
@@ -1,549 +0,0 @@
1/*
2 *
3 * Description: Defines the platform resources for Gaia-based settops.
4 *
5 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 * NOTE: The bootloader allocates persistent memory at an address which is
22 * 16 MiB below the end of the highest address in KSEG0. All fixed
23 * address memory reservations must avoid this region.
24 */
25
26#include <linux/device.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/resource.h>
30#include <linux/serial_reg.h>
31#include <linux/io.h>
32#include <linux/bootmem.h>
33#include <linux/mm.h>
34#include <linux/platform_device.h>
35#include <linux/module.h>
36#include <asm/page.h>
37#include <linux/swap.h>
38#include <linux/highmem.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/mach-powertv/asic.h>
42#include <asm/mach-powertv/asic_regs.h>
43#include <asm/mach-powertv/interrupts.h>
44
45#ifdef CONFIG_BOOTLOADER_DRIVER
46#include <asm/mach-powertv/kbldr.h>
47#endif
48#include <asm/bootinfo.h>
49
50#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
51
52/*
53 * Forward Prototypes
54 */
55static void pmem_setup_resource(void);
56
57/*
58 * Global Variables
59 */
60enum asic_type asic;
61
62unsigned int platform_features;
63unsigned int platform_family;
64struct register_map _asic_register_map;
65EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
66unsigned long asic_phy_base;
67unsigned long asic_base;
68EXPORT_SYMBOL(asic_base); /* Exported for testing */
69struct resource *gp_resources;
70
71/*
72 * Don't recommend to use it directly, it is usually used by kernel internally.
73 * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
74 */
75unsigned long phys_to_dma_offset;
76EXPORT_SYMBOL(phys_to_dma_offset);
77
78/*
79 *
80 * IO Resource Definition
81 *
82 */
83
84struct resource asic_resource = {
85 .name = "ASIC Resource",
86 .start = 0,
87 .end = ASIC_IO_SIZE,
88 .flags = IORESOURCE_MEM,
89};
90
91/*
92 * Allow override of bootloader-specified model
93 * Returns zero on success, a negative errno value on failure. This parameter
94 * allows overriding of the bootloader-specified model.
95 */
96static char __initdata cmdline[COMMAND_LINE_SIZE];
97
98#define FORCEFAMILY_PARAM "forcefamily"
99
100/*
101 * check_forcefamily - check for, and parse, forcefamily command line parameter
102 * @forced_family: Pointer to two-character array in which to store the
103 * value of the forcedfamily parameter, if any.
104 */
105static __init int check_forcefamily(unsigned char forced_family[2])
106{
107 const char *p;
108
109 forced_family[0] = '\0';
110 forced_family[1] = '\0';
111
112 /* Check the command line for a forcefamily directive */
113 strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
114 p = strstr(cmdline, FORCEFAMILY_PARAM);
115 if (p && (p != cmdline) && (*(p - 1) != ' '))
116 p = strstr(p, " " FORCEFAMILY_PARAM "=");
117
118 if (p) {
119 p += strlen(FORCEFAMILY_PARAM "=");
120
121 if (*p == '\0' || *(p + 1) == '\0' ||
122 (*(p + 2) != '\0' && *(p + 2) != ' '))
123 pr_err(FORCEFAMILY_PARAM " must be exactly two "
124 "characters long, ignoring value\n");
125
126 else {
127 forced_family[0] = *p;
128 forced_family[1] = *(p + 1);
129 }
130 }
131
132 return 0;
133}
134
135/*
136 * platform_set_family - determine major platform family type.
137 *
138 * Returns family type; -1 if none
139 * Returns the family type; -1 if none
140 *
141 */
142static __init noinline void platform_set_family(void)
143{
144 unsigned char forced_family[2];
145 unsigned short bootldr_family;
146
147 if (check_forcefamily(forced_family) == 0)
148 bootldr_family = BOOTLDRFAMILY(forced_family[0],
149 forced_family[1]);
150 else
151 bootldr_family = (unsigned short) BOOTLDRFAMILY(
152 CONFIG_BOOTLOADER_FAMILY[0],
153 CONFIG_BOOTLOADER_FAMILY[1]);
154
155 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
156
157 switch (bootldr_family) {
158 case BOOTLDRFAMILY('R', '1'):
159 platform_family = FAMILY_1500;
160 break;
161 case BOOTLDRFAMILY('4', '4'):
162 platform_family = FAMILY_4500;
163 break;
164 case BOOTLDRFAMILY('4', '6'):
165 platform_family = FAMILY_4600;
166 break;
167 case BOOTLDRFAMILY('A', '1'):
168 platform_family = FAMILY_4600VZA;
169 break;
170 case BOOTLDRFAMILY('8', '5'):
171 platform_family = FAMILY_8500;
172 break;
173 case BOOTLDRFAMILY('R', '2'):
174 platform_family = FAMILY_8500RNG;
175 break;
176 case BOOTLDRFAMILY('8', '6'):
177 platform_family = FAMILY_8600;
178 break;
179 case BOOTLDRFAMILY('B', '1'):
180 platform_family = FAMILY_8600VZB;
181 break;
182 case BOOTLDRFAMILY('E', '1'):
183 platform_family = FAMILY_1500VZE;
184 break;
185 case BOOTLDRFAMILY('F', '1'):
186 platform_family = FAMILY_1500VZF;
187 break;
188 case BOOTLDRFAMILY('8', '7'):
189 platform_family = FAMILY_8700;
190 break;
191 default:
192 platform_family = -1;
193 }
194}
195
196unsigned int platform_get_family(void)
197{
198 return platform_family;
199}
200EXPORT_SYMBOL(platform_get_family);
201
202/*
203 * platform_get_asic - determine the ASIC type.
204 *
205 * Returns the ASIC type, or ASIC_UNKNOWN if unknown
206 *
207 */
208enum asic_type platform_get_asic(void)
209{
210 return asic;
211}
212EXPORT_SYMBOL(platform_get_asic);
213
214/*
215 * set_register_map - set ASIC register configuration
216 * @phys_base: Physical address of the base of the ASIC registers
217 * @map: Description of key ASIC registers
218 */
219static void __init set_register_map(unsigned long phys_base,
220 const struct register_map *map)
221{
222 asic_phy_base = phys_base;
223 _asic_register_map = *map;
224 register_map_virtualize(&_asic_register_map);
225 asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
226}
227
228/**
229 * configure_platform - configuration based on platform type.
230 */
231void __init configure_platform(void)
232{
233 platform_set_family();
234
235 switch (platform_family) {
236 case FAMILY_1500:
237 case FAMILY_1500VZE:
238 case FAMILY_1500VZF:
239 platform_features = FFS_CAPABLE;
240 asic = ASIC_CALLIOPE;
241 set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
242
243 if (platform_family == FAMILY_1500VZE) {
244 gp_resources = non_dvr_vze_calliope_resources;
245 pr_info("Platform: 1500/Vz Class E - "
246 "CALLIOPE, NON_DVR_CAPABLE\n");
247 } else if (platform_family == FAMILY_1500VZF) {
248 gp_resources = non_dvr_vzf_calliope_resources;
249 pr_info("Platform: 1500/Vz Class F - "
250 "CALLIOPE, NON_DVR_CAPABLE\n");
251 } else {
252 gp_resources = non_dvr_calliope_resources;
253 pr_info("Platform: 1500/RNG100 - CALLIOPE, "
254 "NON_DVR_CAPABLE\n");
255 }
256 break;
257
258 case FAMILY_4500:
259 platform_features = FFS_CAPABLE | PCIE_CAPABLE |
260 DISPLAY_CAPABLE;
261 asic = ASIC_ZEUS;
262 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
263 gp_resources = non_dvr_zeus_resources;
264
265 pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
266 break;
267
268 case FAMILY_4600:
269 {
270 unsigned int chipversion = 0;
271
272 /* The settop has PCIE but it isn't used, so don't advertise
273 * it*/
274 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
275
276 /* Cronus and Cronus Lite have the same register map */
277 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
278
279 /* ASIC version will determine if this is a real CronusLite or
280 * Castrati(Cronus) */
281 chipversion = asic_read(chipver3) << 24;
282 chipversion |= asic_read(chipver2) << 16;
283 chipversion |= asic_read(chipver1) << 8;
284 chipversion |= asic_read(chipver0);
285
286 if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
287 asic = ASIC_CRONUS;
288 else
289 asic = ASIC_CRONUSLITE;
290
291 gp_resources = non_dvr_cronuslite_resources;
292 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
293 "chipversion=0x%08X\n",
294 (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
295 chipversion);
296 break;
297 }
298 case FAMILY_4600VZA:
299 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
300 asic = ASIC_CRONUS;
301 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
302 gp_resources = non_dvr_cronus_resources;
303
304 pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
305 break;
306
307 case FAMILY_8500:
308 case FAMILY_8500RNG:
309 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
310 DISPLAY_CAPABLE;
311 asic = ASIC_ZEUS;
312 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
313 gp_resources = dvr_zeus_resources;
314
315 pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
316 break;
317
318 case FAMILY_8600:
319 case FAMILY_8600VZB:
320 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
321 DISPLAY_CAPABLE;
322 asic = ASIC_CRONUS;
323 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
324 gp_resources = dvr_cronus_resources;
325
326 pr_info("Platform: 8600/Vz Class B - CRONUS, "
327 "DVR_CAPABLE\n");
328 break;
329
330 case FAMILY_8700:
331 platform_features = FFS_CAPABLE | PCIE_CAPABLE;
332 asic = ASIC_GAIA;
333 set_register_map(GAIA_IO_BASE, &gaia_register_map);
334 gp_resources = dvr_gaia_resources;
335
336 pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
337 break;
338
339 default:
340 pr_crit("Platform: UNKNOWN PLATFORM\n");
341 break;
342 }
343
344 switch (asic) {
345 case ASIC_ZEUS:
346 phys_to_dma_offset = 0x30000000;
347 break;
348 case ASIC_CALLIOPE:
349 phys_to_dma_offset = 0x10000000;
350 break;
351 case ASIC_CRONUSLITE:
352 /* Fall through */
353 case ASIC_CRONUS:
354 /*
355 * TODO: We suppose 0x10000000 aliases into 0x20000000-
356 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
357 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
358 */
359 phys_to_dma_offset = 0x10000000;
360 break;
361 default:
362 phys_to_dma_offset = 0x00000000;
363 break;
364 }
365}
366
367/*
368 * RESOURCE ALLOCATION
369 *
370 */
371/*
372 * Allocates/reserves the Platform memory resources early in the boot process.
373 * This ignores any resources that are designated IORESOURCE_IO
374 */
375void __init platform_alloc_bootmem(void)
376{
377 int i;
378 int total = 0;
379
380 /* Get persistent memory data from command line before allocating
381 * resources. This need to happen before normal command line parsing
382 * has been done */
383 pmem_setup_resource();
384
385 /* Loop through looking for resources that want a particular address */
386 for (i = 0; gp_resources[i].flags != 0; i++) {
387 int size = resource_size(&gp_resources[i]);
388 if ((gp_resources[i].start != 0) &&
389 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
390 reserve_bootmem(dma_to_phys(gp_resources[i].start),
391 size, 0);
392 total += resource_size(&gp_resources[i]);
393 pr_info("reserve resource %s at %08x (%u bytes)\n",
394 gp_resources[i].name, gp_resources[i].start,
395 resource_size(&gp_resources[i]));
396 }
397 }
398
399 /* Loop through assigning addresses for those that are left */
400 for (i = 0; gp_resources[i].flags != 0; i++) {
401 int size = resource_size(&gp_resources[i]);
402 if ((gp_resources[i].start == 0) &&
403 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
404 void *mem = alloc_bootmem_pages(size);
405
406 if (mem == NULL)
407 pr_err("Unable to allocate bootmem pages "
408 "for %s\n", gp_resources[i].name);
409
410 else {
411 gp_resources[i].start =
412 phys_to_dma(virt_to_phys(mem));
413 gp_resources[i].end =
414 gp_resources[i].start + size - 1;
415 total += size;
416 pr_info("allocate resource %s at %08x "
417 "(%u bytes)\n",
418 gp_resources[i].name,
419 gp_resources[i].start, size);
420 }
421 }
422 }
423
424 pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
425
426 /* indicate resources that are platform I/O related */
427 for (i = 0; gp_resources[i].flags != 0; i++) {
428 if ((gp_resources[i].start != 0) &&
429 ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
430 pr_info("reserved platform resource %s at %08x\n",
431 gp_resources[i].name, gp_resources[i].start);
432 }
433 }
434}
435
436/*
437 *
438 * PERSISTENT MEMORY (PMEM) CONFIGURATION
439 *
440 */
441static unsigned long pmemaddr __initdata;
442
443static int __init early_param_pmemaddr(char *p)
444{
445 pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
446 return 0;
447}
448early_param("pmemaddr", early_param_pmemaddr);
449
450static long pmemlen __initdata;
451
452static int __init early_param_pmemlen(char *p)
453{
454/* TODO: we can use this code when and if the bootloader ever changes this */
455#if 0
456 pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
457#else
458 pmemlen = 0x20000;
459#endif
460 return 0;
461}
462early_param("pmemlen", early_param_pmemlen);
463
464/*
465 * Set up persistent memory. If we were given values, we patch the array of
466 * resources. Otherwise, persistent memory may be allocated anywhere at all.
467 */
468static void __init pmem_setup_resource(void)
469{
470 struct resource *resource;
471 resource = asic_resource_get("DiagPersistentMemory");
472
473 if (resource && pmemaddr && pmemlen) {
474 /* The address provided by bootloader is in kseg0. Convert to
475 * a bus address. */
476 resource->start = phys_to_dma(pmemaddr - 0x80000000);
477 resource->end = resource->start + pmemlen - 1;
478
479 pr_info("persistent memory: start=0x%x end=0x%x\n",
480 resource->start, resource->end);
481 }
482}
483
484/*
485 *
486 * RESOURCE ACCESS FUNCTIONS
487 *
488 */
489
490/**
491 * asic_resource_get - retrieves parameters for a platform resource.
492 * @name: string to match resource
493 *
494 * Returns a pointer to a struct resource corresponding to the given name.
495 *
496 * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
497 * as this function name is already declared
498 */
499struct resource *asic_resource_get(const char *name)
500{
501 int i;
502
503 for (i = 0; gp_resources[i].flags != 0; i++) {
504 if (strcmp(gp_resources[i].name, name) == 0)
505 return &gp_resources[i];
506 }
507
508 return NULL;
509}
510EXPORT_SYMBOL(asic_resource_get);
511
512/**
513 * platform_release_memory - release pre-allocated memory
514 * @ptr: pointer to memory to release
515 * @size: size of resource
516 *
517 * This must only be called for memory allocated or reserved via the boot
518 * memory allocator.
519 */
520void platform_release_memory(void *ptr, int size)
521{
522 free_reserved_area(ptr, ptr + size, -1, NULL);
523}
524EXPORT_SYMBOL(platform_release_memory);
525
526/*
527 *
528 * FEATURE AVAILABILITY FUNCTIONS
529 *
530 */
531int platform_supports_dvr(void)
532{
533 return (platform_features & DVR_CAPABLE) != 0;
534}
535
536int platform_supports_ffs(void)
537{
538 return (platform_features & FFS_CAPABLE) != 0;
539}
540
541int platform_supports_pcie(void)
542{
543 return (platform_features & PCIE_CAPABLE) != 0;
544}
545
546int platform_supports_display(void)
547{
548 return (platform_features & DISPLAY_CAPABLE) != 0;
549}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
deleted file mode 100644
index f44cd9295cae..000000000000
--- a/arch/mips/powertv/asic/asic_int.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 * Portions copyright (C) 2009 Cisco Systems, Inc.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Routines for generic manipulation of the interrupts found on the PowerTV
21 * platform.
22 *
23 * The interrupt controller is located in the South Bridge a PIIX4 device
24 * with two internal 82C95 interrupt controllers.
25 */
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/kernel.h>
32#include <linux/random.h>
33
34#include <asm/irq_cpu.h>
35#include <linux/io.h>
36#include <asm/irq_regs.h>
37#include <asm/setup.h>
38#include <asm/mips-boards/generic.h>
39
40#include <asm/mach-powertv/asic_regs.h>
41
42static DEFINE_RAW_SPINLOCK(asic_irq_lock);
43
44static inline int get_int(void)
45{
46 unsigned long flags;
47 int irq;
48
49 raw_spin_lock_irqsave(&asic_irq_lock, flags);
50
51 irq = (asic_read(int_int_scan) >> 4) - 1;
52
53 if (irq == 0 || irq >= NR_IRQS)
54 irq = -1;
55
56 raw_spin_unlock_irqrestore(&asic_irq_lock, flags);
57
58 return irq;
59}
60
61static void asic_irqdispatch(void)
62{
63 int irq;
64
65 irq = get_int();
66 if (irq < 0)
67 return; /* interrupt has already been cleared */
68
69 do_IRQ(irq);
70}
71
72static inline int clz(unsigned long x)
73{
74 __asm__(
75 " .set push \n"
76 " .set mips32 \n"
77 " clz %0, %1 \n"
78 " .set pop \n"
79 : "=r" (x)
80 : "r" (x));
81
82 return x;
83}
84
85/*
86 * Version of ffs that only looks at bits 12..15.
87 */
88static inline unsigned int irq_ffs(unsigned int pending)
89{
90 return fls(pending) - 1 + CAUSEB_IP;
91}
92
93/*
94 * TODO: check how it works under EIC mode.
95 */
96asmlinkage void plat_irq_dispatch(void)
97{
98 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
99 int irq;
100
101 irq = irq_ffs(pending);
102
103 if (irq == CAUSEF_IP3)
104 asic_irqdispatch();
105 else if (irq >= 0)
106 do_IRQ(irq);
107 else
108 spurious_interrupt();
109}
110
111void __init arch_init_irq(void)
112{
113 int i;
114
115 asic_irq_init();
116
117 /*
118 * Initialize interrupt exception vectors.
119 */
120 if (cpu_has_veic || cpu_has_vint) {
121 int nvec = cpu_has_veic ? 64 : 8;
122 for (i = 0; i < nvec; i++)
123 set_vi_handler(i, asic_irqdispatch);
124 }
125}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
deleted file mode 100644
index 9344902dc586..000000000000
--- a/arch/mips/powertv/asic/irq_asic.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Portions copyright (C) 2005-2009 Scientific Atlanta
3 * Portions copyright (C) 2009 Cisco Systems, Inc.
4 *
5 * Modified from arch/mips/kernel/irq-rm7000.c:
6 * Copyright (C) 2003 Ralf Baechle
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/irq.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21#include <asm/mach-powertv/asic_regs.h>
22
23static inline void unmask_asic_irq(struct irq_data *d)
24{
25 unsigned long enable_bit;
26 unsigned int irq = d->irq;
27
28 enable_bit = (1 << (irq & 0x1f));
29
30 switch (irq >> 5) {
31 case 0:
32 asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
33 break;
34 case 1:
35 asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
36 break;
37 case 2:
38 asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
39 break;
40 case 3:
41 asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
42 break;
43 default:
44 BUG();
45 }
46}
47
48static inline void mask_asic_irq(struct irq_data *d)
49{
50 unsigned long disable_mask;
51 unsigned int irq = d->irq;
52
53 disable_mask = ~(1 << (irq & 0x1f));
54
55 switch (irq >> 5) {
56 case 0:
57 asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
58 break;
59 case 1:
60 asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
61 break;
62 case 2:
63 asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
64 break;
65 case 3:
66 asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
67 break;
68 default:
69 BUG();
70 }
71}
72
73static struct irq_chip asic_irq_chip = {
74 .name = "ASIC Level",
75 .irq_mask = mask_asic_irq,
76 .irq_unmask = unmask_asic_irq,
77};
78
79void __init asic_irq_init(void)
80{
81 int i;
82
83 /* set priority to 0 */
84 write_c0_status(read_c0_status() & ~(0x0000fc00));
85
86 asic_write(0, ien_int_0);
87 asic_write(0, ien_int_1);
88 asic_write(0, ien_int_2);
89 asic_write(0, ien_int_3);
90
91 asic_write(0x0fffffff, int_level_3_3);
92 asic_write(0xffffffff, int_level_3_2);
93 asic_write(0xffffffff, int_level_3_1);
94 asic_write(0xffffffff, int_level_3_0);
95 asic_write(0xffffffff, int_level_2_3);
96 asic_write(0xffffffff, int_level_2_2);
97 asic_write(0xffffffff, int_level_2_1);
98 asic_write(0xffffffff, int_level_2_0);
99 asic_write(0xffffffff, int_level_1_3);
100 asic_write(0xffffffff, int_level_1_2);
101 asic_write(0xffffffff, int_level_1_1);
102 asic_write(0xffffffff, int_level_1_0);
103 asic_write(0xffffffff, int_level_0_3);
104 asic_write(0xffffffff, int_level_0_2);
105 asic_write(0xffffffff, int_level_0_1);
106 asic_write(0xffffffff, int_level_0_0);
107
108 asic_write(0xf, int_int_scan);
109
110 /*
111 * Initialize interrupt handlers.
112 */
113 for (i = 0; i < NR_IRQS; i++)
114 irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
115}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
deleted file mode 100644
index 98dc51650577..000000000000
--- a/arch/mips/powertv/asic/prealloc-calliope.c
+++ /dev/null
@@ -1,385 +0,0 @@
1/*
2 * Memory pre-allocations for Calliope boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * NON_DVR_CAPABLE CALLIOPE RESOURCES
31 */
32struct resource non_dvr_calliope_resources[] __initdata =
33{
34 /*
35 * VIDEO / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~36.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26700000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * Sysaudio Driver
49 */
50 /* DSP code and data images (1MiB) */
51 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
52 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
53 /* ADSC CPU PCM buffer (40KiB) */
54 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
55 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
56 /* ADSC AUX buffer (128KiB) */
57 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
58 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
59 /* ADSC Main buffer (128KiB) */
60 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
61 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
62
63 /*
64 * STAVEM driver/STAPI
65 */
66 /* 6MiB */
67 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69
70 /*
71 * DOCSIS Subsystem
72 */
73 /* 7MiB */
74 PREALLOC_DOCSIS("Docsis", 0x27500000, 0x27c00000-1, IORESOURCE_MEM)
75
76 /*
77 * GHW HAL Driver
78 */
79 /* PowerTV Graphics Heap (14MiB) */
80 PREALLOC_NORMAL("GraphicsHeap", 0x26700000, 0x26700000+(14*1048576)-1,
81 IORESOURCE_MEM)
82
83 /*
84 * multi com buffer area
85 */
86 /* 128KiB */
87 PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1,
88 IORESOURCE_MEM)
89
90 /*
91 * DMA Ring buffer (don't need recording buffers)
92 */
93 /* 680KiB */
94 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
95 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
96
97 /*
98 * Display bins buffer for unit0
99 */
100 /* 4KiB */
101 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
102 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
103
104 /*
105 * AVFS: player HAL memory
106 */
107 /* 945K * 3 for playback */
108 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
109 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
110
111 /*
112 * PMEM
113 */
114 /* Persistent memory for diagnostics (64KiB) */
115 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
116 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
117
118 /*
119 * Smartcard
120 */
121 /* Read and write buffers for Internal/External cards (10KiB) */
122 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
123 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
124
125 /*
126 * NAND Flash
127 */
128 /* 10KiB */
129 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
130 IORESOURCE_MEM)
131
132 /*
133 * Synopsys GMAC Memory Region
134 */
135 /* 64KiB */
136 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
137 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
138
139 /*
140 * TFTPBuffer
141 *
142 * This buffer is used in some minimal configurations (e.g. two-way
143 * loader) for storing software images
144 */
145 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
146 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
147
148 /*
149 * Add other resources here
150 */
151
152 /*
153 * End of Resource marker
154 */
155 {
156 .flags = 0,
157 },
158};
159
160
161struct resource non_dvr_vze_calliope_resources[] __initdata =
162{
163 /*
164 * VIDEO / LX1
165 */
166 /* Delta-Mu 1 image (2MiB) */
167 PREALLOC_NORMAL("ST231aImage", 0x22000000, 0x22200000-1,
168 IORESOURCE_MEM)
169 /* Delta-Mu 1 monitor (8KiB) */
170 PREALLOC_NORMAL("ST231aMonitor", 0x22200000, 0x22202000-1,
171 IORESOURCE_MEM)
172 /* Delta-Mu 1 RAM (10.12MiB) */
173 PREALLOC_NORMAL("MediaMemory1", 0x22202000, 0x22C20B85-1,
174 IORESOURCE_MEM)
175
176 /*
177 * Sysaudio Driver
178 */
179 /* DSP code and data images (1MiB) */
180 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
181 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
182 /* ADSC CPU PCM buffer (40KiB) */
183 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
184 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
185 /* ADSC AUX buffer (16KiB) */
186 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
187 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
188 /* ADSC Main buffer (16KiB) */
189 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
190 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
191
192 /*
193 * STAVEM driver/STAPI
194 */
195 /* 3.125MiB */
196 PREALLOC_NORMAL("AVMEMPartition0", 0x20396000, 0x206B6000-1,
197 IORESOURCE_MEM)
198
199 /*
200 * GHW HAL Driver
201 */
202 /* PowerTV Graphics Heap (2.59MiB) */
203 PREALLOC_NORMAL("GraphicsHeap", 0x20100000, 0x20396000-1,
204 IORESOURCE_MEM)
205
206 /*
207 * multi com buffer area
208 */
209 /* 128KiB */
210 PREALLOC_NORMAL("MulticomSHM", 0x206B6000, 0x206D6000-1,
211 IORESOURCE_MEM)
212
213 /*
214 * DMA Ring buffer (don't need recording buffers)
215 */
216 /* 680KiB */
217 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
218 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
219
220 /*
221 * Display bins buffer for unit0
222 */
223 /* 4KiB */
224 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
225 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
226
227 /*
228 * PMEM
229 */
230 /* Persistent memory for diagnostics (64KiB) */
231 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
232 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
233
234 /*
235 * Smartcard
236 */
237 /* Read and write buffers for Internal/External cards (10KiB) */
238 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
239 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
240
241 /*
242 * NAND Flash
243 */
244 /* 10KiB */
245 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
246 IORESOURCE_MEM)
247
248 /*
249 * Synopsys GMAC Memory Region
250 */
251 /* 64KiB */
252 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
253 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
254
255 /*
256 * Add other resources here
257 */
258
259 /*
260 * End of Resource marker
261 */
262 {
263 .flags = 0,
264 },
265};
266
267struct resource non_dvr_vzf_calliope_resources[] __initdata =
268{
269 /*
270 * VIDEO / LX1
271 */
272 /* Delta-Mu 1 image (2MiB) */
273 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
274 IORESOURCE_MEM)
275 /* Delta-Mu 1 monitor (8KiB) */
276 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
277 IORESOURCE_MEM)
278 /* Delta-Mu 1 RAM (~19.4 (21.5MiB - (2MiB + 8KiB))) */
279 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25580000-1,
280 IORESOURCE_MEM)
281
282 /*
283 * Sysaudio Driver
284 */
285 /* DSP code and data images (1MiB) */
286 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
287 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
288 /* ADSC CPU PCM buffer (40KiB) */
289 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
290 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
291 /* ADSC AUX buffer (128KiB) */
292 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
293 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
294 /* ADSC Main buffer (128KiB) */
295 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
296 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
297
298 /*
299 * STAVEM driver/STAPI
300 */
301 /* 4.5MiB */
302 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00480000-1,
303 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
304
305 /*
306 * GHW HAL Driver
307 */
308 /* PowerTV Graphics Heap (14MiB) */
309 PREALLOC_NORMAL("GraphicsHeap", 0x25600000, 0x25600000+(14*1048576)-1,
310 IORESOURCE_MEM)
311
312 /*
313 * multi com buffer area
314 */
315 /* 128KiB */
316 PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1,
317 IORESOURCE_MEM)
318
319 /*
320 * DMA Ring buffer (don't need recording buffers)
321 */
322 /* 680KiB */
323 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
324 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
325
326 /*
327 * Display bins buffer for unit0
328 */
329 /* 4KiB */
330 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
331 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
332
333 /*
334 * Display bins buffer for unit1
335 */
336 /* 4KiB */
337 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
338 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
339
340 /*
341 * AVFS: player HAL memory
342 */
343 /* 945K * 3 for playback */
344 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
345 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
346
347 /*
348 * PMEM
349 */
350 /* Persistent memory for diagnostics (64KiB) */
351 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
352 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
353
354 /*
355 * Smartcard
356 */
357 /* Read and write buffers for Internal/External cards (10KiB) */
358 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
359 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
360
361 /*
362 * NAND Flash
363 */
364 /* 10KiB */
365 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
366 IORESOURCE_MEM)
367
368 /*
369 * Synopsys GMAC Memory Region
370 */
371 /* 64KiB */
372 PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1,
373 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
374
375 /*
376 * Add other resources here
377 */
378
379 /*
380 * End of Resource marker
381 */
382 {
383 .flags = 0,
384 },
385};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
deleted file mode 100644
index 7c6ce7596935..000000000000
--- a/arch/mips/powertv/asic/prealloc-cronus.c
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * Memory pre-allocations for Cronus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * DVR_CAPABLE CRONUS RESOURCES
31 */
32struct resource dvr_cronus_resources[] __initdata =
33{
34 /*
35 * VIDEO1 / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * VIDEO2 / LX2
49 */
50 /* Delta-Mu 2 image (2MiB) */
51 PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1,
52 IORESOURCE_MEM)
53 /* Delta-Mu 2 monitor (8KiB) */
54 PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1,
55 IORESOURCE_MEM)
56 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
57 PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1,
58 IORESOURCE_MEM)
59
60 /*
61 * Sysaudio Driver
62 */
63 /* DSP code and data images (1MiB) */
64 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
65 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
66 /* ADSC CPU PCM buffer (40KiB) */
67 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69 /* ADSC AUX buffer (128KiB) */
70 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
71 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
72 /* ADSC Main buffer (128KiB) */
73 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
74 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
75
76 /*
77 * STAVEM driver/STAPI
78 *
79 * This memory area is used for allocating buffers for Video decoding
80 * purposes. Allocation/De-allocation within this buffer is managed
81 * by the STAVMEM driver of the STAPI. They could be Decimated
82 * Picture Buffers, Intermediate Buffers, as deemed necessary for
83 * video decoding purposes, for any video decoders on Zeus.
84 */
85 /* 12MiB */
86 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
87 IORESOURCE_MEM)
88
89 /*
90 * DOCSIS Subsystem
91 */
92 /* 7MiB */
93 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
94
95 /*
96 * GHW HAL Driver
97 */
98 /* PowerTV Graphics Heap (14MiB) */
99 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
100 IORESOURCE_MEM)
101
102 /*
103 * multi com buffer area
104 */
105 /* 128KiB */
106 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
107 IORESOURCE_MEM)
108
109 /*
110 * DMA Ring buffer
111 */
112 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x002EA000-1,
113 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
114
115 /*
116 * Display bins buffer for unit0
117 */
118 /* 4KiB */
119 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
120 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
121
122 /*
123 * Display bins buffer for unit1
124 */
125 /* 4KiB */
126 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
127 IORESOURCE_MEM)
128
129 /*
130 * ITFS
131 */
132 /* 815,104 bytes each for 2 ITFS partitions. */
133 PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, IORESOURCE_MEM)
134
135 /*
136 * AVFS
137 */
138 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
139 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1,
140 IORESOURCE_MEM)
141
142 /* 4KiB */
143 PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1,
144 IORESOURCE_MEM)
145
146 /*
147 * PMEM
148 */
149 /* Persistent memory for diagnostics (64KiB) */
150 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
151 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
152
153 /*
154 * Smartcard
155 */
156 /* Read and write buffers for Internal/External cards (10KiB) */
157 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
158 IORESOURCE_MEM)
159
160 /*
161 * KAVNET
162 */
163 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
164 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
165 IORESOURCE_MEM)
166 /* NP Image - must be video bank 1 (320KiB) */
167 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
168 /* NP IPC - must be video bank 2 (512KiB) */
169 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
170
171 /*
172 * TFTPBuffer
173 *
174 * This buffer is used in some minimal configurations (e.g. two-way
175 * loader) for storing software images
176 */
177 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
178 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
179
180 /*
181 * Add other resources here
182 */
183
184 /*
185 * End of Resource marker
186 */
187 {
188 .flags = 0,
189 },
190};
191
192/*
193 * NON_DVR_CAPABLE CRONUS RESOURCES
194 */
195struct resource non_dvr_cronus_resources[] __initdata =
196{
197 /*
198 * VIDEO1 / LX1
199 */
200 /* Delta-Mu 1 image (2MiB) */
201 PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1,
202 IORESOURCE_MEM)
203 /* Delta-Mu 1 monitor (8KiB) */
204 PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1,
205 IORESOURCE_MEM)
206 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
207 PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1,
208 IORESOURCE_MEM)
209
210 /*
211 * VIDEO2 / LX2
212 */
213 /* Delta-Mu 2 image (2MiB) */
214 PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1,
215 IORESOURCE_MEM)
216 /* Delta-Mu 2 monitor (8KiB) */
217 PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1,
218 IORESOURCE_MEM)
219 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
220 PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1,
221 IORESOURCE_MEM)
222
223 /*
224 * Sysaudio Driver
225 */
226 /* DSP code and data images (1MiB) */
227 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
228 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
229 /* ADSC CPU PCM buffer (40KiB) */
230 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
231 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
232 /* ADSC AUX buffer (128KiB) */
233 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
234 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
235 /* ADSC Main buffer (128KiB) */
236 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
237 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
238
239 /*
240 * STAVEM driver/STAPI
241 *
242 * This memory area is used for allocating buffers for Video decoding
243 * purposes. Allocation/De-allocation within this buffer is managed
244 * by the STAVMEM driver of the STAPI. They could be Decimated
245 * Picture Buffers, Intermediate Buffers, as deemed necessary for
246 * video decoding purposes, for any video decoders on Zeus.
247 */
248 /* 12MiB */
249 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
250 IORESOURCE_MEM)
251
252 /*
253 * DOCSIS Subsystem
254 */
255 /* 7MiB */
256 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
257
258 /*
259 * GHW HAL Driver
260 */
261 /* PowerTV Graphics Heap (14MiB) */
262 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
263 IORESOURCE_MEM)
264
265 /*
266 * multi com buffer area
267 */
268 /* 128KiB */
269 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
270 IORESOURCE_MEM)
271
272 /*
273 * DMA Ring buffer (don't need recording buffers)
274 */
275 /* 680KiB */
276 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
277 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
278
279 /*
280 * Display bins buffer for unit0
281 */
282 /* 4KiB */
283 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
284 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
285
286 /*
287 * Display bins buffer for unit1
288 */
289 /* 4KiB */
290 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
291 IORESOURCE_MEM)
292
293 /*
294 * AVFS: player HAL memory
295 */
296 /* 945K * 3 for playback */
297 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, IORESOURCE_MEM)
298
299 /*
300 * PMEM
301 */
302 /* Persistent memory for diagnostics (64KiB) */
303 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
304 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
305
306 /*
307 * Smartcard
308 */
309 /* Read and write buffers for Internal/External cards (10KiB) */
310 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM)
311
312 /*
313 * KAVNET
314 */
315 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
316 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
317 IORESOURCE_MEM)
318 /* NP Image - must be video bank 1 (320KiB) */
319 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
320 /* NP IPC - must be video bank 2 (512KiB) */
321 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
322
323 /*
324 * NAND Flash
325 */
326 /* 10KiB */
327 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
328 IORESOURCE_MEM)
329
330 /*
331 * Add other resources here
332 */
333
334 /*
335 * End of Resource marker
336 */
337 {
338 .flags = 0,
339 },
340};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
deleted file mode 100644
index a7937ba7b4c0..000000000000
--- a/arch/mips/powertv/asic/prealloc-cronuslite.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * Memory pre-allocations for Cronus Lite boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * NON_DVR_CAPABLE CRONUSLITE RESOURCES
31 */
32struct resource non_dvr_cronuslite_resources[] __initdata =
33{
34 /*
35 * VIDEO2 / LX2
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x60000000, 0x60200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x60200000, 0x60202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x60202000, 0x62000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * Sysaudio Driver
49 */
50 /* DSP code and data images (1MiB) */
51 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
52 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
53 /* ADSC CPU PCM buffer (40KiB) */
54 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
55 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
56 /* ADSC AUX buffer (128KiB) */
57 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1,
58 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
59 /* ADSC Main buffer (128KiB) */
60 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1,
61 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
62
63 /*
64 * STAVEM driver/STAPI
65 *
66 * This memory area is used for allocating buffers for Video decoding
67 * purposes. Allocation/De-allocation within this buffer is managed
68 * by the STAVMEM driver of the STAPI. They could be Decimated
69 * Picture Buffers, Intermediate Buffers, as deemed necessary for
70 * video decoding purposes, for any video decoders on Zeus.
71 */
72 /* 6MiB */
73 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
74 IORESOURCE_MEM)
75
76 /*
77 * DOCSIS Subsystem
78 */
79 /* 7MiB */
80 PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM)
81
82 /*
83 * GHW HAL Driver
84 */
85 /* PowerTV Graphics Heap (14MiB) */
86 PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1,
87 IORESOURCE_MEM)
88
89 /*
90 * multi com buffer area
91 */
92 /* 128KiB */
93 PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1,
94 IORESOURCE_MEM)
95
96 /*
97 * DMA Ring buffer (don't need recording buffers)
98 */
99 /* 680KiB */
100 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1,
101 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
102
103 /*
104 * Display bins buffer for unit0
105 */
106 /* 4KiB */
107 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
108 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
109
110 /*
111 * Display bins buffer for unit1
112 */
113 /* 4KiB */
114 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
115 IORESOURCE_MEM)
116
117 /*
118 * AVFS: player HAL memory
119 */
120 /* 945K * 3 for playback */
121 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
122 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
123
124 /*
125 * PMEM
126 */
127 /* Persistent memory for diagnostics (64KiB) */
128 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
129 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
130
131 /*
132 * Smartcard
133 */
134 /* Read and write buffers for Internal/External cards (10KiB) */
135 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM)
136
137 /*
138 * KAVNET
139 */
140 /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */
141 PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1,
142 IORESOURCE_MEM)
143 /* NP Image - must be video bank 1 (320KiB) */
144 PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM)
145 /* NP IPC - must be video bank 2 (512KiB) */
146 PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM)
147
148 /*
149 * NAND Flash
150 */
151 /* 10KiB */
152 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
153 IORESOURCE_MEM)
154
155 /*
156 * TFTPBuffer
157 *
158 * This buffer is used in some minimal configurations (e.g. two-way
159 * loader) for storing software images
160 */
161 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
162 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
163
164 /*
165 * Add other resources here
166 */
167
168 /*
169 * End of Resource marker
170 */
171 {
172 .flags = 0,
173 },
174};
diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
deleted file mode 100644
index 2303bbfe6b82..000000000000
--- a/arch/mips/powertv/asic/prealloc-gaia.c
+++ /dev/null
@@ -1,589 +0,0 @@
1/*
2 * Memory pre-allocations for Gaia boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26/*
27 * DVR_CAPABLE GAIA RESOURCES
28 */
29struct resource dvr_gaia_resources[] __initdata = {
30 /*
31 *
32 * VIDEO1 / LX1
33 *
34 */
35 {
36 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
37 .start = 0x24000000,
38 .end = 0x241FFFFF, /* 2MiB */
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
43 .start = 0x24200000,
44 .end = 0x24201FFF,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .name = "MediaMemory1",
49 .start = 0x24202000,
50 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
51 .flags = IORESOURCE_MEM,
52 },
53 /*
54 *
55 * VIDEO2 / LX2
56 *
57 */
58 {
59 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
60 .start = 0x60000000,
61 .end = 0x601FFFFF, /* 2MiB */
62 .flags = IORESOURCE_IO,
63 },
64 {
65 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
66 .start = 0x60200000,
67 .end = 0x60201FFF,
68 .flags = IORESOURCE_IO,
69 },
70 {
71 .name = "MediaMemory2",
72 .start = 0x60202000,
73 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
74 .flags = IORESOURCE_IO,
75 },
76 /*
77 *
78 * Sysaudio Driver
79 *
80 * This driver requires:
81 *
82 * Arbitrary Based Buffers:
83 * DSP_Image_Buff - DSP code and data images (1MB)
84 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
85 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
86 * ADSC_Main_Buff - ADSC Main buffer (16KB)
87 *
88 */
89 {
90 .name = "DSP_Image_Buff",
91 .start = 0x00000000,
92 .end = 0x000FFFFF,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "ADSC_CPU_PCM_Buff",
97 .start = 0x00000000,
98 .end = 0x00009FFF,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .name = "ADSC_AUX_Buff",
103 .start = 0x00000000,
104 .end = 0x00003FFF,
105 .flags = IORESOURCE_MEM,
106 },
107 {
108 .name = "ADSC_Main_Buff",
109 .start = 0x00000000,
110 .end = 0x00003FFF,
111 .flags = IORESOURCE_MEM,
112 },
113 /*
114 *
115 * STAVEM driver/STAPI
116 *
117 * This driver requires:
118 *
119 * Arbitrary Based Buffers:
120 * This memory area is used for allocating buffers for Video decoding
121 * purposes. Allocation/De-allocation within this buffer is managed
122 * by the STAVMEM driver of the STAPI. They could be Decimated
123 * Picture Buffers, Intermediate Buffers, as deemed necessary for
124 * video decoding purposes, for any video decoders on Zeus.
125 *
126 */
127 {
128 .name = "AVMEMPartition0",
129 .start = 0x63580000,
130 .end = 0x64180000 - 1, /* 12 MB total */
131 .flags = IORESOURCE_IO,
132 },
133 /*
134 *
135 * DOCSIS Subsystem
136 *
137 * This driver requires:
138 *
139 * Arbitrary Based Buffers:
140 * Docsis -
141 *
142 */
143 {
144 .name = "Docsis",
145 .start = 0x62000000,
146 .end = 0x62700000 - 1, /* 7 MB total */
147 .flags = IORESOURCE_IO,
148 },
149 /*
150 *
151 * GHW HAL Driver
152 *
153 * This driver requires:
154 *
155 * Arbitrary Based Buffers:
156 * GraphicsHeap - PowerTV Graphics Heap
157 *
158 */
159 {
160 .name = "GraphicsHeap",
161 .start = 0x62700000,
162 .end = 0x63500000 - 1, /* 14 MB total */
163 .flags = IORESOURCE_IO,
164 },
165 /*
166 *
167 * multi com buffer area
168 *
169 * This driver requires:
170 *
171 * Arbitrary Based Buffers:
172 * Docsis -
173 *
174 */
175 {
176 .name = "MulticomSHM",
177 .start = 0x26000000,
178 .end = 0x26020000 - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 /*
182 *
183 * DMA Ring buffer
184 *
185 * This driver requires:
186 *
187 * Arbitrary Based Buffers:
188 * Docsis -
189 *
190 */
191 {
192 .name = "BMM_Buffer",
193 .start = 0x00000000,
194 .end = 0x00280000 - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 /*
198 *
199 * Display bins buffer for unit0
200 *
201 * This driver requires:
202 *
203 * Arbitrary Based Buffers:
204 * Display Bins for unit0
205 *
206 */
207 {
208 .name = "DisplayBins0",
209 .start = 0x00000000,
210 .end = 0x00000FFF, /* 4 KB total */
211 .flags = IORESOURCE_MEM,
212 },
213 /*
214 *
215 * Display bins buffer
216 *
217 * This driver requires:
218 *
219 * Arbitrary Based Buffers:
220 * Display Bins for unit1
221 *
222 */
223 {
224 .name = "DisplayBins1",
225 .start = 0x64AD4000,
226 .end = 0x64AD5000 - 1, /* 4 KB total */
227 .flags = IORESOURCE_IO,
228 },
229 /*
230 *
231 * ITFS
232 *
233 * This driver requires:
234 *
235 * Arbitrary Based Buffers:
236 * Docsis -
237 *
238 */
239 {
240 .name = "ITFS",
241 .start = 0x64180000,
242 /* 815,104 bytes each for 2 ITFS partitions. */
243 .end = 0x6430DFFF,
244 .flags = IORESOURCE_IO,
245 },
246 /*
247 *
248 * AVFS
249 *
250 * This driver requires:
251 *
252 * Arbitrary Based Buffers:
253 * Docsis -
254 *
255 */
256 {
257 .name = "AvfsDmaMem",
258 .start = 0x6430E000,
259 /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
260 .end = 0x64AD0000 - 1,
261 .flags = IORESOURCE_IO,
262 },
263 {
264 .name = "AvfsFileSys",
265 .start = 0x64AD0000,
266 .end = 0x64AD1000 - 1, /* 4K */
267 .flags = IORESOURCE_IO,
268 },
269 /*
270 *
271 * Smartcard
272 *
273 * This driver requires:
274 *
275 * Arbitrary Based Buffers:
276 * Read and write buffers for Internal/External cards
277 *
278 */
279 {
280 .name = "SmartCardInfo",
281 .start = 0x64AD1000,
282 .end = 0x64AD3800 - 1,
283 .flags = IORESOURCE_IO,
284 },
285 /*
286 *
287 * KAVNET
288 * NP Reset Vector - must be of the form xxCxxxxx
289 * NP Image - must be video bank 1
290 * NP IPC - must be video bank 2
291 */
292 {
293 .name = "NP_Reset_Vector",
294 .start = 0x27c00000,
295 .end = 0x27c01000 - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "NP_Image",
300 .start = 0x27020000,
301 .end = 0x27060000 - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .name = "NP_IPC",
306 .start = 0x63500000,
307 .end = 0x63580000 - 1,
308 .flags = IORESOURCE_IO,
309 },
310 /*
311 * Add other resources here
312 */
313 { },
314};
315
316/*
317 * NON_DVR_CAPABLE GAIA RESOURCES
318 */
319struct resource non_dvr_gaia_resources[] __initdata = {
320 /*
321 *
322 * VIDEO1 / LX1
323 *
324 */
325 {
326 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
327 .start = 0x24000000,
328 .end = 0x241FFFFF, /* 2MiB */
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
333 .start = 0x24200000,
334 .end = 0x24201FFF,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "MediaMemory1",
339 .start = 0x24202000,
340 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
341 .flags = IORESOURCE_MEM,
342 },
343 /*
344 *
345 * VIDEO2 / LX2
346 *
347 */
348 {
349 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
350 .start = 0x60000000,
351 .end = 0x601FFFFF, /* 2MiB */
352 .flags = IORESOURCE_IO,
353 },
354 {
355 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
356 .start = 0x60200000,
357 .end = 0x60201FFF,
358 .flags = IORESOURCE_IO,
359 },
360 {
361 .name = "MediaMemory2",
362 .start = 0x60202000,
363 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
364 .flags = IORESOURCE_IO,
365 },
366 /*
367 *
368 * Sysaudio Driver
369 *
370 * This driver requires:
371 *
372 * Arbitrary Based Buffers:
373 * DSP_Image_Buff - DSP code and data images (1MB)
374 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
375 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
376 * ADSC_Main_Buff - ADSC Main buffer (16KB)
377 *
378 */
379 {
380 .name = "DSP_Image_Buff",
381 .start = 0x00000000,
382 .end = 0x000FFFFF,
383 .flags = IORESOURCE_MEM,
384 },
385 {
386 .name = "ADSC_CPU_PCM_Buff",
387 .start = 0x00000000,
388 .end = 0x00009FFF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .name = "ADSC_AUX_Buff",
393 .start = 0x00000000,
394 .end = 0x00003FFF,
395 .flags = IORESOURCE_MEM,
396 },
397 {
398 .name = "ADSC_Main_Buff",
399 .start = 0x00000000,
400 .end = 0x00003FFF,
401 .flags = IORESOURCE_MEM,
402 },
403 /*
404 *
405 * STAVEM driver/STAPI
406 *
407 * This driver requires:
408 *
409 * Arbitrary Based Buffers:
410 * This memory area is used for allocating buffers for Video decoding
411 * purposes. Allocation/De-allocation within this buffer is managed
412 * by the STAVMEM driver of the STAPI. They could be Decimated
413 * Picture Buffers, Intermediate Buffers, as deemed necessary for
414 * video decoding purposes, for any video decoders on Zeus.
415 *
416 */
417 {
418 .name = "AVMEMPartition0",
419 .start = 0x63580000,
420 .end = 0x64180000 - 1, /* 12 MB total */
421 .flags = IORESOURCE_IO,
422 },
423 /*
424 *
425 * DOCSIS Subsystem
426 *
427 * This driver requires:
428 *
429 * Arbitrary Based Buffers:
430 * Docsis -
431 *
432 */
433 {
434 .name = "Docsis",
435 .start = 0x62000000,
436 .end = 0x62700000 - 1, /* 7 MB total */
437 .flags = IORESOURCE_IO,
438 },
439 /*
440 *
441 * GHW HAL Driver
442 *
443 * This driver requires:
444 *
445 * Arbitrary Based Buffers:
446 * GraphicsHeap - PowerTV Graphics Heap
447 *
448 */
449 {
450 .name = "GraphicsHeap",
451 .start = 0x62700000,
452 .end = 0x63500000 - 1, /* 14 MB total */
453 .flags = IORESOURCE_IO,
454 },
455 /*
456 *
457 * multi com buffer area
458 *
459 * This driver requires:
460 *
461 * Arbitrary Based Buffers:
462 * Docsis -
463 *
464 */
465 {
466 .name = "MulticomSHM",
467 .start = 0x26000000,
468 .end = 0x26020000 - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 /*
472 *
473 * DMA Ring buffer
474 *
475 * This driver requires:
476 *
477 * Arbitrary Based Buffers:
478 * Docsis -
479 *
480 */
481 {
482 .name = "BMM_Buffer",
483 .start = 0x00000000,
484 .end = 0x000AA000 - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 /*
488 *
489 * Display bins buffer for unit0
490 *
491 * This driver requires:
492 *
493 * Arbitrary Based Buffers:
494 * Display Bins for unit0
495 *
496 */
497 {
498 .name = "DisplayBins0",
499 .start = 0x00000000,
500 .end = 0x00000FFF, /* 4 KB total */
501 .flags = IORESOURCE_MEM,
502 },
503 /*
504 *
505 * Display bins buffer
506 *
507 * This driver requires:
508 *
509 * Arbitrary Based Buffers:
510 * Display Bins for unit1
511 *
512 */
513 {
514 .name = "DisplayBins1",
515 .start = 0x64AD4000,
516 .end = 0x64AD5000 - 1, /* 4 KB total */
517 .flags = IORESOURCE_IO,
518 },
519 /*
520 *
521 * AVFS: player HAL memory
522 *
523 *
524 */
525 {
526 .name = "AvfsDmaMem",
527 .start = 0x6430E000,
528 .end = 0x645D2C00 - 1, /* 945K * 3 for playback */
529 .flags = IORESOURCE_IO,
530 },
531 /*
532 *
533 * PMEM
534 *
535 * This driver requires:
536 *
537 * Arbitrary Based Buffers:
538 * Persistent memory for diagnostics.
539 *
540 */
541 {
542 .name = "DiagPersistentMemory",
543 .start = 0x00000000,
544 .end = 0x10000 - 1,
545 .flags = IORESOURCE_MEM,
546 },
547 /*
548 *
549 * Smartcard
550 *
551 * This driver requires:
552 *
553 * Arbitrary Based Buffers:
554 * Read and write buffers for Internal/External cards
555 *
556 */
557 {
558 .name = "SmartCardInfo",
559 .start = 0x64AD1000,
560 .end = 0x64AD3800 - 1,
561 .flags = IORESOURCE_IO,
562 },
563 /*
564 *
565 * KAVNET
566 * NP Reset Vector - must be of the form xxCxxxxx
567 * NP Image - must be video bank 1
568 * NP IPC - must be video bank 2
569 */
570 {
571 .name = "NP_Reset_Vector",
572 .start = 0x27c00000,
573 .end = 0x27c01000 - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "NP_Image",
578 .start = 0x27020000,
579 .end = 0x27060000 - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "NP_IPC",
584 .start = 0x63500000,
585 .end = 0x63580000 - 1,
586 .flags = IORESOURCE_IO,
587 },
588 { },
589};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
deleted file mode 100644
index 6e76f09c68d6..000000000000
--- a/arch/mips/powertv/asic/prealloc-zeus.c
+++ /dev/null
@@ -1,304 +0,0 @@
1/*
2 * Memory pre-allocations for Zeus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <asm/mach-powertv/asic.h>
27#include "prealloc.h"
28
29/*
30 * DVR_CAPABLE RESOURCES
31 */
32struct resource dvr_zeus_resources[] __initdata =
33{
34 /*
35 * VIDEO1 / LX1
36 */
37 /* Delta-Mu 1 image (2MiB) */
38 PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1,
39 IORESOURCE_MEM)
40 /* Delta-Mu 1 monitor (8KiB) */
41 PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1,
42 IORESOURCE_MEM)
43 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
44 PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1,
45 IORESOURCE_MEM)
46
47 /*
48 * VIDEO2 / LX2
49 */
50 /* Delta-Mu 2 image (2MiB) */
51 PREALLOC_NORMAL("ST231bImage", 0x30000000, 0x30200000-1,
52 IORESOURCE_MEM)
53 /* Delta-Mu 2 monitor (8KiB) */
54 PREALLOC_NORMAL("ST231bMonitor", 0x30200000, 0x30202000-1,
55 IORESOURCE_MEM)
56 /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
57 PREALLOC_NORMAL("MediaMemory2", 0x30202000, 0x32000000-1,
58 IORESOURCE_MEM)
59
60 /*
61 * Sysaudio Driver
62 */
63 /* DSP code and data images (1MiB) */
64 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
65 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
66 /* ADSC CPU PCM buffer (40KiB) */
67 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
68 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
69 /* ADSC AUX buffer (16KiB) */
70 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
71 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
72 /* ADSC Main buffer (16KiB) */
73 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
74 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
75
76 /*
77 * STAVEM driver/STAPI
78 *
79 * This memory area is used for allocating buffers for Video decoding
80 * purposes. Allocation/De-allocation within this buffer is managed
81 * by the STAVMEM driver of the STAPI. They could be Decimated
82 * Picture Buffers, Intermediate Buffers, as deemed necessary for
83 * video decoding purposes, for any video decoders on Zeus.
84 */
85 /* 12MiB */
86 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1,
87 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
88
89 /*
90 * DOCSIS Subsystem
91 */
92 /* 7MiB */
93 PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM)
94
95 /*
96 * GHW HAL Driver
97 */
98 /* PowerTV Graphics Heap (14MiB) */
99 PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1,
100 IORESOURCE_MEM)
101
102 /*
103 * multi com buffer area
104 */
105 /* 128KiB */
106 PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1,
107 IORESOURCE_MEM)
108
109 /*
110 * DMA Ring buffer
111 */
112 /* 2.5MiB */
113 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1,
114 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
115
116 /*
117 * Display bins buffer for unit0
118 */
119 /* 4KiB */
120 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
121 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
122
123 /*
124 * Display bins buffer for unit1
125 */
126 /* 4KiB */
127 PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1,
128 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
129
130 /*
131 * ITFS
132 */
133 /* 815,104 bytes each for 2 ITFS partitions. */
134 PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1,
135 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
136
137 /*
138 * AVFS
139 */
140 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
141 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1,
142 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
143 /* 4KiB */
144 PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1,
145 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
146
147 /*
148 * PMEM
149 */
150 /* Persistent memory for diagnostics (64KiB) */
151 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
152 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
153
154 /*
155 * Smartcard
156 */
157 /* Read and write buffers for Internal/External cards (10KiB) */
158 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
159 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
160
161 /*
162 * TFTPBuffer
163 *
164 * This buffer is used in some minimal configurations (e.g. two-way
165 * loader) for storing software images
166 */
167 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
168 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
169
170 /*
171 * Add other resources here
172 */
173
174 /*
175 * End of Resource marker
176 */
177 {
178 .flags = 0,
179 },
180};
181
182/*
183 * NON_DVR_CAPABLE ZEUS RESOURCES
184 */
185struct resource non_dvr_zeus_resources[] __initdata =
186{
187 /*
188 * VIDEO1 / LX1
189 */
190 /* Delta-Mu 1 image (2MiB) */
191 PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1,
192 IORESOURCE_MEM)
193 /* Delta-Mu 1 monitor (8KiB) */
194 PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1,
195 IORESOURCE_MEM)
196 /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */
197 PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1,
198 IORESOURCE_MEM)
199
200 /*
201 * Sysaudio Driver
202 */
203 /* DSP code and data images (1MiB) */
204 PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1,
205 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
206 /* ADSC CPU PCM buffer (40KiB) */
207 PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1,
208 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
209 /* ADSC AUX buffer (16KiB) */
210 PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1,
211 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
212 /* ADSC Main buffer (16KiB) */
213 PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1,
214 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
215
216 /*
217 * STAVEM driver/STAPI
218 */
219 /* 6MiB */
220 PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1,
221 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
222
223 /*
224 * DOCSIS Subsystem
225 */
226 /* 7MiB */
227 PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM)
228
229 /*
230 * GHW HAL Driver
231 */
232 /* PowerTV Graphics Heap (14MiB) */
233 PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1,
234 IORESOURCE_MEM)
235
236 /*
237 * multi com buffer area
238 */
239 /* 128KiB */
240 PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1,
241 IORESOURCE_MEM)
242
243 /*
244 * DMA Ring buffer
245 */
246 /* 2.5MiB */
247 PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1,
248 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
249
250 /*
251 * Display bins buffer for unit0
252 */
253 /* 4KiB */
254 PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1,
255 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
256
257 /*
258 * AVFS: player HAL memory
259 */
260 /* 945K * 3 for playback */
261 PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1,
262 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
263
264 /*
265 * PMEM
266 */
267 /* Persistent memory for diagnostics (64KiB) */
268 PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1,
269 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
270
271 /*
272 * Smartcard
273 */
274 /* Read and write buffers for Internal/External cards (10KiB) */
275 PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1,
276 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
277
278 /*
279 * NAND Flash
280 */
281 /* 10KiB */
282 PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1,
283 IORESOURCE_MEM)
284
285 /*
286 * TFTPBuffer
287 *
288 * This buffer is used in some minimal configurations (e.g. two-way
289 * loader) for storing software images
290 */
291 PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1,
292 (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT))
293
294 /*
295 * Add other resources here
296 */
297
298 /*
299 * End of Resource marker
300 */
301 {
302 .flags = 0,
303 },
304};
diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h
deleted file mode 100644
index 8e682df17856..000000000000
--- a/arch/mips/powertv/asic/prealloc.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * Definitions for memory preallocations
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H
22#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H
23
24#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
25#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
26
27/* "struct resource" array element definition */
28#define PREALLOC(NAME, START, END, FLAGS) { \
29 .name = (NAME), \
30 .start = (START), \
31 .end = (END), \
32 .flags = (FLAGS) \
33 },
34
35/* Individual resources in the preallocated resource arrays are defined using
36 * macros. These macros are conditionally defined based on their
37 * corresponding kernel configuration flag:
38 * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box
39 * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource
40 * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource
41 * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory
42 */
43#ifdef CONFIG_PREALLOC_NORMAL
44#define PREALLOC_NORMAL(name, start, end, flags) \
45 PREALLOC(name, start, end, flags)
46#else
47#define PREALLOC_NORMAL(name, start, end, flags)
48#endif
49
50#ifdef CONFIG_PREALLOC_TFTP
51#define PREALLOC_TFTP(name, start, end, flags) \
52 PREALLOC(name, start, end, flags)
53#else
54#define PREALLOC_TFTP(name, start, end, flags)
55#endif
56
57#ifdef CONFIG_PREALLOC_DOCSIS
58#define PREALLOC_DOCSIS(name, start, end, flags) \
59 PREALLOC(name, start, end, flags)
60#else
61#define PREALLOC_DOCSIS(name, start, end, flags)
62#endif
63
64#ifdef CONFIG_PREALLOC_PMEM
65#define PREALLOC_PMEM(name, start, end, flags) \
66 PREALLOC(name, start, end, flags)
67#else
68#define PREALLOC_PMEM(name, start, end, flags)
69#endif
70#endif
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
deleted file mode 100644
index 498926377e51..000000000000
--- a/arch/mips/powertv/init.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * PROM library initialisation code.
22 */
23#include <linux/init.h>
24#include <linux/string.h>
25#include <linux/kernel.h>
26
27#include <asm/bootinfo.h>
28#include <linux/io.h>
29#include <asm/cacheflush.h>
30#include <asm/traps.h>
31
32#include <asm/mips-boards/generic.h>
33#include <asm/mach-powertv/asic.h>
34
35#include "init.h"
36
37static int *_prom_envp;
38unsigned long _prom_memsize;
39
40/*
41 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
42 * This macro take care of sign extension, if running in 64-bit mode.
43 */
44#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
45
46char *prom_getenv(char *envname)
47{
48 char *result = NULL;
49
50 if (_prom_envp != NULL) {
51 /*
52 * Return a pointer to the given environment variable.
53 * In 64-bit mode: we're using 64-bit pointers, but all pointers
54 * in the PROM structures are only 32-bit, so we need some
55 * workarounds, if we are running in 64-bit mode.
56 */
57 int i, index = 0;
58
59 i = strlen(envname);
60
61 while (prom_envp(index)) {
62 if (strncmp(envname, prom_envp(index), i) == 0) {
63 result = prom_envp(index + 1);
64 break;
65 }
66 index += 2;
67 }
68 }
69
70 return result;
71}
72
73void __init prom_init(void)
74{
75 int prom_argc;
76 char *prom_argv;
77
78 prom_argc = fw_arg0;
79 prom_argv = (char *) fw_arg1;
80 _prom_envp = (int *) fw_arg2;
81 _prom_memsize = (unsigned long) fw_arg3;
82
83 if (prom_argc == 1) {
84 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
85 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
86 }
87
88 configure_platform();
89 prom_meminit();
90}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
deleted file mode 100644
index c1a8bd0dbe4b..000000000000
--- a/arch/mips/powertv/init.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Definitions from powertv init.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_INIT_H
24#define _POWERTV_INIT_H
25extern unsigned long _prom_memsize;
26extern void prom_meminit(void);
27extern char *prom_getenv(char *name);
28#endif
diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
deleted file mode 100644
index d060478aab03..000000000000
--- a/arch/mips/powertv/ioremap.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * ioremap.c
3 *
4 * Support for mapping between dma_addr_t values a phys_addr_t values.
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 * Author: David VomLehn <dvomlehn@cisco.com>
23 *
24 * Description: Defines the platform resources for the SA settop.
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33
34#include <asm/mach-powertv/ioremap.h>
35
36/*
37 * Define the sizes of and masks for grains in physical and DMA space. The
38 * values are the same but the types are not.
39 */
40#define IOR_PHYS_GRAIN ((phys_addr_t) 1 << IOR_LSBITS)
41#define IOR_PHYS_GRAIN_MASK (IOR_PHYS_GRAIN - 1)
42
43#define IOR_DMA_GRAIN ((dma_addr_t) 1 << IOR_LSBITS)
44#define IOR_DMA_GRAIN_MASK (IOR_DMA_GRAIN - 1)
45
46/*
47 * Values that, when accessed by an index derived from a phys_addr_t and
48 * added to phys_addr_t value, yield a DMA address
49 */
50struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
51EXPORT_SYMBOL(_ior_phys_to_dma);
52
53/*
54 * Values that, when accessed by an index derived from a dma_addr_t and
55 * added to that dma_addr_t value, yield a physical address
56 */
57struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
58EXPORT_SYMBOL(_ior_dma_to_phys);
59
60/**
61 * setup_dma_to_phys - set up conversion from DMA to physical addresses
62 * @dma_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
63 * into the array _dma_to_phys.
64 * @delta: Value that, when added to the DMA address, will yield the
65 * physical address
66 * @s: Number of bytes in the section of memory with the given delta
67 * between DMA and physical addresses.
68 */
69static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s)
70{
71 int dma_idx, first_idx, last_idx;
72 phys_addr_t first, last;
73
74 /*
75 * Calculate the first and last indices, rounding the first up and
76 * the second down.
77 */
78 first = dma & ~IOR_DMA_GRAIN_MASK;
79 last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK;
80 first_idx = first >> IOR_LSBITS; /* Convert to indices */
81 last_idx = last >> IOR_LSBITS;
82
83 for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++)
84 _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT;
85}
86
87/**
88 * setup_phys_to_dma - set up conversion from DMA to physical addresses
89 * @phys_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
90 * into the array _phys_to_dma.
91 * @delta: Value that, when added to the DMA address, will yield the
92 * physical address
93 * @s: Number of bytes in the section of memory with the given delta
94 * between DMA and physical addresses.
95 */
96static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s)
97{
98 int phys_idx, first_idx, last_idx;
99 phys_addr_t first, last;
100
101 /*
102 * Calculate the first and last indices, rounding the first up and
103 * the second down.
104 */
105 first = phys & ~IOR_PHYS_GRAIN_MASK;
106 last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK;
107 first_idx = first >> IOR_LSBITS; /* Convert to indices */
108 last_idx = last >> IOR_LSBITS;
109
110 for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++)
111 _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT;
112}
113
114/**
115 * ioremap_add_map - add to the physical and DMA address conversion arrays
116 * @phys: Process's view of the address of the start of the memory chunk
117 * @dma: DMA address of the start of the memory chunk
118 * @size: Size, in bytes, of the chunk of memory
119 *
120 * NOTE: It might be obvious, but the assumption is that all @size bytes have
121 * the same offset between the physical address and the DMA address.
122 */
123void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size)
124{
125 if (size == 0)
126 return;
127
128 if ((dma & IOR_DMA_GRAIN_MASK) != 0 ||
129 (phys & IOR_PHYS_GRAIN_MASK) != 0 ||
130 (size & IOR_PHYS_GRAIN_MASK) != 0)
131 pr_crit("Memory allocation must be in chunks of 0x%x bytes\n",
132 IOR_PHYS_GRAIN);
133
134 setup_dma_to_phys(dma, phys - dma, size);
135 setup_phys_to_dma(phys, dma - phys, size);
136}
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
deleted file mode 100644
index bc2f3ca22b41..000000000000
--- a/arch/mips/powertv/memory.c
+++ /dev/null
@@ -1,353 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Apparently originally from arch/mips/malta-memory.c. Modified to work
20 * with the PowerTV bootloader.
21 */
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/bootmem.h>
25#include <linux/pfn.h>
26#include <linux/string.h>
27
28#include <asm/bootinfo.h>
29#include <asm/page.h>
30#include <asm/sections.h>
31
32#include <asm/mach-powertv/asic.h>
33#include <asm/mach-powertv/ioremap.h>
34
35#include "init.h"
36
37/* Memory constants */
38#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
39#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
40#define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */
41
42#define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
43#define RV_SIZE MEBIBYTE(4) /* Size of reset vector */
44
45#define LOW_MEM_END 0x20000000 /* Highest low memory address */
46#define BLDR_ALIAS 0x10000000 /* Bootloader address */
47#define RV_PHYS 0x1fc00000 /* Reset vector address */
48#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */
49
50/*
51 * Very low-level conversion from processor physical address to device
52 * DMA address for the first bank of memory.
53 */
54#define PHYS_TO_DMA(paddr) ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS))
55
56unsigned long ptv_memsize;
57
58/*
59 * struct low_mem_reserved - Items in low memory that are reserved
60 * @start: Physical address of item
61 * @size: Size, in bytes, of this item
62 * @is_aliased: True if this is RAM aliased from another location. If false,
63 * it is something other than aliased RAM and the RAM in the
64 * unaliased address is still visible outside of low memory.
65 */
66struct low_mem_reserved {
67 phys_addr_t start;
68 phys_addr_t size;
69 bool is_aliased;
70};
71
72/*
73 * Must be in ascending address order
74 */
75struct low_mem_reserved low_mem_reserved[] = {
76 {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */
77 {RV_PHYS, RV_SIZE, false}, /* Reset vector */
78};
79
80/*
81 * struct mem_layout - layout of a piece of the system RAM
82 * @phys: Physical address of the start of this piece of RAM. This is the
83 * address at which both the processor and I/O devices see the
84 * RAM.
85 * @alias: Alias of this piece of memory in order to make it appear in
86 * the low memory part of the processor's address space. I/O
87 * devices don't see anything here.
88 * @size: Size, in bytes, of this piece of RAM
89 */
90struct mem_layout {
91 phys_addr_t phys;
92 phys_addr_t alias;
93 phys_addr_t size;
94};
95
96/*
97 * struct mem_layout_list - list descriptor for layouts of system RAM pieces
98 * @family: Specifies the family being described
99 * @n: Number of &struct mem_layout elements
100 * @layout: Pointer to the list of &mem_layout structures
101 */
102struct mem_layout_list {
103 enum family_type family;
104 size_t n;
105 struct mem_layout *layout;
106};
107
108static struct mem_layout f1500_layout[] = {
109 {0x20000000, 0x10000000, MEBIBYTE(256)},
110};
111
112static struct mem_layout f4500_layout[] = {
113 {0x40000000, 0x10000000, MEBIBYTE(256)},
114 {0x20000000, 0x20000000, MEBIBYTE(32)},
115};
116
117static struct mem_layout f8500_layout[] = {
118 {0x40000000, 0x10000000, MEBIBYTE(256)},
119 {0x20000000, 0x20000000, MEBIBYTE(32)},
120 {0x30000000, 0x30000000, MEBIBYTE(32)},
121};
122
123static struct mem_layout fx600_layout[] = {
124 {0x20000000, 0x10000000, MEBIBYTE(256)},
125 {0x60000000, 0x60000000, MEBIBYTE(128)},
126};
127
128static struct mem_layout_list layout_list[] = {
129 {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout},
130 {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout},
131 {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout},
132 {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout},
133 {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout},
134 {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout},
135 {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout},
136 {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout},
137 {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout},
138 {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout},
139};
140
141/* If we can't determine the layout, use this */
142static struct mem_layout default_layout[] = {
143 {0x20000000, 0x10000000, MEBIBYTE(128)},
144};
145
146/**
147 * register_non_ram - register low memory not available for RAM usage
148 */
149static __init void register_non_ram(void)
150{
151 int i;
152
153 for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++)
154 add_memory_region(low_mem_reserved[i].start,
155 low_mem_reserved[i].size, BOOT_MEM_RESERVED);
156}
157
158/**
159 * get_memsize - get the size of memory as a single bank
160 */
161static phys_addr_t get_memsize(void)
162{
163 static char cmdline[COMMAND_LINE_SIZE] __initdata;
164 phys_addr_t memsize = 0;
165 char *memsize_str;
166 char *ptr;
167
168 /* Check the command line first for a memsize directive */
169 strcpy(cmdline, arcs_cmdline);
170 ptr = strstr(cmdline, "memsize=");
171 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
172 ptr = strstr(ptr, " memsize=");
173
174 if (ptr) {
175 memsize = memparse(ptr + 8, &ptr);
176 } else {
177 /* otherwise look in the environment */
178 memsize_str = prom_getenv("memsize");
179
180 if (memsize_str != NULL) {
181 pr_info("prom memsize = %s\n", memsize_str);
182 memsize = simple_strtol(memsize_str, NULL, 0);
183 }
184
185 if (memsize == 0) {
186 if (_prom_memsize != 0) {
187 memsize = _prom_memsize;
188 pr_info("_prom_memsize = 0x%x\n", memsize);
189 /* add in memory that the bootloader doesn't
190 * report */
191 memsize += BLDR_SIZE;
192 } else {
193 memsize = DEFAULT_MEMSIZE;
194 pr_info("Memsize not passed by bootloader, "
195 "defaulting to 0x%x\n", memsize);
196 }
197 }
198 }
199
200 return memsize;
201}
202
203/**
204 * register_low_ram - register an aliased section of RAM
205 * @p: Alias address of memory
206 * @n: Number of bytes in this section of memory
207 *
208 * Returns the number of bytes registered
209 *
210 */
211static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n)
212{
213 phys_addr_t s;
214 int i;
215 phys_addr_t orig_n;
216
217 orig_n = n;
218
219 BUG_ON(p + n > RV_PHYS);
220
221 for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) {
222 phys_addr_t start;
223 phys_addr_t size;
224
225 start = low_mem_reserved[i].start;
226 size = low_mem_reserved[i].size;
227
228 /* Handle memory before this low memory section */
229 if (p < start) {
230 phys_addr_t s;
231 s = min(n, start - p);
232 add_memory_region(p, s, BOOT_MEM_RAM);
233 p += s;
234 n -= s;
235 }
236
237 /* Handle the low memory section itself. If it's aliased,
238 * we reduce the number of byes left, but if not, the RAM
239 * is available elsewhere and we don't reduce the number of
240 * bytes remaining. */
241 if (p == start) {
242 if (low_mem_reserved[i].is_aliased) {
243 s = min(n, size);
244 n -= s;
245 p += s;
246 } else
247 p += n;
248 }
249 }
250
251 return orig_n - n;
252}
253
254/*
255 * register_ram - register real RAM
256 * @p: Address of memory as seen by devices
257 * @alias: If the memory is seen at an additional address by the processor,
258 * this will be the address, otherwise it is the same as @p.
259 * @n: Number of bytes in this section of memory
260 */
261static __init void register_ram(phys_addr_t p, phys_addr_t alias,
262 phys_addr_t n)
263{
264 /*
265 * If some or all of this memory has an alias, break it into the
266 * aliased and non-aliased portion.
267 */
268 if (p != alias) {
269 phys_addr_t alias_size;
270 phys_addr_t registered;
271
272 alias_size = min(n, LOW_RAM_END - alias);
273 registered = register_low_ram(alias, alias_size);
274 ioremap_add_map(alias, p, n);
275 n -= registered;
276 p += registered;
277 }
278
279#ifdef CONFIG_HIGHMEM
280 if (n != 0) {
281 add_memory_region(p, n, BOOT_MEM_RAM);
282 ioremap_add_map(p, p, n);
283 }
284#endif
285}
286
287/**
288 * register_address_space - register things in the address space
289 * @memsize: Number of bytes of RAM installed
290 *
291 * Takes the given number of bytes of RAM and registers as many of the regions,
292 * or partial regions, as it can. So, the default configuration might have
293 * two regions with 256 MiB each. If the memsize passed in on the command line
294 * is 384 MiB, it will register the first region with 256 MiB and the second
295 * with 128 MiB.
296 */
297static __init void register_address_space(phys_addr_t memsize)
298{
299 int i;
300 phys_addr_t size;
301 size_t n;
302 struct mem_layout *layout;
303 enum family_type family;
304
305 /*
306 * Register all of the things that aren't available to the kernel as
307 * memory.
308 */
309 register_non_ram();
310
311 /* Find the appropriate memory description */
312 family = platform_get_family();
313
314 for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
315 if (layout_list[i].family == family)
316 break;
317 }
318
319 if (i == ARRAY_SIZE(layout_list)) {
320 n = ARRAY_SIZE(default_layout);
321 layout = default_layout;
322 } else {
323 n = layout_list[i].n;
324 layout = layout_list[i].layout;
325 }
326
327 for (i = 0; memsize != 0 && i < n; i++) {
328 size = min(memsize, layout[i].size);
329 register_ram(layout[i].phys, layout[i].alias, size);
330 memsize -= size;
331 }
332}
333
334void __init prom_meminit(void)
335{
336 ptv_memsize = get_memsize();
337 register_address_space(ptv_memsize);
338}
339
340void __init prom_free_prom_memory(void)
341{
342 unsigned long addr;
343 int i;
344
345 for (i = 0; i < boot_mem_map.nr_map; i++) {
346 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
347 continue;
348
349 addr = boot_mem_map.map[i].addr;
350 free_init_pages("prom memory",
351 addr, addr + boot_mem_map.map[i].size);
352 }
353}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
deleted file mode 100644
index 2610a6af5b2c..000000000000
--- a/arch/mips/powertv/pci/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-$(CONFIG_PCI) += fixup-powertv.o
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
deleted file mode 100644
index d7ecbae64a6e..000000000000
--- a/arch/mips/powertv/pci/fixup-powertv.c
+++ /dev/null
@@ -1,37 +0,0 @@
1#include <linux/init.h>
2#include <linux/export.h>
3#include <linux/pci.h>
4#include <asm/mach-powertv/interrupts.h>
5#include "powertv-pci.h"
6
7int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
8{
9 return asic_pcie_map_irq(dev, slot, pin);
10}
11
12/* Do platform specific device initialization at pci_enable_device() time */
13int pcibios_plat_dev_init(struct pci_dev *dev)
14{
15 return 0;
16}
17
18/*
19 * asic_pcie_map_irq
20 *
21 * Parameters:
22 * *dev - pointer to a pci_dev structure (not used)
23 * slot - slot number (not used)
24 * pin - pin number (not used)
25 *
26 * Return Value:
27 * Returns: IRQ number (always the PCI Express IRQ number)
28 *
29 * Description:
30 * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
31 *
32 */
33int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
34{
35 return irq_pciexp;
36}
37EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
deleted file mode 100644
index 1b5886bbd759..000000000000
--- a/arch/mips/powertv/pci/powertv-pci.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * powertv-pci.c
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20/*
21 * Local definitions for the powertv PCI code
22 */
23
24#ifndef _POWERTV_PCI_POWERTV_PCI_H_
25#define _POWERTV_PCI_POWERTV_PCI_H_
26extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
27extern int asic_pcie_init(void);
28extern int asic_pcie_init(void);
29
30extern int log_level;
31#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
deleted file mode 100644
index d94c54311485..000000000000
--- a/arch/mips/powertv/powertv-clock.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 * Author: David VomLehn
19 */
20
21#ifndef _POWERTV_POWERTV_CLOCK_H
22#define _POWERTV_POWERTV_CLOCK_H
23extern int powertv_clockevent_init(void);
24extern void powertv_clocksource_init(void);
25extern unsigned int mips_get_pll_freq(void);
26#endif
diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
deleted file mode 100644
index d845eace58e9..000000000000
--- a/arch/mips/powertv/powertv-usb.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * powertv-usb.c
3 *
4 * Description: ASIC-specific USB device setup and shutdown
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 * Author: Ken Eppinett
24 * David Schleef <ds@schleef.org>
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/export.h>
33#include <linux/ioport.h>
34#include <linux/platform_device.h>
35#include <asm/mach-powertv/asic.h>
36#include <asm/mach-powertv/interrupts.h>
37
38/* misc_clk_ctl1 values */
39#define MCC1_30MHZ_POWERUP_SELECT (1 << 14)
40#define MCC1_DIV9 (1 << 13)
41#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11)
42#define MCC1_USB_POWERUP_SELECT (1 << 1)
43#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0)
44
45/* Possible values for clock select */
46#define MCC1_USB_CLOCK_HIGH_Z (0 << 4)
47#define MCC1_USB_CLOCK_48MHZ (1 << 4)
48#define MCC1_USB_CLOCK_24MHZ (2 << 4)
49#define MCC1_USB_CLOCK_6MHZ (3 << 4)
50
51#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \
52 MCC1_DIV9 | \
53 MCC1_ETHMIPS_POWERUP_SELECT | \
54 MCC1_USB_POWERUP_SELECT | \
55 MCC1_CLOCK108_POWERUP_SELECT)
56
57/* misc_clk_ctl2 values */
58#define MCC2_GMII_GCLK_TO_PAD (1 << 31)
59#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29)
60#define MCC2_RMII_0_CLOCK_SELECT (1 << 28)
61#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27)
62#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26)
63#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24)
64#define MCC2_RMII_1_CLOCK_SELECT (1 << 23)
65#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22)
66#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21)
67#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19)
68#define MCC2_RMII_2_CLOCK_SELECT (1 << 18)
69#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17)
70#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16)
71
72#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \
73 MCC2_ETHER125_0_CLOCK_SELECT | \
74 MCC2_RMII_0_CLOCK_SELECT | \
75 MCC2_GMII_TX0_CLOCK_SELECT | \
76 MCC2_GMII_RX0_CLOCK_SELECT | \
77 MCC2_ETHER125_1_CLOCK_SELECT | \
78 MCC2_RMII_1_CLOCK_SELECT | \
79 MCC2_GMII_TX1_CLOCK_SELECT | \
80 MCC2_GMII_RX1_CLOCK_SELECT | \
81 MCC2_ETHER125_2_CLOCK_SELECT | \
82 MCC2_RMII_2_CLOCK_SELECT | \
83 MCC2_GMII_TX2_CLOCK_SELECT | \
84 MCC2_GMII_RX2_CLOCK_SELECT)
85
86/* misc_clk_ctl2 definitions for Gaia */
87#define FSX4A_REF_SELECT (1 << 16)
88#define FSX4B_REF_SELECT (1 << 17)
89#define FSX4C_REF_SELECT (1 << 18)
90#define DDR_PLL_REF_SELECT (1 << 19)
91#define MIPS_PLL_REF_SELECT (1 << 20)
92
93/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
94#define QAM_FS_SDIV_SHIFT 29
95#define QAM_FS_MD_SHIFT 24
96#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */
97#define QAM_FS_PE_SHIFT 8
98
99#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5)
100#define QAM_FS_ENABLE_PROGRAM (1 << 4)
101#define QAM_FS_ENABLE_OUTPUT (1 << 3)
102#define QAM_FS_SELECT_TEST_BYPASS (1 << 2)
103#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1)
104#define QAM_FS_CHOOSE_FS (1 << 0)
105
106/* Definitions for fs432x4a_ctl register */
107#define QAM_FS_NSDIV_54MHZ (1 << 2)
108
109/* Definitions for bcm1_usb2_ctl register */
110#define BCM1_USB2_CTL_BISTOK (1 << 11)
111#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7)
112#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6)
113#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5)
114#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4)
115#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1)
116#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0)
117
118/* Definitions for crt_spare register */
119#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21)
120#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20)
121#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19)
122#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18)
123#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17)
124#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16)
125
126/* Definitions for usb2_stbus_obc register */
127#define USB_STBUS_OBC_STORE32_LOAD32 0x3
128
129/* Definitions for usb2_stbus_mess_size register */
130#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */
131
132/* Definitions for usb2_stbus_chunk_size register */
133#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */
134
135/* Definitions for usb2_strap register */
136#define USB2_STRAP_HFREQ_SELECT 0x1
137
138/*
139 * USB Host Resource Definition
140 */
141
142static struct resource ehci_resources[] = {
143 {
144 .parent = &asic_resource,
145 .start = 0,
146 .end = 0xff,
147 .flags = IORESOURCE_MEM,
148 },
149 {
150 .start = irq_usbehci,
151 .end = irq_usbehci,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static u64 ehci_dmamask = 0xffffffffULL;
157
158static struct platform_device ehci_device = {
159 .name = "powertv-ehci",
160 .id = 0,
161 .num_resources = 2,
162 .resource = ehci_resources,
163 .dev = {
164 .dma_mask = &ehci_dmamask,
165 .coherent_dma_mask = 0xffffffff,
166 },
167};
168
169static struct resource ohci_resources[] = {
170 {
171 .parent = &asic_resource,
172 .start = 0,
173 .end = 0xff,
174 .flags = IORESOURCE_MEM,
175 },
176 {
177 .start = irq_usbohci,
178 .end = irq_usbohci,
179 .flags = IORESOURCE_IRQ,
180 },
181};
182
183static u64 ohci_dmamask = 0xffffffffULL;
184
185static struct platform_device ohci_device = {
186 .name = "powertv-ohci",
187 .id = 0,
188 .num_resources = 2,
189 .resource = ohci_resources,
190 .dev = {
191 .dma_mask = &ohci_dmamask,
192 .coherent_dma_mask = 0xffffffff,
193 },
194};
195
196static unsigned usb_users;
197static DEFINE_SPINLOCK(usb_regs_lock);
198
199/*
200 *
201 * fs_update - set frequency synthesizer for USB
202 * @pe_bits Phase tap setting
203 * @md_bits Coarse selector bus for algorithm of phase tap
204 * @sdiv_bits Output divider setting
205 * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
206 * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
207 *
208 * QAM frequency selection code, which affects the frequency at which USB
209 * runs. The frequency is calculated as:
210 * 2^15 * ndiv * Fin
211 * Fout = ------------------------------------------------------------
212 * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
213 * where:
214 * Fin 54 MHz
215 * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16
216 * sdiv 1 << (sdiv_bits + 1)
217 * ipe Same as pe_bits
218 * md A five-bit, two's-complement integer (range [-16, 15]), which
219 * is the lower 5 bits of md_bits.
220 */
221static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
222 u32 disable_div_by_3, u32 standby)
223{
224 u32 val;
225
226 val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
227 ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
228 (pe_bits << QAM_FS_PE_SHIFT) |
229 QAM_FS_ENABLE_OUTPUT |
230 standby |
231 disable_div_by_3);
232 asic_write(val, fs432x4b4_usb_ctl);
233 asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
234 asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
235 fs432x4b4_usb_ctl);
236}
237
238/*
239 * usb_eye_configure - for optimizing the shape USB eye waveform
240 * @set: Bits to set in the register
241 * @clear: Bits to clear in the register; each bit with a one will
242 * be set in the register, zero bits will not be modified
243 */
244static void usb_eye_configure(u32 set, u32 clear)
245{
246 u32 old;
247
248 old = asic_read(crt_spare);
249 old |= set;
250 old &= ~clear;
251 asic_write(old, crt_spare);
252}
253
254/*
255 * platform_configure_usb - usb configuration based on platform type.
256 */
257static void platform_configure_usb(void)
258{
259 u32 bcm1_usb2_ctl_value;
260 enum asic_type asic_type;
261 unsigned long flags;
262
263 spin_lock_irqsave(&usb_regs_lock, flags);
264 usb_users++;
265
266 if (usb_users != 1) {
267 spin_unlock_irqrestore(&usb_regs_lock, flags);
268 return;
269 }
270
271 asic_type = platform_get_asic();
272
273 switch (asic_type) {
274 case ASIC_ZEUS:
275 fs_update(0x0000, -15, 0x02, 0, 0);
276 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
277 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
278 break;
279
280 case ASIC_CRONUS:
281 case ASIC_CRONUSLITE:
282 usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
283 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
284 QAM_FS_DISABLE_DIGITAL_STANDBY);
285 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
286 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
287 break;
288
289 case ASIC_CALLIOPE:
290 fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
291 QAM_FS_DISABLE_DIGITAL_STANDBY);
292
293 switch (platform_get_family()) {
294 case FAMILY_1500VZE:
295 break;
296
297 case FAMILY_1500VZF:
298 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
299 CRT_SPARE_PORT1_SHIFT_JK |
300 CRT_SPARE_PORT2_FAST_EDGE |
301 CRT_SPARE_PORT1_FAST_EDGE, 0);
302 break;
303
304 default:
305 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
306 CRT_SPARE_PORT1_SHIFT_JK, 0);
307 break;
308 }
309
310 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
311 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
312 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
313 break;
314
315 case ASIC_GAIA:
316 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
317 QAM_FS_DISABLE_DIGITAL_STANDBY);
318 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
319 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
320 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
321 break;
322
323 default:
324 pr_err("Unknown ASIC type: %d\n", asic_type);
325 bcm1_usb2_ctl_value = 0;
326 break;
327 }
328
329 /* turn on USB power */
330 asic_write(0, usb2_strap);
331 /* Enable all OHCI interrupts */
332 asic_write(bcm1_usb2_ctl_value, usb2_control);
333 /* usb2_stbus_obc store32/load32 */
334 asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
335 /* usb2_stbus_mess_size 2 packets */
336 asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
337 /* usb2_stbus_chunk_size 2 packets */
338 asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
339 spin_unlock_irqrestore(&usb_regs_lock, flags);
340}
341
342static void platform_unconfigure_usb(void)
343{
344 unsigned long flags;
345
346 spin_lock_irqsave(&usb_regs_lock, flags);
347 usb_users--;
348 if (usb_users == 0)
349 asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
350 spin_unlock_irqrestore(&usb_regs_lock, flags);
351}
352
353/*
354 * Set up the USB EHCI interface
355 */
356void platform_configure_usb_ehci()
357{
358 platform_configure_usb();
359}
360EXPORT_SYMBOL(platform_configure_usb_ehci);
361
362/*
363 * Set up the USB OHCI interface
364 */
365void platform_configure_usb_ohci()
366{
367 platform_configure_usb();
368}
369EXPORT_SYMBOL(platform_configure_usb_ohci);
370
371/*
372 * Shut the USB EHCI interface down
373 */
374void platform_unconfigure_usb_ehci()
375{
376 platform_unconfigure_usb();
377}
378EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
379
380/*
381 * Shut the USB OHCI interface down
382 */
383void platform_unconfigure_usb_ohci()
384{
385 platform_unconfigure_usb();
386}
387EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
388
389/**
390 * platform_devices_init - sets up USB device resourse.
391 */
392int __init platform_usb_devices_init(struct platform_device **ehci_dev,
393 struct platform_device **ohci_dev)
394{
395 *ehci_dev = &ehci_device;
396 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
397 ehci_resources[0].end += ehci_resources[0].start;
398
399 *ohci_dev = &ohci_device;
400 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
401 ohci_resources[0].end += ohci_resources[0].start;
402
403 return 0;
404}
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
deleted file mode 100644
index 24689bff1039..000000000000
--- a/arch/mips/powertv/powertv_setup.c
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/screen_info.h>
24#include <linux/notifier.h>
25#include <linux/etherdevice.h>
26#include <linux/if_ether.h>
27#include <linux/ctype.h>
28#include <linux/cpu.h>
29#include <linux/time.h>
30
31#include <asm/bootinfo.h>
32#include <asm/irq.h>
33#include <asm/mips-boards/generic.h>
34#include <asm/dma.h>
35#include <asm/asm.h>
36#include <asm/traps.h>
37#include <asm/asm-offsets.h>
38#include "reset.h"
39
40#define VAL(n) STR(n)
41
42/*
43 * Macros for loading addresses and storing registers:
44 * LONG_L_ Stringified version of LONG_L for use in asm() statement
45 * LONG_S_ Stringified version of LONG_S for use in asm() statement
46 * PTR_LA_ Stringified version of PTR_LA for use in asm() statement
47 * REG_SIZE Number of 8-bit bytes in a full width register
48 */
49#define LONG_L_ VAL(LONG_L) " "
50#define LONG_S_ VAL(LONG_S) " "
51#define PTR_LA_ VAL(PTR_LA) " "
52
53#ifdef CONFIG_64BIT
54#warning TODO: 64-bit code needs to be verified
55#define REG_SIZE "8" /* In bytes */
56#endif
57
58#ifdef CONFIG_32BIT
59#define REG_SIZE "4" /* In bytes */
60#endif
61
62static void register_panic_notifier(void);
63static int panic_handler(struct notifier_block *notifier_block,
64 unsigned long event, void *cause_string);
65
66const char *get_system_type(void)
67{
68 return "PowerTV";
69}
70
71void __init plat_mem_setup(void)
72{
73 panic_on_oops = 1;
74 register_panic_notifier();
75
76#if 0
77 mips_pcibios_init();
78#endif
79 mips_reboot_setup();
80}
81
82/*
83 * Install a panic notifier for platform-specific diagnostics
84 */
85static void register_panic_notifier()
86{
87 static struct notifier_block panic_notifier = {
88 .notifier_call = panic_handler,
89 .next = NULL,
90 .priority = INT_MAX
91 };
92 atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
93}
94
95static int panic_handler(struct notifier_block *notifier_block,
96 unsigned long event, void *cause_string)
97{
98 struct pt_regs my_regs;
99
100 /* Save all of the registers */
101 {
102 unsigned long at, v0, v1; /* Must be on the stack */
103
104 /* Start by saving $at and v0 on the stack. We use $at
105 * ourselves, but it looks like the compiler may use v0 or v1
106 * to load the address of the pt_regs structure. We'll come
107 * back later to store the registers in the pt_regs
108 * structure. */
109 __asm__ __volatile__ (
110 ".set noat\n"
111 LONG_S_ "$at, %[at]\n"
112 LONG_S_ "$2, %[v0]\n"
113 LONG_S_ "$3, %[v1]\n"
114 :
115 [at] "=m" (at),
116 [v0] "=m" (v0),
117 [v1] "=m" (v1)
118 :
119 : "at"
120 );
121
122 __asm__ __volatile__ (
123 ".set noat\n"
124 "move $at, %[pt_regs]\n"
125
126 /* Argument registers */
127 LONG_S_ "$4, " VAL(PT_R4) "($at)\n"
128 LONG_S_ "$5, " VAL(PT_R5) "($at)\n"
129 LONG_S_ "$6, " VAL(PT_R6) "($at)\n"
130 LONG_S_ "$7, " VAL(PT_R7) "($at)\n"
131
132 /* Temporary regs */
133 LONG_S_ "$8, " VAL(PT_R8) "($at)\n"
134 LONG_S_ "$9, " VAL(PT_R9) "($at)\n"
135 LONG_S_ "$10, " VAL(PT_R10) "($at)\n"
136 LONG_S_ "$11, " VAL(PT_R11) "($at)\n"
137 LONG_S_ "$12, " VAL(PT_R12) "($at)\n"
138 LONG_S_ "$13, " VAL(PT_R13) "($at)\n"
139 LONG_S_ "$14, " VAL(PT_R14) "($at)\n"
140 LONG_S_ "$15, " VAL(PT_R15) "($at)\n"
141
142 /* "Saved" registers */
143 LONG_S_ "$16, " VAL(PT_R16) "($at)\n"
144 LONG_S_ "$17, " VAL(PT_R17) "($at)\n"
145 LONG_S_ "$18, " VAL(PT_R18) "($at)\n"
146 LONG_S_ "$19, " VAL(PT_R19) "($at)\n"
147 LONG_S_ "$20, " VAL(PT_R20) "($at)\n"
148 LONG_S_ "$21, " VAL(PT_R21) "($at)\n"
149 LONG_S_ "$22, " VAL(PT_R22) "($at)\n"
150 LONG_S_ "$23, " VAL(PT_R23) "($at)\n"
151
152 /* Add'l temp regs */
153 LONG_S_ "$24, " VAL(PT_R24) "($at)\n"
154 LONG_S_ "$25, " VAL(PT_R25) "($at)\n"
155
156 /* Kernel temp regs */
157 LONG_S_ "$26, " VAL(PT_R26) "($at)\n"
158 LONG_S_ "$27, " VAL(PT_R27) "($at)\n"
159
160 /* Global pointer, stack pointer, frame pointer and
161 * return address */
162 LONG_S_ "$gp, " VAL(PT_R28) "($at)\n"
163 LONG_S_ "$sp, " VAL(PT_R29) "($at)\n"
164 LONG_S_ "$fp, " VAL(PT_R30) "($at)\n"
165 LONG_S_ "$ra, " VAL(PT_R31) "($at)\n"
166
167 /* Now we can get the $at and v0 registers back and
168 * store them */
169 LONG_L_ "$8, %[at]\n"
170 LONG_S_ "$8, " VAL(PT_R1) "($at)\n"
171 LONG_L_ "$8, %[v0]\n"
172 LONG_S_ "$8, " VAL(PT_R2) "($at)\n"
173 LONG_L_ "$8, %[v1]\n"
174 LONG_S_ "$8, " VAL(PT_R3) "($at)\n"
175 :
176 :
177 [at] "m" (at),
178 [v0] "m" (v0),
179 [v1] "m" (v1),
180 [pt_regs] "r" (&my_regs)
181 : "at", "t0"
182 );
183
184 /* Set the current EPC value to be the current location in this
185 * function */
186 __asm__ __volatile__ (
187 ".set noat\n"
188 "1:\n"
189 PTR_LA_ "$at, 1b\n"
190 LONG_S_ "$at, %[cp0_epc]\n"
191 :
192 [cp0_epc] "=m" (my_regs.cp0_epc)
193 :
194 : "at"
195 );
196
197 my_regs.cp0_cause = read_c0_cause();
198 my_regs.cp0_status = read_c0_status();
199 }
200
201 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
202 "zzzz... \n");
203
204 return NOTIFY_DONE;
205}
206
207/* Information about the RF MAC address, if one was supplied on the
208 * command line. */
209static bool have_rfmac;
210static u8 rfmac[ETH_ALEN];
211
212static int rfmac_param(char *p)
213{
214 u8 *q;
215 bool is_high_nibble;
216 int c;
217
218 /* Skip a leading "0x", if present */
219 if (*p == '0' && *(p+1) == 'x')
220 p += 2;
221
222 q = rfmac;
223 is_high_nibble = true;
224
225 for (c = (unsigned char) *p++;
226 isxdigit(c) && q - rfmac < ETH_ALEN;
227 c = (unsigned char) *p++) {
228 int nibble;
229
230 nibble = (isdigit(c) ? (c - '0') :
231 (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
232
233 if (is_high_nibble)
234 *q = nibble << 4;
235 else
236 *q++ |= nibble;
237
238 is_high_nibble = !is_high_nibble;
239 }
240
241 /* If we parsed all the way to the end of the parameter value and
242 * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
243 have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
244
245 return 0;
246}
247
248early_param("rfmac", rfmac_param);
249
250/*
251 * Generate an Ethernet MAC address that has a good chance of being unique.
252 * @addr: Pointer to six-byte array containing the Ethernet address
253 * Generates an Ethernet MAC address that is highly likely to be unique for
254 * this particular system on a network with other systems of the same type.
255 *
256 * The problem we are solving is that, when eth_random_addr() is used to
257 * generate MAC addresses at startup, there isn't much entropy for the random
258 * number generator to use and the addresses it produces are fairly likely to
259 * be the same as those of other identical systems on the same local network.
260 * This is true even for relatively small numbers of systems (for the reason
261 * why, see the Wikipedia entry for "Birthday problem" at:
262 * http://en.wikipedia.org/wiki/Birthday_problem
263 *
264 * The good news is that we already have a MAC address known to be unique, the
265 * RF MAC address. The bad news is that this address is already in use on the
266 * RF interface. Worse, the obvious trick, taking the RF MAC address and
267 * turning on the locally managed bit, has already been used for other devices.
268 * Still, this does give us something to work with.
269 *
270 * The approach we take is:
271 * 1. If we can't get the RF MAC Address, just call eth_random_addr.
272 * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
273 * bits of the new address. This is very likely to be unique, except for
274 * the current box.
275 * 3. To avoid using addresses already on the current box, we set the top
276 * six bits of the address with a value different from any currently
277 * registered Scientific Atlanta organizationally unique identifyer
278 * (OUI). This avoids duplication with any addresses on the system that
279 * were generated from valid Scientific Atlanta-registered address by
280 * simply flipping the locally managed bit.
281 * 4. We aren't generating a multicast address, so we leave the multicast
282 * bit off. Since we aren't using a registered address, we have to set
283 * the locally managed bit.
284 * 5. We then randomly generate the remaining 16-bits. This does two
285 * things:
286 * a. It allows us to call this function for more than one device
287 * in this system
288 * b. It ensures that things will probably still work even if
289 * some device on the device network has a locally managed
290 * address that matches the top six bits from step 2.
291 */
292void platform_random_ether_addr(u8 addr[ETH_ALEN])
293{
294 const int num_random_bytes = 2;
295 const unsigned char non_sciatl_oui_bits = 0xc0u;
296 const unsigned char mac_addr_locally_managed = (1 << 1);
297
298 if (!have_rfmac) {
299 pr_warning("rfmac not available on command line; "
300 "generating random MAC address\n");
301 eth_random_addr(addr);
302 }
303
304 else {
305 int i;
306
307 /* Set the first byte to something that won't match a Scientific
308 * Atlanta OUI, is locally managed, and isn't a multicast
309 * address */
310 addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
311
312 /* Get some bytes of random address information */
313 get_random_bytes(&addr[1], num_random_bytes);
314
315 /* Copy over the NIC-specific bits of the RF MAC address */
316 for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
317 addr[i] = rfmac[i];
318 }
319}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
deleted file mode 100644
index 11c32fbf2784..000000000000
--- a/arch/mips/powertv/reset.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/pm.h>
20
21#include <linux/io.h>
22#include <asm/reboot.h> /* Not included by linux/reboot.h */
23
24#include <asm/mach-powertv/asic_regs.h>
25#include "reset.h"
26
27static void mips_machine_restart(char *command)
28{
29 writel(0x1, asic_reg_addr(watchdog));
30}
31
32void mips_reboot_setup(void)
33{
34 _machine_restart = mips_machine_restart;
35}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
deleted file mode 100644
index 888fd09e2620..000000000000
--- a/arch/mips/powertv/reset.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Definitions from powertv reset.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_POWERTV_RESET_H
24#define _POWERTV_POWERTV_RESET_H
25extern void mips_reboot_setup(void);
26#endif
diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c
deleted file mode 100644
index f38b0d45eca9..000000000000
--- a/arch/mips/powertv/time.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Setting up the clock on the MIPS boards.
20 */
21
22#include <linux/init.h>
23#include <asm/mach-powertv/interrupts.h>
24#include <asm/time.h>
25
26#include "powertv-clock.h"
27
28unsigned int get_c0_compare_int(void)
29{
30 return irq_mips_timer;
31}
32
33void __init plat_time_init(void)
34{
35 powertv_clocksource_init();
36}
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index bba0cdfd83bc..5d0983d47161 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -26,7 +26,7 @@ void ralink_clk_add(const char *dev, unsigned long rate)
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
27 27
28 if (!clk) 28 if (!clk)
29 panic("failed to add clock\n"); 29 panic("failed to add clock");
30 30
31 clk->cl.dev_id = dev; 31 clk->cl.dev_id = dev;
32 clk->cl.clk = clk; 32 clk->cl.clk = clk;
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index d217509e5300..a3ad56c2372d 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -350,7 +350,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
350 name = "MT7620A"; 350 name = "MT7620A";
351 soc_info->compatible = "ralink,mt7620a-soc"; 351 soc_info->compatible = "ralink,mt7620a-soc";
352 } else { 352 } else {
353 panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 353 panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
354 } 354 }
355 355
356 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 356 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index ce38d11f9da5..15f21ea96121 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -108,7 +108,7 @@ static int __init plat_of_setup(void)
108 strncpy(of_ids[1].compatible, "palmbus", len); 108 strncpy(of_ids[1].compatible, "palmbus", len);
109 109
110 if (of_platform_populate(NULL, of_ids, NULL, NULL)) 110 if (of_platform_populate(NULL, of_ids, NULL, NULL))
111 panic("failed to populate DT\n"); 111 panic("failed to populate DT");
112 112
113 /* make sure ithat the reset controller is setup early */ 113 /* make sure ithat the reset controller is setup early */
114 ralink_rst_init(); 114 ralink_rst_init();
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index ca7ee3a33790..bb82a82da9e7 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -276,7 +276,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
276 name = "RT5350"; 276 name = "RT5350";
277 soc_info->compatible = "ralink,rt5350-soc"; 277 soc_info->compatible = "ralink,rt5350-soc";
278 } else { 278 } else {
279 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 279 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
280 } 280 }
281 281
282 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 282 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
diff --git a/drivers/net/ethernet/amd/declance.c b/drivers/net/ethernet/amd/declance.c
index 94edc9c6fbbf..1b89f1a9127e 100644
--- a/drivers/net/ethernet/amd/declance.c
+++ b/drivers/net/ethernet/amd/declance.c
@@ -725,7 +725,6 @@ static irqreturn_t lance_dma_merr_int(int irq, void *dev_id)
725{ 725{
726 struct net_device *dev = dev_id; 726 struct net_device *dev = dev_id;
727 727
728 clear_ioasic_dma_irq(irq);
729 printk(KERN_ERR "%s: DMA error\n", dev->name); 728 printk(KERN_ERR "%s: DMA error\n", dev->name);
730 return IRQ_HANDLED; 729 return IRQ_HANDLED;
731} 730}
@@ -812,7 +811,7 @@ static int lance_open(struct net_device *dev)
812 if (lp->dma_irq >= 0) { 811 if (lp->dma_irq >= 0) {
813 unsigned long flags; 812 unsigned long flags;
814 813
815 if (request_irq(lp->dma_irq, lance_dma_merr_int, 0, 814 if (request_irq(lp->dma_irq, lance_dma_merr_int, IRQF_ONESHOT,
816 "lance error", dev)) { 815 "lance error", dev)) {
817 free_irq(dev->irq, dev); 816 free_irq(dev->irq, dev);
818 printk("%s: Can't get DMA IRQ %d\n", dev->name, 817 printk("%s: Can't get DMA IRQ %d\n", dev->name,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 09:57:35 -0500