diff options
Diffstat (limited to 'arch/mips/powertv/asic/asic-cronus.c')
-rw-r--r-- | arch/mips/powertv/asic/asic-cronus.c | 101 |
1 files changed, 0 insertions, 101 deletions
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c deleted file mode 100644 index 7f8f3429b35a..000000000000 --- a/arch/mips/powertv/asic/asic-cronus.c +++ /dev/null | |||
@@ -1,101 +0,0 @@ | |||
1 | /* | ||
2 | * Locations of devices in the Cronus ASIC | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | * | ||
20 | * Author: Ken Eppinett | ||
21 | * David Schleef <ds@schleef.org> | ||
22 | * | ||
23 | * Description: Defines the platform resources for the SA settop. | ||
24 | */ | ||
25 | |||
26 | #include <linux/init.h> | ||
27 | #include <asm/mach-powertv/asic.h> | ||
28 | |||
29 | #define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) | ||
30 | |||
31 | const struct register_map cronus_register_map __initconst = { | ||
32 | .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, | ||
33 | .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, | ||
34 | .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, | ||
35 | |||
36 | .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)}, | ||
37 | .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)}, | ||
38 | .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)}, | ||
39 | .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)}, | ||
40 | |||
41 | /* The registers of IRBlaster */ | ||
42 | .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)}, | ||
43 | .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)}, | ||
44 | .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)}, | ||
45 | .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)}, | ||
46 | .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)}, | ||
47 | .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)}, | ||
48 | .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)}, | ||
49 | .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)}, | ||
50 | |||
51 | .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)}, | ||
52 | .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)}, | ||
53 | .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)}, | ||
54 | .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)}, | ||
55 | .int_config = {.phys = CRONUS_ADDR(0x2A2810)}, | ||
56 | .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)}, | ||
57 | .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)}, | ||
58 | .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)}, | ||
59 | .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)}, | ||
60 | .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)}, | ||
61 | .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)}, | ||
62 | .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)}, | ||
63 | .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)}, | ||
64 | .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)}, | ||
65 | .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)}, | ||
66 | .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)}, | ||
67 | .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)}, | ||
68 | .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)}, | ||
69 | .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)}, | ||
70 | .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)}, | ||
71 | .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)}, | ||
72 | .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)}, | ||
73 | .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)}, | ||
74 | .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)}, | ||
75 | .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)}, | ||
76 | .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)}, | ||
77 | .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)}, | ||
78 | |||
79 | .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)}, | ||
80 | .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)}, | ||
81 | .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)}, | ||
82 | .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)}, | ||
83 | .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)}, | ||
84 | .usb2_strap = {.phys = CRONUS_ADDR(0x200014)}, | ||
85 | .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)}, | ||
86 | .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)}, | ||
87 | .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)}, | ||
88 | .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)}, | ||
89 | .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)}, | ||
90 | .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)}, | ||
91 | .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)}, | ||
92 | |||
93 | .pcie_regs = {.phys = CRONUS_ADDR(0x220000)}, | ||
94 | .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)}, | ||
95 | .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)}, | ||
96 | .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)}, | ||
97 | .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)}, | ||
98 | .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)}, | ||
99 | .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)}, | ||
100 | .front_panel = {.phys = CRONUS_ADDR(0x2A3800)}, | ||
101 | }; | ||