MIPS: uasm: Add sltiu uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6730/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 8 insertions, 4 deletions

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 38312d8cde57..abf0845f5007 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -143,6 +143,7 @@ Ip_u2s3u1(_scd);
 Ip_u2s3u1(_sd);
 Ip_u2u1u3(_sll);
 Ip_u3u2u1(_sllv);
+Ip_u2u1s3(_sltiu);
 Ip_u2u1u3(_sra);
 Ip_u2u1u3(_srl);
 Ip_u3u2u1(_srlv);
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 6128cf3c8f1c..e81649a0551b 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -98,6 +98,7 @@ static struct insn insn_table_MM[] = {
         { insn_sd, 0, 0 },
         { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
         { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
+        { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
         { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
         { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
         { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 07184927b733..8231d7ddeccd 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -106,6 +106,7 @@ static struct insn insn_table[] = {
         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
         { insn_sllv,  M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD },
+        { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_srlv,  M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD },
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 29fc43278801..3a3d8a21cd56 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -52,10 +52,10 @@ enum opcode {
         insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
         insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
         insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe,
-        insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra,
-        insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
-        insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_xor,
-        insn_xori, insn_yield,
+        insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sltiu,
+        insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
+        insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
+        insn_xor, insn_xori, insn_yield,
 };
 
 struct insn {
@@ -284,6 +284,7 @@ I_u2s3u1(_scd)
 I_u2s3u1(_sd)
 I_u2u1u3(_sll)
 I_u3u2u1(_sllv)
+I_u2u1s3(_sltiu)
 I_u2u1u3(_sra)
 I_u2u1u3(_srl)
 I_u3u2u1(_srlv)